drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "amdgpu_gfx.h"
  27 #include "amdgpu_ucode.h"
  28 #include "si/clearstate_si.h"
  29 #include "si/sid.h"
  30
  31 #define GFX6_NUM_GFX_RINGS     1
  32 #define GFX6_NUM_COMPUTE_RINGS 2
  33 #define STATIC_PER_CU_PG_ENABLE                    (1 << 3)
  34 #define DYN_PER_CU_PG_ENABLE                       (1 << 2)
  35 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
  36 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
  37
  38
  39 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  40 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
  44 MODULE_FIRMWARE("radeon/tahiti_me.bin");
  45 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
  46 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
  47
  48 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
  49 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
  50 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
  51 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
  52
  53 MODULE_FIRMWARE("radeon/verde_pfp.bin");
  54 MODULE_FIRMWARE("radeon/verde_me.bin");
  55 MODULE_FIRMWARE("radeon/verde_ce.bin");
  56 MODULE_FIRMWARE("radeon/verde_rlc.bin");
  57
  58 MODULE_FIRMWARE("radeon/oland_pfp.bin");
  59 MODULE_FIRMWARE("radeon/oland_me.bin");
  60 MODULE_FIRMWARE("radeon/oland_ce.bin");
  61 MODULE_FIRMWARE("radeon/oland_rlc.bin");
  62
  63 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
  64 MODULE_FIRMWARE("radeon/hainan_me.bin");
  65 MODULE_FIRMWARE("radeon/hainan_ce.bin");
  66 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
  67
  68 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
  69 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
  70 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
  71 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
  72
  73
  74 static const u32 verde_rlc_save_restore_register_list[] =
  75 {
  76         (0x8000 << 16) | (0x98f4 >> 2),
  77         0x00000000,
  78         (0x8040 << 16) | (0x98f4 >> 2),
  79         0x00000000,
  80         (0x8000 << 16) | (0xe80 >> 2),
  81         0x00000000,
  82         (0x8040 << 16) | (0xe80 >> 2),
  83         0x00000000,
  84         (0x8000 << 16) | (0x89bc >> 2),
  85         0x00000000,
  86         (0x8040 << 16) | (0x89bc >> 2),
  87         0x00000000,
  88         (0x8000 << 16) | (0x8c1c >> 2),
  89         0x00000000,
  90         (0x8040 << 16) | (0x8c1c >> 2),
  91         0x00000000,
  92         (0x9c00 << 16) | (0x98f0 >> 2),
  93         0x00000000,
  94         (0x9c00 << 16) | (0xe7c >> 2),
  95         0x00000000,
  96         (0x8000 << 16) | (0x9148 >> 2),
  97         0x00000000,
  98         (0x8040 << 16) | (0x9148 >> 2),
  99         0x00000000,
 100         (0x9c00 << 16) | (0x9150 >> 2),
 101         0x00000000,
 102         (0x9c00 << 16) | (0x897c >> 2),
 103         0x00000000,
 104         (0x9c00 << 16) | (0x8d8c >> 2),
 105         0x00000000,
 106         (0x9c00 << 16) | (0xac54 >> 2),
 107         0X00000000,
 108         0x3,
 109         (0x9c00 << 16) | (0x98f8 >> 2),
 110         0x00000000,
 111         (0x9c00 << 16) | (0x9910 >> 2),
 112         0x00000000,
 113         (0x9c00 << 16) | (0x9914 >> 2),
 114         0x00000000,
 115         (0x9c00 << 16) | (0x9918 >> 2),
 116         0x00000000,
 117         (0x9c00 << 16) | (0x991c >> 2),
 118         0x00000000,
 119         (0x9c00 << 16) | (0x9920 >> 2),
 120         0x00000000,
 121         (0x9c00 << 16) | (0x9924 >> 2),
 122         0x00000000,
 123         (0x9c00 << 16) | (0x9928 >> 2),
 124         0x00000000,
 125         (0x9c00 << 16) | (0x992c >> 2),
 126         0x00000000,
 127         (0x9c00 << 16) | (0x9930 >> 2),
 128         0x00000000,
 129         (0x9c00 << 16) | (0x9934 >> 2),
 130         0x00000000,
 131         (0x9c00 << 16) | (0x9938 >> 2),
 132         0x00000000,
 133         (0x9c00 << 16) | (0x993c >> 2),
 134         0x00000000,
 135         (0x9c00 << 16) | (0x9940 >> 2),
 136         0x00000000,
 137         (0x9c00 << 16) | (0x9944 >> 2),
 138         0x00000000,
 139         (0x9c00 << 16) | (0x9948 >> 2),
 140         0x00000000,
 141         (0x9c00 << 16) | (0x994c >> 2),
 142         0x00000000,
 143         (0x9c00 << 16) | (0x9950 >> 2),
 144         0x00000000,
 145         (0x9c00 << 16) | (0x9954 >> 2),
 146         0x00000000,
 147         (0x9c00 << 16) | (0x9958 >> 2),
 148         0x00000000,
 149         (0x9c00 << 16) | (0x995c >> 2),
 150         0x00000000,
 151         (0x9c00 << 16) | (0x9960 >> 2),
 152         0x00000000,
 153         (0x9c00 << 16) | (0x9964 >> 2),
 154         0x00000000,
 155         (0x9c00 << 16) | (0x9968 >> 2),
 156         0x00000000,
 157         (0x9c00 << 16) | (0x996c >> 2),
 158         0x00000000,
 159         (0x9c00 << 16) | (0x9970 >> 2),
 160         0x00000000,
 161         (0x9c00 << 16) | (0x9974 >> 2),
 162         0x00000000,
 163         (0x9c00 << 16) | (0x9978 >> 2),
 164         0x00000000,
 165         (0x9c00 << 16) | (0x997c >> 2),
 166         0x00000000,
 167         (0x9c00 << 16) | (0x9980 >> 2),
 168         0x00000000,
 169         (0x9c00 << 16) | (0x9984 >> 2),
 170         0x00000000,
 171         (0x9c00 << 16) | (0x9988 >> 2),
 172         0x00000000,
 173         (0x9c00 << 16) | (0x998c >> 2),
 174         0x00000000,
 175         (0x9c00 << 16) | (0x8c00 >> 2),
 176         0x00000000,
 177         (0x9c00 << 16) | (0x8c14 >> 2),
 178         0x00000000,
 179         (0x9c00 << 16) | (0x8c04 >> 2),
 180         0x00000000,
 181         (0x9c00 << 16) | (0x8c08 >> 2),
 182         0x00000000,
 183         (0x8000 << 16) | (0x9b7c >> 2),
 184         0x00000000,
 185         (0x8040 << 16) | (0x9b7c >> 2),
 186         0x00000000,
 187         (0x8000 << 16) | (0xe84 >> 2),
 188         0x00000000,
 189         (0x8040 << 16) | (0xe84 >> 2),
 190         0x00000000,
 191         (0x8000 << 16) | (0x89c0 >> 2),
 192         0x00000000,
 193         (0x8040 << 16) | (0x89c0 >> 2),
 194         0x00000000,
 195         (0x8000 << 16) | (0x914c >> 2),
 196         0x00000000,
 197         (0x8040 << 16) | (0x914c >> 2),
 198         0x00000000,
 199         (0x8000 << 16) | (0x8c20 >> 2),
 200         0x00000000,
 201         (0x8040 << 16) | (0x8c20 >> 2),
 202         0x00000000,
 203         (0x8000 << 16) | (0x9354 >> 2),
 204         0x00000000,
 205         (0x8040 << 16) | (0x9354 >> 2),
 206         0x00000000,
 207         (0x9c00 << 16) | (0x9060 >> 2),
 208         0x00000000,
 209         (0x9c00 << 16) | (0x9364 >> 2),
 210         0x00000000,
 211         (0x9c00 << 16) | (0x9100 >> 2),
 212         0x00000000,
 213         (0x9c00 << 16) | (0x913c >> 2),
 214         0x00000000,
 215         (0x8000 << 16) | (0x90e0 >> 2),
 216         0x00000000,
 217         (0x8000 << 16) | (0x90e4 >> 2),
 218         0x00000000,
 219         (0x8000 << 16) | (0x90e8 >> 2),
 220         0x00000000,
 221         (0x8040 << 16) | (0x90e0 >> 2),
 222         0x00000000,
 223         (0x8040 << 16) | (0x90e4 >> 2),
 224         0x00000000,
 225         (0x8040 << 16) | (0x90e8 >> 2),
 226         0x00000000,
 227         (0x9c00 << 16) | (0x8bcc >> 2),
 228         0x00000000,
 229         (0x9c00 << 16) | (0x8b24 >> 2),
 230         0x00000000,
 231         (0x9c00 << 16) | (0x88c4 >> 2),
 232         0x00000000,
 233         (0x9c00 << 16) | (0x8e50 >> 2),
 234         0x00000000,
 235         (0x9c00 << 16) | (0x8c0c >> 2),
 236         0x00000000,
 237         (0x9c00 << 16) | (0x8e58 >> 2),
 238         0x00000000,
 239         (0x9c00 << 16) | (0x8e5c >> 2),
 240         0x00000000,
 241         (0x9c00 << 16) | (0x9508 >> 2),
 242         0x00000000,
 243         (0x9c00 << 16) | (0x950c >> 2),
 244         0x00000000,
 245         (0x9c00 << 16) | (0x9494 >> 2),
 246         0x00000000,
 247         (0x9c00 << 16) | (0xac0c >> 2),
 248         0x00000000,
 249         (0x9c00 << 16) | (0xac10 >> 2),
 250         0x00000000,
 251         (0x9c00 << 16) | (0xac14 >> 2),
 252         0x00000000,
 253         (0x9c00 << 16) | (0xae00 >> 2),
 254         0x00000000,
 255         (0x9c00 << 16) | (0xac08 >> 2),
 256         0x00000000,
 257         (0x9c00 << 16) | (0x88d4 >> 2),
 258         0x00000000,
 259         (0x9c00 << 16) | (0x88c8 >> 2),
 260         0x00000000,
 261         (0x9c00 << 16) | (0x88cc >> 2),
 262         0x00000000,
 263         (0x9c00 << 16) | (0x89b0 >> 2),
 264         0x00000000,
 265         (0x9c00 << 16) | (0x8b10 >> 2),
 266         0x00000000,
 267         (0x9c00 << 16) | (0x8a14 >> 2),
 268         0x00000000,
 269         (0x9c00 << 16) | (0x9830 >> 2),
 270         0x00000000,
 271         (0x9c00 << 16) | (0x9834 >> 2),
 272         0x00000000,
 273         (0x9c00 << 16) | (0x9838 >> 2),
 274         0x00000000,
 275         (0x9c00 << 16) | (0x9a10 >> 2),
 276         0x00000000,
 277         (0x8000 << 16) | (0x9870 >> 2),
 278         0x00000000,
 279         (0x8000 << 16) | (0x9874 >> 2),
 280         0x00000000,
 281         (0x8001 << 16) | (0x9870 >> 2),
 282         0x00000000,
 283         (0x8001 << 16) | (0x9874 >> 2),
 284         0x00000000,
 285         (0x8040 << 16) | (0x9870 >> 2),
 286         0x00000000,
 287         (0x8040 << 16) | (0x9874 >> 2),
 288         0x00000000,
 289         (0x8041 << 16) | (0x9870 >> 2),
 290         0x00000000,
 291         (0x8041 << 16) | (0x9874 >> 2),
 292         0x00000000,
 293         0x00000000
 294 };
 295
 296 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 297 {
 298         const char *chip_name;
 299         char fw_name[30];
 300         int err;
 301         const struct gfx_firmware_header_v1_0 *cp_hdr;
 302         const struct rlc_firmware_header_v1_0 *rlc_hdr;
 303
 304         DRM_DEBUG("\n");
 305
 306         switch (adev->asic_type) {
 307         case CHIP_TAHITI:
 308                 chip_name = "tahiti";
 309                 break;
 310         case CHIP_PITCAIRN:
 311                 chip_name = "pitcairn";
 312                 break;
 313         case CHIP_VERDE:
 314                 chip_name = "verde";
 315                 break;
 316         case CHIP_OLAND:
 317                 chip_name = "oland";
 318                 break;
 319         case CHIP_HAINAN:
 320                 chip_name = "hainan";
 321                 break;
 322         default: BUG();
 323         }
 324
 325         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 326         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 327         if (err)
 328                 goto out;
 329         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 330         if (err)
 331                 goto out;
 332         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 333         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 334         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 335
 336         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 337         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 338         if (err)
 339                 goto out;
 340         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 341         if (err)
 342                 goto out;
 343         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 344         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 345         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 346
 347         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 348         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 349         if (err)
 350                 goto out;
 351         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 352         if (err)
 353                 goto out;
 354         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 355         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 356         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 357
 358         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 359         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 360         if (err)
 361                 goto out;
 362         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 363         rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 364         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 365         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 366
 367 out:
 368         if (err) {
 369                 printk(KERN_ERR
 370                        "gfx6: Failed to load firmware \"%s\"\n",
 371                        fw_name);
 372                 release_firmware(adev->gfx.pfp_fw);
 373                 adev->gfx.pfp_fw = NULL;
 374                 release_firmware(adev->gfx.me_fw);
 375                 adev->gfx.me_fw = NULL;
 376                 release_firmware(adev->gfx.ce_fw);
 377                 adev->gfx.ce_fw = NULL;
 378                 release_firmware(adev->gfx.rlc_fw);
 379                 adev->gfx.rlc_fw = NULL;
 380         }
 381         return err;
 382 }
 383
 384 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
 385 {
 386         const u32 num_tile_mode_states = 32;
 387         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 388
 389         switch (adev->gfx.config.mem_row_size_in_kb) {
 390         case 1:
 391                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 392                 break;
 393         case 2:
 394         default:
 395                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 396                 break;
 397         case 4:
 398                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 399                 break;
 400         }
 401
 402         if (adev->asic_type == CHIP_VERDE ||
 403                 adev->asic_type == CHIP_OLAND ||
 404                 adev->asic_type == CHIP_HAINAN) {
 405                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 406                         switch (reg_offset) {
 407                         case 0:
 408                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 409                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 410                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 411                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 412                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 413                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 414                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 415                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 416                                 break;
 417                         case 1:
 418                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 419                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 420                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 421                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 422                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 423                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 424                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 425                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 426                                 break;
 427                         case 2:
 428                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 429                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 430                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 431                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 432                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 433                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 434                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 435                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 436                                 break;
 437                         case 3:
 438                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 439                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 440                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 441                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 442                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 443                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 444                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 445                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 446                                 break;
 447                         case 4:
 448                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 449                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 450                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 451                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 452                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 453                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 454                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 455                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 456                                 break;
 457                         case 5:
 458                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 459                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 460                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 461                                                  TILE_SPLIT(split_equal_to_row_size) |
 462                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 463                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 464                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 465                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 466                                 break;
 467                         case 6:
 468                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 469                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 470                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 471                                                  TILE_SPLIT(split_equal_to_row_size) |
 472                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 473                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 474                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 475                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 476                                 break;
 477                         case 7:
 478                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 479                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 480                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 481                                                  TILE_SPLIT(split_equal_to_row_size) |
 482                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 483                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 484                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 485                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 486                                 break;
 487                         case 8:
 488                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 489                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 490                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 491                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 492                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 493                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 494                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 495                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 496                                 break;
 497                         case 9:
 498                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 499                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 500                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 501                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 502                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 503                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 504                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 505                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 506                                 break;
 507                         case 10:
 508                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 509                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 510                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 511                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 512                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 513                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 514                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 515                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 516                                 break;
 517                         case 11:
 518                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 519                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 520                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 521                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 522                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 523                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 524                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 525                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 526                                 break;
 527                         case 12:
 528                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 529                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 530                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 531                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 532                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 533                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 534                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 535                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 536                                 break;
 537                         case 13:
 538                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 539                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 540                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 541                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 542                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 543                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 544                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 545                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 546                                 break;
 547                         case 14:
 548                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 549                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 550                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 551                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 552                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 553                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 554                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 555                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 556                                 break;
 557                         case 15:
 558                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 559                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 560                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 561                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 562                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 563                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 564                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 565                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 566                                 break;
 567                         case 16:
 568                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 569                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 570                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 571                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 572                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 573                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 574                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 575                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 576                                 break;
 577                         case 17:
 578                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 579                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 580                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 581                                                  TILE_SPLIT(split_equal_to_row_size) |
 582                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 583                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 584                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 585                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 586                                 break;
 587                         case 21:
 588                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 589                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 590                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 591                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 592                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 593                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 594                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 595                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 596                                 break;
 597                         case 22:
 598                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 599                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 600                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 601                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 602                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 603                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 604                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 605                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 606                                 break;
 607                         case 23:
 608                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 609                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 610                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 611                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 612                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 613                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 614                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 615                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 616                                 break;
 617                         case 24:
 618                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 619                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 620                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 621                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 622                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 623                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 624                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 625                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 626                                 break;
 627                         case 25:
 628                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 629                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 630                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 631                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 632                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 633                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 634                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 635                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 636                                 break;
 637                         default:
 638                                 gb_tile_moden = 0;
 639                                 break;
 640                         }
 641                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 642                         WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
 643                 }
 644         } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
 645                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 646                         switch (reg_offset) {
 647                         case 0:  /* non-AA compressed depth or any compressed stencil */
 648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 649                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 650                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 651                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 652                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 653                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 654                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 655                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 656                                 break;
 657                         case 1:  /* 2xAA/4xAA compressed depth only */
 658                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 659                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 660                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 661                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 662                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 663                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 664                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 665                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 666                                 break;
 667                         case 2:  /* 8xAA compressed depth only */
 668                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 669                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 670                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 671                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 672                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 673                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 674                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 675                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 676                                 break;
 677                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 678                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 679                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 680                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 681                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 682                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 683                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 684                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 685                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 686                                 break;
 687                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 688                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 689                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 690                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 691                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 692                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 693                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 694                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 695                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 696                                 break;
 697                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
 698                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 699                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 700                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 701                                                  TILE_SPLIT(split_equal_to_row_size) |
 702                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 703                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 704                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 705                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 706                                 break;
 707                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
 708                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 709                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 710                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 711                                                  TILE_SPLIT(split_equal_to_row_size) |
 712                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 713                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 714                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 715                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 716                                 break;
 717                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
 718                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 719                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 720                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 721                                                  TILE_SPLIT(split_equal_to_row_size) |
 722                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 723                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 724                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 725                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 726                                 break;
 727                         case 8:  /* 1D and 1D Array Surfaces */
 728                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 729                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 730                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 731                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 732                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 733                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 734                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 735                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 736                                 break;
 737                         case 9:  /* Displayable maps. */
 738                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 739                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 740                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 741                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 742                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 743                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 744                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 745                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 746                                 break;
 747                         case 10:  /* Display 8bpp. */
 748                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 749                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 750                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 751                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 752                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 753                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 754                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 755                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 756                                 break;
 757                         case 11:  /* Display 16bpp. */
 758                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 759                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 760                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 761                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 762                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 763                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 764                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 765                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 766                                 break;
 767                         case 12:  /* Display 32bpp. */
 768                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 769                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 770                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 771                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 772                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 773                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 774                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 775                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 776                                 break;
 777                         case 13:  /* Thin. */
 778                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 779                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 780                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 781                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 782                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 783                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 784                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 785                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 786                                 break;
 787                         case 14:  /* Thin 8 bpp. */
 788                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 789                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 790                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 791                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 792                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 793                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 794                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 795                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 796                                 break;
 797                         case 15:  /* Thin 16 bpp. */
 798                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 799                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 800                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 801                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 802                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 803                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 804                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 805                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 806                                 break;
 807                         case 16:  /* Thin 32 bpp. */
 808                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 809                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 810                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 811                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 812                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 813                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 814                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 815                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 816                                 break;
 817                         case 17:  /* Thin 64 bpp. */
 818                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 819                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 820                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 821                                                  TILE_SPLIT(split_equal_to_row_size) |
 822                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 823                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 824                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 825                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 826                                 break;
 827                         case 21:  /* 8 bpp PRT. */
 828                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 829                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 830                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 831                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 832                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 833                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 834                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 835                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 836                                 break;
 837                         case 22:  /* 16 bpp PRT */
 838                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 839                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 840                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 841                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 842                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 843                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 844                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 845                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 846                                 break;
 847                         case 23:  /* 32 bpp PRT */
 848                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 849                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 850                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 851                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 852                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 853                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 854                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 855                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 856                                 break;
 857                         case 24:  /* 64 bpp PRT */
 858                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 859                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 860                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 861                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 862                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 863                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 864                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 865                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 866                                 break;
 867                         case 25:  /* 128 bpp PRT */
 868                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 869                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 870                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 871                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 872                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 873                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 874                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 875                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 876                                 break;
 877                         default:
 878                                 gb_tile_moden = 0;
 879                                 break;
 880                         }
 881                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 882                         WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
 883                 }
 884         } else{
 885
 886                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
 887         }
 888
 889 }
 890
 891 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 892                                   u32 sh_num, u32 instance)
 893 {
 894         u32 data;
 895
 896         if (instance == 0xffffffff)
 897                 data = INSTANCE_BROADCAST_WRITES;
 898         else
 899                 data = INSTANCE_INDEX(instance);
 900
 901         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
 902                 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
 903         else if (se_num == 0xffffffff)
 904                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
 905         else if (sh_num == 0xffffffff)
 906                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
 907         else
 908                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
 909         WREG32(GRBM_GFX_INDEX, data);
 910 }
 911
 912 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
 913 {
 914         return (u32)(((u64)1 << bit_width) - 1);
 915 }
 916
 917 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
 918                                     u32 max_rb_num_per_se,
 919                                     u32 sh_per_se)
 920 {
 921         u32 data, mask;
 922
 923         data = RREG32(CC_RB_BACKEND_DISABLE);
 924         data &= BACKEND_DISABLE_MASK;
 925         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
 926
 927         data >>= BACKEND_DISABLE_SHIFT;
 928
 929         mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
 930
 931         return data & mask;
 932 }
 933
 934 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 935                               u32 se_num, u32 sh_per_se,
 936                               u32 max_rb_num_per_se)
 937 {
 938         int i, j;
 939         u32 data, mask;
 940         u32 disabled_rbs = 0;
 941         u32 enabled_rbs = 0;
 942
 943         mutex_lock(&adev->grbm_idx_mutex);
 944         for (i = 0; i < se_num; i++) {
 945                 for (j = 0; j < sh_per_se; j++) {
 946                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
 947                         data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
 948                         disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
 949                 }
 950         }
 951         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 952         mutex_unlock(&adev->grbm_idx_mutex);
 953
 954         mask = 1;
 955         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
 956                 if (!(disabled_rbs & mask))
 957                         enabled_rbs |= mask;
 958                 mask <<= 1;
 959         }
 960
 961         adev->gfx.config.backend_enable_mask = enabled_rbs;
 962         adev->gfx.config.num_rbs = hweight32(enabled_rbs);
 963
 964         mutex_lock(&adev->grbm_idx_mutex);
 965         for (i = 0; i < se_num; i++) {
 966                 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
 967                 data = 0;
 968                 for (j = 0; j < sh_per_se; j++) {
 969                         switch (enabled_rbs & 3) {
 970                         case 1:
 971                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
 972                                 break;
 973                         case 2:
 974                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
 975                                 break;
 976                         case 3:
 977                         default:
 978                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
 979                                 break;
 980                         }
 981                         enabled_rbs >>= 2;
 982                 }
 983                 WREG32(PA_SC_RASTER_CONFIG, data);
 984         }
 985         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 986         mutex_unlock(&adev->grbm_idx_mutex);
 987 }
 988 /*
 989 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
 990 {
 991 }
 992 */
 993
 994 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
 995 {
 996         u32 data, mask;
 997
 998         data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
 999         data &= INACTIVE_CUS_MASK;
1000         data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1001
1002         data >>= INACTIVE_CUS_SHIFT;
1003
1004         mask = gfx_v6_0_create_bitmask(cu_per_sh);
1005
1006         return ~data & mask;
1007 }
1008
1009
1010 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1011                          u32 se_num, u32 sh_per_se,
1012                          u32 cu_per_sh)
1013 {
1014         int i, j, k;
1015         u32 data, mask;
1016         u32 active_cu = 0;
1017
1018         mutex_lock(&adev->grbm_idx_mutex);
1019         for (i = 0; i < se_num; i++) {
1020                 for (j = 0; j < sh_per_se; j++) {
1021                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1022                         data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1023                         active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1024
1025                         mask = 1;
1026                         for (k = 0; k < 16; k++) {
1027                                 mask <<= k;
1028                                 if (active_cu & mask) {
1029                                         data &= ~mask;
1030                                         WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1031                                         break;
1032                                 }
1033                         }
1034                 }
1035         }
1036         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1037         mutex_unlock(&adev->grbm_idx_mutex);
1038 }
1039
1040 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1041 {
1042         u32 gb_addr_config = 0;
1043         u32 mc_shared_chmap, mc_arb_ramcfg;
1044         u32 sx_debug_1;
1045         u32 hdp_host_path_cntl;
1046         u32 tmp;
1047
1048         switch (adev->asic_type) {
1049         case CHIP_TAHITI:
1050                 adev->gfx.config.max_shader_engines = 2;
1051                 adev->gfx.config.max_tile_pipes = 12;
1052                 adev->gfx.config.max_cu_per_sh = 8;
1053                 adev->gfx.config.max_sh_per_se = 2;
1054                 adev->gfx.config.max_backends_per_se = 4;
1055                 adev->gfx.config.max_texture_channel_caches = 12;
1056                 adev->gfx.config.max_gprs = 256;
1057                 adev->gfx.config.max_gs_threads = 32;
1058                 adev->gfx.config.max_hw_contexts = 8;
1059
1060                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1061                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1062                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1063                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1064                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1065                 break;
1066         case CHIP_PITCAIRN:
1067                 adev->gfx.config.max_shader_engines = 2;
1068                 adev->gfx.config.max_tile_pipes = 8;
1069                 adev->gfx.config.max_cu_per_sh = 5;
1070                 adev->gfx.config.max_sh_per_se = 2;
1071                 adev->gfx.config.max_backends_per_se = 4;
1072                 adev->gfx.config.max_texture_channel_caches = 8;
1073                 adev->gfx.config.max_gprs = 256;
1074                 adev->gfx.config.max_gs_threads = 32;
1075                 adev->gfx.config.max_hw_contexts = 8;
1076
1077                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1078                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1079                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1080                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1081                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1082                 break;
1083
1084         case CHIP_VERDE:
1085                 adev->gfx.config.max_shader_engines = 1;
1086                 adev->gfx.config.max_tile_pipes = 4;
1087                 adev->gfx.config.max_cu_per_sh = 5;
1088                 adev->gfx.config.max_sh_per_se = 2;
1089                 adev->gfx.config.max_backends_per_se = 4;
1090                 adev->gfx.config.max_texture_channel_caches = 4;
1091                 adev->gfx.config.max_gprs = 256;
1092                 adev->gfx.config.max_gs_threads = 32;
1093                 adev->gfx.config.max_hw_contexts = 8;
1094
1095                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1096                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1097                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1098                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1099                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1100                 break;
1101         case CHIP_OLAND:
1102                 adev->gfx.config.max_shader_engines = 1;
1103                 adev->gfx.config.max_tile_pipes = 4;
1104                 adev->gfx.config.max_cu_per_sh = 6;
1105                 adev->gfx.config.max_sh_per_se = 1;
1106                 adev->gfx.config.max_backends_per_se = 2;
1107                 adev->gfx.config.max_texture_channel_caches = 4;
1108                 adev->gfx.config.max_gprs = 256;
1109                 adev->gfx.config.max_gs_threads = 16;
1110                 adev->gfx.config.max_hw_contexts = 8;
1111
1112                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1113                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1114                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1115                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1116                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1117                 break;
1118         case CHIP_HAINAN:
1119                 adev->gfx.config.max_shader_engines = 1;
1120                 adev->gfx.config.max_tile_pipes = 4;
1121                 adev->gfx.config.max_cu_per_sh = 5;
1122                 adev->gfx.config.max_sh_per_se = 1;
1123                 adev->gfx.config.max_backends_per_se = 1;
1124                 adev->gfx.config.max_texture_channel_caches = 2;
1125                 adev->gfx.config.max_gprs = 256;
1126                 adev->gfx.config.max_gs_threads = 16;
1127                 adev->gfx.config.max_hw_contexts = 8;
1128
1129                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1130                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1131                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1132                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1133                 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1134                 break;
1135         default:
1136                 BUG();
1137                 break;
1138         }
1139
1140         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1141         WREG32(SRBM_INT_CNTL, 1);
1142         WREG32(SRBM_INT_ACK, 1);
1143
1144         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1145
1146         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1147         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1148
1149         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1150         adev->gfx.config.mem_max_burst_length_bytes = 256;
1151         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1152         adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1153         if (adev->gfx.config.mem_row_size_in_kb > 4)
1154                 adev->gfx.config.mem_row_size_in_kb = 4;
1155         adev->gfx.config.shader_engine_tile_size = 32;
1156         adev->gfx.config.num_gpus = 1;
1157         adev->gfx.config.multi_gpu_tile_size = 64;
1158
1159         gb_addr_config &= ~ROW_SIZE_MASK;
1160         switch (adev->gfx.config.mem_row_size_in_kb) {
1161         case 1:
1162         default:
1163                 gb_addr_config |= ROW_SIZE(0);
1164                 break;
1165         case 2:
1166                 gb_addr_config |= ROW_SIZE(1);
1167                 break;
1168         case 4:
1169                 gb_addr_config |= ROW_SIZE(2);
1170                 break;
1171         }
1172         adev->gfx.config.gb_addr_config = gb_addr_config;
1173
1174         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1175         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1176         WREG32(DMIF_ADDR_CALC, gb_addr_config);
1177         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1178         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1179         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1180 #if 0
1181         if (adev->has_uvd) {
1182                 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1183                 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1184                 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1185         }
1186 #endif
1187         gfx_v6_0_tiling_mode_table_init(adev);
1188
1189         gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1190                     adev->gfx.config.max_sh_per_se,
1191                     adev->gfx.config.max_backends_per_se);
1192
1193         gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1194                      adev->gfx.config.max_sh_per_se,
1195                      adev->gfx.config.max_cu_per_sh);
1196
1197         gfx_v6_0_get_cu_info(adev);
1198
1199         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1200                                      ROQ_IB2_START(0x2b)));
1201         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1202
1203         sx_debug_1 = RREG32(SX_DEBUG_1);
1204         WREG32(SX_DEBUG_1, sx_debug_1);
1205
1206         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1207
1208         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1209                                  SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1210                                  SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1211                                  SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1212
1213         WREG32(VGT_NUM_INSTANCES, 1);
1214         WREG32(CP_PERFMON_CNTL, 0);
1215         WREG32(SQ_CONFIG, 0);
1216         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1217                                           FORCE_EOV_MAX_REZ_CNT(255)));
1218
1219         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1220                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1221
1222         WREG32(VGT_GS_VERTEX_REUSE, 16);
1223         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1224
1225         WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1226         WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1227         WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1228         WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1229         WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1230         WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1231         WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1232         WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1233
1234         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1235         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1236
1237         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1238
1239         udelay(50);
1240 }
1241
1242
1243 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1244 {
1245         int i;
1246
1247         adev->gfx.scratch.num_reg = 7;
1248         adev->gfx.scratch.reg_base = SCRATCH_REG0;
1249         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1250                 adev->gfx.scratch.free[i] = true;
1251                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1252         }
1253 }
1254
1255 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1256 {
1257         struct amdgpu_device *adev = ring->adev;
1258         uint32_t scratch;
1259         uint32_t tmp = 0;
1260         unsigned i;
1261         int r;
1262
1263         r = amdgpu_gfx_scratch_get(adev, &scratch);
1264         if (r) {
1265                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1266                 return r;
1267         }
1268         WREG32(scratch, 0xCAFEDEAD);
1269
1270         r = amdgpu_ring_alloc(ring, 3);
1271         if (r) {
1272                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1273                 amdgpu_gfx_scratch_free(adev, scratch);
1274                 return r;
1275         }
1276         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1277         amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1278         amdgpu_ring_write(ring, 0xDEADBEEF);
1279         amdgpu_ring_commit(ring);
1280
1281         for (i = 0; i < adev->usec_timeout; i++) {
1282                 tmp = RREG32(scratch);
1283                 if (tmp == 0xDEADBEEF)
1284                         break;
1285                 DRM_UDELAY(1);
1286         }
1287         if (i < adev->usec_timeout) {
1288                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1289         } else {
1290                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1291                           ring->idx, scratch, tmp);
1292                 r = -EINVAL;
1293         }
1294         amdgpu_gfx_scratch_free(adev, scratch);
1295         return r;
1296 }
1297
1298 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1299 {
1300         /* flush hdp cache */
1301         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1302         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1303                                  WRITE_DATA_DST_SEL(0)));
1304         amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1305         amdgpu_ring_write(ring, 0);
1306         amdgpu_ring_write(ring, 0x1);
1307 }
1308
1309 /**
1310  * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1311  *
1312  * @adev: amdgpu_device pointer
1313  * @ridx: amdgpu ring index
1314  *
1315  * Emits an hdp invalidate on the cp.
1316  */
1317 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1318 {
1319         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1320         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1321                                  WRITE_DATA_DST_SEL(0)));
1322         amdgpu_ring_write(ring, HDP_DEBUG0);
1323         amdgpu_ring_write(ring, 0);
1324         amdgpu_ring_write(ring, 0x1);
1325 }
1326
1327 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1328                                      u64 seq, unsigned flags)
1329 {
1330         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1331         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1332         /* flush read cache over gart */
1333         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1334         amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1335         amdgpu_ring_write(ring, 0);
1336         amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1337         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1338                           PACKET3_TC_ACTION_ENA |
1339                           PACKET3_SH_KCACHE_ACTION_ENA |
1340                           PACKET3_SH_ICACHE_ACTION_ENA);
1341         amdgpu_ring_write(ring, 0xFFFFFFFF);
1342         amdgpu_ring_write(ring, 0);
1343         amdgpu_ring_write(ring, 10); /* poll interval */
1344         /* EVENT_WRITE_EOP - flush caches, send int */
1345         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1346         amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1347         amdgpu_ring_write(ring, addr & 0xfffffffc);
1348         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1349                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1350         amdgpu_ring_write(ring, lower_32_bits(seq));
1351         amdgpu_ring_write(ring, upper_32_bits(seq));
1352 }
1353
1354 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1355                                   struct amdgpu_ib *ib,
1356                                   unsigned vm_id, bool ctx_switch)
1357 {
1358         u32 header, control = 0;
1359
1360         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1361         if (ctx_switch) {
1362                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1363                 amdgpu_ring_write(ring, 0);
1364         }
1365
1366         if (ib->flags & AMDGPU_IB_FLAG_CE)
1367                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1368         else
1369                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1370
1371         control |= ib->length_dw | (vm_id << 24);
1372
1373         amdgpu_ring_write(ring, header);
1374         amdgpu_ring_write(ring,
1375 #ifdef __BIG_ENDIAN
1376                           (2 << 0) |
1377 #endif
1378                           (ib->gpu_addr & 0xFFFFFFFC));
1379         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1380         amdgpu_ring_write(ring, control);
1381 }
1382
1383 /**
1384  * gfx_v6_0_ring_test_ib - basic ring IB test
1385  *
1386  * @ring: amdgpu_ring structure holding ring information
1387  *
1388  * Allocate an IB and execute it on the gfx ring (SI).
1389  * Provides a basic gfx ring test to verify that IBs are working.
1390  * Returns 0 on success, error on failure.
1391  */
1392 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1393 {
1394         struct amdgpu_device *adev = ring->adev;
1395         struct amdgpu_ib ib;
1396         struct fence *f = NULL;
1397         uint32_t scratch;
1398         uint32_t tmp = 0;
1399         long r;
1400
1401         r = amdgpu_gfx_scratch_get(adev, &scratch);
1402         if (r) {
1403                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1404                 return r;
1405         }
1406         WREG32(scratch, 0xCAFEDEAD);
1407         memset(&ib, 0, sizeof(ib));
1408         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1409         if (r) {
1410                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1411                 goto err1;
1412         }
1413         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1414         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1415         ib.ptr[2] = 0xDEADBEEF;
1416         ib.length_dw = 3;
1417
1418         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1419         if (r)
1420                 goto err2;
1421
1422         r = fence_wait_timeout(f, false, timeout);
1423         if (r == 0) {
1424                 DRM_ERROR("amdgpu: IB test timed out\n");
1425                 r = -ETIMEDOUT;
1426                 goto err2;
1427         } else if (r < 0) {
1428                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1429                 goto err2;
1430         }
1431         tmp = RREG32(scratch);
1432         if (tmp == 0xDEADBEEF) {
1433                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1434                 r = 0;
1435         } else {
1436                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1437                           scratch, tmp);
1438                 r = -EINVAL;
1439         }
1440
1441 err2:
1442         amdgpu_ib_free(adev, &ib, NULL);
1443         fence_put(f);
1444 err1:
1445         amdgpu_gfx_scratch_free(adev, scratch);
1446         return r;
1447 }
1448
1449 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1450 {
1451         int i;
1452         if (enable)
1453                 WREG32(CP_ME_CNTL, 0);
1454         else {
1455                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1456                 WREG32(SCRATCH_UMSK, 0);
1457                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1458                         adev->gfx.gfx_ring[i].ready = false;
1459                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1460                         adev->gfx.compute_ring[i].ready = false;
1461         }
1462         udelay(50);
1463 }
1464
1465 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1466 {
1467         unsigned i;
1468         const struct gfx_firmware_header_v1_0 *pfp_hdr;
1469         const struct gfx_firmware_header_v1_0 *ce_hdr;
1470         const struct gfx_firmware_header_v1_0 *me_hdr;
1471         const __le32 *fw_data;
1472         u32 fw_size;
1473
1474         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1475                 return -EINVAL;
1476
1477         gfx_v6_0_cp_gfx_enable(adev, false);
1478         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1479         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1480         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1481
1482         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1483         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1484         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1485
1486         /* PFP */
1487         fw_data = (const __le32 *)
1488                 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1489         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1490         WREG32(CP_PFP_UCODE_ADDR, 0);
1491         for (i = 0; i < fw_size; i++)
1492                 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1493         WREG32(CP_PFP_UCODE_ADDR, 0);
1494
1495         /* CE */
1496         fw_data = (const __le32 *)
1497                 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1498         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1499         WREG32(CP_CE_UCODE_ADDR, 0);
1500         for (i = 0; i < fw_size; i++)
1501                 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1502         WREG32(CP_CE_UCODE_ADDR, 0);
1503
1504         /* ME */
1505         fw_data = (const __be32 *)
1506                 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1507         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1508         WREG32(CP_ME_RAM_WADDR, 0);
1509         for (i = 0; i < fw_size; i++)
1510                 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1511         WREG32(CP_ME_RAM_WADDR, 0);
1512
1513
1514         WREG32(CP_PFP_UCODE_ADDR, 0);
1515         WREG32(CP_CE_UCODE_ADDR, 0);
1516         WREG32(CP_ME_RAM_WADDR, 0);
1517         WREG32(CP_ME_RAM_RADDR, 0);
1518         return 0;
1519 }
1520
1521 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1522 {
1523         const struct cs_section_def *sect = NULL;
1524         const struct cs_extent_def *ext = NULL;
1525         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1526         int r, i;
1527
1528         r = amdgpu_ring_alloc(ring, 7 + 4);
1529         if (r) {
1530                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1531                 return r;
1532         }
1533         amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1534         amdgpu_ring_write(ring, 0x1);
1535         amdgpu_ring_write(ring, 0x0);
1536         amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1537         amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1538         amdgpu_ring_write(ring, 0);
1539         amdgpu_ring_write(ring, 0);
1540
1541         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1542         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1543         amdgpu_ring_write(ring, 0xc000);
1544         amdgpu_ring_write(ring, 0xe000);
1545         amdgpu_ring_commit(ring);
1546
1547         gfx_v6_0_cp_gfx_enable(adev, true);
1548
1549         r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1550         if (r) {
1551                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1552                 return r;
1553         }
1554
1555         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1556         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1557
1558         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1559                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1560                         if (sect->id == SECT_CONTEXT) {
1561                                 amdgpu_ring_write(ring,
1562                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1563                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1564                                 for (i = 0; i < ext->reg_count; i++)
1565                                         amdgpu_ring_write(ring, ext->extent[i]);
1566                         }
1567                 }
1568         }
1569
1570         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1571         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1572
1573         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1574         amdgpu_ring_write(ring, 0);
1575
1576         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1577         amdgpu_ring_write(ring, 0x00000316);
1578         amdgpu_ring_write(ring, 0x0000000e);
1579         amdgpu_ring_write(ring, 0x00000010);
1580
1581         amdgpu_ring_commit(ring);
1582
1583         return 0;
1584 }
1585
1586 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1587 {
1588         struct amdgpu_ring *ring;
1589         u32 tmp;
1590         u32 rb_bufsz;
1591         int r;
1592         u64 rptr_addr;
1593
1594         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1595         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1596
1597         /* Set the write pointer delay */
1598         WREG32(CP_RB_WPTR_DELAY, 0);
1599
1600         WREG32(CP_DEBUG, 0);
1601         WREG32(SCRATCH_ADDR, 0);
1602
1603         /* ring 0 - compute and gfx */
1604         /* Set ring buffer size */
1605         ring = &adev->gfx.gfx_ring[0];
1606         rb_bufsz = order_base_2(ring->ring_size / 8);
1607         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1608
1609 #ifdef __BIG_ENDIAN
1610         tmp |= BUF_SWAP_32BIT;
1611 #endif
1612         WREG32(CP_RB0_CNTL, tmp);
1613
1614         /* Initialize the ring buffer's read and write pointers */
1615         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1616         ring->wptr = 0;
1617         WREG32(CP_RB0_WPTR, ring->wptr);
1618
1619         /* set the wb address whether it's enabled or not */
1620         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1621         WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1622         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1623
1624         WREG32(SCRATCH_UMSK, 0);
1625
1626         mdelay(1);
1627         WREG32(CP_RB0_CNTL, tmp);
1628
1629         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1630
1631         /* start the rings */
1632         gfx_v6_0_cp_gfx_start(adev);
1633         ring->ready = true;
1634         r = amdgpu_ring_test_ring(ring);
1635         if (r) {
1636                 ring->ready = false;
1637                 return r;
1638         }
1639
1640         return 0;
1641 }
1642
1643 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
1644 {
1645         return ring->adev->wb.wb[ring->rptr_offs];
1646 }
1647
1648 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1649 {
1650         struct amdgpu_device *adev = ring->adev;
1651
1652         if (ring == &adev->gfx.gfx_ring[0])
1653                 return RREG32(CP_RB0_WPTR);
1654         else if (ring == &adev->gfx.compute_ring[0])
1655                 return RREG32(CP_RB1_WPTR);
1656         else if (ring == &adev->gfx.compute_ring[1])
1657                 return RREG32(CP_RB2_WPTR);
1658         else
1659                 BUG();
1660 }
1661
1662 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1663 {
1664         struct amdgpu_device *adev = ring->adev;
1665
1666         WREG32(CP_RB0_WPTR, ring->wptr);
1667         (void)RREG32(CP_RB0_WPTR);
1668 }
1669
1670 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1671 {
1672         struct amdgpu_device *adev = ring->adev;
1673
1674         if (ring == &adev->gfx.compute_ring[0]) {
1675                 WREG32(CP_RB1_WPTR, ring->wptr);
1676                 (void)RREG32(CP_RB1_WPTR);
1677         } else if (ring == &adev->gfx.compute_ring[1]) {
1678                 WREG32(CP_RB2_WPTR, ring->wptr);
1679                 (void)RREG32(CP_RB2_WPTR);
1680         } else {
1681                 BUG();
1682         }
1683
1684 }
1685
1686 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1687 {
1688         struct amdgpu_ring *ring;
1689         u32 tmp;
1690         u32 rb_bufsz;
1691         int r;
1692         u64 rptr_addr;
1693
1694         /* ring1  - compute only */
1695         /* Set ring buffer size */
1696
1697         ring = &adev->gfx.compute_ring[0];
1698         rb_bufsz = order_base_2(ring->ring_size / 8);
1699         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1700 #ifdef __BIG_ENDIAN
1701         tmp |= BUF_SWAP_32BIT;
1702 #endif
1703         WREG32(CP_RB1_CNTL, tmp);
1704
1705         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1706         ring->wptr = 0;
1707         WREG32(CP_RB1_WPTR, ring->wptr);
1708
1709         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1710         WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1711         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1712
1713         mdelay(1);
1714         WREG32(CP_RB1_CNTL, tmp);
1715         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1716
1717         ring = &adev->gfx.compute_ring[1];
1718         rb_bufsz = order_base_2(ring->ring_size / 8);
1719         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1720 #ifdef __BIG_ENDIAN
1721         tmp |= BUF_SWAP_32BIT;
1722 #endif
1723         WREG32(CP_RB2_CNTL, tmp);
1724
1725         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1726         ring->wptr = 0;
1727         WREG32(CP_RB2_WPTR, ring->wptr);
1728         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1729         WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1730         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1731
1732         mdelay(1);
1733         WREG32(CP_RB2_CNTL, tmp);
1734         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1735
1736         adev->gfx.compute_ring[0].ready = true;
1737         adev->gfx.compute_ring[1].ready = true;
1738
1739         r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1740         if (r) {
1741                 adev->gfx.compute_ring[0].ready = false;
1742                 return r;
1743         }
1744
1745         r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1746         if (r) {
1747                 adev->gfx.compute_ring[1].ready = false;
1748                 return r;
1749         }
1750
1751         return 0;
1752 }
1753
1754 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1755 {
1756         gfx_v6_0_cp_gfx_enable(adev, enable);
1757 }
1758
1759 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1760 {
1761         return gfx_v6_0_cp_gfx_load_microcode(adev);
1762 }
1763
1764 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1765                                                bool enable)
1766 {
1767         u32 tmp = RREG32(CP_INT_CNTL_RING0);
1768         u32 mask;
1769         int i;
1770
1771         if (enable)
1772                 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1773         else
1774                 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1775         WREG32(CP_INT_CNTL_RING0, tmp);
1776
1777         if (!enable) {
1778                 /* read a gfx register */
1779                 tmp = RREG32(DB_DEPTH_INFO);
1780
1781                 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1782                 for (i = 0; i < adev->usec_timeout; i++) {
1783                         if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1784                                 break;
1785                         udelay(1);
1786                 }
1787         }
1788 }
1789
1790 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1791 {
1792         int r;
1793
1794         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1795
1796         r = gfx_v6_0_cp_load_microcode(adev);
1797         if (r)
1798                 return r;
1799
1800         r = gfx_v6_0_cp_gfx_resume(adev);
1801         if (r)
1802                 return r;
1803         r = gfx_v6_0_cp_compute_resume(adev);
1804         if (r)
1805                 return r;
1806
1807         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1808
1809         return 0;
1810 }
1811
1812 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1813 {
1814         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1815         uint32_t seq = ring->fence_drv.sync_seq;
1816         uint64_t addr = ring->fence_drv.gpu_addr;
1817
1818         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1819         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1820                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
1821                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
1822         amdgpu_ring_write(ring, addr & 0xfffffffc);
1823         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1824         amdgpu_ring_write(ring, seq);
1825         amdgpu_ring_write(ring, 0xffffffff);
1826         amdgpu_ring_write(ring, 4); /* poll interval */
1827
1828         if (usepfp) {
1829                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1830                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1831                 amdgpu_ring_write(ring, 0);
1832                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1833                 amdgpu_ring_write(ring, 0);
1834         }
1835 }
1836
1837 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1838                                         unsigned vm_id, uint64_t pd_addr)
1839 {
1840         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1841
1842         /* write new base address */
1843         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1844         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1845                                  WRITE_DATA_DST_SEL(0)));
1846         if (vm_id < 8) {
1847                 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1848         } else {
1849                 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1850         }
1851         amdgpu_ring_write(ring, 0);
1852         amdgpu_ring_write(ring, pd_addr >> 12);
1853
1854         /* bits 0-15 are the VM contexts0-15 */
1855         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1856         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1857                                  WRITE_DATA_DST_SEL(0)));
1858         amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1859         amdgpu_ring_write(ring, 0);
1860         amdgpu_ring_write(ring, 1 << vm_id);
1861
1862         /* wait for the invalidate to complete */
1863         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1864         amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
1865                                  WAIT_REG_MEM_ENGINE(0))); /* me */
1866         amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1867         amdgpu_ring_write(ring, 0);
1868         amdgpu_ring_write(ring, 0); /* ref */
1869         amdgpu_ring_write(ring, 0); /* mask */
1870         amdgpu_ring_write(ring, 0x20); /* poll interval */
1871
1872         if (usepfp) {
1873                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1874                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1875                 amdgpu_ring_write(ring, 0x0);
1876
1877                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1878                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1879                 amdgpu_ring_write(ring, 0);
1880                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1881                 amdgpu_ring_write(ring, 0);
1882         }
1883 }
1884
1885
1886 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
1887 {
1888         int r;
1889
1890         if (adev->gfx.rlc.save_restore_obj) {
1891                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1892                 if (unlikely(r != 0))
1893                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
1894                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
1895                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1896
1897                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
1898                 adev->gfx.rlc.save_restore_obj = NULL;
1899         }
1900
1901         if (adev->gfx.rlc.clear_state_obj) {
1902                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1903                 if (unlikely(r != 0))
1904                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1905                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1906                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1907
1908                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1909                 adev->gfx.rlc.clear_state_obj = NULL;
1910         }
1911
1912         if (adev->gfx.rlc.cp_table_obj) {
1913                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1914                 if (unlikely(r != 0))
1915                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1916                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1917                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1918
1919                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1920                 adev->gfx.rlc.cp_table_obj = NULL;
1921         }
1922 }
1923
1924 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
1925 {
1926         const u32 *src_ptr;
1927         volatile u32 *dst_ptr;
1928         u32 dws, i;
1929         u64 reg_list_mc_addr;
1930         const struct cs_section_def *cs_data;
1931         int r;
1932
1933         adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
1934         adev->gfx.rlc.reg_list_size =
1935                         (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
1936
1937         adev->gfx.rlc.cs_data = si_cs_data;
1938         src_ptr = adev->gfx.rlc.reg_list;
1939         dws = adev->gfx.rlc.reg_list_size;
1940         cs_data = adev->gfx.rlc.cs_data;
1941
1942         if (src_ptr) {
1943                 /* save restore block */
1944                 if (adev->gfx.rlc.save_restore_obj == NULL) {
1945
1946                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1947                                              AMDGPU_GEM_DOMAIN_VRAM,
1948                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1949                                              NULL, NULL,
1950                                              &adev->gfx.rlc.save_restore_obj);
1951
1952                         if (r) {
1953                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
1954                                 return r;
1955                         }
1956                 }
1957
1958                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1959                 if (unlikely(r != 0)) {
1960                         gfx_v6_0_rlc_fini(adev);
1961                         return r;
1962                 }
1963                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
1964                                   &adev->gfx.rlc.save_restore_gpu_addr);
1965                 if (r) {
1966                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1967                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
1968                         gfx_v6_0_rlc_fini(adev);
1969                         return r;
1970                 }
1971
1972                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
1973                 if (r) {
1974                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
1975                         gfx_v6_0_rlc_fini(adev);
1976                         return r;
1977                 }
1978                 /* write the sr buffer */
1979                 dst_ptr = adev->gfx.rlc.sr_ptr;
1980                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
1981                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
1982                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
1983                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1984         }
1985
1986         if (cs_data) {
1987                 /* clear state block */
1988                 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
1989                 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
1990
1991                 if (adev->gfx.rlc.clear_state_obj == NULL) {
1992                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1993                                              AMDGPU_GEM_DOMAIN_VRAM,
1994                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1995                                              NULL, NULL,
1996                                              &adev->gfx.rlc.clear_state_obj);
1997
1998                         if (r) {
1999                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2000                                 gfx_v6_0_rlc_fini(adev);
2001                                 return r;
2002                         }
2003                 }
2004                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2005                 if (unlikely(r != 0)) {
2006                         gfx_v6_0_rlc_fini(adev);
2007                         return r;
2008                 }
2009                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2010                                   &adev->gfx.rlc.clear_state_gpu_addr);
2011                 if (r) {
2012                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2013                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2014                         gfx_v6_0_rlc_fini(adev);
2015                         return r;
2016                 }
2017
2018                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2019                 if (r) {
2020                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2021                         gfx_v6_0_rlc_fini(adev);
2022                         return r;
2023                 }
2024                 /* set up the cs buffer */
2025                 dst_ptr = adev->gfx.rlc.cs_ptr;
2026                 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2027                 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2028                 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2029                 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2030                 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2031                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2032                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2033         }
2034
2035         return 0;
2036 }
2037
2038 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2039 {
2040         u32 tmp;
2041
2042         tmp = RREG32(RLC_LB_CNTL);
2043         if (enable)
2044                 tmp |= LOAD_BALANCE_ENABLE;
2045         else
2046                 tmp &= ~LOAD_BALANCE_ENABLE;
2047         WREG32(RLC_LB_CNTL, tmp);
2048
2049         if (!enable) {
2050                 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2051                 WREG32(SPI_LB_CU_MASK, 0x00ff);
2052         }
2053
2054 }
2055
2056 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2057 {
2058         int i;
2059
2060         for (i = 0; i < adev->usec_timeout; i++) {
2061                 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2062                         break;
2063                 udelay(1);
2064         }
2065
2066         for (i = 0; i < adev->usec_timeout; i++) {
2067                 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2068                         break;
2069                 udelay(1);
2070         }
2071 }
2072
2073 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2074 {
2075         u32 tmp;
2076
2077         tmp = RREG32(RLC_CNTL);
2078         if (tmp != rlc)
2079                 WREG32(RLC_CNTL, rlc);
2080 }
2081
2082 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2083 {
2084         u32 data, orig;
2085
2086         orig = data = RREG32(RLC_CNTL);
2087
2088         if (data & RLC_ENABLE) {
2089                 data &= ~RLC_ENABLE;
2090                 WREG32(RLC_CNTL, data);
2091
2092                 gfx_v6_0_wait_for_rlc_serdes(adev);
2093         }
2094
2095         return orig;
2096 }
2097
2098 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2099 {
2100         WREG32(RLC_CNTL, 0);
2101
2102         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2103         gfx_v6_0_wait_for_rlc_serdes(adev);
2104 }
2105
2106 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2107 {
2108         WREG32(RLC_CNTL, RLC_ENABLE);
2109
2110         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2111
2112         udelay(50);
2113 }
2114
2115 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2116 {
2117         u32 tmp = RREG32(GRBM_SOFT_RESET);
2118
2119         tmp |= SOFT_RESET_RLC;
2120         WREG32(GRBM_SOFT_RESET, tmp);
2121         udelay(50);
2122         tmp &= ~SOFT_RESET_RLC;
2123         WREG32(GRBM_SOFT_RESET, tmp);
2124         udelay(50);
2125 }
2126
2127 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2128 {
2129         u32 tmp;
2130
2131         /* Enable LBPW only for DDR3 */
2132         tmp = RREG32(MC_SEQ_MISC0);
2133         if ((tmp & 0xF0000000) == 0xB0000000)
2134                 return true;
2135         return false;
2136 }
2137 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2138 {
2139 }
2140
2141 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2142 {
2143         u32 i;
2144         const struct rlc_firmware_header_v1_0 *hdr;
2145         const __le32 *fw_data;
2146         u32 fw_size;
2147
2148
2149         if (!adev->gfx.rlc_fw)
2150                 return -EINVAL;
2151
2152         gfx_v6_0_rlc_stop(adev);
2153         gfx_v6_0_rlc_reset(adev);
2154         gfx_v6_0_init_pg(adev);
2155         gfx_v6_0_init_cg(adev);
2156
2157         WREG32(RLC_RL_BASE, 0);
2158         WREG32(RLC_RL_SIZE, 0);
2159         WREG32(RLC_LB_CNTL, 0);
2160         WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2161         WREG32(RLC_LB_CNTR_INIT, 0);
2162         WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2163
2164         WREG32(RLC_MC_CNTL, 0);
2165         WREG32(RLC_UCODE_CNTL, 0);
2166
2167         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2168         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2169         fw_data = (const __le32 *)
2170                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2171
2172         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2173
2174         for (i = 0; i < fw_size; i++) {
2175                 WREG32(RLC_UCODE_ADDR, i);
2176                 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2177         }
2178         WREG32(RLC_UCODE_ADDR, 0);
2179
2180         gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2181         gfx_v6_0_rlc_start(adev);
2182
2183         return 0;
2184 }
2185
2186 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2187 {
2188         u32 data, orig, tmp;
2189
2190         orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2191
2192         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2193                 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2194
2195                 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2196
2197                 tmp = gfx_v6_0_halt_rlc(adev);
2198
2199                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2200                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2201                 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2202
2203                 gfx_v6_0_wait_for_rlc_serdes(adev);
2204                 gfx_v6_0_update_rlc(adev, tmp);
2205
2206                 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2207
2208                 data |= CGCG_EN | CGLS_EN;
2209         } else {
2210                 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2211
2212                 RREG32(CB_CGTT_SCLK_CTRL);
2213                 RREG32(CB_CGTT_SCLK_CTRL);
2214                 RREG32(CB_CGTT_SCLK_CTRL);
2215                 RREG32(CB_CGTT_SCLK_CTRL);
2216
2217                 data &= ~(CGCG_EN | CGLS_EN);
2218         }
2219
2220         if (orig != data)
2221                 WREG32(RLC_CGCG_CGLS_CTRL, data);
2222
2223 }
2224
2225 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2226 {
2227
2228         u32 data, orig, tmp = 0;
2229
2230         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2231                 orig = data = RREG32(CGTS_SM_CTRL_REG);
2232                 data = 0x96940200;
2233                 if (orig != data)
2234                         WREG32(CGTS_SM_CTRL_REG, data);
2235
2236                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2237                         orig = data = RREG32(CP_MEM_SLP_CNTL);
2238                         data |= CP_MEM_LS_EN;
2239                         if (orig != data)
2240                                 WREG32(CP_MEM_SLP_CNTL, data);
2241                 }
2242
2243                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2244                 data &= 0xffffffc0;
2245                 if (orig != data)
2246                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2247
2248                 tmp = gfx_v6_0_halt_rlc(adev);
2249
2250                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2251                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2252                 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2253
2254                 gfx_v6_0_update_rlc(adev, tmp);
2255         } else {
2256                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2257                 data |= 0x00000003;
2258                 if (orig != data)
2259                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2260
2261                 data = RREG32(CP_MEM_SLP_CNTL);
2262                 if (data & CP_MEM_LS_EN) {
2263                         data &= ~CP_MEM_LS_EN;
2264                         WREG32(CP_MEM_SLP_CNTL, data);
2265                 }
2266                 orig = data = RREG32(CGTS_SM_CTRL_REG);
2267                 data |= LS_OVERRIDE | OVERRIDE;
2268                 if (orig != data)
2269                         WREG32(CGTS_SM_CTRL_REG, data);
2270
2271                 tmp = gfx_v6_0_halt_rlc(adev);
2272
2273                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2274                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2275                 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2276
2277                 gfx_v6_0_update_rlc(adev, tmp);
2278         }
2279 }
2280 /*
2281 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2282                                bool enable)
2283 {
2284         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2285         if (enable) {
2286                 gfx_v6_0_enable_mgcg(adev, true);
2287                 gfx_v6_0_enable_cgcg(adev, true);
2288         } else {
2289                 gfx_v6_0_enable_cgcg(adev, false);
2290                 gfx_v6_0_enable_mgcg(adev, false);
2291         }
2292         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2293 }
2294 */
2295 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2296                                                 bool enable)
2297 {
2298 }
2299
2300 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2301                                                 bool enable)
2302 {
2303 }
2304
2305 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2306 {
2307         u32 data, orig;
2308
2309         orig = data = RREG32(RLC_PG_CNTL);
2310         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2311                 data &= ~0x8000;
2312         else
2313                 data |= 0x8000;
2314         if (orig != data)
2315                 WREG32(RLC_PG_CNTL, data);
2316 }
2317
2318 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2319 {
2320 }
2321 /*
2322 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2323 {
2324         const __le32 *fw_data;
2325         volatile u32 *dst_ptr;
2326         int me, i, max_me = 4;
2327         u32 bo_offset = 0;
2328         u32 table_offset, table_size;
2329
2330         if (adev->asic_type == CHIP_KAVERI)
2331                 max_me = 5;
2332
2333         if (adev->gfx.rlc.cp_table_ptr == NULL)
2334                 return;
2335
2336         dst_ptr = adev->gfx.rlc.cp_table_ptr;
2337         for (me = 0; me < max_me; me++) {
2338                 if (me == 0) {
2339                         const struct gfx_firmware_header_v1_0 *hdr =
2340                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2341                         fw_data = (const __le32 *)
2342                                 (adev->gfx.ce_fw->data +
2343                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2344                         table_offset = le32_to_cpu(hdr->jt_offset);
2345                         table_size = le32_to_cpu(hdr->jt_size);
2346                 } else if (me == 1) {
2347                         const struct gfx_firmware_header_v1_0 *hdr =
2348                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2349                         fw_data = (const __le32 *)
2350                                 (adev->gfx.pfp_fw->data +
2351                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2352                         table_offset = le32_to_cpu(hdr->jt_offset);
2353                         table_size = le32_to_cpu(hdr->jt_size);
2354                 } else if (me == 2) {
2355                         const struct gfx_firmware_header_v1_0 *hdr =
2356                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2357                         fw_data = (const __le32 *)
2358                                 (adev->gfx.me_fw->data +
2359                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2360                         table_offset = le32_to_cpu(hdr->jt_offset);
2361                         table_size = le32_to_cpu(hdr->jt_size);
2362                 } else if (me == 3) {
2363                         const struct gfx_firmware_header_v1_0 *hdr =
2364                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2365                         fw_data = (const __le32 *)
2366                                 (adev->gfx.mec_fw->data +
2367                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2368                         table_offset = le32_to_cpu(hdr->jt_offset);
2369                         table_size = le32_to_cpu(hdr->jt_size);
2370                 } else {
2371                         const struct gfx_firmware_header_v1_0 *hdr =
2372                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2373                         fw_data = (const __le32 *)
2374                                 (adev->gfx.mec2_fw->data +
2375                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2376                         table_offset = le32_to_cpu(hdr->jt_offset);
2377                         table_size = le32_to_cpu(hdr->jt_size);
2378                 }
2379
2380                 for (i = 0; i < table_size; i ++) {
2381                         dst_ptr[bo_offset + i] =
2382                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2383                 }
2384
2385                 bo_offset += table_size;
2386         }
2387 }
2388 */
2389 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2390                                      bool enable)
2391 {
2392
2393         u32 tmp;
2394
2395         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2396                 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2397                 WREG32(RLC_TTOP_D, tmp);
2398
2399                 tmp = RREG32(RLC_PG_CNTL);
2400                 tmp |= GFX_PG_ENABLE;
2401                 WREG32(RLC_PG_CNTL, tmp);
2402
2403                 tmp = RREG32(RLC_AUTO_PG_CTRL);
2404                 tmp |= AUTO_PG_EN;
2405                 WREG32(RLC_AUTO_PG_CTRL, tmp);
2406         } else {
2407                 tmp = RREG32(RLC_AUTO_PG_CTRL);
2408                 tmp &= ~AUTO_PG_EN;
2409                 WREG32(RLC_AUTO_PG_CTRL, tmp);
2410
2411                 tmp = RREG32(DB_RENDER_CONTROL);
2412         }
2413 }
2414
2415 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2416                                          u32 se, u32 sh)
2417 {
2418
2419         u32 mask = 0, tmp, tmp1;
2420         int i;
2421
2422         mutex_lock(&adev->grbm_idx_mutex);
2423         gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2424         tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2425         tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2426         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2427         mutex_unlock(&adev->grbm_idx_mutex);
2428
2429         tmp &= 0xffff0000;
2430
2431         tmp |= tmp1;
2432         tmp >>= 16;
2433
2434         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2435                 mask <<= 1;
2436                 mask |= 1;
2437         }
2438
2439         return (~tmp) & mask;
2440 }
2441
2442 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2443 {
2444         u32 i, j, k, active_cu_number = 0;
2445
2446         u32 mask, counter, cu_bitmap;
2447         u32 tmp = 0;
2448
2449         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2450                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2451                         mask = 1;
2452                         cu_bitmap = 0;
2453                         counter  = 0;
2454                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2455                                 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2456                                         if (counter < 2)
2457                                                 cu_bitmap |= mask;
2458                                         counter++;
2459                                 }
2460                                 mask <<= 1;
2461                         }
2462
2463                         active_cu_number += counter;
2464                         tmp |= (cu_bitmap << (i * 16 + j * 8));
2465                 }
2466         }
2467
2468         WREG32(RLC_PG_AO_CU_MASK, tmp);
2469
2470         tmp = RREG32(RLC_MAX_PG_CU);
2471         tmp &= ~MAX_PU_CU_MASK;
2472         tmp |= MAX_PU_CU(active_cu_number);
2473         WREG32(RLC_MAX_PG_CU, tmp);
2474 }
2475
2476 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2477                                             bool enable)
2478 {
2479         u32 data, orig;
2480
2481         orig = data = RREG32(RLC_PG_CNTL);
2482         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2483                 data |= STATIC_PER_CU_PG_ENABLE;
2484         else
2485                 data &= ~STATIC_PER_CU_PG_ENABLE;
2486         if (orig != data)
2487                 WREG32(RLC_PG_CNTL, data);
2488 }
2489
2490 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2491                                              bool enable)
2492 {
2493         u32 data, orig;
2494
2495         orig = data = RREG32(RLC_PG_CNTL);
2496         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2497                 data |= DYN_PER_CU_PG_ENABLE;
2498         else
2499                 data &= ~DYN_PER_CU_PG_ENABLE;
2500         if (orig != data)
2501                 WREG32(RLC_PG_CNTL, data);
2502 }
2503
2504 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2505 {
2506         u32 tmp;
2507
2508         WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2509
2510         tmp = RREG32(RLC_PG_CNTL);
2511         tmp |= GFX_PG_SRC;
2512         WREG32(RLC_PG_CNTL, tmp);
2513
2514         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2515
2516         tmp = RREG32(RLC_AUTO_PG_CTRL);
2517
2518         tmp &= ~GRBM_REG_SGIT_MASK;
2519         tmp |= GRBM_REG_SGIT(0x700);
2520         tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2521         WREG32(RLC_AUTO_PG_CTRL, tmp);
2522 }
2523
2524 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2525 {
2526         gfx_v6_0_enable_gfx_cgpg(adev, enable);
2527         gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2528         gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2529 }
2530
2531 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2532 {
2533         u32 count = 0;
2534         const struct cs_section_def *sect = NULL;
2535         const struct cs_extent_def *ext = NULL;
2536
2537         if (adev->gfx.rlc.cs_data == NULL)
2538                 return 0;
2539
2540         /* begin clear state */
2541         count += 2;
2542         /* context control state */
2543         count += 3;
2544
2545         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2546                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2547                         if (sect->id == SECT_CONTEXT)
2548                                 count += 2 + ext->reg_count;
2549                         else
2550                                 return 0;
2551                 }
2552         }
2553         /* pa_sc_raster_config */
2554         count += 3;
2555         /* end clear state */
2556         count += 2;
2557         /* clear state */
2558         count += 2;
2559
2560         return count;
2561 }
2562
2563 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2564                                     volatile u32 *buffer)
2565 {
2566         u32 count = 0, i;
2567         const struct cs_section_def *sect = NULL;
2568         const struct cs_extent_def *ext = NULL;
2569
2570         if (adev->gfx.rlc.cs_data == NULL)
2571                 return;
2572         if (buffer == NULL)
2573                 return;
2574
2575         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2576         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2577
2578         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2579         buffer[count++] = cpu_to_le32(0x80000000);
2580         buffer[count++] = cpu_to_le32(0x80000000);
2581
2582         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2583                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2584                         if (sect->id == SECT_CONTEXT) {
2585                                 buffer[count++] =
2586                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2587                                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2588                                 for (i = 0; i < ext->reg_count; i++)
2589                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
2590                         } else {
2591                                 return;
2592                         }
2593                 }
2594         }
2595
2596         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2597         buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2598
2599         switch (adev->asic_type) {
2600         case CHIP_TAHITI:
2601         case CHIP_PITCAIRN:
2602                 buffer[count++] = cpu_to_le32(0x2a00126a);
2603                 break;
2604         case CHIP_VERDE:
2605                 buffer[count++] = cpu_to_le32(0x0000124a);
2606                 break;
2607         case CHIP_OLAND:
2608                 buffer[count++] = cpu_to_le32(0x00000082);
2609                 break;
2610         case CHIP_HAINAN:
2611                 buffer[count++] = cpu_to_le32(0x00000000);
2612                 break;
2613         default:
2614                 buffer[count++] = cpu_to_le32(0x00000000);
2615                 break;
2616         }
2617
2618         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2619         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2620
2621         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2622         buffer[count++] = cpu_to_le32(0);
2623 }
2624
2625 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2626 {
2627         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2628                               AMD_PG_SUPPORT_GFX_SMG |
2629                               AMD_PG_SUPPORT_GFX_DMG |
2630                               AMD_PG_SUPPORT_CP |
2631                               AMD_PG_SUPPORT_GDS |
2632                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2633                 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2634                 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2635                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2636                         gfx_v6_0_init_gfx_cgpg(adev);
2637                         gfx_v6_0_enable_cp_pg(adev, true);
2638                         gfx_v6_0_enable_gds_pg(adev, true);
2639                 } else {
2640                         WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2641                         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2642
2643                 }
2644                 gfx_v6_0_init_ao_cu_mask(adev);
2645                 gfx_v6_0_update_gfx_pg(adev, true);
2646         } else {
2647
2648                 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2649                 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2650         }
2651 }
2652
2653 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2654 {
2655         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2656                               AMD_PG_SUPPORT_GFX_SMG |
2657                               AMD_PG_SUPPORT_GFX_DMG |
2658                               AMD_PG_SUPPORT_CP |
2659                               AMD_PG_SUPPORT_GDS |
2660                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2661                 gfx_v6_0_update_gfx_pg(adev, false);
2662                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2663                         gfx_v6_0_enable_cp_pg(adev, false);
2664                         gfx_v6_0_enable_gds_pg(adev, false);
2665                 }
2666         }
2667 }
2668
2669 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2670 {
2671         uint64_t clock;
2672
2673         mutex_lock(&adev->gfx.gpu_clock_mutex);
2674         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2675         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2676                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2677         mutex_unlock(&adev->gfx.gpu_clock_mutex);
2678         return clock;
2679 }
2680
2681 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2682 {
2683         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2684         amdgpu_ring_write(ring, 0x80000000);
2685         amdgpu_ring_write(ring, 0);
2686 }
2687
2688 static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
2689 {
2690         return
2691                 6; /* gfx_v6_0_ring_emit_ib */
2692 }
2693
2694 static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
2695 {
2696         return
2697                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2698                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2699                 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2700                 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
2701                 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
2702                 3; /* gfx_v6_ring_emit_cntxcntl */
2703 }
2704
2705 static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
2706 {
2707         return
2708                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2709                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2710                 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
2711                 17 + /* gfx_v6_0_ring_emit_vm_flush */
2712                 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2713 }
2714
2715 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2716         .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2717         .select_se_sh = &gfx_v6_0_select_se_sh,
2718 };
2719
2720 static int gfx_v6_0_early_init(void *handle)
2721 {
2722         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2723
2724         adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2725         adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2726         adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2727         gfx_v6_0_set_ring_funcs(adev);
2728         gfx_v6_0_set_irq_funcs(adev);
2729
2730         return 0;
2731 }
2732
2733 static int gfx_v6_0_sw_init(void *handle)
2734 {
2735         struct amdgpu_ring *ring;
2736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2737         int i, r;
2738
2739         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2740         if (r)
2741                 return r;
2742
2743         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2744         if (r)
2745                 return r;
2746
2747         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2748         if (r)
2749                 return r;
2750
2751         gfx_v6_0_scratch_init(adev);
2752
2753         r = gfx_v6_0_init_microcode(adev);
2754         if (r) {
2755                 DRM_ERROR("Failed to load gfx firmware!\n");
2756                 return r;
2757         }
2758
2759         r = gfx_v6_0_rlc_init(adev);
2760         if (r) {
2761                 DRM_ERROR("Failed to init rlc BOs!\n");
2762                 return r;
2763         }
2764
2765         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2766                 ring = &adev->gfx.gfx_ring[i];
2767                 ring->ring_obj = NULL;
2768                 sprintf(ring->name, "gfx");
2769                 r = amdgpu_ring_init(adev, ring, 1024,
2770                                      0x80000000, 0xf,
2771                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2772                                      AMDGPU_RING_TYPE_GFX);
2773                 if (r)
2774                         return r;
2775         }
2776
2777         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2778                 unsigned irq_type;
2779
2780                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2781                         DRM_ERROR("Too many (%d) compute rings!\n", i);
2782                         break;
2783                 }
2784                 ring = &adev->gfx.compute_ring[i];
2785                 ring->ring_obj = NULL;
2786                 ring->use_doorbell = false;
2787                 ring->doorbell_index = 0;
2788                 ring->me = 1;
2789                 ring->pipe = i;
2790                 ring->queue = i;
2791                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2792                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2793                 r = amdgpu_ring_init(adev, ring, 1024,
2794                                      0x80000000, 0xf,
2795                                      &adev->gfx.eop_irq, irq_type,
2796                                      AMDGPU_RING_TYPE_COMPUTE);
2797                 if (r)
2798                         return r;
2799         }
2800
2801         return r;
2802 }
2803
2804 static int gfx_v6_0_sw_fini(void *handle)
2805 {
2806         int i;
2807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2808
2809         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2810         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2811         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2812
2813         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2814                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2815         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2816                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2817
2818         gfx_v6_0_rlc_fini(adev);
2819
2820         return 0;
2821 }
2822
2823 static int gfx_v6_0_hw_init(void *handle)
2824 {
2825         int r;
2826         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2827
2828         gfx_v6_0_gpu_init(adev);
2829
2830         r = gfx_v6_0_rlc_resume(adev);
2831         if (r)
2832                 return r;
2833
2834         r = gfx_v6_0_cp_resume(adev);
2835         if (r)
2836                 return r;
2837
2838         adev->gfx.ce_ram_size = 0x8000;
2839
2840         return r;
2841 }
2842
2843 static int gfx_v6_0_hw_fini(void *handle)
2844 {
2845         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2846
2847         gfx_v6_0_cp_enable(adev, false);
2848         gfx_v6_0_rlc_stop(adev);
2849         gfx_v6_0_fini_pg(adev);
2850
2851         return 0;
2852 }
2853
2854 static int gfx_v6_0_suspend(void *handle)
2855 {
2856         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2857
2858         return gfx_v6_0_hw_fini(adev);
2859 }
2860
2861 static int gfx_v6_0_resume(void *handle)
2862 {
2863         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2864
2865         return gfx_v6_0_hw_init(adev);
2866 }
2867
2868 static bool gfx_v6_0_is_idle(void *handle)
2869 {
2870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2871
2872         if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2873                 return false;
2874         else
2875                 return true;
2876 }
2877
2878 static int gfx_v6_0_wait_for_idle(void *handle)
2879 {
2880         unsigned i;
2881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2882
2883         for (i = 0; i < adev->usec_timeout; i++) {
2884                 if (gfx_v6_0_is_idle(handle))
2885                         return 0;
2886                 udelay(1);
2887         }
2888         return -ETIMEDOUT;
2889 }
2890
2891 static int gfx_v6_0_soft_reset(void *handle)
2892 {
2893         return 0;
2894 }
2895
2896 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2897                                                  enum amdgpu_interrupt_state state)
2898 {
2899         u32 cp_int_cntl;
2900
2901         switch (state) {
2902         case AMDGPU_IRQ_STATE_DISABLE:
2903                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2904                 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2905                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2906                 break;
2907         case AMDGPU_IRQ_STATE_ENABLE:
2908                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2909                 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2910                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2911                 break;
2912         default:
2913                 break;
2914         }
2915 }
2916
2917 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2918                                                      int ring,
2919                                                      enum amdgpu_interrupt_state state)
2920 {
2921         u32 cp_int_cntl;
2922         switch (state){
2923         case AMDGPU_IRQ_STATE_DISABLE:
2924                 if (ring == 0) {
2925                         cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2926                         cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2927                         WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2928                         break;
2929                 } else {
2930                         cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2931                         cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2932                         WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2933                         break;
2934
2935                 }
2936         case AMDGPU_IRQ_STATE_ENABLE:
2937                 if (ring == 0) {
2938                         cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2939                         cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2940                         WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2941                         break;
2942                 } else {
2943                         cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2944                         cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2945                         WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2946                         break;
2947
2948                 }
2949
2950         default:
2951                 BUG();
2952                 break;
2953
2954         }
2955 }
2956
2957 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2958                                              struct amdgpu_irq_src *src,
2959                                              unsigned type,
2960                                              enum amdgpu_interrupt_state state)
2961 {
2962         u32 cp_int_cntl;
2963
2964         switch (state) {
2965         case AMDGPU_IRQ_STATE_DISABLE:
2966                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2967                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
2968                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2969                 break;
2970         case AMDGPU_IRQ_STATE_ENABLE:
2971                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2972                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
2973                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2974                 break;
2975         default:
2976                 break;
2977         }
2978
2979         return 0;
2980 }
2981
2982 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
2983                                               struct amdgpu_irq_src *src,
2984                                               unsigned type,
2985                                               enum amdgpu_interrupt_state state)
2986 {
2987         u32 cp_int_cntl;
2988
2989         switch (state) {
2990         case AMDGPU_IRQ_STATE_DISABLE:
2991                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2992                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
2993                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2994                 break;
2995         case AMDGPU_IRQ_STATE_ENABLE:
2996                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2997                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
2998                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2999                 break;
3000         default:
3001                 break;
3002         }
3003
3004         return 0;
3005 }
3006
3007 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3008                                             struct amdgpu_irq_src *src,
3009                                             unsigned type,
3010                                             enum amdgpu_interrupt_state state)
3011 {
3012         switch (type) {
3013         case AMDGPU_CP_IRQ_GFX_EOP:
3014                 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3015                 break;
3016         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3017                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3018                 break;
3019         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3020                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3021                 break;
3022         default:
3023                 break;
3024         }
3025         return 0;
3026 }
3027
3028 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3029                             struct amdgpu_irq_src *source,
3030                             struct amdgpu_iv_entry *entry)
3031 {
3032         switch (entry->ring_id) {
3033         case 0:
3034                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3035                 break;
3036         case 1:
3037         case 2:
3038                 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3039                 break;
3040         default:
3041                 break;
3042         }
3043         return 0;
3044 }
3045
3046 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3047                                  struct amdgpu_irq_src *source,
3048                                  struct amdgpu_iv_entry *entry)
3049 {
3050         DRM_ERROR("Illegal register access in command stream\n");
3051         schedule_work(&adev->reset_work);
3052         return 0;
3053 }
3054
3055 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3056                                   struct amdgpu_irq_src *source,
3057                                   struct amdgpu_iv_entry *entry)
3058 {
3059         DRM_ERROR("Illegal instruction in command stream\n");
3060         schedule_work(&adev->reset_work);
3061         return 0;
3062 }
3063
3064 static int gfx_v6_0_set_clockgating_state(void *handle,
3065                                           enum amd_clockgating_state state)
3066 {
3067         bool gate = false;
3068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3069
3070         if (state == AMD_CG_STATE_GATE)
3071                 gate = true;
3072
3073         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3074         if (gate) {
3075                 gfx_v6_0_enable_mgcg(adev, true);
3076                 gfx_v6_0_enable_cgcg(adev, true);
3077         } else {
3078                 gfx_v6_0_enable_cgcg(adev, false);
3079                 gfx_v6_0_enable_mgcg(adev, false);
3080         }
3081         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3082
3083         return 0;
3084 }
3085
3086 static int gfx_v6_0_set_powergating_state(void *handle,
3087                                           enum amd_powergating_state state)
3088 {
3089         bool gate = false;
3090         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3091
3092         if (state == AMD_PG_STATE_GATE)
3093                 gate = true;
3094
3095         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3096                               AMD_PG_SUPPORT_GFX_SMG |
3097                               AMD_PG_SUPPORT_GFX_DMG |
3098                               AMD_PG_SUPPORT_CP |
3099                               AMD_PG_SUPPORT_GDS |
3100                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3101                 gfx_v6_0_update_gfx_pg(adev, gate);
3102                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3103                         gfx_v6_0_enable_cp_pg(adev, gate);
3104                         gfx_v6_0_enable_gds_pg(adev, gate);
3105                 }
3106         }
3107
3108         return 0;
3109 }
3110
3111 const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3112         .name = "gfx_v6_0",
3113         .early_init = gfx_v6_0_early_init,
3114         .late_init = NULL,
3115         .sw_init = gfx_v6_0_sw_init,
3116         .sw_fini = gfx_v6_0_sw_fini,
3117         .hw_init = gfx_v6_0_hw_init,
3118         .hw_fini = gfx_v6_0_hw_fini,
3119         .suspend = gfx_v6_0_suspend,
3120         .resume = gfx_v6_0_resume,
3121         .is_idle = gfx_v6_0_is_idle,
3122         .wait_for_idle = gfx_v6_0_wait_for_idle,
3123         .soft_reset = gfx_v6_0_soft_reset,
3124         .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3125         .set_powergating_state = gfx_v6_0_set_powergating_state,
3126 };
3127
3128 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3129         .get_rptr = gfx_v6_0_ring_get_rptr,
3130         .get_wptr = gfx_v6_0_ring_get_wptr,
3131         .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3132         .parse_cs = NULL,
3133         .emit_ib = gfx_v6_0_ring_emit_ib,
3134         .emit_fence = gfx_v6_0_ring_emit_fence,
3135         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3136         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3137         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3138         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3139         .test_ring = gfx_v6_0_ring_test_ring,
3140         .test_ib = gfx_v6_0_ring_test_ib,
3141         .insert_nop = amdgpu_ring_insert_nop,
3142         .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3143         .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3144         .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx,
3145 };
3146
3147 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3148         .get_rptr = gfx_v6_0_ring_get_rptr,
3149         .get_wptr = gfx_v6_0_ring_get_wptr,
3150         .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3151         .parse_cs = NULL,
3152         .emit_ib = gfx_v6_0_ring_emit_ib,
3153         .emit_fence = gfx_v6_0_ring_emit_fence,
3154         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3155         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3156         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3157         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3158         .test_ring = gfx_v6_0_ring_test_ring,
3159         .test_ib = gfx_v6_0_ring_test_ib,
3160         .insert_nop = amdgpu_ring_insert_nop,
3161         .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3162         .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute,
3163 };
3164
3165 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3166 {
3167         int i;
3168
3169         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3170                 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3171         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3172                 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3173 }
3174
3175 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3176         .set = gfx_v6_0_set_eop_interrupt_state,
3177         .process = gfx_v6_0_eop_irq,
3178 };
3179
3180 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3181         .set = gfx_v6_0_set_priv_reg_fault_state,
3182         .process = gfx_v6_0_priv_reg_irq,
3183 };
3184
3185 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3186         .set = gfx_v6_0_set_priv_inst_fault_state,
3187         .process = gfx_v6_0_priv_inst_irq,
3188 };
3189
3190 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3191 {
3192         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3193         adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3194
3195         adev->gfx.priv_reg_irq.num_types = 1;
3196         adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3197
3198         adev->gfx.priv_inst_irq.num_types = 1;
3199         adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3200 }
3201
3202 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3203 {
3204         int i, j, k, counter, active_cu_number = 0;
3205         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3206         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3207
3208         memset(cu_info, 0, sizeof(*cu_info));
3209
3210         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3211                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3212                         mask = 1;
3213                         ao_bitmap = 0;
3214                         counter = 0;
3215                         bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3216                         cu_info->bitmap[i][j] = bitmap;
3217
3218                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3219                                 if (bitmap & mask) {
3220                                         if (counter < 2)
3221                                                 ao_bitmap |= mask;
3222                                         counter ++;
3223                                 }
3224                                 mask <<= 1;
3225                         }
3226                         active_cu_number += counter;
3227                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3228                 }
3229         }
3230
3231         cu_info->number = active_cu_number;
3232         cu_info->ao_cu_mask = ao_cu_mask;
3233 }