2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_ih.h"
26 #include "amdgpu_gfx.h"
27 #include "amdgpu_ucode.h"
28 #include "si/clearstate_si.h"
31 #define GFX6_NUM_GFX_RINGS 1
32 #define GFX6_NUM_COMPUTE_RINGS 2
33 #define STATIC_PER_CU_PG_ENABLE (1 << 3)
34 #define DYN_PER_CU_PG_ENABLE (1 << 2)
35 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
36 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
39 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
43 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
44 MODULE_FIRMWARE("radeon/tahiti_me.bin");
45 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
46 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
48 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
49 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
50 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
51 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
53 MODULE_FIRMWARE("radeon/verde_pfp.bin");
54 MODULE_FIRMWARE("radeon/verde_me.bin");
55 MODULE_FIRMWARE("radeon/verde_ce.bin");
56 MODULE_FIRMWARE("radeon/verde_rlc.bin");
58 MODULE_FIRMWARE("radeon/oland_pfp.bin");
59 MODULE_FIRMWARE("radeon/oland_me.bin");
60 MODULE_FIRMWARE("radeon/oland_ce.bin");
61 MODULE_FIRMWARE("radeon/oland_rlc.bin");
63 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
64 MODULE_FIRMWARE("radeon/hainan_me.bin");
65 MODULE_FIRMWARE("radeon/hainan_ce.bin");
66 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
68 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
69 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
70 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
71 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
74 static const u32 verde_rlc_save_restore_register_list[] =
76 (0x8000 << 16) | (0x98f4 >> 2),
78 (0x8040 << 16) | (0x98f4 >> 2),
80 (0x8000 << 16) | (0xe80 >> 2),
82 (0x8040 << 16) | (0xe80 >> 2),
84 (0x8000 << 16) | (0x89bc >> 2),
86 (0x8040 << 16) | (0x89bc >> 2),
88 (0x8000 << 16) | (0x8c1c >> 2),
90 (0x8040 << 16) | (0x8c1c >> 2),
92 (0x9c00 << 16) | (0x98f0 >> 2),
94 (0x9c00 << 16) | (0xe7c >> 2),
96 (0x8000 << 16) | (0x9148 >> 2),
98 (0x8040 << 16) | (0x9148 >> 2),
100 (0x9c00 << 16) | (0x9150 >> 2),
102 (0x9c00 << 16) | (0x897c >> 2),
104 (0x9c00 << 16) | (0x8d8c >> 2),
106 (0x9c00 << 16) | (0xac54 >> 2),
109 (0x9c00 << 16) | (0x98f8 >> 2),
111 (0x9c00 << 16) | (0x9910 >> 2),
113 (0x9c00 << 16) | (0x9914 >> 2),
115 (0x9c00 << 16) | (0x9918 >> 2),
117 (0x9c00 << 16) | (0x991c >> 2),
119 (0x9c00 << 16) | (0x9920 >> 2),
121 (0x9c00 << 16) | (0x9924 >> 2),
123 (0x9c00 << 16) | (0x9928 >> 2),
125 (0x9c00 << 16) | (0x992c >> 2),
127 (0x9c00 << 16) | (0x9930 >> 2),
129 (0x9c00 << 16) | (0x9934 >> 2),
131 (0x9c00 << 16) | (0x9938 >> 2),
133 (0x9c00 << 16) | (0x993c >> 2),
135 (0x9c00 << 16) | (0x9940 >> 2),
137 (0x9c00 << 16) | (0x9944 >> 2),
139 (0x9c00 << 16) | (0x9948 >> 2),
141 (0x9c00 << 16) | (0x994c >> 2),
143 (0x9c00 << 16) | (0x9950 >> 2),
145 (0x9c00 << 16) | (0x9954 >> 2),
147 (0x9c00 << 16) | (0x9958 >> 2),
149 (0x9c00 << 16) | (0x995c >> 2),
151 (0x9c00 << 16) | (0x9960 >> 2),
153 (0x9c00 << 16) | (0x9964 >> 2),
155 (0x9c00 << 16) | (0x9968 >> 2),
157 (0x9c00 << 16) | (0x996c >> 2),
159 (0x9c00 << 16) | (0x9970 >> 2),
161 (0x9c00 << 16) | (0x9974 >> 2),
163 (0x9c00 << 16) | (0x9978 >> 2),
165 (0x9c00 << 16) | (0x997c >> 2),
167 (0x9c00 << 16) | (0x9980 >> 2),
169 (0x9c00 << 16) | (0x9984 >> 2),
171 (0x9c00 << 16) | (0x9988 >> 2),
173 (0x9c00 << 16) | (0x998c >> 2),
175 (0x9c00 << 16) | (0x8c00 >> 2),
177 (0x9c00 << 16) | (0x8c14 >> 2),
179 (0x9c00 << 16) | (0x8c04 >> 2),
181 (0x9c00 << 16) | (0x8c08 >> 2),
183 (0x8000 << 16) | (0x9b7c >> 2),
185 (0x8040 << 16) | (0x9b7c >> 2),
187 (0x8000 << 16) | (0xe84 >> 2),
189 (0x8040 << 16) | (0xe84 >> 2),
191 (0x8000 << 16) | (0x89c0 >> 2),
193 (0x8040 << 16) | (0x89c0 >> 2),
195 (0x8000 << 16) | (0x914c >> 2),
197 (0x8040 << 16) | (0x914c >> 2),
199 (0x8000 << 16) | (0x8c20 >> 2),
201 (0x8040 << 16) | (0x8c20 >> 2),
203 (0x8000 << 16) | (0x9354 >> 2),
205 (0x8040 << 16) | (0x9354 >> 2),
207 (0x9c00 << 16) | (0x9060 >> 2),
209 (0x9c00 << 16) | (0x9364 >> 2),
211 (0x9c00 << 16) | (0x9100 >> 2),
213 (0x9c00 << 16) | (0x913c >> 2),
215 (0x8000 << 16) | (0x90e0 >> 2),
217 (0x8000 << 16) | (0x90e4 >> 2),
219 (0x8000 << 16) | (0x90e8 >> 2),
221 (0x8040 << 16) | (0x90e0 >> 2),
223 (0x8040 << 16) | (0x90e4 >> 2),
225 (0x8040 << 16) | (0x90e8 >> 2),
227 (0x9c00 << 16) | (0x8bcc >> 2),
229 (0x9c00 << 16) | (0x8b24 >> 2),
231 (0x9c00 << 16) | (0x88c4 >> 2),
233 (0x9c00 << 16) | (0x8e50 >> 2),
235 (0x9c00 << 16) | (0x8c0c >> 2),
237 (0x9c00 << 16) | (0x8e58 >> 2),
239 (0x9c00 << 16) | (0x8e5c >> 2),
241 (0x9c00 << 16) | (0x9508 >> 2),
243 (0x9c00 << 16) | (0x950c >> 2),
245 (0x9c00 << 16) | (0x9494 >> 2),
247 (0x9c00 << 16) | (0xac0c >> 2),
249 (0x9c00 << 16) | (0xac10 >> 2),
251 (0x9c00 << 16) | (0xac14 >> 2),
253 (0x9c00 << 16) | (0xae00 >> 2),
255 (0x9c00 << 16) | (0xac08 >> 2),
257 (0x9c00 << 16) | (0x88d4 >> 2),
259 (0x9c00 << 16) | (0x88c8 >> 2),
261 (0x9c00 << 16) | (0x88cc >> 2),
263 (0x9c00 << 16) | (0x89b0 >> 2),
265 (0x9c00 << 16) | (0x8b10 >> 2),
267 (0x9c00 << 16) | (0x8a14 >> 2),
269 (0x9c00 << 16) | (0x9830 >> 2),
271 (0x9c00 << 16) | (0x9834 >> 2),
273 (0x9c00 << 16) | (0x9838 >> 2),
275 (0x9c00 << 16) | (0x9a10 >> 2),
277 (0x8000 << 16) | (0x9870 >> 2),
279 (0x8000 << 16) | (0x9874 >> 2),
281 (0x8001 << 16) | (0x9870 >> 2),
283 (0x8001 << 16) | (0x9874 >> 2),
285 (0x8040 << 16) | (0x9870 >> 2),
287 (0x8040 << 16) | (0x9874 >> 2),
289 (0x8041 << 16) | (0x9870 >> 2),
291 (0x8041 << 16) | (0x9874 >> 2),
296 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
298 const char *chip_name;
301 const struct gfx_firmware_header_v1_0 *cp_hdr;
302 const struct rlc_firmware_header_v1_0 *rlc_hdr;
306 switch (adev->asic_type) {
308 chip_name = "tahiti";
311 chip_name = "pitcairn";
320 chip_name = "hainan";
325 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
326 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
329 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
332 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
333 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
334 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
336 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
337 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
340 err = amdgpu_ucode_validate(adev->gfx.me_fw);
343 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
344 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
345 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
348 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
351 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
354 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
355 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
356 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
358 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
359 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
362 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
363 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
364 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
365 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
370 "gfx6: Failed to load firmware \"%s\"\n",
372 release_firmware(adev->gfx.pfp_fw);
373 adev->gfx.pfp_fw = NULL;
374 release_firmware(adev->gfx.me_fw);
375 adev->gfx.me_fw = NULL;
376 release_firmware(adev->gfx.ce_fw);
377 adev->gfx.ce_fw = NULL;
378 release_firmware(adev->gfx.rlc_fw);
379 adev->gfx.rlc_fw = NULL;
384 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
386 const u32 num_tile_mode_states = 32;
387 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
389 switch (adev->gfx.config.mem_row_size_in_kb) {
391 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
395 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
398 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
402 if (adev->asic_type == CHIP_VERDE ||
403 adev->asic_type == CHIP_OLAND ||
404 adev->asic_type == CHIP_HAINAN) {
405 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
406 switch (reg_offset) {
408 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
409 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
410 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
412 NUM_BANKS(ADDR_SURF_16_BANK) |
413 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
422 NUM_BANKS(ADDR_SURF_16_BANK) |
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
428 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
429 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
432 NUM_BANKS(ADDR_SURF_16_BANK) |
433 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
442 NUM_BANKS(ADDR_SURF_16_BANK) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
449 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
452 NUM_BANKS(ADDR_SURF_16_BANK) |
453 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
461 TILE_SPLIT(split_equal_to_row_size) |
462 NUM_BANKS(ADDR_SURF_16_BANK) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(split_equal_to_row_size) |
472 NUM_BANKS(ADDR_SURF_16_BANK) |
473 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
479 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
480 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
481 TILE_SPLIT(split_equal_to_row_size) |
482 NUM_BANKS(ADDR_SURF_16_BANK) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
488 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
489 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
492 NUM_BANKS(ADDR_SURF_16_BANK) |
493 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
499 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
502 NUM_BANKS(ADDR_SURF_16_BANK) |
503 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
512 NUM_BANKS(ADDR_SURF_16_BANK) |
513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
522 NUM_BANKS(ADDR_SURF_16_BANK) |
523 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
529 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
530 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
531 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
532 NUM_BANKS(ADDR_SURF_16_BANK) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
538 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
539 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
541 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
542 NUM_BANKS(ADDR_SURF_16_BANK) |
543 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
548 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
549 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
552 NUM_BANKS(ADDR_SURF_16_BANK) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
558 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 NUM_BANKS(ADDR_SURF_16_BANK) |
563 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
568 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
581 TILE_SPLIT(split_equal_to_row_size) |
582 NUM_BANKS(ADDR_SURF_16_BANK) |
583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
589 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
592 NUM_BANKS(ADDR_SURF_16_BANK) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
598 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
602 NUM_BANKS(ADDR_SURF_16_BANK) |
603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
608 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
611 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
612 NUM_BANKS(ADDR_SURF_16_BANK) |
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
622 NUM_BANKS(ADDR_SURF_16_BANK) |
623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
629 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
632 NUM_BANKS(ADDR_SURF_8_BANK) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
641 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
642 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
644 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
646 switch (reg_offset) {
647 case 0: /* non-AA compressed depth or any compressed stencil */
648 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
649 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
652 NUM_BANKS(ADDR_SURF_16_BANK) |
653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
657 case 1: /* 2xAA/4xAA compressed depth only */
658 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
660 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
661 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
662 NUM_BANKS(ADDR_SURF_16_BANK) |
663 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
667 case 2: /* 8xAA compressed depth only */
668 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
669 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
670 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
671 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
672 NUM_BANKS(ADDR_SURF_16_BANK) |
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
677 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
678 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
679 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
680 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
681 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
682 NUM_BANKS(ADDR_SURF_16_BANK) |
683 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
687 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
688 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
689 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
692 NUM_BANKS(ADDR_SURF_16_BANK) |
693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
697 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
698 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
700 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
701 TILE_SPLIT(split_equal_to_row_size) |
702 NUM_BANKS(ADDR_SURF_16_BANK) |
703 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
707 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
708 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
709 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
710 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
711 TILE_SPLIT(split_equal_to_row_size) |
712 NUM_BANKS(ADDR_SURF_16_BANK) |
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
717 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
718 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
719 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
720 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
721 TILE_SPLIT(split_equal_to_row_size) |
722 NUM_BANKS(ADDR_SURF_16_BANK) |
723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
727 case 8: /* 1D and 1D Array Surfaces */
728 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
729 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
732 NUM_BANKS(ADDR_SURF_16_BANK) |
733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
737 case 9: /* Displayable maps. */
738 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
739 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
740 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
742 NUM_BANKS(ADDR_SURF_16_BANK) |
743 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
744 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
745 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
747 case 10: /* Display 8bpp. */
748 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
749 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
750 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
752 NUM_BANKS(ADDR_SURF_16_BANK) |
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
757 case 11: /* Display 16bpp. */
758 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
759 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
760 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
761 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
762 NUM_BANKS(ADDR_SURF_16_BANK) |
763 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
764 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
765 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
767 case 12: /* Display 32bpp. */
768 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
769 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
770 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772 NUM_BANKS(ADDR_SURF_16_BANK) |
773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
778 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
779 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
780 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
781 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
784 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
785 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
787 case 14: /* Thin 8 bpp. */
788 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
789 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
790 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
791 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
792 NUM_BANKS(ADDR_SURF_16_BANK) |
793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
797 case 15: /* Thin 16 bpp. */
798 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
799 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
800 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
801 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
802 NUM_BANKS(ADDR_SURF_16_BANK) |
803 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
804 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
805 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
807 case 16: /* Thin 32 bpp. */
808 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
809 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
817 case 17: /* Thin 64 bpp. */
818 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
821 TILE_SPLIT(split_equal_to_row_size) |
822 NUM_BANKS(ADDR_SURF_16_BANK) |
823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
827 case 21: /* 8 bpp PRT. */
828 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
829 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
832 NUM_BANKS(ADDR_SURF_16_BANK) |
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
837 case 22: /* 16 bpp PRT */
838 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
839 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
842 NUM_BANKS(ADDR_SURF_16_BANK) |
843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
847 case 23: /* 32 bpp PRT */
848 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
849 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
852 NUM_BANKS(ADDR_SURF_16_BANK) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
857 case 24: /* 64 bpp PRT */
858 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
859 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
861 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
862 NUM_BANKS(ADDR_SURF_16_BANK) |
863 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
867 case 25: /* 128 bpp PRT */
868 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
869 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
872 NUM_BANKS(ADDR_SURF_8_BANK) |
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
881 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
882 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
886 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
891 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
892 u32 sh_num, u32 instance)
896 if (instance == 0xffffffff)
897 data = INSTANCE_BROADCAST_WRITES;
899 data = INSTANCE_INDEX(instance);
901 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
902 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
903 else if (se_num == 0xffffffff)
904 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
905 else if (sh_num == 0xffffffff)
906 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
908 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
909 WREG32(GRBM_GFX_INDEX, data);
912 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
914 return (u32)(((u64)1 << bit_width) - 1);
917 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
918 u32 max_rb_num_per_se,
923 data = RREG32(CC_RB_BACKEND_DISABLE);
924 data &= BACKEND_DISABLE_MASK;
925 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
927 data >>= BACKEND_DISABLE_SHIFT;
929 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
934 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
936 switch (adev->asic_type) {
939 *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) |
940 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2);
943 *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1);
952 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
957 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
958 u32 raster_config, unsigned rb_mask,
961 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
962 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
963 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
964 unsigned rb_per_se = num_rb / num_se;
968 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
969 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
970 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
971 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
973 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
974 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
975 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
977 for (se = 0; se < num_se; se++) {
978 unsigned raster_config_se = raster_config;
979 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
980 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
981 int idx = (se / 2) * 2;
983 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
984 raster_config_se &= ~SE_MAP_MASK;
987 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
989 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
993 pkr0_mask &= rb_mask;
994 pkr1_mask &= rb_mask;
995 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
996 raster_config_se &= ~PKR_MAP_MASK;
999 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1001 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1005 if (rb_per_se >= 2) {
1006 unsigned rb0_mask = 1 << (se * rb_per_se);
1007 unsigned rb1_mask = rb0_mask << 1;
1009 rb0_mask &= rb_mask;
1010 rb1_mask &= rb_mask;
1011 if (!rb0_mask || !rb1_mask) {
1012 raster_config_se &= ~RB_MAP_PKR0_MASK;
1016 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1019 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1023 if (rb_per_se > 2) {
1024 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1025 rb1_mask = rb0_mask << 1;
1026 rb0_mask &= rb_mask;
1027 rb1_mask &= rb_mask;
1028 if (!rb0_mask || !rb1_mask) {
1029 raster_config_se &= ~RB_MAP_PKR1_MASK;
1033 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1036 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1042 /* GRBM_GFX_INDEX has a different offset on SI */
1043 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1044 WREG32(PA_SC_RASTER_CONFIG, raster_config_se);
1047 /* GRBM_GFX_INDEX has a different offset on SI */
1048 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1051 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1052 u32 se_num, u32 sh_per_se,
1053 u32 max_rb_num_per_se)
1057 u32 disabled_rbs = 0;
1058 u32 enabled_rbs = 0;
1059 unsigned num_rb_pipes;
1061 mutex_lock(&adev->grbm_idx_mutex);
1062 for (i = 0; i < se_num; i++) {
1063 for (j = 0; j < sh_per_se; j++) {
1064 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1065 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1066 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1069 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1070 mutex_unlock(&adev->grbm_idx_mutex);
1073 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1074 if (!(disabled_rbs & mask))
1075 enabled_rbs |= mask;
1079 adev->gfx.config.backend_enable_mask = enabled_rbs;
1080 adev->gfx.config.num_rbs = hweight32(enabled_rbs);
1082 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1083 adev->gfx.config.max_shader_engines, 16);
1085 mutex_lock(&adev->grbm_idx_mutex);
1086 for (i = 0; i < se_num; i++) {
1087 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1089 for (j = 0; j < sh_per_se; j++) {
1090 switch (enabled_rbs & 3) {
1092 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1095 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1099 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1104 gfx_v6_0_raster_config(adev, &data);
1106 if (!adev->gfx.config.backend_enable_mask ||
1107 adev->gfx.config.num_rbs >= num_rb_pipes)
1108 WREG32(PA_SC_RASTER_CONFIG, data);
1110 gfx_v6_0_write_harvested_raster_configs(adev, data,
1111 adev->gfx.config.backend_enable_mask,
1114 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1115 mutex_unlock(&adev->grbm_idx_mutex);
1118 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1123 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1127 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1128 data &= INACTIVE_CUS_MASK;
1129 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1131 data >>= INACTIVE_CUS_SHIFT;
1133 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1135 return ~data & mask;
1139 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1140 u32 se_num, u32 sh_per_se,
1147 mutex_lock(&adev->grbm_idx_mutex);
1148 for (i = 0; i < se_num; i++) {
1149 for (j = 0; j < sh_per_se; j++) {
1150 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1151 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1152 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1155 for (k = 0; k < 16; k++) {
1157 if (active_cu & mask) {
1159 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1165 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1166 mutex_unlock(&adev->grbm_idx_mutex);
1169 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1171 u32 gb_addr_config = 0;
1172 u32 mc_shared_chmap, mc_arb_ramcfg;
1174 u32 hdp_host_path_cntl;
1177 switch (adev->asic_type) {
1179 adev->gfx.config.max_shader_engines = 2;
1180 adev->gfx.config.max_tile_pipes = 12;
1181 adev->gfx.config.max_cu_per_sh = 8;
1182 adev->gfx.config.max_sh_per_se = 2;
1183 adev->gfx.config.max_backends_per_se = 4;
1184 adev->gfx.config.max_texture_channel_caches = 12;
1185 adev->gfx.config.max_gprs = 256;
1186 adev->gfx.config.max_gs_threads = 32;
1187 adev->gfx.config.max_hw_contexts = 8;
1189 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1190 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1191 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1192 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1193 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1196 adev->gfx.config.max_shader_engines = 2;
1197 adev->gfx.config.max_tile_pipes = 8;
1198 adev->gfx.config.max_cu_per_sh = 5;
1199 adev->gfx.config.max_sh_per_se = 2;
1200 adev->gfx.config.max_backends_per_se = 4;
1201 adev->gfx.config.max_texture_channel_caches = 8;
1202 adev->gfx.config.max_gprs = 256;
1203 adev->gfx.config.max_gs_threads = 32;
1204 adev->gfx.config.max_hw_contexts = 8;
1206 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1207 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1208 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1209 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1210 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1214 adev->gfx.config.max_shader_engines = 1;
1215 adev->gfx.config.max_tile_pipes = 4;
1216 adev->gfx.config.max_cu_per_sh = 5;
1217 adev->gfx.config.max_sh_per_se = 2;
1218 adev->gfx.config.max_backends_per_se = 4;
1219 adev->gfx.config.max_texture_channel_caches = 4;
1220 adev->gfx.config.max_gprs = 256;
1221 adev->gfx.config.max_gs_threads = 32;
1222 adev->gfx.config.max_hw_contexts = 8;
1224 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1225 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1226 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1227 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1228 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1231 adev->gfx.config.max_shader_engines = 1;
1232 adev->gfx.config.max_tile_pipes = 4;
1233 adev->gfx.config.max_cu_per_sh = 6;
1234 adev->gfx.config.max_sh_per_se = 1;
1235 adev->gfx.config.max_backends_per_se = 2;
1236 adev->gfx.config.max_texture_channel_caches = 4;
1237 adev->gfx.config.max_gprs = 256;
1238 adev->gfx.config.max_gs_threads = 16;
1239 adev->gfx.config.max_hw_contexts = 8;
1241 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1242 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1243 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1244 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1245 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1248 adev->gfx.config.max_shader_engines = 1;
1249 adev->gfx.config.max_tile_pipes = 4;
1250 adev->gfx.config.max_cu_per_sh = 5;
1251 adev->gfx.config.max_sh_per_se = 1;
1252 adev->gfx.config.max_backends_per_se = 1;
1253 adev->gfx.config.max_texture_channel_caches = 2;
1254 adev->gfx.config.max_gprs = 256;
1255 adev->gfx.config.max_gs_threads = 16;
1256 adev->gfx.config.max_hw_contexts = 8;
1258 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1259 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1260 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1261 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1262 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1269 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1270 WREG32(SRBM_INT_CNTL, 1);
1271 WREG32(SRBM_INT_ACK, 1);
1273 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1275 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1276 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1278 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1279 adev->gfx.config.mem_max_burst_length_bytes = 256;
1280 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1281 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1282 if (adev->gfx.config.mem_row_size_in_kb > 4)
1283 adev->gfx.config.mem_row_size_in_kb = 4;
1284 adev->gfx.config.shader_engine_tile_size = 32;
1285 adev->gfx.config.num_gpus = 1;
1286 adev->gfx.config.multi_gpu_tile_size = 64;
1288 gb_addr_config &= ~ROW_SIZE_MASK;
1289 switch (adev->gfx.config.mem_row_size_in_kb) {
1292 gb_addr_config |= ROW_SIZE(0);
1295 gb_addr_config |= ROW_SIZE(1);
1298 gb_addr_config |= ROW_SIZE(2);
1301 adev->gfx.config.gb_addr_config = gb_addr_config;
1303 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1304 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1305 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1306 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1307 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1308 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1310 if (adev->has_uvd) {
1311 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1312 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1313 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1316 gfx_v6_0_tiling_mode_table_init(adev);
1318 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1319 adev->gfx.config.max_sh_per_se,
1320 adev->gfx.config.max_backends_per_se);
1322 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1323 adev->gfx.config.max_sh_per_se,
1324 adev->gfx.config.max_cu_per_sh);
1326 gfx_v6_0_get_cu_info(adev);
1328 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1329 ROQ_IB2_START(0x2b)));
1330 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1332 sx_debug_1 = RREG32(SX_DEBUG_1);
1333 WREG32(SX_DEBUG_1, sx_debug_1);
1335 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1337 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1338 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1339 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1340 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1342 WREG32(VGT_NUM_INSTANCES, 1);
1343 WREG32(CP_PERFMON_CNTL, 0);
1344 WREG32(SQ_CONFIG, 0);
1345 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1346 FORCE_EOV_MAX_REZ_CNT(255)));
1348 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1349 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1351 WREG32(VGT_GS_VERTEX_REUSE, 16);
1352 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1354 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1355 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1356 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1357 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1358 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1359 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1360 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1361 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1363 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1364 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1366 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1372 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1376 adev->gfx.scratch.num_reg = 7;
1377 adev->gfx.scratch.reg_base = SCRATCH_REG0;
1378 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1379 adev->gfx.scratch.free[i] = true;
1380 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1384 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1386 struct amdgpu_device *adev = ring->adev;
1392 r = amdgpu_gfx_scratch_get(adev, &scratch);
1394 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1397 WREG32(scratch, 0xCAFEDEAD);
1399 r = amdgpu_ring_alloc(ring, 3);
1401 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1402 amdgpu_gfx_scratch_free(adev, scratch);
1405 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1406 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1407 amdgpu_ring_write(ring, 0xDEADBEEF);
1408 amdgpu_ring_commit(ring);
1410 for (i = 0; i < adev->usec_timeout; i++) {
1411 tmp = RREG32(scratch);
1412 if (tmp == 0xDEADBEEF)
1416 if (i < adev->usec_timeout) {
1417 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1419 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1420 ring->idx, scratch, tmp);
1423 amdgpu_gfx_scratch_free(adev, scratch);
1427 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1429 /* flush hdp cache */
1430 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1431 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1432 WRITE_DATA_DST_SEL(0)));
1433 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1434 amdgpu_ring_write(ring, 0);
1435 amdgpu_ring_write(ring, 0x1);
1439 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1441 * @adev: amdgpu_device pointer
1442 * @ridx: amdgpu ring index
1444 * Emits an hdp invalidate on the cp.
1446 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1448 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1449 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1450 WRITE_DATA_DST_SEL(0)));
1451 amdgpu_ring_write(ring, HDP_DEBUG0);
1452 amdgpu_ring_write(ring, 0);
1453 amdgpu_ring_write(ring, 0x1);
1456 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1457 u64 seq, unsigned flags)
1459 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1460 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1461 /* flush read cache over gart */
1462 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1463 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1464 amdgpu_ring_write(ring, 0);
1465 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1466 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1467 PACKET3_TC_ACTION_ENA |
1468 PACKET3_SH_KCACHE_ACTION_ENA |
1469 PACKET3_SH_ICACHE_ACTION_ENA);
1470 amdgpu_ring_write(ring, 0xFFFFFFFF);
1471 amdgpu_ring_write(ring, 0);
1472 amdgpu_ring_write(ring, 10); /* poll interval */
1473 /* EVENT_WRITE_EOP - flush caches, send int */
1474 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1475 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1476 amdgpu_ring_write(ring, addr & 0xfffffffc);
1477 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1478 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1479 amdgpu_ring_write(ring, lower_32_bits(seq));
1480 amdgpu_ring_write(ring, upper_32_bits(seq));
1483 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1484 struct amdgpu_ib *ib,
1485 unsigned vm_id, bool ctx_switch)
1487 u32 header, control = 0;
1489 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1491 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1492 amdgpu_ring_write(ring, 0);
1495 if (ib->flags & AMDGPU_IB_FLAG_CE)
1496 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1498 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1500 control |= ib->length_dw | (vm_id << 24);
1502 amdgpu_ring_write(ring, header);
1503 amdgpu_ring_write(ring,
1507 (ib->gpu_addr & 0xFFFFFFFC));
1508 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1509 amdgpu_ring_write(ring, control);
1513 * gfx_v6_0_ring_test_ib - basic ring IB test
1515 * @ring: amdgpu_ring structure holding ring information
1517 * Allocate an IB and execute it on the gfx ring (SI).
1518 * Provides a basic gfx ring test to verify that IBs are working.
1519 * Returns 0 on success, error on failure.
1521 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1523 struct amdgpu_device *adev = ring->adev;
1524 struct amdgpu_ib ib;
1525 struct fence *f = NULL;
1530 r = amdgpu_gfx_scratch_get(adev, &scratch);
1532 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1535 WREG32(scratch, 0xCAFEDEAD);
1536 memset(&ib, 0, sizeof(ib));
1537 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1539 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1542 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1543 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1544 ib.ptr[2] = 0xDEADBEEF;
1547 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1551 r = fence_wait_timeout(f, false, timeout);
1553 DRM_ERROR("amdgpu: IB test timed out\n");
1557 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1560 tmp = RREG32(scratch);
1561 if (tmp == 0xDEADBEEF) {
1562 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1565 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1571 amdgpu_ib_free(adev, &ib, NULL);
1574 amdgpu_gfx_scratch_free(adev, scratch);
1578 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1582 WREG32(CP_ME_CNTL, 0);
1584 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1585 WREG32(SCRATCH_UMSK, 0);
1586 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1587 adev->gfx.gfx_ring[i].ready = false;
1588 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1589 adev->gfx.compute_ring[i].ready = false;
1594 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1597 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1598 const struct gfx_firmware_header_v1_0 *ce_hdr;
1599 const struct gfx_firmware_header_v1_0 *me_hdr;
1600 const __le32 *fw_data;
1603 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1606 gfx_v6_0_cp_gfx_enable(adev, false);
1607 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1608 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1609 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1611 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1612 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1613 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1616 fw_data = (const __le32 *)
1617 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1618 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1619 WREG32(CP_PFP_UCODE_ADDR, 0);
1620 for (i = 0; i < fw_size; i++)
1621 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1622 WREG32(CP_PFP_UCODE_ADDR, 0);
1625 fw_data = (const __le32 *)
1626 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1627 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1628 WREG32(CP_CE_UCODE_ADDR, 0);
1629 for (i = 0; i < fw_size; i++)
1630 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1631 WREG32(CP_CE_UCODE_ADDR, 0);
1634 fw_data = (const __be32 *)
1635 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1636 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1637 WREG32(CP_ME_RAM_WADDR, 0);
1638 for (i = 0; i < fw_size; i++)
1639 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1640 WREG32(CP_ME_RAM_WADDR, 0);
1643 WREG32(CP_PFP_UCODE_ADDR, 0);
1644 WREG32(CP_CE_UCODE_ADDR, 0);
1645 WREG32(CP_ME_RAM_WADDR, 0);
1646 WREG32(CP_ME_RAM_RADDR, 0);
1650 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1652 const struct cs_section_def *sect = NULL;
1653 const struct cs_extent_def *ext = NULL;
1654 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1657 r = amdgpu_ring_alloc(ring, 7 + 4);
1659 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1662 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1663 amdgpu_ring_write(ring, 0x1);
1664 amdgpu_ring_write(ring, 0x0);
1665 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1666 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1667 amdgpu_ring_write(ring, 0);
1668 amdgpu_ring_write(ring, 0);
1670 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1671 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1672 amdgpu_ring_write(ring, 0xc000);
1673 amdgpu_ring_write(ring, 0xe000);
1674 amdgpu_ring_commit(ring);
1676 gfx_v6_0_cp_gfx_enable(adev, true);
1678 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1680 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1684 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1685 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1687 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1688 for (ext = sect->section; ext->extent != NULL; ++ext) {
1689 if (sect->id == SECT_CONTEXT) {
1690 amdgpu_ring_write(ring,
1691 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1692 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1693 for (i = 0; i < ext->reg_count; i++)
1694 amdgpu_ring_write(ring, ext->extent[i]);
1699 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1700 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1702 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1703 amdgpu_ring_write(ring, 0);
1705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1706 amdgpu_ring_write(ring, 0x00000316);
1707 amdgpu_ring_write(ring, 0x0000000e);
1708 amdgpu_ring_write(ring, 0x00000010);
1710 amdgpu_ring_commit(ring);
1715 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1717 struct amdgpu_ring *ring;
1723 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1724 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1726 /* Set the write pointer delay */
1727 WREG32(CP_RB_WPTR_DELAY, 0);
1729 WREG32(CP_DEBUG, 0);
1730 WREG32(SCRATCH_ADDR, 0);
1732 /* ring 0 - compute and gfx */
1733 /* Set ring buffer size */
1734 ring = &adev->gfx.gfx_ring[0];
1735 rb_bufsz = order_base_2(ring->ring_size / 8);
1736 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1739 tmp |= BUF_SWAP_32BIT;
1741 WREG32(CP_RB0_CNTL, tmp);
1743 /* Initialize the ring buffer's read and write pointers */
1744 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1746 WREG32(CP_RB0_WPTR, ring->wptr);
1748 /* set the wb address whether it's enabled or not */
1749 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1750 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1751 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1753 WREG32(SCRATCH_UMSK, 0);
1756 WREG32(CP_RB0_CNTL, tmp);
1758 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1760 /* start the rings */
1761 gfx_v6_0_cp_gfx_start(adev);
1763 r = amdgpu_ring_test_ring(ring);
1765 ring->ready = false;
1772 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
1774 return ring->adev->wb.wb[ring->rptr_offs];
1777 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1779 struct amdgpu_device *adev = ring->adev;
1781 if (ring == &adev->gfx.gfx_ring[0])
1782 return RREG32(CP_RB0_WPTR);
1783 else if (ring == &adev->gfx.compute_ring[0])
1784 return RREG32(CP_RB1_WPTR);
1785 else if (ring == &adev->gfx.compute_ring[1])
1786 return RREG32(CP_RB2_WPTR);
1791 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1793 struct amdgpu_device *adev = ring->adev;
1795 WREG32(CP_RB0_WPTR, ring->wptr);
1796 (void)RREG32(CP_RB0_WPTR);
1799 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1801 struct amdgpu_device *adev = ring->adev;
1803 if (ring == &adev->gfx.compute_ring[0]) {
1804 WREG32(CP_RB1_WPTR, ring->wptr);
1805 (void)RREG32(CP_RB1_WPTR);
1806 } else if (ring == &adev->gfx.compute_ring[1]) {
1807 WREG32(CP_RB2_WPTR, ring->wptr);
1808 (void)RREG32(CP_RB2_WPTR);
1815 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1817 struct amdgpu_ring *ring;
1823 /* ring1 - compute only */
1824 /* Set ring buffer size */
1826 ring = &adev->gfx.compute_ring[0];
1827 rb_bufsz = order_base_2(ring->ring_size / 8);
1828 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1830 tmp |= BUF_SWAP_32BIT;
1832 WREG32(CP_RB1_CNTL, tmp);
1834 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1836 WREG32(CP_RB1_WPTR, ring->wptr);
1838 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1839 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1840 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1843 WREG32(CP_RB1_CNTL, tmp);
1844 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1846 ring = &adev->gfx.compute_ring[1];
1847 rb_bufsz = order_base_2(ring->ring_size / 8);
1848 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1850 tmp |= BUF_SWAP_32BIT;
1852 WREG32(CP_RB2_CNTL, tmp);
1854 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1856 WREG32(CP_RB2_WPTR, ring->wptr);
1857 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1858 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1859 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1862 WREG32(CP_RB2_CNTL, tmp);
1863 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1865 adev->gfx.compute_ring[0].ready = true;
1866 adev->gfx.compute_ring[1].ready = true;
1868 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1870 adev->gfx.compute_ring[0].ready = false;
1874 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1876 adev->gfx.compute_ring[1].ready = false;
1883 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1885 gfx_v6_0_cp_gfx_enable(adev, enable);
1888 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1890 return gfx_v6_0_cp_gfx_load_microcode(adev);
1893 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1896 u32 tmp = RREG32(CP_INT_CNTL_RING0);
1901 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1903 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1904 WREG32(CP_INT_CNTL_RING0, tmp);
1907 /* read a gfx register */
1908 tmp = RREG32(DB_DEPTH_INFO);
1910 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1911 for (i = 0; i < adev->usec_timeout; i++) {
1912 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1919 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1923 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1925 r = gfx_v6_0_cp_load_microcode(adev);
1929 r = gfx_v6_0_cp_gfx_resume(adev);
1932 r = gfx_v6_0_cp_compute_resume(adev);
1936 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1941 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1943 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1944 uint32_t seq = ring->fence_drv.sync_seq;
1945 uint64_t addr = ring->fence_drv.gpu_addr;
1947 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1948 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1949 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1950 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1951 amdgpu_ring_write(ring, addr & 0xfffffffc);
1952 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1953 amdgpu_ring_write(ring, seq);
1954 amdgpu_ring_write(ring, 0xffffffff);
1955 amdgpu_ring_write(ring, 4); /* poll interval */
1958 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1959 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1960 amdgpu_ring_write(ring, 0);
1961 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1962 amdgpu_ring_write(ring, 0);
1966 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1967 unsigned vm_id, uint64_t pd_addr)
1969 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1971 /* write new base address */
1972 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1973 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1974 WRITE_DATA_DST_SEL(0)));
1976 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1978 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1980 amdgpu_ring_write(ring, 0);
1981 amdgpu_ring_write(ring, pd_addr >> 12);
1983 /* bits 0-15 are the VM contexts0-15 */
1984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1986 WRITE_DATA_DST_SEL(0)));
1987 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1988 amdgpu_ring_write(ring, 0);
1989 amdgpu_ring_write(ring, 1 << vm_id);
1991 /* wait for the invalidate to complete */
1992 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1993 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1994 WAIT_REG_MEM_ENGINE(0))); /* me */
1995 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1996 amdgpu_ring_write(ring, 0);
1997 amdgpu_ring_write(ring, 0); /* ref */
1998 amdgpu_ring_write(ring, 0); /* mask */
1999 amdgpu_ring_write(ring, 0x20); /* poll interval */
2002 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2003 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2004 amdgpu_ring_write(ring, 0x0);
2006 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2007 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2008 amdgpu_ring_write(ring, 0);
2009 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2010 amdgpu_ring_write(ring, 0);
2015 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2019 if (adev->gfx.rlc.save_restore_obj) {
2020 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2021 if (unlikely(r != 0))
2022 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2023 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2024 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2026 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2027 adev->gfx.rlc.save_restore_obj = NULL;
2030 if (adev->gfx.rlc.clear_state_obj) {
2031 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2032 if (unlikely(r != 0))
2033 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2034 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2035 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2037 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2038 adev->gfx.rlc.clear_state_obj = NULL;
2041 if (adev->gfx.rlc.cp_table_obj) {
2042 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2043 if (unlikely(r != 0))
2044 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2045 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2046 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2048 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2049 adev->gfx.rlc.cp_table_obj = NULL;
2053 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2056 volatile u32 *dst_ptr;
2058 u64 reg_list_mc_addr;
2059 const struct cs_section_def *cs_data;
2062 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2063 adev->gfx.rlc.reg_list_size =
2064 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2066 adev->gfx.rlc.cs_data = si_cs_data;
2067 src_ptr = adev->gfx.rlc.reg_list;
2068 dws = adev->gfx.rlc.reg_list_size;
2069 cs_data = adev->gfx.rlc.cs_data;
2072 /* save restore block */
2073 if (adev->gfx.rlc.save_restore_obj == NULL) {
2075 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2076 AMDGPU_GEM_DOMAIN_VRAM,
2077 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2079 &adev->gfx.rlc.save_restore_obj);
2082 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2087 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2088 if (unlikely(r != 0)) {
2089 gfx_v6_0_rlc_fini(adev);
2092 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2093 &adev->gfx.rlc.save_restore_gpu_addr);
2095 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2096 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2097 gfx_v6_0_rlc_fini(adev);
2101 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2103 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2104 gfx_v6_0_rlc_fini(adev);
2107 /* write the sr buffer */
2108 dst_ptr = adev->gfx.rlc.sr_ptr;
2109 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2110 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2111 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2112 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2116 /* clear state block */
2117 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2118 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2120 if (adev->gfx.rlc.clear_state_obj == NULL) {
2121 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2122 AMDGPU_GEM_DOMAIN_VRAM,
2123 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2125 &adev->gfx.rlc.clear_state_obj);
2128 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2129 gfx_v6_0_rlc_fini(adev);
2133 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2134 if (unlikely(r != 0)) {
2135 gfx_v6_0_rlc_fini(adev);
2138 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2139 &adev->gfx.rlc.clear_state_gpu_addr);
2141 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2142 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2143 gfx_v6_0_rlc_fini(adev);
2147 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2149 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2150 gfx_v6_0_rlc_fini(adev);
2153 /* set up the cs buffer */
2154 dst_ptr = adev->gfx.rlc.cs_ptr;
2155 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2156 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2157 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2158 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2159 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2160 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2161 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2167 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2171 tmp = RREG32(RLC_LB_CNTL);
2173 tmp |= LOAD_BALANCE_ENABLE;
2175 tmp &= ~LOAD_BALANCE_ENABLE;
2176 WREG32(RLC_LB_CNTL, tmp);
2179 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2180 WREG32(SPI_LB_CU_MASK, 0x00ff);
2185 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2189 for (i = 0; i < adev->usec_timeout; i++) {
2190 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2195 for (i = 0; i < adev->usec_timeout; i++) {
2196 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2202 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2206 tmp = RREG32(RLC_CNTL);
2208 WREG32(RLC_CNTL, rlc);
2211 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2215 orig = data = RREG32(RLC_CNTL);
2217 if (data & RLC_ENABLE) {
2218 data &= ~RLC_ENABLE;
2219 WREG32(RLC_CNTL, data);
2221 gfx_v6_0_wait_for_rlc_serdes(adev);
2227 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2229 WREG32(RLC_CNTL, 0);
2231 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2232 gfx_v6_0_wait_for_rlc_serdes(adev);
2235 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2237 WREG32(RLC_CNTL, RLC_ENABLE);
2239 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2244 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2246 u32 tmp = RREG32(GRBM_SOFT_RESET);
2248 tmp |= SOFT_RESET_RLC;
2249 WREG32(GRBM_SOFT_RESET, tmp);
2251 tmp &= ~SOFT_RESET_RLC;
2252 WREG32(GRBM_SOFT_RESET, tmp);
2256 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2260 /* Enable LBPW only for DDR3 */
2261 tmp = RREG32(MC_SEQ_MISC0);
2262 if ((tmp & 0xF0000000) == 0xB0000000)
2266 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2270 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2273 const struct rlc_firmware_header_v1_0 *hdr;
2274 const __le32 *fw_data;
2278 if (!adev->gfx.rlc_fw)
2281 gfx_v6_0_rlc_stop(adev);
2282 gfx_v6_0_rlc_reset(adev);
2283 gfx_v6_0_init_pg(adev);
2284 gfx_v6_0_init_cg(adev);
2286 WREG32(RLC_RL_BASE, 0);
2287 WREG32(RLC_RL_SIZE, 0);
2288 WREG32(RLC_LB_CNTL, 0);
2289 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2290 WREG32(RLC_LB_CNTR_INIT, 0);
2291 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2293 WREG32(RLC_MC_CNTL, 0);
2294 WREG32(RLC_UCODE_CNTL, 0);
2296 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2297 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2298 fw_data = (const __le32 *)
2299 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2301 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2303 for (i = 0; i < fw_size; i++) {
2304 WREG32(RLC_UCODE_ADDR, i);
2305 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2307 WREG32(RLC_UCODE_ADDR, 0);
2309 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2310 gfx_v6_0_rlc_start(adev);
2315 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2317 u32 data, orig, tmp;
2319 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2322 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2324 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2326 tmp = gfx_v6_0_halt_rlc(adev);
2328 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2329 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2330 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2332 gfx_v6_0_wait_for_rlc_serdes(adev);
2333 gfx_v6_0_update_rlc(adev, tmp);
2335 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2337 data |= CGCG_EN | CGLS_EN;
2339 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2341 RREG32(CB_CGTT_SCLK_CTRL);
2342 RREG32(CB_CGTT_SCLK_CTRL);
2343 RREG32(CB_CGTT_SCLK_CTRL);
2344 RREG32(CB_CGTT_SCLK_CTRL);
2346 data &= ~(CGCG_EN | CGLS_EN);
2350 WREG32(RLC_CGCG_CGLS_CTRL, data);
2354 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2357 u32 data, orig, tmp = 0;
2359 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2360 orig = data = RREG32(CGTS_SM_CTRL_REG);
2363 WREG32(CGTS_SM_CTRL_REG, data);
2365 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2366 orig = data = RREG32(CP_MEM_SLP_CNTL);
2367 data |= CP_MEM_LS_EN;
2369 WREG32(CP_MEM_SLP_CNTL, data);
2372 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2375 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2377 tmp = gfx_v6_0_halt_rlc(adev);
2379 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2380 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2381 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2383 gfx_v6_0_update_rlc(adev, tmp);
2385 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2388 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2390 data = RREG32(CP_MEM_SLP_CNTL);
2391 if (data & CP_MEM_LS_EN) {
2392 data &= ~CP_MEM_LS_EN;
2393 WREG32(CP_MEM_SLP_CNTL, data);
2395 orig = data = RREG32(CGTS_SM_CTRL_REG);
2396 data |= LS_OVERRIDE | OVERRIDE;
2398 WREG32(CGTS_SM_CTRL_REG, data);
2400 tmp = gfx_v6_0_halt_rlc(adev);
2402 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2403 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2404 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2406 gfx_v6_0_update_rlc(adev, tmp);
2410 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2413 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2415 gfx_v6_0_enable_mgcg(adev, true);
2416 gfx_v6_0_enable_cgcg(adev, true);
2418 gfx_v6_0_enable_cgcg(adev, false);
2419 gfx_v6_0_enable_mgcg(adev, false);
2421 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2424 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2429 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2434 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2438 orig = data = RREG32(RLC_PG_CNTL);
2439 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2444 WREG32(RLC_PG_CNTL, data);
2447 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2451 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2453 const __le32 *fw_data;
2454 volatile u32 *dst_ptr;
2455 int me, i, max_me = 4;
2457 u32 table_offset, table_size;
2459 if (adev->asic_type == CHIP_KAVERI)
2462 if (adev->gfx.rlc.cp_table_ptr == NULL)
2465 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2466 for (me = 0; me < max_me; me++) {
2468 const struct gfx_firmware_header_v1_0 *hdr =
2469 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2470 fw_data = (const __le32 *)
2471 (adev->gfx.ce_fw->data +
2472 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2473 table_offset = le32_to_cpu(hdr->jt_offset);
2474 table_size = le32_to_cpu(hdr->jt_size);
2475 } else if (me == 1) {
2476 const struct gfx_firmware_header_v1_0 *hdr =
2477 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2478 fw_data = (const __le32 *)
2479 (adev->gfx.pfp_fw->data +
2480 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2481 table_offset = le32_to_cpu(hdr->jt_offset);
2482 table_size = le32_to_cpu(hdr->jt_size);
2483 } else if (me == 2) {
2484 const struct gfx_firmware_header_v1_0 *hdr =
2485 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2486 fw_data = (const __le32 *)
2487 (adev->gfx.me_fw->data +
2488 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2489 table_offset = le32_to_cpu(hdr->jt_offset);
2490 table_size = le32_to_cpu(hdr->jt_size);
2491 } else if (me == 3) {
2492 const struct gfx_firmware_header_v1_0 *hdr =
2493 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2494 fw_data = (const __le32 *)
2495 (adev->gfx.mec_fw->data +
2496 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2497 table_offset = le32_to_cpu(hdr->jt_offset);
2498 table_size = le32_to_cpu(hdr->jt_size);
2500 const struct gfx_firmware_header_v1_0 *hdr =
2501 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2502 fw_data = (const __le32 *)
2503 (adev->gfx.mec2_fw->data +
2504 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2505 table_offset = le32_to_cpu(hdr->jt_offset);
2506 table_size = le32_to_cpu(hdr->jt_size);
2509 for (i = 0; i < table_size; i ++) {
2510 dst_ptr[bo_offset + i] =
2511 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2514 bo_offset += table_size;
2518 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2524 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2525 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2526 WREG32(RLC_TTOP_D, tmp);
2528 tmp = RREG32(RLC_PG_CNTL);
2529 tmp |= GFX_PG_ENABLE;
2530 WREG32(RLC_PG_CNTL, tmp);
2532 tmp = RREG32(RLC_AUTO_PG_CTRL);
2534 WREG32(RLC_AUTO_PG_CTRL, tmp);
2536 tmp = RREG32(RLC_AUTO_PG_CTRL);
2538 WREG32(RLC_AUTO_PG_CTRL, tmp);
2540 tmp = RREG32(DB_RENDER_CONTROL);
2544 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2548 u32 mask = 0, tmp, tmp1;
2551 mutex_lock(&adev->grbm_idx_mutex);
2552 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2553 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2554 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2555 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2556 mutex_unlock(&adev->grbm_idx_mutex);
2563 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2568 return (~tmp) & mask;
2571 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2573 u32 i, j, k, active_cu_number = 0;
2575 u32 mask, counter, cu_bitmap;
2578 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2579 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2583 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2584 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2592 active_cu_number += counter;
2593 tmp |= (cu_bitmap << (i * 16 + j * 8));
2597 WREG32(RLC_PG_AO_CU_MASK, tmp);
2599 tmp = RREG32(RLC_MAX_PG_CU);
2600 tmp &= ~MAX_PU_CU_MASK;
2601 tmp |= MAX_PU_CU(active_cu_number);
2602 WREG32(RLC_MAX_PG_CU, tmp);
2605 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2610 orig = data = RREG32(RLC_PG_CNTL);
2611 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2612 data |= STATIC_PER_CU_PG_ENABLE;
2614 data &= ~STATIC_PER_CU_PG_ENABLE;
2616 WREG32(RLC_PG_CNTL, data);
2619 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2624 orig = data = RREG32(RLC_PG_CNTL);
2625 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2626 data |= DYN_PER_CU_PG_ENABLE;
2628 data &= ~DYN_PER_CU_PG_ENABLE;
2630 WREG32(RLC_PG_CNTL, data);
2633 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2637 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2639 tmp = RREG32(RLC_PG_CNTL);
2641 WREG32(RLC_PG_CNTL, tmp);
2643 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2645 tmp = RREG32(RLC_AUTO_PG_CTRL);
2647 tmp &= ~GRBM_REG_SGIT_MASK;
2648 tmp |= GRBM_REG_SGIT(0x700);
2649 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2650 WREG32(RLC_AUTO_PG_CTRL, tmp);
2653 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2655 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2656 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2657 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2660 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2663 const struct cs_section_def *sect = NULL;
2664 const struct cs_extent_def *ext = NULL;
2666 if (adev->gfx.rlc.cs_data == NULL)
2669 /* begin clear state */
2671 /* context control state */
2674 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2675 for (ext = sect->section; ext->extent != NULL; ++ext) {
2676 if (sect->id == SECT_CONTEXT)
2677 count += 2 + ext->reg_count;
2682 /* pa_sc_raster_config */
2684 /* end clear state */
2692 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2693 volatile u32 *buffer)
2696 const struct cs_section_def *sect = NULL;
2697 const struct cs_extent_def *ext = NULL;
2699 if (adev->gfx.rlc.cs_data == NULL)
2704 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2705 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2708 buffer[count++] = cpu_to_le32(0x80000000);
2709 buffer[count++] = cpu_to_le32(0x80000000);
2711 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2712 for (ext = sect->section; ext->extent != NULL; ++ext) {
2713 if (sect->id == SECT_CONTEXT) {
2715 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2716 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2717 for (i = 0; i < ext->reg_count; i++)
2718 buffer[count++] = cpu_to_le32(ext->extent[i]);
2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2726 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2728 switch (adev->asic_type) {
2731 buffer[count++] = cpu_to_le32(0x2a00126a);
2734 buffer[count++] = cpu_to_le32(0x0000124a);
2737 buffer[count++] = cpu_to_le32(0x00000082);
2740 buffer[count++] = cpu_to_le32(0x00000000);
2743 buffer[count++] = cpu_to_le32(0x00000000);
2747 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2748 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2750 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2751 buffer[count++] = cpu_to_le32(0);
2754 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2756 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2757 AMD_PG_SUPPORT_GFX_SMG |
2758 AMD_PG_SUPPORT_GFX_DMG |
2760 AMD_PG_SUPPORT_GDS |
2761 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2762 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2763 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2764 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2765 gfx_v6_0_init_gfx_cgpg(adev);
2766 gfx_v6_0_enable_cp_pg(adev, true);
2767 gfx_v6_0_enable_gds_pg(adev, true);
2769 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2770 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2773 gfx_v6_0_init_ao_cu_mask(adev);
2774 gfx_v6_0_update_gfx_pg(adev, true);
2777 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2778 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2782 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2784 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2785 AMD_PG_SUPPORT_GFX_SMG |
2786 AMD_PG_SUPPORT_GFX_DMG |
2788 AMD_PG_SUPPORT_GDS |
2789 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2790 gfx_v6_0_update_gfx_pg(adev, false);
2791 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2792 gfx_v6_0_enable_cp_pg(adev, false);
2793 gfx_v6_0_enable_gds_pg(adev, false);
2798 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2802 mutex_lock(&adev->gfx.gpu_clock_mutex);
2803 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2804 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2805 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2806 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2810 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2812 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2813 amdgpu_ring_write(ring, 0x80000000);
2814 amdgpu_ring_write(ring, 0);
2817 static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
2820 6; /* gfx_v6_0_ring_emit_ib */
2823 static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
2826 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2827 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2828 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2829 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
2830 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
2831 3; /* gfx_v6_ring_emit_cntxcntl */
2834 static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
2837 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2838 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2839 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
2840 17 + /* gfx_v6_0_ring_emit_vm_flush */
2841 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2844 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2845 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2846 .select_se_sh = &gfx_v6_0_select_se_sh,
2849 static int gfx_v6_0_early_init(void *handle)
2851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2853 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2854 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2855 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2856 gfx_v6_0_set_ring_funcs(adev);
2857 gfx_v6_0_set_irq_funcs(adev);
2862 static int gfx_v6_0_sw_init(void *handle)
2864 struct amdgpu_ring *ring;
2865 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2868 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2872 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2876 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2880 gfx_v6_0_scratch_init(adev);
2882 r = gfx_v6_0_init_microcode(adev);
2884 DRM_ERROR("Failed to load gfx firmware!\n");
2888 r = gfx_v6_0_rlc_init(adev);
2890 DRM_ERROR("Failed to init rlc BOs!\n");
2894 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2895 ring = &adev->gfx.gfx_ring[i];
2896 ring->ring_obj = NULL;
2897 sprintf(ring->name, "gfx");
2898 r = amdgpu_ring_init(adev, ring, 1024,
2900 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2901 AMDGPU_RING_TYPE_GFX);
2906 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2909 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2910 DRM_ERROR("Too many (%d) compute rings!\n", i);
2913 ring = &adev->gfx.compute_ring[i];
2914 ring->ring_obj = NULL;
2915 ring->use_doorbell = false;
2916 ring->doorbell_index = 0;
2920 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2921 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2922 r = amdgpu_ring_init(adev, ring, 1024,
2924 &adev->gfx.eop_irq, irq_type,
2925 AMDGPU_RING_TYPE_COMPUTE);
2933 static int gfx_v6_0_sw_fini(void *handle)
2936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2938 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2939 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2940 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2942 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2943 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2944 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2945 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2947 gfx_v6_0_rlc_fini(adev);
2952 static int gfx_v6_0_hw_init(void *handle)
2955 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2957 gfx_v6_0_gpu_init(adev);
2959 r = gfx_v6_0_rlc_resume(adev);
2963 r = gfx_v6_0_cp_resume(adev);
2967 adev->gfx.ce_ram_size = 0x8000;
2972 static int gfx_v6_0_hw_fini(void *handle)
2974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2976 gfx_v6_0_cp_enable(adev, false);
2977 gfx_v6_0_rlc_stop(adev);
2978 gfx_v6_0_fini_pg(adev);
2983 static int gfx_v6_0_suspend(void *handle)
2985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2987 return gfx_v6_0_hw_fini(adev);
2990 static int gfx_v6_0_resume(void *handle)
2992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2994 return gfx_v6_0_hw_init(adev);
2997 static bool gfx_v6_0_is_idle(void *handle)
2999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3001 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3007 static int gfx_v6_0_wait_for_idle(void *handle)
3010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3012 for (i = 0; i < adev->usec_timeout; i++) {
3013 if (gfx_v6_0_is_idle(handle))
3020 static int gfx_v6_0_soft_reset(void *handle)
3025 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3026 enum amdgpu_interrupt_state state)
3031 case AMDGPU_IRQ_STATE_DISABLE:
3032 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3033 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3034 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3036 case AMDGPU_IRQ_STATE_ENABLE:
3037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3038 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3039 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3046 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3048 enum amdgpu_interrupt_state state)
3052 case AMDGPU_IRQ_STATE_DISABLE:
3054 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3055 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3056 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3059 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3060 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3061 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3065 case AMDGPU_IRQ_STATE_ENABLE:
3067 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3068 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3069 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3072 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3073 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3074 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3086 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3087 struct amdgpu_irq_src *src,
3089 enum amdgpu_interrupt_state state)
3094 case AMDGPU_IRQ_STATE_DISABLE:
3095 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3096 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3097 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3099 case AMDGPU_IRQ_STATE_ENABLE:
3100 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3101 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3102 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3111 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3112 struct amdgpu_irq_src *src,
3114 enum amdgpu_interrupt_state state)
3119 case AMDGPU_IRQ_STATE_DISABLE:
3120 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3121 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3122 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3124 case AMDGPU_IRQ_STATE_ENABLE:
3125 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3126 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3127 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3136 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3137 struct amdgpu_irq_src *src,
3139 enum amdgpu_interrupt_state state)
3142 case AMDGPU_CP_IRQ_GFX_EOP:
3143 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3145 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3146 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3148 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3149 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3157 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3158 struct amdgpu_irq_src *source,
3159 struct amdgpu_iv_entry *entry)
3161 switch (entry->ring_id) {
3163 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3167 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3175 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3176 struct amdgpu_irq_src *source,
3177 struct amdgpu_iv_entry *entry)
3179 DRM_ERROR("Illegal register access in command stream\n");
3180 schedule_work(&adev->reset_work);
3184 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3185 struct amdgpu_irq_src *source,
3186 struct amdgpu_iv_entry *entry)
3188 DRM_ERROR("Illegal instruction in command stream\n");
3189 schedule_work(&adev->reset_work);
3193 static int gfx_v6_0_set_clockgating_state(void *handle,
3194 enum amd_clockgating_state state)
3197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3199 if (state == AMD_CG_STATE_GATE)
3202 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3204 gfx_v6_0_enable_mgcg(adev, true);
3205 gfx_v6_0_enable_cgcg(adev, true);
3207 gfx_v6_0_enable_cgcg(adev, false);
3208 gfx_v6_0_enable_mgcg(adev, false);
3210 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3215 static int gfx_v6_0_set_powergating_state(void *handle,
3216 enum amd_powergating_state state)
3219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3221 if (state == AMD_PG_STATE_GATE)
3224 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3225 AMD_PG_SUPPORT_GFX_SMG |
3226 AMD_PG_SUPPORT_GFX_DMG |
3228 AMD_PG_SUPPORT_GDS |
3229 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3230 gfx_v6_0_update_gfx_pg(adev, gate);
3231 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3232 gfx_v6_0_enable_cp_pg(adev, gate);
3233 gfx_v6_0_enable_gds_pg(adev, gate);
3240 const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3242 .early_init = gfx_v6_0_early_init,
3244 .sw_init = gfx_v6_0_sw_init,
3245 .sw_fini = gfx_v6_0_sw_fini,
3246 .hw_init = gfx_v6_0_hw_init,
3247 .hw_fini = gfx_v6_0_hw_fini,
3248 .suspend = gfx_v6_0_suspend,
3249 .resume = gfx_v6_0_resume,
3250 .is_idle = gfx_v6_0_is_idle,
3251 .wait_for_idle = gfx_v6_0_wait_for_idle,
3252 .soft_reset = gfx_v6_0_soft_reset,
3253 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3254 .set_powergating_state = gfx_v6_0_set_powergating_state,
3257 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3258 .get_rptr = gfx_v6_0_ring_get_rptr,
3259 .get_wptr = gfx_v6_0_ring_get_wptr,
3260 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3262 .emit_ib = gfx_v6_0_ring_emit_ib,
3263 .emit_fence = gfx_v6_0_ring_emit_fence,
3264 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3265 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3266 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3267 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3268 .test_ring = gfx_v6_0_ring_test_ring,
3269 .test_ib = gfx_v6_0_ring_test_ib,
3270 .insert_nop = amdgpu_ring_insert_nop,
3271 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3272 .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3273 .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx,
3276 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3277 .get_rptr = gfx_v6_0_ring_get_rptr,
3278 .get_wptr = gfx_v6_0_ring_get_wptr,
3279 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3281 .emit_ib = gfx_v6_0_ring_emit_ib,
3282 .emit_fence = gfx_v6_0_ring_emit_fence,
3283 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3284 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3285 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3286 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3287 .test_ring = gfx_v6_0_ring_test_ring,
3288 .test_ib = gfx_v6_0_ring_test_ib,
3289 .insert_nop = amdgpu_ring_insert_nop,
3290 .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3291 .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute,
3294 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3298 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3299 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3300 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3301 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3304 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3305 .set = gfx_v6_0_set_eop_interrupt_state,
3306 .process = gfx_v6_0_eop_irq,
3309 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3310 .set = gfx_v6_0_set_priv_reg_fault_state,
3311 .process = gfx_v6_0_priv_reg_irq,
3314 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3315 .set = gfx_v6_0_set_priv_inst_fault_state,
3316 .process = gfx_v6_0_priv_inst_irq,
3319 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3321 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3322 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3324 adev->gfx.priv_reg_irq.num_types = 1;
3325 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3327 adev->gfx.priv_inst_irq.num_types = 1;
3328 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3331 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3333 int i, j, k, counter, active_cu_number = 0;
3334 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3335 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3337 memset(cu_info, 0, sizeof(*cu_info));
3339 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3340 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3344 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3345 cu_info->bitmap[i][j] = bitmap;
3347 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3348 if (bitmap & mask) {
3355 active_cu_number += counter;
3356 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3360 cu_info->number = active_cu_number;
3361 cu_info->ao_cu_mask = ao_cu_mask;