drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 114
 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 119
 120 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 139
 140 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 142 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 144 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 146 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 148 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 150 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 152
 153 #define mmCPG_PSP_DEBUG                         0x5c10
 154 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 155 #define mmCPC_PSP_DEBUG                         0x5c11
 156 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 159
 160 //CC_GC_SA_UNIT_DISABLE
 161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 165 //GC_USER_SA_UNIT_DISABLE
 166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 170 //PA_SC_ENHANCE_3
 171 #define mmPA_SC_ENHANCE_3                       0x1085
 172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 175
 176 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 178
 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 183
 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 186
 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 189
 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 196
 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 222
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 229
 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 236
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 243
 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 250
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 257
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 264
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 271
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 278
 279 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 320 };
 321
 322 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
 323         /* Pending on emulation bring up */
 324 };
 325
 326 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1379 };
1380
1381 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1420 };
1421
1422 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1468         /* Pending on emulation bring up */
1469 };
1470
1471 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2092 };
2093
2094 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2095         /* Pending on emulation bring up */
2096 };
2097
2098 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3151 };
3152
3153 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3197 };
3198
3199 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3200         /* Pending on emulation bring up */
3201 };
3202
3203 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3245
3246         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3248 };
3249
3250 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3275
3276         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3278 };
3279
3280 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3301 };
3302
3303 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3340 };
3341
3342 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3375 };
3376
3377 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3412 };
3413
3414 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3437 };
3438
3439 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3462 };
3463
3464 #define DEFAULT_SH_MEM_CONFIG \
3465         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3466          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3467          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3468          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3469
3470 /* TODO: pending on golden setting value of gb address config */
3471 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3472
3473 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3474 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3475 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3476 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3477 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3478 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3479                                  struct amdgpu_cu_info *cu_info);
3480 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3481 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3482                                    u32 sh_num, u32 instance, int xcc_id);
3483 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3484
3485 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3486 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3487 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3488 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3489 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3490 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3491 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3492 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3493 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3494 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3495 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3496                                            uint16_t pasid, uint32_t flush_type,
3497                                            bool all_hub, uint8_t dst_sel);
3498 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3499                                                unsigned int vmid);
3500
3501 static int gfx_v10_0_set_powergating_state(void *handle,
3502                                           enum amd_powergating_state state);
3503 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3504 {
3505         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3506         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3507                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3508         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3509         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3510         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3511         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3512         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3513         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3514 }
3515
3516 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3517                                  struct amdgpu_ring *ring)
3518 {
3519         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3520         uint64_t wptr_addr = ring->wptr_gpu_addr;
3521         uint32_t eng_sel = 0;
3522
3523         switch (ring->funcs->type) {
3524         case AMDGPU_RING_TYPE_COMPUTE:
3525                 eng_sel = 0;
3526                 break;
3527         case AMDGPU_RING_TYPE_GFX:
3528                 eng_sel = 4;
3529                 break;
3530         case AMDGPU_RING_TYPE_MES:
3531                 eng_sel = 5;
3532                 break;
3533         default:
3534                 WARN_ON(1);
3535         }
3536
3537         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3538         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3539         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3540                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3541                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3542                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3543                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3544                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3545                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3546                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3547                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3548                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3549         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3550         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3551         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3552         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3553         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3554 }
3555
3556 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3557                                    struct amdgpu_ring *ring,
3558                                    enum amdgpu_unmap_queues_action action,
3559                                    u64 gpu_addr, u64 seq)
3560 {
3561         struct amdgpu_device *adev = kiq_ring->adev;
3562         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3563
3564         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3565                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3566                 return;
3567         }
3568
3569         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3570         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3571                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3572                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3573                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3574                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3575         amdgpu_ring_write(kiq_ring,
3576                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3577
3578         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3579                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3580                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3581                 amdgpu_ring_write(kiq_ring, seq);
3582         } else {
3583                 amdgpu_ring_write(kiq_ring, 0);
3584                 amdgpu_ring_write(kiq_ring, 0);
3585                 amdgpu_ring_write(kiq_ring, 0);
3586         }
3587 }
3588
3589 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3590                                    struct amdgpu_ring *ring,
3591                                    u64 addr,
3592                                    u64 seq)
3593 {
3594         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3595
3596         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3597         amdgpu_ring_write(kiq_ring,
3598                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3599                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3600                           PACKET3_QUERY_STATUS_COMMAND(2));
3601         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3602                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3603                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3604         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3605         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3606         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3607         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3608 }
3609
3610 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3611                                 uint16_t pasid, uint32_t flush_type,
3612                                 bool all_hub)
3613 {
3614         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3615 }
3616
3617 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3618         .kiq_set_resources = gfx10_kiq_set_resources,
3619         .kiq_map_queues = gfx10_kiq_map_queues,
3620         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3621         .kiq_query_status = gfx10_kiq_query_status,
3622         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3623         .set_resources_size = 8,
3624         .map_queues_size = 7,
3625         .unmap_queues_size = 6,
3626         .query_status_size = 7,
3627         .invalidate_tlbs_size = 2,
3628 };
3629
3630 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3631 {
3632         adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3633 }
3634
3635 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3636 {
3637         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3638         case IP_VERSION(10, 1, 10):
3639                 soc15_program_register_sequence(adev,
3640                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3641                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3642                 break;
3643         case IP_VERSION(10, 1, 1):
3644                 soc15_program_register_sequence(adev,
3645                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3646                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3647                 break;
3648         case IP_VERSION(10, 1, 2):
3649                 soc15_program_register_sequence(adev,
3650                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3651                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3659 {
3660         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3661         case IP_VERSION(10, 1, 10):
3662                 soc15_program_register_sequence(adev,
3663                                                 golden_settings_gc_10_1,
3664                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3665                 soc15_program_register_sequence(adev,
3666                                                 golden_settings_gc_10_0_nv10,
3667                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3668                 break;
3669         case IP_VERSION(10, 1, 1):
3670                 soc15_program_register_sequence(adev,
3671                                                 golden_settings_gc_10_1_1,
3672                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3673                 soc15_program_register_sequence(adev,
3674                                                 golden_settings_gc_10_1_nv14,
3675                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3676                 break;
3677         case IP_VERSION(10, 1, 2):
3678                 soc15_program_register_sequence(adev,
3679                                                 golden_settings_gc_10_1_2,
3680                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3681                 soc15_program_register_sequence(adev,
3682                                                 golden_settings_gc_10_1_2_nv12,
3683                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3684                 break;
3685         case IP_VERSION(10, 3, 0):
3686                 soc15_program_register_sequence(adev,
3687                                                 golden_settings_gc_10_3,
3688                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3689                 soc15_program_register_sequence(adev,
3690                                                 golden_settings_gc_10_3_sienna_cichlid,
3691                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3692                 break;
3693         case IP_VERSION(10, 3, 2):
3694                 soc15_program_register_sequence(adev,
3695                                                 golden_settings_gc_10_3_2,
3696                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3697                 break;
3698         case IP_VERSION(10, 3, 1):
3699                 soc15_program_register_sequence(adev,
3700                                                 golden_settings_gc_10_3_vangogh,
3701                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3702                 break;
3703         case IP_VERSION(10, 3, 3):
3704                 soc15_program_register_sequence(adev,
3705                                                 golden_settings_gc_10_3_3,
3706                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3707                 break;
3708         case IP_VERSION(10, 3, 4):
3709                 soc15_program_register_sequence(adev,
3710                                                 golden_settings_gc_10_3_4,
3711                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3712                 break;
3713         case IP_VERSION(10, 3, 5):
3714                 soc15_program_register_sequence(adev,
3715                                                 golden_settings_gc_10_3_5,
3716                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3717                 break;
3718         case IP_VERSION(10, 1, 3):
3719         case IP_VERSION(10, 1, 4):
3720                 soc15_program_register_sequence(adev,
3721                                                 golden_settings_gc_10_0_cyan_skillfish,
3722                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3723                 break;
3724         case IP_VERSION(10, 3, 6):
3725                 soc15_program_register_sequence(adev,
3726                                                 golden_settings_gc_10_3_6,
3727                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3728                 break;
3729         case IP_VERSION(10, 3, 7):
3730                 soc15_program_register_sequence(adev,
3731                                                 golden_settings_gc_10_3_7,
3732                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3733                 break;
3734         default:
3735                 break;
3736         }
3737         gfx_v10_0_init_spm_golden_registers(adev);
3738 }
3739
3740 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3741                                        bool wc, uint32_t reg, uint32_t val)
3742 {
3743         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3744         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3745                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3746         amdgpu_ring_write(ring, reg);
3747         amdgpu_ring_write(ring, 0);
3748         amdgpu_ring_write(ring, val);
3749 }
3750
3751 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3752                                   int mem_space, int opt, uint32_t addr0,
3753                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3754                                   uint32_t inv)
3755 {
3756         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3757         amdgpu_ring_write(ring,
3758                           /* memory (1) or register (0) */
3759                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3760                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3761                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3762                            WAIT_REG_MEM_ENGINE(eng_sel)));
3763
3764         if (mem_space)
3765                 BUG_ON(addr0 & 0x3); /* Dword align */
3766         amdgpu_ring_write(ring, addr0);
3767         amdgpu_ring_write(ring, addr1);
3768         amdgpu_ring_write(ring, ref);
3769         amdgpu_ring_write(ring, mask);
3770         amdgpu_ring_write(ring, inv); /* poll interval */
3771 }
3772
3773 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3774 {
3775         struct amdgpu_device *adev = ring->adev;
3776         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3777         uint32_t tmp = 0;
3778         unsigned int i;
3779         int r;
3780
3781         WREG32(scratch, 0xCAFEDEAD);
3782         r = amdgpu_ring_alloc(ring, 3);
3783         if (r) {
3784                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3785                           ring->idx, r);
3786                 return r;
3787         }
3788
3789         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3790         amdgpu_ring_write(ring, scratch -
3791                           PACKET3_SET_UCONFIG_REG_START);
3792         amdgpu_ring_write(ring, 0xDEADBEEF);
3793         amdgpu_ring_commit(ring);
3794
3795         for (i = 0; i < adev->usec_timeout; i++) {
3796                 tmp = RREG32(scratch);
3797                 if (tmp == 0xDEADBEEF)
3798                         break;
3799                 if (amdgpu_emu_mode == 1)
3800                         msleep(1);
3801                 else
3802                         udelay(1);
3803         }
3804
3805         if (i >= adev->usec_timeout)
3806                 r = -ETIMEDOUT;
3807
3808         return r;
3809 }
3810
3811 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3812 {
3813         struct amdgpu_device *adev = ring->adev;
3814         struct amdgpu_ib ib;
3815         struct dma_fence *f = NULL;
3816         unsigned int index;
3817         uint64_t gpu_addr;
3818         volatile uint32_t *cpu_ptr;
3819         long r;
3820
3821         memset(&ib, 0, sizeof(ib));
3822
3823         if (ring->is_mes_queue) {
3824                 uint32_t padding, offset;
3825
3826                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3827                 padding = amdgpu_mes_ctx_get_offs(ring,
3828                                                   AMDGPU_MES_CTX_PADDING_OFFS);
3829
3830                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3831                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3832
3833                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3834                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3835                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3836         } else {
3837                 r = amdgpu_device_wb_get(adev, &index);
3838                 if (r)
3839                         return r;
3840
3841                 gpu_addr = adev->wb.gpu_addr + (index * 4);
3842                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3843                 cpu_ptr = &adev->wb.wb[index];
3844
3845                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3846                 if (r) {
3847                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3848                         goto err1;
3849                 }
3850         }
3851
3852         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3853         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3854         ib.ptr[2] = lower_32_bits(gpu_addr);
3855         ib.ptr[3] = upper_32_bits(gpu_addr);
3856         ib.ptr[4] = 0xDEADBEEF;
3857         ib.length_dw = 5;
3858
3859         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3860         if (r)
3861                 goto err2;
3862
3863         r = dma_fence_wait_timeout(f, false, timeout);
3864         if (r == 0) {
3865                 r = -ETIMEDOUT;
3866                 goto err2;
3867         } else if (r < 0) {
3868                 goto err2;
3869         }
3870
3871         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3872                 r = 0;
3873         else
3874                 r = -EINVAL;
3875 err2:
3876         if (!ring->is_mes_queue)
3877                 amdgpu_ib_free(adev, &ib, NULL);
3878         dma_fence_put(f);
3879 err1:
3880         if (!ring->is_mes_queue)
3881                 amdgpu_device_wb_free(adev, index);
3882         return r;
3883 }
3884
3885 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3886 {
3887         amdgpu_ucode_release(&adev->gfx.pfp_fw);
3888         amdgpu_ucode_release(&adev->gfx.me_fw);
3889         amdgpu_ucode_release(&adev->gfx.ce_fw);
3890         amdgpu_ucode_release(&adev->gfx.rlc_fw);
3891         amdgpu_ucode_release(&adev->gfx.mec_fw);
3892         amdgpu_ucode_release(&adev->gfx.mec2_fw);
3893
3894         kfree(adev->gfx.rlc.register_list_format);
3895 }
3896
3897 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3898 {
3899         adev->gfx.cp_fw_write_wait = false;
3900
3901         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3902         case IP_VERSION(10, 1, 10):
3903         case IP_VERSION(10, 1, 2):
3904         case IP_VERSION(10, 1, 1):
3905         case IP_VERSION(10, 1, 3):
3906         case IP_VERSION(10, 1, 4):
3907                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3908                     (adev->gfx.me_feature_version >= 27) &&
3909                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3910                     (adev->gfx.pfp_feature_version >= 27) &&
3911                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3912                     (adev->gfx.mec_feature_version >= 27))
3913                         adev->gfx.cp_fw_write_wait = true;
3914                 break;
3915         case IP_VERSION(10, 3, 0):
3916         case IP_VERSION(10, 3, 2):
3917         case IP_VERSION(10, 3, 1):
3918         case IP_VERSION(10, 3, 4):
3919         case IP_VERSION(10, 3, 5):
3920         case IP_VERSION(10, 3, 6):
3921         case IP_VERSION(10, 3, 3):
3922         case IP_VERSION(10, 3, 7):
3923                 adev->gfx.cp_fw_write_wait = true;
3924                 break;
3925         default:
3926                 break;
3927         }
3928
3929         if (!adev->gfx.cp_fw_write_wait)
3930                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3931 }
3932
3933 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3934 {
3935         bool ret = false;
3936
3937         switch (adev->pdev->revision) {
3938         case 0xc2:
3939         case 0xc3:
3940                 ret = true;
3941                 break;
3942         default:
3943                 ret = false;
3944                 break;
3945         }
3946
3947         return ret;
3948 }
3949
3950 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3951 {
3952         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3953         case IP_VERSION(10, 1, 10):
3954                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3955                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3956                 break;
3957         default:
3958                 break;
3959         }
3960 }
3961
3962 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3963 {
3964         char fw_name[40];
3965         char ucode_prefix[30];
3966         const char *wks = "";
3967         int err;
3968         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3969         uint16_t version_major;
3970         uint16_t version_minor;
3971
3972         DRM_DEBUG("\n");
3973
3974         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
3975             (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
3976                 wks = "_wks";
3977         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
3978
3979         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
3980         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
3981         if (err)
3982                 goto out;
3983         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
3984
3985         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
3986         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
3987         if (err)
3988                 goto out;
3989         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
3990
3991         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
3992         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
3993         if (err)
3994                 goto out;
3995         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
3996
3997         if (!amdgpu_sriov_vf(adev)) {
3998                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
3999                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4000                 if (err)
4001                         goto out;
4002
4003                 /* don't validate this firmware. There are apparently firmwares
4004                  * in the wild with incorrect size in the header
4005                  */
4006                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4007                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4008                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4009                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4010                 if (err)
4011                         goto out;
4012         }
4013
4014         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4015         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4016         if (err)
4017                 goto out;
4018         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4019         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4020
4021         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4022         err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4023         if (!err) {
4024                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4025                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4026         } else {
4027                 err = 0;
4028                 adev->gfx.mec2_fw = NULL;
4029         }
4030         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4031         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4032
4033         gfx_v10_0_check_fw_write_wait(adev);
4034 out:
4035         if (err) {
4036                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4037                 amdgpu_ucode_release(&adev->gfx.me_fw);
4038                 amdgpu_ucode_release(&adev->gfx.ce_fw);
4039                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4040                 amdgpu_ucode_release(&adev->gfx.mec_fw);
4041                 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4042         }
4043
4044         gfx_v10_0_check_gfxoff_flag(adev);
4045
4046         return err;
4047 }
4048
4049 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4050 {
4051         u32 count = 0;
4052         const struct cs_section_def *sect = NULL;
4053         const struct cs_extent_def *ext = NULL;
4054
4055         /* begin clear state */
4056         count += 2;
4057         /* context control state */
4058         count += 3;
4059
4060         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4061                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4062                         if (sect->id == SECT_CONTEXT)
4063                                 count += 2 + ext->reg_count;
4064                         else
4065                                 return 0;
4066                 }
4067         }
4068
4069         /* set PA_SC_TILE_STEERING_OVERRIDE */
4070         count += 3;
4071         /* end clear state */
4072         count += 2;
4073         /* clear state */
4074         count += 2;
4075
4076         return count;
4077 }
4078
4079 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4080                                     volatile u32 *buffer)
4081 {
4082         u32 count = 0, i;
4083         const struct cs_section_def *sect = NULL;
4084         const struct cs_extent_def *ext = NULL;
4085         int ctx_reg_offset;
4086
4087         if (adev->gfx.rlc.cs_data == NULL)
4088                 return;
4089         if (buffer == NULL)
4090                 return;
4091
4092         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4093         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4094
4095         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4096         buffer[count++] = cpu_to_le32(0x80000000);
4097         buffer[count++] = cpu_to_le32(0x80000000);
4098
4099         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4100                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4101                         if (sect->id == SECT_CONTEXT) {
4102                                 buffer[count++] =
4103                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4104                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4105                                                 PACKET3_SET_CONTEXT_REG_START);
4106                                 for (i = 0; i < ext->reg_count; i++)
4107                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4108                         } else {
4109                                 return;
4110                         }
4111                 }
4112         }
4113
4114         ctx_reg_offset =
4115                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4116         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4117         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4118         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4119
4120         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4121         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4122
4123         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4124         buffer[count++] = cpu_to_le32(0);
4125 }
4126
4127 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4128 {
4129         /* clear state block */
4130         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4131                         &adev->gfx.rlc.clear_state_gpu_addr,
4132                         (void **)&adev->gfx.rlc.cs_ptr);
4133
4134         /* jump table block */
4135         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4136                         &adev->gfx.rlc.cp_table_gpu_addr,
4137                         (void **)&adev->gfx.rlc.cp_table_ptr);
4138 }
4139
4140 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4141 {
4142         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4143
4144         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4145         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4146         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4147         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4148         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4149         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4150         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4151         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4152         case IP_VERSION(10, 3, 0):
4153                 reg_access_ctrl->spare_int =
4154                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4155                 break;
4156         default:
4157                 reg_access_ctrl->spare_int =
4158                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4159                 break;
4160         }
4161         adev->gfx.rlc.rlcg_reg_access_supported = true;
4162 }
4163
4164 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4165 {
4166         const struct cs_section_def *cs_data;
4167         int r;
4168
4169         adev->gfx.rlc.cs_data = gfx10_cs_data;
4170
4171         cs_data = adev->gfx.rlc.cs_data;
4172
4173         if (cs_data) {
4174                 /* init clear state block */
4175                 r = amdgpu_gfx_rlc_init_csb(adev);
4176                 if (r)
4177                         return r;
4178         }
4179
4180         return 0;
4181 }
4182
4183 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4184 {
4185         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4186         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4187 }
4188
4189 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4190 {
4191         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4192
4193         amdgpu_gfx_graphics_queue_acquire(adev);
4194 }
4195
4196 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4197 {
4198         int r;
4199         u32 *hpd;
4200         const __le32 *fw_data = NULL;
4201         unsigned int fw_size;
4202         u32 *fw = NULL;
4203         size_t mec_hpd_size;
4204
4205         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4206
4207         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4208
4209         /* take ownership of the relevant compute queues */
4210         amdgpu_gfx_compute_queue_acquire(adev);
4211         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4212
4213         if (mec_hpd_size) {
4214                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4215                                               AMDGPU_GEM_DOMAIN_GTT,
4216                                               &adev->gfx.mec.hpd_eop_obj,
4217                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4218                                               (void **)&hpd);
4219                 if (r) {
4220                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4221                         gfx_v10_0_mec_fini(adev);
4222                         return r;
4223                 }
4224
4225                 memset(hpd, 0, mec_hpd_size);
4226
4227                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4228                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4229         }
4230
4231         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4232                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4233
4234                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4235                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4236                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4237
4238                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4239                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4240                                               &adev->gfx.mec.mec_fw_obj,
4241                                               &adev->gfx.mec.mec_fw_gpu_addr,
4242                                               (void **)&fw);
4243                 if (r) {
4244                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4245                         gfx_v10_0_mec_fini(adev);
4246                         return r;
4247                 }
4248
4249                 memcpy(fw, fw_data, fw_size);
4250
4251                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4252                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4253         }
4254
4255         return 0;
4256 }
4257
4258 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4259 {
4260         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4261                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4262                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4263         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4264 }
4265
4266 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4267                            uint32_t thread, uint32_t regno,
4268                            uint32_t num, uint32_t *out)
4269 {
4270         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4271                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4272                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4273                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4274                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4275         while (num--)
4276                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4277 }
4278
4279 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4280 {
4281         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4282          * field when performing a select_se_sh so it should be
4283          * zero here
4284          */
4285         WARN_ON(simd != 0);
4286
4287         /* type 2 wave data */
4288         dst[(*no_fields)++] = 2;
4289         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4290         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4291         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4292         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4293         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4294         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4295         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4296         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4297         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4298         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4299         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4300         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4301         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4302         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4303         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4304         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4305 }
4306
4307 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4308                                      uint32_t wave, uint32_t start,
4309                                      uint32_t size, uint32_t *dst)
4310 {
4311         WARN_ON(simd != 0);
4312
4313         wave_read_regs(
4314                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4315                 dst);
4316 }
4317
4318 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4319                                       uint32_t wave, uint32_t thread,
4320                                       uint32_t start, uint32_t size,
4321                                       uint32_t *dst)
4322 {
4323         wave_read_regs(
4324                 adev, wave, thread,
4325                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4326 }
4327
4328 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4329                                        u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4330 {
4331         nv_grbm_select(adev, me, pipe, q, vm);
4332 }
4333
4334 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4335                                           bool enable)
4336 {
4337         uint32_t data, def;
4338
4339         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4340
4341         if (enable)
4342                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4343         else
4344                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4345
4346         if (data != def)
4347                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4348 }
4349
4350 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4351         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4352         .select_se_sh = &gfx_v10_0_select_se_sh,
4353         .read_wave_data = &gfx_v10_0_read_wave_data,
4354         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4355         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4356         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4357         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4358         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4359 };
4360
4361 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4362 {
4363         u32 gb_addr_config;
4364
4365         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4366         case IP_VERSION(10, 1, 10):
4367         case IP_VERSION(10, 1, 1):
4368         case IP_VERSION(10, 1, 2):
4369                 adev->gfx.config.max_hw_contexts = 8;
4370                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4371                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4372                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4373                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4374                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4375                 break;
4376         case IP_VERSION(10, 3, 0):
4377         case IP_VERSION(10, 3, 2):
4378         case IP_VERSION(10, 3, 1):
4379         case IP_VERSION(10, 3, 4):
4380         case IP_VERSION(10, 3, 5):
4381         case IP_VERSION(10, 3, 6):
4382         case IP_VERSION(10, 3, 3):
4383         case IP_VERSION(10, 3, 7):
4384                 adev->gfx.config.max_hw_contexts = 8;
4385                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4386                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4387                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4388                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4389                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4390                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4391                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4392                 break;
4393         case IP_VERSION(10, 1, 3):
4394         case IP_VERSION(10, 1, 4):
4395                 adev->gfx.config.max_hw_contexts = 8;
4396                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4397                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4398                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4399                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4400                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4401                 break;
4402         default:
4403                 BUG();
4404                 break;
4405         }
4406
4407         adev->gfx.config.gb_addr_config = gb_addr_config;
4408
4409         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4410                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4411                                       GB_ADDR_CONFIG, NUM_PIPES);
4412
4413         adev->gfx.config.max_tile_pipes =
4414                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4415
4416         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4417                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4418                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4419         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4420                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4421                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4422         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4423                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4424                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4425         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4426                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4427                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4428 }
4429
4430 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4431                                    int me, int pipe, int queue)
4432 {
4433         struct amdgpu_ring *ring;
4434         unsigned int irq_type;
4435         unsigned int hw_prio;
4436
4437         ring = &adev->gfx.gfx_ring[ring_id];
4438
4439         ring->me = me;
4440         ring->pipe = pipe;
4441         ring->queue = queue;
4442
4443         ring->ring_obj = NULL;
4444         ring->use_doorbell = true;
4445
4446         if (!ring_id)
4447                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4448         else
4449                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4450         ring->vm_hub = AMDGPU_GFXHUB(0);
4451         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4452
4453         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4454         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4455                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4456         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4457                                 hw_prio, NULL);
4458 }
4459
4460 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4461                                        int mec, int pipe, int queue)
4462 {
4463         unsigned int irq_type;
4464         struct amdgpu_ring *ring;
4465         unsigned int hw_prio;
4466
4467         ring = &adev->gfx.compute_ring[ring_id];
4468
4469         /* mec0 is me1 */
4470         ring->me = mec + 1;
4471         ring->pipe = pipe;
4472         ring->queue = queue;
4473
4474         ring->ring_obj = NULL;
4475         ring->use_doorbell = true;
4476         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4477         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4478                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4479         ring->vm_hub = AMDGPU_GFXHUB(0);
4480         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4481
4482         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4483                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4484                 + ring->pipe;
4485         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4486                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4487         /* type-2 packets are deprecated on MEC, use type-3 instead */
4488         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4489                              hw_prio, NULL);
4490 }
4491
4492 static int gfx_v10_0_sw_init(void *handle)
4493 {
4494         int i, j, k, r, ring_id = 0;
4495         struct amdgpu_kiq *kiq;
4496         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4497
4498         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4499         case IP_VERSION(10, 1, 10):
4500         case IP_VERSION(10, 1, 1):
4501         case IP_VERSION(10, 1, 2):
4502         case IP_VERSION(10, 1, 3):
4503         case IP_VERSION(10, 1, 4):
4504                 adev->gfx.me.num_me = 1;
4505                 adev->gfx.me.num_pipe_per_me = 1;
4506                 adev->gfx.me.num_queue_per_pipe = 1;
4507                 adev->gfx.mec.num_mec = 2;
4508                 adev->gfx.mec.num_pipe_per_mec = 4;
4509                 adev->gfx.mec.num_queue_per_pipe = 8;
4510                 break;
4511         case IP_VERSION(10, 3, 0):
4512         case IP_VERSION(10, 3, 2):
4513         case IP_VERSION(10, 3, 1):
4514         case IP_VERSION(10, 3, 4):
4515         case IP_VERSION(10, 3, 5):
4516         case IP_VERSION(10, 3, 6):
4517         case IP_VERSION(10, 3, 3):
4518         case IP_VERSION(10, 3, 7):
4519                 adev->gfx.me.num_me = 1;
4520                 adev->gfx.me.num_pipe_per_me = 1;
4521                 adev->gfx.me.num_queue_per_pipe = 1;
4522                 adev->gfx.mec.num_mec = 2;
4523                 adev->gfx.mec.num_pipe_per_mec = 4;
4524                 adev->gfx.mec.num_queue_per_pipe = 4;
4525                 break;
4526         default:
4527                 adev->gfx.me.num_me = 1;
4528                 adev->gfx.me.num_pipe_per_me = 1;
4529                 adev->gfx.me.num_queue_per_pipe = 1;
4530                 adev->gfx.mec.num_mec = 1;
4531                 adev->gfx.mec.num_pipe_per_mec = 4;
4532                 adev->gfx.mec.num_queue_per_pipe = 8;
4533                 break;
4534         }
4535
4536         /* KIQ event */
4537         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4538                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4539                               &adev->gfx.kiq[0].irq);
4540         if (r)
4541                 return r;
4542
4543         /* EOP Event */
4544         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4545                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4546                               &adev->gfx.eop_irq);
4547         if (r)
4548                 return r;
4549
4550         /* Privileged reg */
4551         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4552                               &adev->gfx.priv_reg_irq);
4553         if (r)
4554                 return r;
4555
4556         /* Privileged inst */
4557         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4558                               &adev->gfx.priv_inst_irq);
4559         if (r)
4560                 return r;
4561
4562         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4563
4564         gfx_v10_0_me_init(adev);
4565
4566         if (adev->gfx.rlc.funcs) {
4567                 if (adev->gfx.rlc.funcs->init) {
4568                         r = adev->gfx.rlc.funcs->init(adev);
4569                         if (r) {
4570                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4571                                 return r;
4572                         }
4573                 }
4574         }
4575
4576         r = gfx_v10_0_mec_init(adev);
4577         if (r) {
4578                 DRM_ERROR("Failed to init MEC BOs!\n");
4579                 return r;
4580         }
4581
4582         /* set up the gfx ring */
4583         for (i = 0; i < adev->gfx.me.num_me; i++) {
4584                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4585                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4586                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4587                                         continue;
4588
4589                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4590                                                             i, k, j);
4591                                 if (r)
4592                                         return r;
4593                                 ring_id++;
4594                         }
4595                 }
4596         }
4597
4598         ring_id = 0;
4599         /* set up the compute queues - allocate horizontally across pipes */
4600         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4601                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4602                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4603                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4604                                                                      k, j))
4605                                         continue;
4606
4607                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4608                                                                 i, k, j);
4609                                 if (r)
4610                                         return r;
4611
4612                                 ring_id++;
4613                         }
4614                 }
4615         }
4616
4617         if (!adev->enable_mes_kiq) {
4618                 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4619                 if (r) {
4620                         DRM_ERROR("Failed to init KIQ BOs!\n");
4621                         return r;
4622                 }
4623
4624                 kiq = &adev->gfx.kiq[0];
4625                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
4626                 if (r)
4627                         return r;
4628         }
4629
4630         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4631         if (r)
4632                 return r;
4633
4634         /* allocate visible FB for rlc auto-loading fw */
4635         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4636                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4637                 if (r)
4638                         return r;
4639         }
4640
4641         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4642
4643         gfx_v10_0_gpu_early_init(adev);
4644
4645         return 0;
4646 }
4647
4648 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4649 {
4650         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4651                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4652                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4653 }
4654
4655 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4656 {
4657         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4658                               &adev->gfx.ce.ce_fw_gpu_addr,
4659                               (void **)&adev->gfx.ce.ce_fw_ptr);
4660 }
4661
4662 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4663 {
4664         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4665                               &adev->gfx.me.me_fw_gpu_addr,
4666                               (void **)&adev->gfx.me.me_fw_ptr);
4667 }
4668
4669 static int gfx_v10_0_sw_fini(void *handle)
4670 {
4671         int i;
4672         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4673
4674         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4675                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4676         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4677                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4678
4679         amdgpu_gfx_mqd_sw_fini(adev, 0);
4680
4681         if (!adev->enable_mes_kiq) {
4682                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4683                 amdgpu_gfx_kiq_fini(adev, 0);
4684         }
4685
4686         gfx_v10_0_pfp_fini(adev);
4687         gfx_v10_0_ce_fini(adev);
4688         gfx_v10_0_me_fini(adev);
4689         gfx_v10_0_rlc_fini(adev);
4690         gfx_v10_0_mec_fini(adev);
4691
4692         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4693                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4694
4695         gfx_v10_0_free_microcode(adev);
4696
4697         return 0;
4698 }
4699
4700 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4701                                    u32 sh_num, u32 instance, int xcc_id)
4702 {
4703         u32 data;
4704
4705         if (instance == 0xffffffff)
4706                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4707                                      INSTANCE_BROADCAST_WRITES, 1);
4708         else
4709                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4710                                      instance);
4711
4712         if (se_num == 0xffffffff)
4713                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4714                                      1);
4715         else
4716                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4717
4718         if (sh_num == 0xffffffff)
4719                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4720                                      1);
4721         else
4722                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4723
4724         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4725 }
4726
4727 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4728 {
4729         u32 data, mask;
4730
4731         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4732         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4733
4734         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4735         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4736
4737         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4738                                          adev->gfx.config.max_sh_per_se);
4739
4740         return (~data) & mask;
4741 }
4742
4743 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4744 {
4745         int i, j;
4746         u32 data;
4747         u32 active_rbs = 0;
4748         u32 bitmap;
4749         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4750                                         adev->gfx.config.max_sh_per_se;
4751
4752         mutex_lock(&adev->grbm_idx_mutex);
4753         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4754                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4755                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4756                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4757                               IP_VERSION(10, 3, 0)) ||
4758                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4759                               IP_VERSION(10, 3, 3)) ||
4760                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4761                               IP_VERSION(10, 3, 6))) &&
4762                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4763                                 continue;
4764                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4765                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4766                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4767                                                rb_bitmap_width_per_sh);
4768                 }
4769         }
4770         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4771         mutex_unlock(&adev->grbm_idx_mutex);
4772
4773         adev->gfx.config.backend_enable_mask = active_rbs;
4774         adev->gfx.config.num_rbs = hweight32(active_rbs);
4775 }
4776
4777 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4778 {
4779         uint32_t num_sc;
4780         uint32_t enabled_rb_per_sh;
4781         uint32_t active_rb_bitmap;
4782         uint32_t num_rb_per_sc;
4783         uint32_t num_packer_per_sc;
4784         uint32_t pa_sc_tile_steering_override;
4785
4786         /* for ASICs that integrates GFX v10.3
4787          * pa_sc_tile_steering_override should be set to 0
4788          */
4789         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4790                 return 0;
4791
4792         /* init num_sc */
4793         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4794                         adev->gfx.config.num_sc_per_sh;
4795         /* init num_rb_per_sc */
4796         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4797         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4798         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4799         /* init num_packer_per_sc */
4800         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4801
4802         pa_sc_tile_steering_override = 0;
4803         pa_sc_tile_steering_override |=
4804                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4805                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4806         pa_sc_tile_steering_override |=
4807                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4808                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4809         pa_sc_tile_steering_override |=
4810                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4811                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4812
4813         return pa_sc_tile_steering_override;
4814 }
4815
4816 #define DEFAULT_SH_MEM_BASES    (0x6000)
4817
4818 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
4819                                 uint32_t first_vmid,
4820                                 uint32_t last_vmid)
4821 {
4822         uint32_t data;
4823         uint32_t trap_config_vmid_mask = 0;
4824         int i;
4825
4826         /* Calculate trap config vmid mask */
4827         for (i = first_vmid; i < last_vmid; i++)
4828                 trap_config_vmid_mask |= (1 << i);
4829
4830         data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
4831                         VMID_SEL, trap_config_vmid_mask);
4832         data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
4833                         TRAP_EN, 1);
4834         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
4835         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
4836
4837         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
4838         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
4839 }
4840
4841 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4842 {
4843         int i;
4844         uint32_t sh_mem_bases;
4845
4846         /*
4847          * Configure apertures:
4848          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4849          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4850          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4851          */
4852         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4853
4854         mutex_lock(&adev->srbm_mutex);
4855         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4856                 nv_grbm_select(adev, 0, 0, 0, i);
4857                 /* CP and shaders */
4858                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4859                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4860         }
4861         nv_grbm_select(adev, 0, 0, 0, 0);
4862         mutex_unlock(&adev->srbm_mutex);
4863
4864         /*
4865          * Initialize all compute VMIDs to have no GDS, GWS, or OA
4866          * access. These should be enabled by FW for target VMIDs.
4867          */
4868         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4869                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4870                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4871                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4872                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4873         }
4874
4875         gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
4876                                         AMDGPU_NUM_VMID);
4877 }
4878
4879 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4880 {
4881         int vmid;
4882
4883         /*
4884          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4885          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4886          * the driver can enable them for graphics. VMID0 should maintain
4887          * access so that HWS firmware can save/restore entries.
4888          */
4889         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4890                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4891                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4892                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4893                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4894         }
4895 }
4896
4897
4898 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4899 {
4900         int i, j, k;
4901         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4902         u32 tmp, wgp_active_bitmap = 0;
4903         u32 gcrd_targets_disable_tcp = 0;
4904         u32 utcl_invreq_disable = 0;
4905         /*
4906          * GCRD_TARGETS_DISABLE field contains
4907          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4908          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4909          */
4910         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4911                 2 * max_wgp_per_sh + /* TCP */
4912                 max_wgp_per_sh + /* SQC */
4913                 4); /* GL1C */
4914         /*
4915          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4916          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4917          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4918          */
4919         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4920                 2 * max_wgp_per_sh + /* TCP */
4921                 2 * max_wgp_per_sh + /* SQC */
4922                 4 + /* RMI */
4923                 1); /* SQG */
4924
4925         mutex_lock(&adev->grbm_idx_mutex);
4926         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4927                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4928                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4929                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4930                         /*
4931                          * Set corresponding TCP bits for the inactive WGPs in
4932                          * GCRD_SA_TARGETS_DISABLE
4933                          */
4934                         gcrd_targets_disable_tcp = 0;
4935                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4936                         utcl_invreq_disable = 0;
4937
4938                         for (k = 0; k < max_wgp_per_sh; k++) {
4939                                 if (!(wgp_active_bitmap & (1 << k))) {
4940                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
4941                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
4942                                         utcl_invreq_disable |= (3 << (2 * k)) |
4943                                                 (3 << (2 * (max_wgp_per_sh + k)));
4944                                 }
4945                         }
4946
4947                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4948                         /* only override TCP & SQC bits */
4949                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
4950                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4951                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4952
4953                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4954                         /* only override TCP & SQC bits */
4955                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
4956                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4957                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4958                 }
4959         }
4960
4961         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4962         mutex_unlock(&adev->grbm_idx_mutex);
4963 }
4964
4965 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4966 {
4967         /* TCCs are global (not instanced). */
4968         uint32_t tcc_disable;
4969
4970         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
4971                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
4972                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
4973         } else {
4974                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4975                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4976         }
4977
4978         adev->gfx.config.tcc_disabled_mask =
4979                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4980                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4981 }
4982
4983 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4984 {
4985         u32 tmp;
4986         int i;
4987
4988         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4989
4990         gfx_v10_0_setup_rb(adev);
4991         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4992         gfx_v10_0_get_tcc_info(adev);
4993         adev->gfx.config.pa_sc_tile_steering_override =
4994                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4995
4996         /* XXX SH_MEM regs */
4997         /* where to put LDS, scratch, GPUVM in FSA64 space */
4998         mutex_lock(&adev->srbm_mutex);
4999         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5000                 nv_grbm_select(adev, 0, 0, 0, i);
5001                 /* CP and shaders */
5002                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5003                 if (i != 0) {
5004                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5005                                 (adev->gmc.private_aperture_start >> 48));
5006                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5007                                 (adev->gmc.shared_aperture_start >> 48));
5008                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5009                 }
5010         }
5011         nv_grbm_select(adev, 0, 0, 0, 0);
5012
5013         mutex_unlock(&adev->srbm_mutex);
5014
5015         gfx_v10_0_init_compute_vmid(adev);
5016         gfx_v10_0_init_gds_vmid(adev);
5017
5018 }
5019
5020 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5021                                                bool enable)
5022 {
5023         u32 tmp;
5024
5025         if (amdgpu_sriov_vf(adev))
5026                 return;
5027
5028         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5029
5030         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5031                             enable ? 1 : 0);
5032         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5033                             enable ? 1 : 0);
5034         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5035                             enable ? 1 : 0);
5036         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5037                             enable ? 1 : 0);
5038
5039         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5040 }
5041
5042 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5043 {
5044         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5045
5046         /* csib */
5047         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5048                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5049                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5050                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5051                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5052                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5053         } else {
5054                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5055                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5056                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5057                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5058                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5059         }
5060         return 0;
5061 }
5062
5063 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5064 {
5065         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5066
5067         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5068         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5069 }
5070
5071 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5072 {
5073         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5074         udelay(50);
5075         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5076         udelay(50);
5077 }
5078
5079 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5080                                              bool enable)
5081 {
5082         uint32_t rlc_pg_cntl;
5083
5084         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5085
5086         if (!enable) {
5087                 /* RLC_PG_CNTL[23] = 0 (default)
5088                  * RLC will wait for handshake acks with SMU
5089                  * GFXOFF will be enabled
5090                  * RLC_PG_CNTL[23] = 1
5091                  * RLC will not issue any message to SMU
5092                  * hence no handshake between SMU & RLC
5093                  * GFXOFF will be disabled
5094                  */
5095                 rlc_pg_cntl |= 0x800000;
5096         } else
5097                 rlc_pg_cntl &= ~0x800000;
5098         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5099 }
5100
5101 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5102 {
5103         /*
5104          * TODO: enable rlc & smu handshake until smu
5105          * and gfxoff feature works as expected
5106          */
5107         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5108                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5109
5110         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5111         udelay(50);
5112 }
5113
5114 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5115 {
5116         uint32_t tmp;
5117
5118         /* enable Save Restore Machine */
5119         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5120         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5121         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5122         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5123 }
5124
5125 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5126 {
5127         const struct rlc_firmware_header_v2_0 *hdr;
5128         const __le32 *fw_data;
5129         unsigned int i, fw_size;
5130
5131         if (!adev->gfx.rlc_fw)
5132                 return -EINVAL;
5133
5134         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5135         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5136
5137         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5138                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5139         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5140
5141         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5142                      RLCG_UCODE_LOADING_START_ADDRESS);
5143
5144         for (i = 0; i < fw_size; i++)
5145                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5146                              le32_to_cpup(fw_data++));
5147
5148         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5149
5150         return 0;
5151 }
5152
5153 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5154 {
5155         int r;
5156
5157         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5158                 adev->psp.autoload_supported) {
5159
5160                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5161                 if (r)
5162                         return r;
5163
5164                 gfx_v10_0_init_csb(adev);
5165
5166                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5167
5168                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5169                         gfx_v10_0_rlc_enable_srm(adev);
5170         } else {
5171                 if (amdgpu_sriov_vf(adev)) {
5172                         gfx_v10_0_init_csb(adev);
5173                         return 0;
5174                 }
5175
5176                 adev->gfx.rlc.funcs->stop(adev);
5177
5178                 /* disable CG */
5179                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5180
5181                 /* disable PG */
5182                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5183
5184                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5185                         /* legacy rlc firmware loading */
5186                         r = gfx_v10_0_rlc_load_microcode(adev);
5187                         if (r)
5188                                 return r;
5189                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5190                         /* rlc backdoor autoload firmware */
5191                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5192                         if (r)
5193                                 return r;
5194                 }
5195
5196                 gfx_v10_0_init_csb(adev);
5197
5198                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5199
5200                 adev->gfx.rlc.funcs->start(adev);
5201
5202                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5203                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5204                         if (r)
5205                                 return r;
5206                 }
5207         }
5208
5209         return 0;
5210 }
5211
5212 static struct {
5213         FIRMWARE_ID     id;
5214         unsigned int    offset;
5215         unsigned int    size;
5216 } rlc_autoload_info[FIRMWARE_ID_MAX];
5217
5218 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5219 {
5220         int ret;
5221         RLC_TABLE_OF_CONTENT *rlc_toc;
5222
5223         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5224                                         AMDGPU_GEM_DOMAIN_GTT,
5225                                         &adev->gfx.rlc.rlc_toc_bo,
5226                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5227                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5228         if (ret) {
5229                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5230                 return ret;
5231         }
5232
5233         /* Copy toc from psp sos fw to rlc toc buffer */
5234         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5235
5236         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5237         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5238                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5239                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5240                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5241                         /* Offset needs 4KB alignment */
5242                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5243                 }
5244
5245                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5246                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5247                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5248
5249                 rlc_toc++;
5250         }
5251
5252         return 0;
5253 }
5254
5255 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5256 {
5257         uint32_t total_size = 0;
5258         FIRMWARE_ID id;
5259         int ret;
5260
5261         ret = gfx_v10_0_parse_rlc_toc(adev);
5262         if (ret) {
5263                 dev_err(adev->dev, "failed to parse rlc toc\n");
5264                 return 0;
5265         }
5266
5267         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5268                 total_size += rlc_autoload_info[id].size;
5269
5270         /* In case the offset in rlc toc ucode is aligned */
5271         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5272                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5273                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5274
5275         return total_size;
5276 }
5277
5278 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5279 {
5280         int r;
5281         uint32_t total_size;
5282
5283         total_size = gfx_v10_0_calc_toc_total_size(adev);
5284
5285         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5286                                       AMDGPU_GEM_DOMAIN_GTT,
5287                                       &adev->gfx.rlc.rlc_autoload_bo,
5288                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5289                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5290         if (r) {
5291                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5292                 return r;
5293         }
5294
5295         return 0;
5296 }
5297
5298 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5299 {
5300         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5301                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5302                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5303         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5304                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5305                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5306 }
5307
5308 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5309                                                        FIRMWARE_ID id,
5310                                                        const void *fw_data,
5311                                                        uint32_t fw_size)
5312 {
5313         uint32_t toc_offset;
5314         uint32_t toc_fw_size;
5315         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5316
5317         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5318                 return;
5319
5320         toc_offset = rlc_autoload_info[id].offset;
5321         toc_fw_size = rlc_autoload_info[id].size;
5322
5323         if (fw_size == 0)
5324                 fw_size = toc_fw_size;
5325
5326         if (fw_size > toc_fw_size)
5327                 fw_size = toc_fw_size;
5328
5329         memcpy(ptr + toc_offset, fw_data, fw_size);
5330
5331         if (fw_size < toc_fw_size)
5332                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5333 }
5334
5335 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5336 {
5337         void *data;
5338         uint32_t size;
5339
5340         data = adev->gfx.rlc.rlc_toc_buf;
5341         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5342
5343         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5344                                                    FIRMWARE_ID_RLC_TOC,
5345                                                    data, size);
5346 }
5347
5348 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5349 {
5350         const __le32 *fw_data;
5351         uint32_t fw_size;
5352         const struct gfx_firmware_header_v1_0 *cp_hdr;
5353         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5354
5355         /* pfp ucode */
5356         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5357                 adev->gfx.pfp_fw->data;
5358         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5359                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5360         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5361         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5362                                                    FIRMWARE_ID_CP_PFP,
5363                                                    fw_data, fw_size);
5364
5365         /* ce ucode */
5366         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5367                 adev->gfx.ce_fw->data;
5368         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5369                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5370         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5371         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5372                                                    FIRMWARE_ID_CP_CE,
5373                                                    fw_data, fw_size);
5374
5375         /* me ucode */
5376         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5377                 adev->gfx.me_fw->data;
5378         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5379                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5380         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5381         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5382                                                    FIRMWARE_ID_CP_ME,
5383                                                    fw_data, fw_size);
5384
5385         /* rlc ucode */
5386         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5387                 adev->gfx.rlc_fw->data;
5388         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5389                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5390         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5391         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5392                                                    FIRMWARE_ID_RLC_G_UCODE,
5393                                                    fw_data, fw_size);
5394
5395         /* mec1 ucode */
5396         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5397                 adev->gfx.mec_fw->data;
5398         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5399                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5400         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5401                 cp_hdr->jt_size * 4;
5402         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5403                                                    FIRMWARE_ID_CP_MEC,
5404                                                    fw_data, fw_size);
5405         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5406 }
5407
5408 /* Temporarily put sdma part here */
5409 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5410 {
5411         const __le32 *fw_data;
5412         uint32_t fw_size;
5413         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5414         int i;
5415
5416         for (i = 0; i < adev->sdma.num_instances; i++) {
5417                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5418                         adev->sdma.instance[i].fw->data;
5419                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5420                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5421                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5422
5423                 if (i == 0) {
5424                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5425                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5426                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5427                                 FIRMWARE_ID_SDMA0_JT,
5428                                 (uint32_t *)fw_data +
5429                                 sdma_hdr->jt_offset,
5430                                 sdma_hdr->jt_size * 4);
5431                 } else if (i == 1) {
5432                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5433                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5434                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5435                                 FIRMWARE_ID_SDMA1_JT,
5436                                 (uint32_t *)fw_data +
5437                                 sdma_hdr->jt_offset,
5438                                 sdma_hdr->jt_size * 4);
5439                 }
5440         }
5441 }
5442
5443 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5444 {
5445         uint32_t rlc_g_offset, rlc_g_size, tmp;
5446         uint64_t gpu_addr;
5447
5448         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5449         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5450         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5451
5452         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5453         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5454         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5455
5456         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5457         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5458         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5459
5460         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5461         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5462                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5463                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5464                 return -EINVAL;
5465         }
5466
5467         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5468         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5469                 DRM_ERROR("RLC ROM should halt itself\n");
5470                 return -EINVAL;
5471         }
5472
5473         return 0;
5474 }
5475
5476 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5477 {
5478         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5479         uint32_t tmp;
5480         int i;
5481         uint64_t addr;
5482
5483         /* Trigger an invalidation of the L1 instruction caches */
5484         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5485         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5486         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5487
5488         /* Wait for invalidation complete */
5489         for (i = 0; i < usec_timeout; i++) {
5490                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5491                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5492                         INVALIDATE_CACHE_COMPLETE))
5493                         break;
5494                 udelay(1);
5495         }
5496
5497         if (i >= usec_timeout) {
5498                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5499                 return -EINVAL;
5500         }
5501
5502         /* Program me ucode address into intruction cache address register */
5503         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5504                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5505         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5506                         lower_32_bits(addr) & 0xFFFFF000);
5507         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5508                         upper_32_bits(addr));
5509
5510         return 0;
5511 }
5512
5513 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5514 {
5515         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5516         uint32_t tmp;
5517         int i;
5518         uint64_t addr;
5519
5520         /* Trigger an invalidation of the L1 instruction caches */
5521         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5522         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5523         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5524
5525         /* Wait for invalidation complete */
5526         for (i = 0; i < usec_timeout; i++) {
5527                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5528                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5529                         INVALIDATE_CACHE_COMPLETE))
5530                         break;
5531                 udelay(1);
5532         }
5533
5534         if (i >= usec_timeout) {
5535                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5536                 return -EINVAL;
5537         }
5538
5539         /* Program ce ucode address into intruction cache address register */
5540         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5541                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5542         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5543                         lower_32_bits(addr) & 0xFFFFF000);
5544         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5545                         upper_32_bits(addr));
5546
5547         return 0;
5548 }
5549
5550 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5551 {
5552         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5553         uint32_t tmp;
5554         int i;
5555         uint64_t addr;
5556
5557         /* Trigger an invalidation of the L1 instruction caches */
5558         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5559         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5560         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5561
5562         /* Wait for invalidation complete */
5563         for (i = 0; i < usec_timeout; i++) {
5564                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5565                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5566                         INVALIDATE_CACHE_COMPLETE))
5567                         break;
5568                 udelay(1);
5569         }
5570
5571         if (i >= usec_timeout) {
5572                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5573                 return -EINVAL;
5574         }
5575
5576         /* Program pfp ucode address into intruction cache address register */
5577         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5578                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5579         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5580                         lower_32_bits(addr) & 0xFFFFF000);
5581         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5582                         upper_32_bits(addr));
5583
5584         return 0;
5585 }
5586
5587 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5588 {
5589         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5590         uint32_t tmp;
5591         int i;
5592         uint64_t addr;
5593
5594         /* Trigger an invalidation of the L1 instruction caches */
5595         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5596         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5597         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5598
5599         /* Wait for invalidation complete */
5600         for (i = 0; i < usec_timeout; i++) {
5601                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5602                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5603                         INVALIDATE_CACHE_COMPLETE))
5604                         break;
5605                 udelay(1);
5606         }
5607
5608         if (i >= usec_timeout) {
5609                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5610                 return -EINVAL;
5611         }
5612
5613         /* Program mec1 ucode address into intruction cache address register */
5614         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5615                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5616         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5617                         lower_32_bits(addr) & 0xFFFFF000);
5618         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5619                         upper_32_bits(addr));
5620
5621         return 0;
5622 }
5623
5624 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5625 {
5626         uint32_t cp_status;
5627         uint32_t bootload_status;
5628         int i, r;
5629
5630         for (i = 0; i < adev->usec_timeout; i++) {
5631                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5632                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5633                 if ((cp_status == 0) &&
5634                     (REG_GET_FIELD(bootload_status,
5635                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5636                         break;
5637                 }
5638                 udelay(1);
5639         }
5640
5641         if (i >= adev->usec_timeout) {
5642                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5643                 return -ETIMEDOUT;
5644         }
5645
5646         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5647                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5648                 if (r)
5649                         return r;
5650
5651                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5652                 if (r)
5653                         return r;
5654
5655                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5656                 if (r)
5657                         return r;
5658
5659                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5660                 if (r)
5661                         return r;
5662         }
5663
5664         return 0;
5665 }
5666
5667 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5668 {
5669         int i;
5670         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5671
5672         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5673         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5674         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5675
5676         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5677                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5678         else
5679                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5680
5681         if (adev->job_hang && !enable)
5682                 return 0;
5683
5684         for (i = 0; i < adev->usec_timeout; i++) {
5685                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5686                         break;
5687                 udelay(1);
5688         }
5689
5690         if (i >= adev->usec_timeout)
5691                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5692
5693         return 0;
5694 }
5695
5696 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5697 {
5698         int r;
5699         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5700         const __le32 *fw_data;
5701         unsigned int i, fw_size;
5702         uint32_t tmp;
5703         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5704
5705         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5706                 adev->gfx.pfp_fw->data;
5707
5708         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5709
5710         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5711                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5712         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5713
5714         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5715                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5716                                       &adev->gfx.pfp.pfp_fw_obj,
5717                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5718                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5719         if (r) {
5720                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5721                 gfx_v10_0_pfp_fini(adev);
5722                 return r;
5723         }
5724
5725         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5726
5727         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5728         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5729
5730         /* Trigger an invalidation of the L1 instruction caches */
5731         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5732         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5733         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5734
5735         /* Wait for invalidation complete */
5736         for (i = 0; i < usec_timeout; i++) {
5737                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5738                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5739                         INVALIDATE_CACHE_COMPLETE))
5740                         break;
5741                 udelay(1);
5742         }
5743
5744         if (i >= usec_timeout) {
5745                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5746                 return -EINVAL;
5747         }
5748
5749         if (amdgpu_emu_mode == 1)
5750                 adev->hdp.funcs->flush_hdp(adev, NULL);
5751
5752         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5753         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5754         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5755         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5756         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5757         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5758         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5759                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5760         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5761                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5762
5763         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5764
5765         for (i = 0; i < pfp_hdr->jt_size; i++)
5766                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5767                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5768
5769         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5770
5771         return 0;
5772 }
5773
5774 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5775 {
5776         int r;
5777         const struct gfx_firmware_header_v1_0 *ce_hdr;
5778         const __le32 *fw_data;
5779         unsigned int i, fw_size;
5780         uint32_t tmp;
5781         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5782
5783         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5784                 adev->gfx.ce_fw->data;
5785
5786         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5787
5788         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5789                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5790         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5791
5792         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5793                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5794                                       &adev->gfx.ce.ce_fw_obj,
5795                                       &adev->gfx.ce.ce_fw_gpu_addr,
5796                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5797         if (r) {
5798                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5799                 gfx_v10_0_ce_fini(adev);
5800                 return r;
5801         }
5802
5803         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5804
5805         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5806         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5807
5808         /* Trigger an invalidation of the L1 instruction caches */
5809         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5810         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5811         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5812
5813         /* Wait for invalidation complete */
5814         for (i = 0; i < usec_timeout; i++) {
5815                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5816                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5817                         INVALIDATE_CACHE_COMPLETE))
5818                         break;
5819                 udelay(1);
5820         }
5821
5822         if (i >= usec_timeout) {
5823                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5824                 return -EINVAL;
5825         }
5826
5827         if (amdgpu_emu_mode == 1)
5828                 adev->hdp.funcs->flush_hdp(adev, NULL);
5829
5830         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5831         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5832         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5833         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5834         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5835         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5836                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5837         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5838                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5839
5840         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5841
5842         for (i = 0; i < ce_hdr->jt_size; i++)
5843                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5844                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5845
5846         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5847
5848         return 0;
5849 }
5850
5851 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5852 {
5853         int r;
5854         const struct gfx_firmware_header_v1_0 *me_hdr;
5855         const __le32 *fw_data;
5856         unsigned int i, fw_size;
5857         uint32_t tmp;
5858         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5859
5860         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5861                 adev->gfx.me_fw->data;
5862
5863         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5864
5865         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5866                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5867         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5868
5869         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5870                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5871                                       &adev->gfx.me.me_fw_obj,
5872                                       &adev->gfx.me.me_fw_gpu_addr,
5873                                       (void **)&adev->gfx.me.me_fw_ptr);
5874         if (r) {
5875                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5876                 gfx_v10_0_me_fini(adev);
5877                 return r;
5878         }
5879
5880         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5881
5882         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5883         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5884
5885         /* Trigger an invalidation of the L1 instruction caches */
5886         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5887         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5888         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5889
5890         /* Wait for invalidation complete */
5891         for (i = 0; i < usec_timeout; i++) {
5892                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5893                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5894                         INVALIDATE_CACHE_COMPLETE))
5895                         break;
5896                 udelay(1);
5897         }
5898
5899         if (i >= usec_timeout) {
5900                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5901                 return -EINVAL;
5902         }
5903
5904         if (amdgpu_emu_mode == 1)
5905                 adev->hdp.funcs->flush_hdp(adev, NULL);
5906
5907         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5908         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5909         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5910         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5911         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5912         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5913                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5914         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5915                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5916
5917         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5918
5919         for (i = 0; i < me_hdr->jt_size; i++)
5920                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5921                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5922
5923         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5924
5925         return 0;
5926 }
5927
5928 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5929 {
5930         int r;
5931
5932         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5933                 return -EINVAL;
5934
5935         gfx_v10_0_cp_gfx_enable(adev, false);
5936
5937         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5938         if (r) {
5939                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5940                 return r;
5941         }
5942
5943         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5944         if (r) {
5945                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5946                 return r;
5947         }
5948
5949         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5950         if (r) {
5951                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5952                 return r;
5953         }
5954
5955         return 0;
5956 }
5957
5958 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5959 {
5960         struct amdgpu_ring *ring;
5961         const struct cs_section_def *sect = NULL;
5962         const struct cs_extent_def *ext = NULL;
5963         int r, i;
5964         int ctx_reg_offset;
5965
5966         /* init the CP */
5967         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5968                      adev->gfx.config.max_hw_contexts - 1);
5969         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5970
5971         gfx_v10_0_cp_gfx_enable(adev, true);
5972
5973         ring = &adev->gfx.gfx_ring[0];
5974         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5975         if (r) {
5976                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5977                 return r;
5978         }
5979
5980         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5981         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5982
5983         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5984         amdgpu_ring_write(ring, 0x80000000);
5985         amdgpu_ring_write(ring, 0x80000000);
5986
5987         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5988                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5989                         if (sect->id == SECT_CONTEXT) {
5990                                 amdgpu_ring_write(ring,
5991                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5992                                                           ext->reg_count));
5993                                 amdgpu_ring_write(ring, ext->reg_index -
5994                                                   PACKET3_SET_CONTEXT_REG_START);
5995                                 for (i = 0; i < ext->reg_count; i++)
5996                                         amdgpu_ring_write(ring, ext->extent[i]);
5997                         }
5998                 }
5999         }
6000
6001         ctx_reg_offset =
6002                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6003         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6004         amdgpu_ring_write(ring, ctx_reg_offset);
6005         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6006
6007         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6008         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6009
6010         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6011         amdgpu_ring_write(ring, 0);
6012
6013         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6014         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6015         amdgpu_ring_write(ring, 0x8000);
6016         amdgpu_ring_write(ring, 0x8000);
6017
6018         amdgpu_ring_commit(ring);
6019
6020         /* submit cs packet to copy state 0 to next available state */
6021         if (adev->gfx.num_gfx_rings > 1) {
6022                 /* maximum supported gfx ring is 2 */
6023                 ring = &adev->gfx.gfx_ring[1];
6024                 r = amdgpu_ring_alloc(ring, 2);
6025                 if (r) {
6026                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6027                         return r;
6028                 }
6029
6030                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6031                 amdgpu_ring_write(ring, 0);
6032
6033                 amdgpu_ring_commit(ring);
6034         }
6035         return 0;
6036 }
6037
6038 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6039                                          CP_PIPE_ID pipe)
6040 {
6041         u32 tmp;
6042
6043         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6044         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6045
6046         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6047 }
6048
6049 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6050                                           struct amdgpu_ring *ring)
6051 {
6052         u32 tmp;
6053
6054         if (!amdgpu_async_gfx_ring) {
6055                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6056                 if (ring->use_doorbell) {
6057                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6058                                                 DOORBELL_OFFSET, ring->doorbell_index);
6059                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6060                                                 DOORBELL_EN, 1);
6061                 } else {
6062                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6063                                                 DOORBELL_EN, 0);
6064                 }
6065                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6066         }
6067         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6068         case IP_VERSION(10, 3, 0):
6069         case IP_VERSION(10, 3, 2):
6070         case IP_VERSION(10, 3, 1):
6071         case IP_VERSION(10, 3, 4):
6072         case IP_VERSION(10, 3, 5):
6073         case IP_VERSION(10, 3, 6):
6074         case IP_VERSION(10, 3, 3):
6075         case IP_VERSION(10, 3, 7):
6076                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6077                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6078                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6079
6080                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6081                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6082                 break;
6083         default:
6084                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6085                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6086                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6087
6088                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6089                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6090                 break;
6091         }
6092 }
6093
6094 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6095 {
6096         struct amdgpu_ring *ring;
6097         u32 tmp;
6098         u32 rb_bufsz;
6099         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6100
6101         /* Set the write pointer delay */
6102         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6103
6104         /* set the RB to use vmid 0 */
6105         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6106
6107         /* Init gfx ring 0 for pipe 0 */
6108         mutex_lock(&adev->srbm_mutex);
6109         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6110
6111         /* Set ring buffer size */
6112         ring = &adev->gfx.gfx_ring[0];
6113         rb_bufsz = order_base_2(ring->ring_size / 8);
6114         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6115         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6116 #ifdef __BIG_ENDIAN
6117         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6118 #endif
6119         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6120
6121         /* Initialize the ring buffer's write pointers */
6122         ring->wptr = 0;
6123         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6124         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6125
6126         /* set the wb address wether it's enabled or not */
6127         rptr_addr = ring->rptr_gpu_addr;
6128         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6129         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6130                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6131
6132         wptr_gpu_addr = ring->wptr_gpu_addr;
6133         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6134                      lower_32_bits(wptr_gpu_addr));
6135         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6136                      upper_32_bits(wptr_gpu_addr));
6137
6138         mdelay(1);
6139         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6140
6141         rb_addr = ring->gpu_addr >> 8;
6142         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6143         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6144
6145         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6146
6147         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6148         mutex_unlock(&adev->srbm_mutex);
6149
6150         /* Init gfx ring 1 for pipe 1 */
6151         if (adev->gfx.num_gfx_rings > 1) {
6152                 mutex_lock(&adev->srbm_mutex);
6153                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6154                 /* maximum supported gfx ring is 2 */
6155                 ring = &adev->gfx.gfx_ring[1];
6156                 rb_bufsz = order_base_2(ring->ring_size / 8);
6157                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6158                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6159                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6160                 /* Initialize the ring buffer's write pointers */
6161                 ring->wptr = 0;
6162                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6163                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6164                 /* Set the wb address wether it's enabled or not */
6165                 rptr_addr = ring->rptr_gpu_addr;
6166                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6167                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6168                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6169                 wptr_gpu_addr = ring->wptr_gpu_addr;
6170                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6171                              lower_32_bits(wptr_gpu_addr));
6172                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6173                              upper_32_bits(wptr_gpu_addr));
6174
6175                 mdelay(1);
6176                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6177
6178                 rb_addr = ring->gpu_addr >> 8;
6179                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6180                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6181                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6182
6183                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6184                 mutex_unlock(&adev->srbm_mutex);
6185         }
6186         /* Switch to pipe 0 */
6187         mutex_lock(&adev->srbm_mutex);
6188         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6189         mutex_unlock(&adev->srbm_mutex);
6190
6191         /* start the ring */
6192         gfx_v10_0_cp_gfx_start(adev);
6193
6194         return 0;
6195 }
6196
6197 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6198 {
6199         if (enable) {
6200                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6201                 case IP_VERSION(10, 3, 0):
6202                 case IP_VERSION(10, 3, 2):
6203                 case IP_VERSION(10, 3, 1):
6204                 case IP_VERSION(10, 3, 4):
6205                 case IP_VERSION(10, 3, 5):
6206                 case IP_VERSION(10, 3, 6):
6207                 case IP_VERSION(10, 3, 3):
6208                 case IP_VERSION(10, 3, 7):
6209                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6210                         break;
6211                 default:
6212                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6213                         break;
6214                 }
6215         } else {
6216                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6217                 case IP_VERSION(10, 3, 0):
6218                 case IP_VERSION(10, 3, 2):
6219                 case IP_VERSION(10, 3, 1):
6220                 case IP_VERSION(10, 3, 4):
6221                 case IP_VERSION(10, 3, 5):
6222                 case IP_VERSION(10, 3, 6):
6223                 case IP_VERSION(10, 3, 3):
6224                 case IP_VERSION(10, 3, 7):
6225                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6226                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6227                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6228                         break;
6229                 default:
6230                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6231                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6232                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6233                         break;
6234                 }
6235                 adev->gfx.kiq[0].ring.sched.ready = false;
6236         }
6237         udelay(50);
6238 }
6239
6240 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6241 {
6242         const struct gfx_firmware_header_v1_0 *mec_hdr;
6243         const __le32 *fw_data;
6244         unsigned int i;
6245         u32 tmp;
6246         u32 usec_timeout = 50000; /* Wait for 50 ms */
6247
6248         if (!adev->gfx.mec_fw)
6249                 return -EINVAL;
6250
6251         gfx_v10_0_cp_compute_enable(adev, false);
6252
6253         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6254         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6255
6256         fw_data = (const __le32 *)
6257                 (adev->gfx.mec_fw->data +
6258                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6259
6260         /* Trigger an invalidation of the L1 instruction caches */
6261         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6262         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6263         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6264
6265         /* Wait for invalidation complete */
6266         for (i = 0; i < usec_timeout; i++) {
6267                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6268                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6269                                        INVALIDATE_CACHE_COMPLETE))
6270                         break;
6271                 udelay(1);
6272         }
6273
6274         if (i >= usec_timeout) {
6275                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6276                 return -EINVAL;
6277         }
6278
6279         if (amdgpu_emu_mode == 1)
6280                 adev->hdp.funcs->flush_hdp(adev, NULL);
6281
6282         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6283         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6284         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6285         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6286         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6287
6288         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6289                      0xFFFFF000);
6290         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6291                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6292
6293         /* MEC1 */
6294         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6295
6296         for (i = 0; i < mec_hdr->jt_size; i++)
6297                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6298                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6299
6300         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6301
6302         /*
6303          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6304          * different microcode than MEC1.
6305          */
6306
6307         return 0;
6308 }
6309
6310 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6311 {
6312         uint32_t tmp;
6313         struct amdgpu_device *adev = ring->adev;
6314
6315         /* tell RLC which is KIQ queue */
6316         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6317         case IP_VERSION(10, 3, 0):
6318         case IP_VERSION(10, 3, 2):
6319         case IP_VERSION(10, 3, 1):
6320         case IP_VERSION(10, 3, 4):
6321         case IP_VERSION(10, 3, 5):
6322         case IP_VERSION(10, 3, 6):
6323         case IP_VERSION(10, 3, 3):
6324         case IP_VERSION(10, 3, 7):
6325                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6326                 tmp &= 0xffffff00;
6327                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6328                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6329                 tmp |= 0x80;
6330                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6331                 break;
6332         default:
6333                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6334                 tmp &= 0xffffff00;
6335                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6336                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6337                 tmp |= 0x80;
6338                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6339                 break;
6340         }
6341 }
6342
6343 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6344                                            struct v10_gfx_mqd *mqd,
6345                                            struct amdgpu_mqd_prop *prop)
6346 {
6347         bool priority = 0;
6348         u32 tmp;
6349
6350         /* set up default queue priority level
6351          * 0x0 = low priority, 0x1 = high priority
6352          */
6353         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6354                 priority = 1;
6355
6356         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6357         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6358         mqd->cp_gfx_hqd_queue_priority = tmp;
6359 }
6360
6361 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6362                                   struct amdgpu_mqd_prop *prop)
6363 {
6364         struct v10_gfx_mqd *mqd = m;
6365         uint64_t hqd_gpu_addr, wb_gpu_addr;
6366         uint32_t tmp;
6367         uint32_t rb_bufsz;
6368
6369         /* set up gfx hqd wptr */
6370         mqd->cp_gfx_hqd_wptr = 0;
6371         mqd->cp_gfx_hqd_wptr_hi = 0;
6372
6373         /* set the pointer to the MQD */
6374         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6375         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6376
6377         /* set up mqd control */
6378         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6379         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6380         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6381         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6382         mqd->cp_gfx_mqd_control = tmp;
6383
6384         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6385         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6386         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6387         mqd->cp_gfx_hqd_vmid = 0;
6388
6389         /* set up gfx queue priority */
6390         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6391
6392         /* set up time quantum */
6393         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6394         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6395         mqd->cp_gfx_hqd_quantum = tmp;
6396
6397         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6398         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6399         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6400         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6401
6402         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6403         wb_gpu_addr = prop->rptr_gpu_addr;
6404         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6405         mqd->cp_gfx_hqd_rptr_addr_hi =
6406                 upper_32_bits(wb_gpu_addr) & 0xffff;
6407
6408         /* set up rb_wptr_poll addr */
6409         wb_gpu_addr = prop->wptr_gpu_addr;
6410         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6411         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6412
6413         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6414         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6415         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6416         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6417         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6418 #ifdef __BIG_ENDIAN
6419         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6420 #endif
6421         mqd->cp_gfx_hqd_cntl = tmp;
6422
6423         /* set up cp_doorbell_control */
6424         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6425         if (prop->use_doorbell) {
6426                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6427                                     DOORBELL_OFFSET, prop->doorbell_index);
6428                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6429                                     DOORBELL_EN, 1);
6430         } else
6431                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6432                                     DOORBELL_EN, 0);
6433         mqd->cp_rb_doorbell_control = tmp;
6434
6435         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6436         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6437
6438         /* active the queue */
6439         mqd->cp_gfx_hqd_active = 1;
6440
6441         return 0;
6442 }
6443
6444 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6445 {
6446         struct amdgpu_device *adev = ring->adev;
6447         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6448         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6449
6450         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6451                 memset((void *)mqd, 0, sizeof(*mqd));
6452                 mutex_lock(&adev->srbm_mutex);
6453                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6454                 amdgpu_ring_init_mqd(ring);
6455
6456                 /*
6457                  * if there are 2 gfx rings, set the lower doorbell
6458                  * range of the first ring, otherwise the range of
6459                  * the second ring will override the first ring
6460                  */
6461                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6462                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6463
6464                 nv_grbm_select(adev, 0, 0, 0, 0);
6465                 mutex_unlock(&adev->srbm_mutex);
6466                 if (adev->gfx.me.mqd_backup[mqd_idx])
6467                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6468         } else {
6469                 mutex_lock(&adev->srbm_mutex);
6470                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6471                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6472                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6473
6474                 nv_grbm_select(adev, 0, 0, 0, 0);
6475                 mutex_unlock(&adev->srbm_mutex);
6476                 /* restore mqd with the backup copy */
6477                 if (adev->gfx.me.mqd_backup[mqd_idx])
6478                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6479                 /* reset the ring */
6480                 ring->wptr = 0;
6481                 *ring->wptr_cpu_addr = 0;
6482                 amdgpu_ring_clear_ring(ring);
6483         }
6484
6485         return 0;
6486 }
6487
6488 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6489 {
6490         int r, i;
6491         struct amdgpu_ring *ring;
6492
6493         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6494                 ring = &adev->gfx.gfx_ring[i];
6495
6496                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6497                 if (unlikely(r != 0))
6498                         return r;
6499
6500                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6501                 if (!r) {
6502                         r = gfx_v10_0_gfx_init_queue(ring);
6503                         amdgpu_bo_kunmap(ring->mqd_obj);
6504                         ring->mqd_ptr = NULL;
6505                 }
6506                 amdgpu_bo_unreserve(ring->mqd_obj);
6507                 if (r)
6508                         return r;
6509         }
6510
6511         r = amdgpu_gfx_enable_kgq(adev, 0);
6512         if (r)
6513                 return r;
6514
6515         return gfx_v10_0_cp_gfx_start(adev);
6516 }
6517
6518 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6519                                       struct amdgpu_mqd_prop *prop)
6520 {
6521         struct v10_compute_mqd *mqd = m;
6522         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6523         uint32_t tmp;
6524
6525         mqd->header = 0xC0310800;
6526         mqd->compute_pipelinestat_enable = 0x00000001;
6527         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6528         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6529         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6530         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6531         mqd->compute_misc_reserved = 0x00000003;
6532
6533         eop_base_addr = prop->eop_gpu_addr >> 8;
6534         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6535         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6536
6537         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6538         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6539         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6540                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6541
6542         mqd->cp_hqd_eop_control = tmp;
6543
6544         /* enable doorbell? */
6545         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6546
6547         if (prop->use_doorbell) {
6548                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6549                                     DOORBELL_OFFSET, prop->doorbell_index);
6550                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6551                                     DOORBELL_EN, 1);
6552                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6553                                     DOORBELL_SOURCE, 0);
6554                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6555                                     DOORBELL_HIT, 0);
6556         } else {
6557                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6558                                     DOORBELL_EN, 0);
6559         }
6560
6561         mqd->cp_hqd_pq_doorbell_control = tmp;
6562
6563         /* disable the queue if it's active */
6564         mqd->cp_hqd_dequeue_request = 0;
6565         mqd->cp_hqd_pq_rptr = 0;
6566         mqd->cp_hqd_pq_wptr_lo = 0;
6567         mqd->cp_hqd_pq_wptr_hi = 0;
6568
6569         /* set the pointer to the MQD */
6570         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6571         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6572
6573         /* set MQD vmid to 0 */
6574         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6575         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6576         mqd->cp_mqd_control = tmp;
6577
6578         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6579         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6580         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6581         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6582
6583         /* set up the HQD, this is similar to CP_RB0_CNTL */
6584         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6585         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6586                             (order_base_2(prop->queue_size / 4) - 1));
6587         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6588                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6589 #ifdef __BIG_ENDIAN
6590         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6591 #endif
6592         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6593         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6594                             prop->allow_tunneling);
6595         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6596         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6597         mqd->cp_hqd_pq_control = tmp;
6598
6599         /* set the wb address whether it's enabled or not */
6600         wb_gpu_addr = prop->rptr_gpu_addr;
6601         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6602         mqd->cp_hqd_pq_rptr_report_addr_hi =
6603                 upper_32_bits(wb_gpu_addr) & 0xffff;
6604
6605         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6606         wb_gpu_addr = prop->wptr_gpu_addr;
6607         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6608         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6609
6610         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6611         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6612
6613         /* set the vmid for the queue */
6614         mqd->cp_hqd_vmid = 0;
6615
6616         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6617         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6618         mqd->cp_hqd_persistent_state = tmp;
6619
6620         /* set MIN_IB_AVAIL_SIZE */
6621         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6622         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6623         mqd->cp_hqd_ib_control = tmp;
6624
6625         /* set static priority for a compute queue/ring */
6626         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6627         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6628
6629         mqd->cp_hqd_active = prop->hqd_active;
6630
6631         return 0;
6632 }
6633
6634 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6635 {
6636         struct amdgpu_device *adev = ring->adev;
6637         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6638         int j;
6639
6640         /* inactivate the queue */
6641         if (amdgpu_sriov_vf(adev))
6642                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6643
6644         /* disable wptr polling */
6645         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6646
6647         /* disable the queue if it's active */
6648         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6649                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6650                 for (j = 0; j < adev->usec_timeout; j++) {
6651                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6652                                 break;
6653                         udelay(1);
6654                 }
6655                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6656                        mqd->cp_hqd_dequeue_request);
6657                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6658                        mqd->cp_hqd_pq_rptr);
6659                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6660                        mqd->cp_hqd_pq_wptr_lo);
6661                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6662                        mqd->cp_hqd_pq_wptr_hi);
6663         }
6664
6665         /* disable doorbells */
6666         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6667
6668         /* write the EOP addr */
6669         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6670                mqd->cp_hqd_eop_base_addr_lo);
6671         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6672                mqd->cp_hqd_eop_base_addr_hi);
6673
6674         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6675         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6676                mqd->cp_hqd_eop_control);
6677
6678         /* set the pointer to the MQD */
6679         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6680                mqd->cp_mqd_base_addr_lo);
6681         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6682                mqd->cp_mqd_base_addr_hi);
6683
6684         /* set MQD vmid to 0 */
6685         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6686                mqd->cp_mqd_control);
6687
6688         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6689         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6690                mqd->cp_hqd_pq_base_lo);
6691         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6692                mqd->cp_hqd_pq_base_hi);
6693
6694         /* set up the HQD, this is similar to CP_RB0_CNTL */
6695         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6696                mqd->cp_hqd_pq_control);
6697
6698         /* set the wb address whether it's enabled or not */
6699         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6700                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6701         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6702                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6703
6704         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6705         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6706                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6707         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6708                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6709
6710         /* enable the doorbell if requested */
6711         if (ring->use_doorbell) {
6712                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6713                         (adev->doorbell_index.kiq * 2) << 2);
6714                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6715                         (adev->doorbell_index.userqueue_end * 2) << 2);
6716         }
6717
6718         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6719                mqd->cp_hqd_pq_doorbell_control);
6720
6721         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6722         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6723                mqd->cp_hqd_pq_wptr_lo);
6724         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6725                mqd->cp_hqd_pq_wptr_hi);
6726
6727         /* set the vmid for the queue */
6728         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6729
6730         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6731                mqd->cp_hqd_persistent_state);
6732
6733         /* activate the queue */
6734         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6735                mqd->cp_hqd_active);
6736
6737         if (ring->use_doorbell)
6738                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6739
6740         return 0;
6741 }
6742
6743 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6744 {
6745         struct amdgpu_device *adev = ring->adev;
6746         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6747
6748         gfx_v10_0_kiq_setting(ring);
6749
6750         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6751                 /* reset MQD to a clean status */
6752                 if (adev->gfx.kiq[0].mqd_backup)
6753                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6754
6755                 /* reset ring buffer */
6756                 ring->wptr = 0;
6757                 amdgpu_ring_clear_ring(ring);
6758
6759                 mutex_lock(&adev->srbm_mutex);
6760                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6761                 gfx_v10_0_kiq_init_register(ring);
6762                 nv_grbm_select(adev, 0, 0, 0, 0);
6763                 mutex_unlock(&adev->srbm_mutex);
6764         } else {
6765                 memset((void *)mqd, 0, sizeof(*mqd));
6766                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6767                         amdgpu_ring_clear_ring(ring);
6768                 mutex_lock(&adev->srbm_mutex);
6769                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6770                 amdgpu_ring_init_mqd(ring);
6771                 gfx_v10_0_kiq_init_register(ring);
6772                 nv_grbm_select(adev, 0, 0, 0, 0);
6773                 mutex_unlock(&adev->srbm_mutex);
6774
6775                 if (adev->gfx.kiq[0].mqd_backup)
6776                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6777         }
6778
6779         return 0;
6780 }
6781
6782 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6783 {
6784         struct amdgpu_device *adev = ring->adev;
6785         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6786         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6787
6788         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6789                 memset((void *)mqd, 0, sizeof(*mqd));
6790                 mutex_lock(&adev->srbm_mutex);
6791                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6792                 amdgpu_ring_init_mqd(ring);
6793                 nv_grbm_select(adev, 0, 0, 0, 0);
6794                 mutex_unlock(&adev->srbm_mutex);
6795
6796                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6797                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6798         } else {
6799                 /* restore MQD to a clean status */
6800                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6801                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6802                 /* reset ring buffer */
6803                 ring->wptr = 0;
6804                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6805                 amdgpu_ring_clear_ring(ring);
6806         }
6807
6808         return 0;
6809 }
6810
6811 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6812 {
6813         struct amdgpu_ring *ring;
6814         int r;
6815
6816         ring = &adev->gfx.kiq[0].ring;
6817
6818         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6819         if (unlikely(r != 0))
6820                 return r;
6821
6822         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6823         if (unlikely(r != 0)) {
6824                 amdgpu_bo_unreserve(ring->mqd_obj);
6825                 return r;
6826         }
6827
6828         gfx_v10_0_kiq_init_queue(ring);
6829         amdgpu_bo_kunmap(ring->mqd_obj);
6830         ring->mqd_ptr = NULL;
6831         amdgpu_bo_unreserve(ring->mqd_obj);
6832         return 0;
6833 }
6834
6835 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6836 {
6837         struct amdgpu_ring *ring = NULL;
6838         int r = 0, i;
6839
6840         gfx_v10_0_cp_compute_enable(adev, true);
6841
6842         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6843                 ring = &adev->gfx.compute_ring[i];
6844
6845                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6846                 if (unlikely(r != 0))
6847                         goto done;
6848                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6849                 if (!r) {
6850                         r = gfx_v10_0_kcq_init_queue(ring);
6851                         amdgpu_bo_kunmap(ring->mqd_obj);
6852                         ring->mqd_ptr = NULL;
6853                 }
6854                 amdgpu_bo_unreserve(ring->mqd_obj);
6855                 if (r)
6856                         goto done;
6857         }
6858
6859         r = amdgpu_gfx_enable_kcq(adev, 0);
6860 done:
6861         return r;
6862 }
6863
6864 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6865 {
6866         int r, i;
6867         struct amdgpu_ring *ring;
6868
6869         if (!(adev->flags & AMD_IS_APU))
6870                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6871
6872         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6873                 /* legacy firmware loading */
6874                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6875                 if (r)
6876                         return r;
6877
6878                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6879                 if (r)
6880                         return r;
6881         }
6882
6883         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
6884                 r = amdgpu_mes_kiq_hw_init(adev);
6885         else
6886                 r = gfx_v10_0_kiq_resume(adev);
6887         if (r)
6888                 return r;
6889
6890         r = gfx_v10_0_kcq_resume(adev);
6891         if (r)
6892                 return r;
6893
6894         if (!amdgpu_async_gfx_ring) {
6895                 r = gfx_v10_0_cp_gfx_resume(adev);
6896                 if (r)
6897                         return r;
6898         } else {
6899                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6900                 if (r)
6901                         return r;
6902         }
6903
6904         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6905                 ring = &adev->gfx.gfx_ring[i];
6906                 r = amdgpu_ring_test_helper(ring);
6907                 if (r)
6908                         return r;
6909         }
6910
6911         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6912                 ring = &adev->gfx.compute_ring[i];
6913                 r = amdgpu_ring_test_helper(ring);
6914                 if (r)
6915                         return r;
6916         }
6917
6918         return 0;
6919 }
6920
6921 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6922 {
6923         gfx_v10_0_cp_gfx_enable(adev, enable);
6924         gfx_v10_0_cp_compute_enable(adev, enable);
6925 }
6926
6927 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6928 {
6929         uint32_t data, pattern = 0xDEADBEEF;
6930
6931         /*
6932          * check if mmVGT_ESGS_RING_SIZE_UMD
6933          * has been remapped to mmVGT_ESGS_RING_SIZE
6934          */
6935         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6936         case IP_VERSION(10, 3, 0):
6937         case IP_VERSION(10, 3, 2):
6938         case IP_VERSION(10, 3, 4):
6939         case IP_VERSION(10, 3, 5):
6940                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6941                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6942                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6943
6944                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6945                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6946                         return true;
6947                 }
6948                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6949                 break;
6950         case IP_VERSION(10, 3, 1):
6951         case IP_VERSION(10, 3, 3):
6952         case IP_VERSION(10, 3, 6):
6953         case IP_VERSION(10, 3, 7):
6954                 return true;
6955         default:
6956                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6957                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6958                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6959
6960                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6961                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6962                         return true;
6963                 }
6964                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6965                 break;
6966         }
6967
6968         return false;
6969 }
6970
6971 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6972 {
6973         uint32_t data;
6974
6975         if (amdgpu_sriov_vf(adev))
6976                 return;
6977
6978         /*
6979          * Initialize cam_index to 0
6980          * index will auto-inc after each data writing
6981          */
6982         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6983
6984         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6985         case IP_VERSION(10, 3, 0):
6986         case IP_VERSION(10, 3, 2):
6987         case IP_VERSION(10, 3, 1):
6988         case IP_VERSION(10, 3, 4):
6989         case IP_VERSION(10, 3, 5):
6990         case IP_VERSION(10, 3, 6):
6991         case IP_VERSION(10, 3, 3):
6992         case IP_VERSION(10, 3, 7):
6993                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6994                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6995                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6996                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6997                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6998                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6999                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7000
7001                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7002                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7003                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7004                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7005                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7006                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7007                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7008
7009                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7010                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7011                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7012                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7013                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7014                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7015                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7016
7017                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7018                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7019                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7020                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7021                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7022                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7023                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7024
7025                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7026                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7027                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7028                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7029                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7030                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7031                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7032
7033                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7034                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7035                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7036                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7037                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7038                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7039                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7040
7041                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7042                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7043                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7044                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7045                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7046                 break;
7047         default:
7048                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7049                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7050                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7051                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7052                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7053                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7054                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7055
7056                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7057                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7058                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7059                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7060                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7061                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7062                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7063
7064                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7065                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7066                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7067                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7068                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7069                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7070                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7071
7072                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7073                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7074                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7075                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7076                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7077                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7078                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7079
7080                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7081                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7082                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7083                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7084                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7085                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7086                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7087
7088                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7089                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7090                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7091                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7092                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7093                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7094                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7095
7096                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7097                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7098                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7099                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7100                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7101                 break;
7102         }
7103
7104         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7105         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7106 }
7107
7108 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7109 {
7110         uint32_t data;
7111
7112         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7113         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7114         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7115
7116         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7117         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7118         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7119 }
7120
7121 static int gfx_v10_0_hw_init(void *handle)
7122 {
7123         int r;
7124         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7125
7126         if (!amdgpu_emu_mode)
7127                 gfx_v10_0_init_golden_registers(adev);
7128
7129         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7130                 /**
7131                  * For gfx 10, rlc firmware loading relies on smu firmware is
7132                  * loaded firstly, so in direct type, it has to load smc ucode
7133                  * here before rlc.
7134                  */
7135                 if (!(adev->flags & AMD_IS_APU)) {
7136                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7137                         if (r)
7138                                 return r;
7139                 }
7140                 gfx_v10_0_disable_gpa_mode(adev);
7141         }
7142
7143         /* if GRBM CAM not remapped, set up the remapping */
7144         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7145                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7146
7147         gfx_v10_0_constants_init(adev);
7148
7149         r = gfx_v10_0_rlc_resume(adev);
7150         if (r)
7151                 return r;
7152
7153         /*
7154          * init golden registers and rlc resume may override some registers,
7155          * reconfig them here
7156          */
7157         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7158             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7159             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7160                 gfx_v10_0_tcp_harvest(adev);
7161
7162         r = gfx_v10_0_cp_resume(adev);
7163         if (r)
7164                 return r;
7165
7166         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7167                 gfx_v10_3_program_pbb_mode(adev);
7168
7169         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
7170                 gfx_v10_3_set_power_brake_sequence(adev);
7171
7172         return r;
7173 }
7174
7175 static int gfx_v10_0_hw_fini(void *handle)
7176 {
7177         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7178
7179         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7180         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7181
7182         /* WA added for Vangogh asic fixing the SMU suspend failure
7183          * It needs to set power gating again during gfxoff control
7184          * otherwise the gfxoff disallowing will be failed to set.
7185          */
7186         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7187                 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
7188
7189         if (!adev->no_hw_access) {
7190                 if (amdgpu_async_gfx_ring) {
7191                         if (amdgpu_gfx_disable_kgq(adev, 0))
7192                                 DRM_ERROR("KGQ disable failed\n");
7193                 }
7194
7195                 if (amdgpu_gfx_disable_kcq(adev, 0))
7196                         DRM_ERROR("KCQ disable failed\n");
7197         }
7198
7199         if (amdgpu_sriov_vf(adev)) {
7200                 gfx_v10_0_cp_gfx_enable(adev, false);
7201                 /* Remove the steps of clearing KIQ position.
7202                  * It causes GFX hang when another Win guest is rendering.
7203                  */
7204                 return 0;
7205         }
7206         gfx_v10_0_cp_enable(adev, false);
7207         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7208
7209         return 0;
7210 }
7211
7212 static int gfx_v10_0_suspend(void *handle)
7213 {
7214         return gfx_v10_0_hw_fini(handle);
7215 }
7216
7217 static int gfx_v10_0_resume(void *handle)
7218 {
7219         return gfx_v10_0_hw_init(handle);
7220 }
7221
7222 static bool gfx_v10_0_is_idle(void *handle)
7223 {
7224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7225
7226         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7227                                 GRBM_STATUS, GUI_ACTIVE))
7228                 return false;
7229         else
7230                 return true;
7231 }
7232
7233 static int gfx_v10_0_wait_for_idle(void *handle)
7234 {
7235         unsigned int i;
7236         u32 tmp;
7237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7238
7239         for (i = 0; i < adev->usec_timeout; i++) {
7240                 /* read MC_STATUS */
7241                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7242                         GRBM_STATUS__GUI_ACTIVE_MASK;
7243
7244                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7245                         return 0;
7246                 udelay(1);
7247         }
7248         return -ETIMEDOUT;
7249 }
7250
7251 static int gfx_v10_0_soft_reset(void *handle)
7252 {
7253         u32 grbm_soft_reset = 0;
7254         u32 tmp;
7255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7256
7257         /* GRBM_STATUS */
7258         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7259         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7260                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7261                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7262                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7263                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7264                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7265                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7266                                                 1);
7267                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7268                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7269                                                 1);
7270         }
7271
7272         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7273                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7274                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7275                                                 1);
7276         }
7277
7278         /* GRBM_STATUS2 */
7279         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7280         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7281         case IP_VERSION(10, 3, 0):
7282         case IP_VERSION(10, 3, 2):
7283         case IP_VERSION(10, 3, 1):
7284         case IP_VERSION(10, 3, 4):
7285         case IP_VERSION(10, 3, 5):
7286         case IP_VERSION(10, 3, 6):
7287         case IP_VERSION(10, 3, 3):
7288                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7289                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7290                                                         GRBM_SOFT_RESET,
7291                                                         SOFT_RESET_RLC,
7292                                                         1);
7293                 break;
7294         default:
7295                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7296                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7297                                                         GRBM_SOFT_RESET,
7298                                                         SOFT_RESET_RLC,
7299                                                         1);
7300                 break;
7301         }
7302
7303         if (grbm_soft_reset) {
7304                 /* stop the rlc */
7305                 gfx_v10_0_rlc_stop(adev);
7306
7307                 /* Disable GFX parsing/prefetching */
7308                 gfx_v10_0_cp_gfx_enable(adev, false);
7309
7310                 /* Disable MEC parsing/prefetching */
7311                 gfx_v10_0_cp_compute_enable(adev, false);
7312
7313                 if (grbm_soft_reset) {
7314                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7315                         tmp |= grbm_soft_reset;
7316                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7317                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7318                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7319
7320                         udelay(50);
7321
7322                         tmp &= ~grbm_soft_reset;
7323                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7324                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7325                 }
7326
7327                 /* Wait a little for things to settle down */
7328                 udelay(50);
7329         }
7330         return 0;
7331 }
7332
7333 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7334 {
7335         uint64_t clock, clock_lo, clock_hi, hi_check;
7336
7337         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7338         case IP_VERSION(10, 1, 3):
7339         case IP_VERSION(10, 1, 4):
7340                 preempt_disable();
7341                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7342                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7343                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7344                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7345                  * roughly every 42 seconds.
7346                  */
7347                 if (hi_check != clock_hi) {
7348                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7349                         clock_hi = hi_check;
7350                 }
7351                 preempt_enable();
7352                 clock = clock_lo | (clock_hi << 32ULL);
7353                 break;
7354         case IP_VERSION(10, 3, 1):
7355         case IP_VERSION(10, 3, 3):
7356         case IP_VERSION(10, 3, 7):
7357                 preempt_disable();
7358                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7359                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7360                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7361                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7362                  * roughly every 42 seconds.
7363                  */
7364                 if (hi_check != clock_hi) {
7365                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7366                         clock_hi = hi_check;
7367                 }
7368                 preempt_enable();
7369                 clock = clock_lo | (clock_hi << 32ULL);
7370                 break;
7371         case IP_VERSION(10, 3, 6):
7372                 preempt_disable();
7373                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7374                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7375                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7376                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7377                  * roughly every 42 seconds.
7378                  */
7379                 if (hi_check != clock_hi) {
7380                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7381                         clock_hi = hi_check;
7382                 }
7383                 preempt_enable();
7384                 clock = clock_lo | (clock_hi << 32ULL);
7385                 break;
7386         default:
7387                 preempt_disable();
7388                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7389                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7390                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7391                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7392                  * roughly every 42 seconds.
7393                  */
7394                 if (hi_check != clock_hi) {
7395                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7396                         clock_hi = hi_check;
7397                 }
7398                 preempt_enable();
7399                 clock = clock_lo | (clock_hi << 32ULL);
7400                 break;
7401         }
7402         return clock;
7403 }
7404
7405 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7406                                            uint32_t vmid,
7407                                            uint32_t gds_base, uint32_t gds_size,
7408                                            uint32_t gws_base, uint32_t gws_size,
7409                                            uint32_t oa_base, uint32_t oa_size)
7410 {
7411         struct amdgpu_device *adev = ring->adev;
7412
7413         /* GDS Base */
7414         gfx_v10_0_write_data_to_reg(ring, 0, false,
7415                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7416                                     gds_base);
7417
7418         /* GDS Size */
7419         gfx_v10_0_write_data_to_reg(ring, 0, false,
7420                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7421                                     gds_size);
7422
7423         /* GWS */
7424         gfx_v10_0_write_data_to_reg(ring, 0, false,
7425                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7426                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7427
7428         /* OA */
7429         gfx_v10_0_write_data_to_reg(ring, 0, false,
7430                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7431                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7432 }
7433
7434 static int gfx_v10_0_early_init(void *handle)
7435 {
7436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7437
7438         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7439
7440         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7441         case IP_VERSION(10, 1, 10):
7442         case IP_VERSION(10, 1, 1):
7443         case IP_VERSION(10, 1, 2):
7444         case IP_VERSION(10, 1, 3):
7445         case IP_VERSION(10, 1, 4):
7446                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7447                 break;
7448         case IP_VERSION(10, 3, 0):
7449         case IP_VERSION(10, 3, 2):
7450         case IP_VERSION(10, 3, 1):
7451         case IP_VERSION(10, 3, 4):
7452         case IP_VERSION(10, 3, 5):
7453         case IP_VERSION(10, 3, 6):
7454         case IP_VERSION(10, 3, 3):
7455         case IP_VERSION(10, 3, 7):
7456                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7457                 break;
7458         default:
7459                 break;
7460         }
7461
7462         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7463                                           AMDGPU_MAX_COMPUTE_RINGS);
7464
7465         gfx_v10_0_set_kiq_pm4_funcs(adev);
7466         gfx_v10_0_set_ring_funcs(adev);
7467         gfx_v10_0_set_irq_funcs(adev);
7468         gfx_v10_0_set_gds_init(adev);
7469         gfx_v10_0_set_rlc_funcs(adev);
7470         gfx_v10_0_set_mqd_funcs(adev);
7471
7472         /* init rlcg reg access ctrl */
7473         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7474
7475         return gfx_v10_0_init_microcode(adev);
7476 }
7477
7478 static int gfx_v10_0_late_init(void *handle)
7479 {
7480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7481         int r;
7482
7483         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7484         if (r)
7485                 return r;
7486
7487         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7488         if (r)
7489                 return r;
7490
7491         return 0;
7492 }
7493
7494 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7495 {
7496         uint32_t rlc_cntl;
7497
7498         /* if RLC is not enabled, do nothing */
7499         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7500         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7501 }
7502
7503 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7504 {
7505         uint32_t data;
7506         unsigned int i;
7507
7508         data = RLC_SAFE_MODE__CMD_MASK;
7509         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7510
7511         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7512         case IP_VERSION(10, 3, 0):
7513         case IP_VERSION(10, 3, 2):
7514         case IP_VERSION(10, 3, 1):
7515         case IP_VERSION(10, 3, 4):
7516         case IP_VERSION(10, 3, 5):
7517         case IP_VERSION(10, 3, 6):
7518         case IP_VERSION(10, 3, 3):
7519         case IP_VERSION(10, 3, 7):
7520                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7521
7522                 /* wait for RLC_SAFE_MODE */
7523                 for (i = 0; i < adev->usec_timeout; i++) {
7524                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7525                                            RLC_SAFE_MODE, CMD))
7526                                 break;
7527                         udelay(1);
7528                 }
7529                 break;
7530         default:
7531                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7532
7533                 /* wait for RLC_SAFE_MODE */
7534                 for (i = 0; i < adev->usec_timeout; i++) {
7535                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7536                                            RLC_SAFE_MODE, CMD))
7537                                 break;
7538                         udelay(1);
7539                 }
7540                 break;
7541         }
7542 }
7543
7544 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7545 {
7546         uint32_t data;
7547
7548         data = RLC_SAFE_MODE__CMD_MASK;
7549         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7550         case IP_VERSION(10, 3, 0):
7551         case IP_VERSION(10, 3, 2):
7552         case IP_VERSION(10, 3, 1):
7553         case IP_VERSION(10, 3, 4):
7554         case IP_VERSION(10, 3, 5):
7555         case IP_VERSION(10, 3, 6):
7556         case IP_VERSION(10, 3, 3):
7557         case IP_VERSION(10, 3, 7):
7558                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7559                 break;
7560         default:
7561                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7562                 break;
7563         }
7564 }
7565
7566 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7567                                                       bool enable)
7568 {
7569         uint32_t data, def;
7570
7571         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7572                 return;
7573
7574         /* It is disabled by HW by default */
7575         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7576                 /* 0 - Disable some blocks' MGCG */
7577                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7578                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7579                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7580                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7581
7582                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7583                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7584                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7585                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7586                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7587                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7588                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7589                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7590
7591                 if (def != data)
7592                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7593
7594                 /* MGLS is a global flag to control all MGLS in GFX */
7595                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7596                         /* 2 - RLC memory Light sleep */
7597                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7598                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7599                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7600                                 if (def != data)
7601                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7602                         }
7603                         /* 3 - CP memory Light sleep */
7604                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7605                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7606                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7607                                 if (def != data)
7608                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7609                         }
7610                 }
7611         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7612                 /* 1 - MGCG_OVERRIDE */
7613                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7614                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7615                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7616                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7617                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7618                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7619                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7620                 if (def != data)
7621                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7622
7623                 /* 2 - disable MGLS in CP */
7624                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7625                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7626                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7627                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7628                 }
7629
7630                 /* 3 - disable MGLS in RLC */
7631                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7632                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7633                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7634                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7635                 }
7636
7637         }
7638 }
7639
7640 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7641                                            bool enable)
7642 {
7643         uint32_t data, def;
7644
7645         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7646                 return;
7647
7648         /* Enable 3D CGCG/CGLS */
7649         if (enable) {
7650                 /* write cmd to clear cgcg/cgls ov */
7651                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7652
7653                 /* unset CGCG override */
7654                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7655                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7656
7657                 /* update CGCG and CGLS override bits */
7658                 if (def != data)
7659                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7660
7661                 /* enable 3Dcgcg FSM(0x0000363f) */
7662                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7663                 data = 0;
7664
7665                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7666                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7667                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7668
7669                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7670                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7671                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7672
7673                 if (def != data)
7674                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7675
7676                 /* set IDLE_POLL_COUNT(0x00900100) */
7677                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7678                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7679                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7680                 if (def != data)
7681                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7682         } else {
7683                 /* Disable CGCG/CGLS */
7684                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7685
7686                 /* disable cgcg, cgls should be disabled */
7687                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7688                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7689
7690                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7691                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7692
7693                 /* disable cgcg and cgls in FSM */
7694                 if (def != data)
7695                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7696         }
7697 }
7698
7699 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7700                                                       bool enable)
7701 {
7702         uint32_t def, data;
7703
7704         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7705                 return;
7706
7707         if (enable) {
7708                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7709
7710                 /* unset CGCG override */
7711                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7712                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7713
7714                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7715                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7716
7717                 /* update CGCG and CGLS override bits */
7718                 if (def != data)
7719                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7720
7721                 /* enable cgcg FSM(0x0000363F) */
7722                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7723                 data = 0;
7724
7725                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7726                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7727                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7728
7729                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7730                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7731                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7732
7733                 if (def != data)
7734                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7735
7736                 /* set IDLE_POLL_COUNT(0x00900100) */
7737                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7738                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7739                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7740                 if (def != data)
7741                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7742         } else {
7743                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7744
7745                 /* reset CGCG/CGLS bits */
7746                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7747                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7748
7749                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7750                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7751
7752                 /* disable cgcg and cgls in FSM */
7753                 if (def != data)
7754                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7755         }
7756 }
7757
7758 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7759                                                       bool enable)
7760 {
7761         uint32_t def, data;
7762
7763         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7764                 return;
7765
7766         if (enable) {
7767                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7768                 /* unset FGCG override */
7769                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7770                 /* update FGCG override bits */
7771                 if (def != data)
7772                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7773
7774                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7775                 /* unset RLC SRAM CLK GATER override */
7776                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7777                 /* update RLC SRAM CLK GATER override bits */
7778                 if (def != data)
7779                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7780         } else {
7781                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7782                 /* reset FGCG bits */
7783                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7784                 /* disable FGCG*/
7785                 if (def != data)
7786                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7787
7788                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7789                 /* reset RLC SRAM CLK GATER bits */
7790                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7791                 /* disable RLC SRAM CLK*/
7792                 if (def != data)
7793                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7794         }
7795 }
7796
7797 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7798 {
7799         uint32_t reg_data = 0;
7800         uint32_t reg_idx = 0;
7801         uint32_t i;
7802
7803         const uint32_t tcp_ctrl_regs[] = {
7804                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7805                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7806                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7807                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7808                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7809                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7810                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7811                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7812                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7813                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7814                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
7815                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
7816                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7817                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7818                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7819                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7820                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7821                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7822                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7823                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7824                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7825                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7826                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
7827                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
7828         };
7829
7830         const uint32_t tcp_ctrl_regs_nv12[] = {
7831                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7832                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7833                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7834                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7835                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7836                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7837                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7838                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7839                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7840                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7841                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7842                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7843                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7844                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7845                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7846                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7847                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7848                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7849                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7850                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7851         };
7852
7853         const uint32_t sm_ctlr_regs[] = {
7854                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
7855                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
7856                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
7857                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
7858         };
7859
7860         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
7861                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
7862                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7863                                   tcp_ctrl_regs_nv12[i];
7864                         reg_data = RREG32(reg_idx);
7865                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7866                         WREG32(reg_idx, reg_data);
7867                 }
7868         } else {
7869                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
7870                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7871                                   tcp_ctrl_regs[i];
7872                         reg_data = RREG32(reg_idx);
7873                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7874                         WREG32(reg_idx, reg_data);
7875                 }
7876         }
7877
7878         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
7879                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
7880                           sm_ctlr_regs[i];
7881                 reg_data = RREG32(reg_idx);
7882                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
7883                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
7884                 WREG32(reg_idx, reg_data);
7885         }
7886 }
7887
7888 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7889                                             bool enable)
7890 {
7891         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
7892
7893         if (enable) {
7894                 /* enable FGCG firstly*/
7895                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7896                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7897                  * ===  MGCG + MGLS ===
7898                  */
7899                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7900                 /* ===  CGCG /CGLS for GFX 3D Only === */
7901                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7902                 /* ===  CGCG + CGLS === */
7903                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7904
7905                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
7906                      IP_VERSION(10, 1, 10)) ||
7907                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7908                      IP_VERSION(10, 1, 1)) ||
7909                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7910                      IP_VERSION(10, 1, 2)))
7911                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
7912         } else {
7913                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7914                  * ===  CGCG + CGLS ===
7915                  */
7916                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7917                 /* ===  CGCG /CGLS for GFX 3D Only === */
7918                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7919                 /* ===  MGCG + MGLS === */
7920                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7921                 /* disable fgcg at last*/
7922                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7923         }
7924
7925         if (adev->cg_flags &
7926             (AMD_CG_SUPPORT_GFX_MGCG |
7927              AMD_CG_SUPPORT_GFX_CGLS |
7928              AMD_CG_SUPPORT_GFX_CGCG |
7929              AMD_CG_SUPPORT_GFX_3D_CGCG |
7930              AMD_CG_SUPPORT_GFX_3D_CGLS))
7931                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7932
7933         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
7934
7935         return 0;
7936 }
7937
7938 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
7939                                                unsigned int vmid)
7940 {
7941         u32 data;
7942
7943         /* not for *_SOC15 */
7944         data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
7945
7946         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7947         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7948
7949         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7950 }
7951
7952 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
7953 {
7954         amdgpu_gfx_off_ctrl(adev, false);
7955
7956         gfx_v10_0_update_spm_vmid_internal(adev, vmid);
7957
7958         amdgpu_gfx_off_ctrl(adev, true);
7959 }
7960
7961 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7962                                         uint32_t offset,
7963                                         struct soc15_reg_rlcg *entries, int arr_size)
7964 {
7965         int i;
7966         uint32_t reg;
7967
7968         if (!entries)
7969                 return false;
7970
7971         for (i = 0; i < arr_size; i++) {
7972                 const struct soc15_reg_rlcg *entry;
7973
7974                 entry = &entries[i];
7975                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7976                 if (offset == reg)
7977                         return true;
7978         }
7979
7980         return false;
7981 }
7982
7983 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7984 {
7985         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7986 }
7987
7988 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7989 {
7990         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7991
7992         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7993                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7994         else
7995                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7996
7997         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7998
7999         /*
8000          * CGPG enablement required and the register to program the hysteresis value
8001          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8002          * in refclk count. Note that RLC FW is modified to take 16 bits from
8003          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8004          *
8005          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8006          * of CGPG enablement starting point.
8007          * Power/performance team will optimize it and might give a new value later.
8008          */
8009         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8010                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8011                 case IP_VERSION(10, 3, 1):
8012                 case IP_VERSION(10, 3, 3):
8013                 case IP_VERSION(10, 3, 6):
8014                 case IP_VERSION(10, 3, 7):
8015                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8016                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8017                         break;
8018                 default:
8019                         break;
8020                 }
8021         }
8022 }
8023
8024 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8025 {
8026         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8027
8028         gfx_v10_cntl_power_gating(adev, enable);
8029
8030         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8031 }
8032
8033 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8034         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8035         .set_safe_mode = gfx_v10_0_set_safe_mode,
8036         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8037         .init = gfx_v10_0_rlc_init,
8038         .get_csb_size = gfx_v10_0_get_csb_size,
8039         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8040         .resume = gfx_v10_0_rlc_resume,
8041         .stop = gfx_v10_0_rlc_stop,
8042         .reset = gfx_v10_0_rlc_reset,
8043         .start = gfx_v10_0_rlc_start,
8044         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8045 };
8046
8047 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8048         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8049         .set_safe_mode = gfx_v10_0_set_safe_mode,
8050         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8051         .init = gfx_v10_0_rlc_init,
8052         .get_csb_size = gfx_v10_0_get_csb_size,
8053         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8054         .resume = gfx_v10_0_rlc_resume,
8055         .stop = gfx_v10_0_rlc_stop,
8056         .reset = gfx_v10_0_rlc_reset,
8057         .start = gfx_v10_0_rlc_start,
8058         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8059         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8060 };
8061
8062 static int gfx_v10_0_set_powergating_state(void *handle,
8063                                           enum amd_powergating_state state)
8064 {
8065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8066         bool enable = (state == AMD_PG_STATE_GATE);
8067
8068         if (amdgpu_sriov_vf(adev))
8069                 return 0;
8070
8071         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8072         case IP_VERSION(10, 1, 10):
8073         case IP_VERSION(10, 1, 1):
8074         case IP_VERSION(10, 1, 2):
8075         case IP_VERSION(10, 3, 0):
8076         case IP_VERSION(10, 3, 2):
8077         case IP_VERSION(10, 3, 4):
8078         case IP_VERSION(10, 3, 5):
8079                 amdgpu_gfx_off_ctrl(adev, enable);
8080                 break;
8081         case IP_VERSION(10, 3, 1):
8082         case IP_VERSION(10, 3, 3):
8083         case IP_VERSION(10, 3, 6):
8084         case IP_VERSION(10, 3, 7):
8085                 if (!enable)
8086                         amdgpu_gfx_off_ctrl(adev, false);
8087
8088                 gfx_v10_cntl_pg(adev, enable);
8089
8090                 if (enable)
8091                         amdgpu_gfx_off_ctrl(adev, true);
8092
8093                 break;
8094         default:
8095                 break;
8096         }
8097         return 0;
8098 }
8099
8100 static int gfx_v10_0_set_clockgating_state(void *handle,
8101                                           enum amd_clockgating_state state)
8102 {
8103         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8104
8105         if (amdgpu_sriov_vf(adev))
8106                 return 0;
8107
8108         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8109         case IP_VERSION(10, 1, 10):
8110         case IP_VERSION(10, 1, 1):
8111         case IP_VERSION(10, 1, 2):
8112         case IP_VERSION(10, 3, 0):
8113         case IP_VERSION(10, 3, 2):
8114         case IP_VERSION(10, 3, 1):
8115         case IP_VERSION(10, 3, 4):
8116         case IP_VERSION(10, 3, 5):
8117         case IP_VERSION(10, 3, 6):
8118         case IP_VERSION(10, 3, 3):
8119         case IP_VERSION(10, 3, 7):
8120                 gfx_v10_0_update_gfx_clock_gating(adev,
8121                                                  state == AMD_CG_STATE_GATE);
8122                 break;
8123         default:
8124                 break;
8125         }
8126         return 0;
8127 }
8128
8129 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8130 {
8131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8132         int data;
8133
8134         /* AMD_CG_SUPPORT_GFX_FGCG */
8135         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8136         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8137                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8138
8139         /* AMD_CG_SUPPORT_GFX_MGCG */
8140         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8141         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8142                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8143
8144         /* AMD_CG_SUPPORT_GFX_CGCG */
8145         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8146         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8147                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8148
8149         /* AMD_CG_SUPPORT_GFX_CGLS */
8150         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8151                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8152
8153         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8154         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8155         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8156                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8157
8158         /* AMD_CG_SUPPORT_GFX_CP_LS */
8159         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8160         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8161                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8162
8163         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8164         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8165         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8166                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8167
8168         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8169         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8170                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8171 }
8172
8173 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8174 {
8175         /* gfx10 is 32bit rptr*/
8176         return *(uint32_t *)ring->rptr_cpu_addr;
8177 }
8178
8179 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8180 {
8181         struct amdgpu_device *adev = ring->adev;
8182         u64 wptr;
8183
8184         /* XXX check if swapping is necessary on BE */
8185         if (ring->use_doorbell) {
8186                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8187         } else {
8188                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8189                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8190         }
8191
8192         return wptr;
8193 }
8194
8195 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8196 {
8197         struct amdgpu_device *adev = ring->adev;
8198         uint32_t *wptr_saved;
8199         uint32_t *is_queue_unmap;
8200         uint64_t aggregated_db_index;
8201         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8202         uint64_t wptr_tmp;
8203
8204         if (ring->is_mes_queue) {
8205                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8206                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8207                                               sizeof(uint32_t));
8208                 aggregated_db_index =
8209                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8210                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8211
8212                 wptr_tmp = ring->wptr & ring->buf_mask;
8213                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8214                 *wptr_saved = wptr_tmp;
8215                 /* assume doorbell always being used by mes mapped queue */
8216                 if (*is_queue_unmap) {
8217                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8218                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8219                 } else {
8220                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8221
8222                         if (*is_queue_unmap)
8223                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8224                 }
8225         } else {
8226                 if (ring->use_doorbell) {
8227                         /* XXX check if swapping is necessary on BE */
8228                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8229                                      ring->wptr);
8230                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8231                 } else {
8232                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8233                                      lower_32_bits(ring->wptr));
8234                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8235                                      upper_32_bits(ring->wptr));
8236                 }
8237         }
8238 }
8239
8240 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8241 {
8242         /* gfx10 hardware is 32bit rptr */
8243         return *(uint32_t *)ring->rptr_cpu_addr;
8244 }
8245
8246 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8247 {
8248         u64 wptr;
8249
8250         /* XXX check if swapping is necessary on BE */
8251         if (ring->use_doorbell)
8252                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8253         else
8254                 BUG();
8255         return wptr;
8256 }
8257
8258 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8259 {
8260         struct amdgpu_device *adev = ring->adev;
8261         uint32_t *wptr_saved;
8262         uint32_t *is_queue_unmap;
8263         uint64_t aggregated_db_index;
8264         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8265         uint64_t wptr_tmp;
8266
8267         if (ring->is_mes_queue) {
8268                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8269                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8270                                               sizeof(uint32_t));
8271                 aggregated_db_index =
8272                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8273                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8274
8275                 wptr_tmp = ring->wptr & ring->buf_mask;
8276                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8277                 *wptr_saved = wptr_tmp;
8278                 /* assume doorbell always used by mes mapped queue */
8279                 if (*is_queue_unmap) {
8280                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8281                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8282                 } else {
8283                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8284
8285                         if (*is_queue_unmap)
8286                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8287                 }
8288         } else {
8289                 /* XXX check if swapping is necessary on BE */
8290                 if (ring->use_doorbell) {
8291                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8292                                      ring->wptr);
8293                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8294                 } else {
8295                         BUG(); /* only DOORBELL method supported on gfx10 now */
8296                 }
8297         }
8298 }
8299
8300 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8301 {
8302         struct amdgpu_device *adev = ring->adev;
8303         u32 ref_and_mask, reg_mem_engine;
8304         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8305
8306         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8307                 switch (ring->me) {
8308                 case 1:
8309                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8310                         break;
8311                 case 2:
8312                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8313                         break;
8314                 default:
8315                         return;
8316                 }
8317                 reg_mem_engine = 0;
8318         } else {
8319                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8320                 reg_mem_engine = 1; /* pfp */
8321         }
8322
8323         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8324                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8325                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8326                                ref_and_mask, ref_and_mask, 0x20);
8327 }
8328
8329 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8330                                        struct amdgpu_job *job,
8331                                        struct amdgpu_ib *ib,
8332                                        uint32_t flags)
8333 {
8334         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8335         u32 header, control = 0;
8336
8337         if (ib->flags & AMDGPU_IB_FLAG_CE)
8338                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8339         else
8340                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8341
8342         control |= ib->length_dw | (vmid << 24);
8343
8344         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8345                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8346
8347                 if (flags & AMDGPU_IB_PREEMPTED)
8348                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8349
8350                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8351                         gfx_v10_0_ring_emit_de_meta(ring,
8352                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8353         }
8354
8355         if (ring->is_mes_queue)
8356                 /* inherit vmid from mqd */
8357                 control |= 0x400000;
8358
8359         amdgpu_ring_write(ring, header);
8360         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8361         amdgpu_ring_write(ring,
8362 #ifdef __BIG_ENDIAN
8363                 (2 << 0) |
8364 #endif
8365                 lower_32_bits(ib->gpu_addr));
8366         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8367         amdgpu_ring_write(ring, control);
8368 }
8369
8370 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8371                                            struct amdgpu_job *job,
8372                                            struct amdgpu_ib *ib,
8373                                            uint32_t flags)
8374 {
8375         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8376         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8377
8378         if (ring->is_mes_queue)
8379                 /* inherit vmid from mqd */
8380                 control |= 0x40000000;
8381
8382         /* Currently, there is a high possibility to get wave ID mismatch
8383          * between ME and GDS, leading to a hw deadlock, because ME generates
8384          * different wave IDs than the GDS expects. This situation happens
8385          * randomly when at least 5 compute pipes use GDS ordered append.
8386          * The wave IDs generated by ME are also wrong after suspend/resume.
8387          * Those are probably bugs somewhere else in the kernel driver.
8388          *
8389          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8390          * GDS to 0 for this ring (me/pipe).
8391          */
8392         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8393                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8394                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8395                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8396         }
8397
8398         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8399         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8400         amdgpu_ring_write(ring,
8401 #ifdef __BIG_ENDIAN
8402                                 (2 << 0) |
8403 #endif
8404                                 lower_32_bits(ib->gpu_addr));
8405         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8406         amdgpu_ring_write(ring, control);
8407 }
8408
8409 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8410                                      u64 seq, unsigned int flags)
8411 {
8412         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8413         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8414
8415         /* RELEASE_MEM - flush caches, send int */
8416         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8417         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8418                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8419                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8420                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8421                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8422                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8423                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8424         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8425                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8426
8427         /*
8428          * the address should be Qword aligned if 64bit write, Dword
8429          * aligned if only send 32bit data low (discard data high)
8430          */
8431         if (write64bit)
8432                 BUG_ON(addr & 0x7);
8433         else
8434                 BUG_ON(addr & 0x3);
8435         amdgpu_ring_write(ring, lower_32_bits(addr));
8436         amdgpu_ring_write(ring, upper_32_bits(addr));
8437         amdgpu_ring_write(ring, lower_32_bits(seq));
8438         amdgpu_ring_write(ring, upper_32_bits(seq));
8439         amdgpu_ring_write(ring, ring->is_mes_queue ?
8440                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8441 }
8442
8443 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8444 {
8445         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8446         uint32_t seq = ring->fence_drv.sync_seq;
8447         uint64_t addr = ring->fence_drv.gpu_addr;
8448
8449         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8450                                upper_32_bits(addr), seq, 0xffffffff, 4);
8451 }
8452
8453 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8454                                    uint16_t pasid, uint32_t flush_type,
8455                                    bool all_hub, uint8_t dst_sel)
8456 {
8457         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8458         amdgpu_ring_write(ring,
8459                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8460                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8461                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8462                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8463 }
8464
8465 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8466                                          unsigned int vmid, uint64_t pd_addr)
8467 {
8468         if (ring->is_mes_queue)
8469                 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8470         else
8471                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8472
8473         /* compute doesn't have PFP */
8474         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8475                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8476                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8477                 amdgpu_ring_write(ring, 0x0);
8478         }
8479 }
8480
8481 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8482                                           u64 seq, unsigned int flags)
8483 {
8484         struct amdgpu_device *adev = ring->adev;
8485
8486         /* we only allocate 32bit for each seq wb address */
8487         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8488
8489         /* write fence seq to the "addr" */
8490         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8491         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8492                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8493         amdgpu_ring_write(ring, lower_32_bits(addr));
8494         amdgpu_ring_write(ring, upper_32_bits(addr));
8495         amdgpu_ring_write(ring, lower_32_bits(seq));
8496
8497         if (flags & AMDGPU_FENCE_FLAG_INT) {
8498                 /* set register to trigger INT */
8499                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8500                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8501                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8502                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8503                 amdgpu_ring_write(ring, 0);
8504                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8505         }
8506 }
8507
8508 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8509 {
8510         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8511         amdgpu_ring_write(ring, 0);
8512 }
8513
8514 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8515                                          uint32_t flags)
8516 {
8517         uint32_t dw2 = 0;
8518
8519         if (ring->adev->gfx.mcbp)
8520                 gfx_v10_0_ring_emit_ce_meta(ring,
8521                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8522
8523         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8524         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8525                 /* set load_global_config & load_global_uconfig */
8526                 dw2 |= 0x8001;
8527                 /* set load_cs_sh_regs */
8528                 dw2 |= 0x01000000;
8529                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8530                 dw2 |= 0x10002;
8531
8532                 /* set load_ce_ram if preamble presented */
8533                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8534                         dw2 |= 0x10000000;
8535         } else {
8536                 /* still load_ce_ram if this is the first time preamble presented
8537                  * although there is no context switch happens.
8538                  */
8539                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8540                         dw2 |= 0x10000000;
8541         }
8542
8543         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8544         amdgpu_ring_write(ring, dw2);
8545         amdgpu_ring_write(ring, 0);
8546 }
8547
8548 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8549 {
8550         unsigned int ret;
8551
8552         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8553         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8554         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8555         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8556         ret = ring->wptr & ring->buf_mask;
8557         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8558
8559         return ret;
8560 }
8561
8562 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)
8563 {
8564         unsigned int cur;
8565
8566         BUG_ON(offset > ring->buf_mask);
8567         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8568
8569         cur = (ring->wptr - 1) & ring->buf_mask;
8570         if (likely(cur > offset))
8571                 ring->ring[offset] = cur - offset;
8572         else
8573                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8574 }
8575
8576 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8577 {
8578         int i, r = 0;
8579         struct amdgpu_device *adev = ring->adev;
8580         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8581         struct amdgpu_ring *kiq_ring = &kiq->ring;
8582         unsigned long flags;
8583
8584         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8585                 return -EINVAL;
8586
8587         spin_lock_irqsave(&kiq->ring_lock, flags);
8588
8589         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8590                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8591                 return -ENOMEM;
8592         }
8593
8594         /* assert preemption condition */
8595         amdgpu_ring_set_preempt_cond_exec(ring, false);
8596
8597         /* assert IB preemption, emit the trailing fence */
8598         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8599                                    ring->trail_fence_gpu_addr,
8600                                    ++ring->trail_seq);
8601         amdgpu_ring_commit(kiq_ring);
8602
8603         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8604
8605         /* poll the trailing fence */
8606         for (i = 0; i < adev->usec_timeout; i++) {
8607                 if (ring->trail_seq ==
8608                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8609                         break;
8610                 udelay(1);
8611         }
8612
8613         if (i >= adev->usec_timeout) {
8614                 r = -EINVAL;
8615                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8616         }
8617
8618         /* deassert preemption condition */
8619         amdgpu_ring_set_preempt_cond_exec(ring, true);
8620         return r;
8621 }
8622
8623 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8624 {
8625         struct amdgpu_device *adev = ring->adev;
8626         struct v10_ce_ib_state ce_payload = {0};
8627         uint64_t offset, ce_payload_gpu_addr;
8628         void *ce_payload_cpu_addr;
8629         int cnt;
8630
8631         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8632
8633         if (ring->is_mes_queue) {
8634                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8635                                   gfx[0].gfx_meta_data) +
8636                         offsetof(struct v10_gfx_meta_data, ce_payload);
8637                 ce_payload_gpu_addr =
8638                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8639                 ce_payload_cpu_addr =
8640                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8641         } else {
8642                 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8643                 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8644                 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8645         }
8646
8647         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8648         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8649                                  WRITE_DATA_DST_SEL(8) |
8650                                  WR_CONFIRM) |
8651                                  WRITE_DATA_CACHE_POLICY(0));
8652         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8653         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8654
8655         if (resume)
8656                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8657                                            sizeof(ce_payload) >> 2);
8658         else
8659                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8660                                            sizeof(ce_payload) >> 2);
8661 }
8662
8663 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8664 {
8665         struct amdgpu_device *adev = ring->adev;
8666         struct v10_de_ib_state de_payload = {0};
8667         uint64_t offset, gds_addr, de_payload_gpu_addr;
8668         void *de_payload_cpu_addr;
8669         int cnt;
8670
8671         if (ring->is_mes_queue) {
8672                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8673                                   gfx[0].gfx_meta_data) +
8674                         offsetof(struct v10_gfx_meta_data, de_payload);
8675                 de_payload_gpu_addr =
8676                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8677                 de_payload_cpu_addr =
8678                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8679
8680                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8681                                   gfx[0].gds_backup) +
8682                         offsetof(struct v10_gfx_meta_data, de_payload);
8683                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8684         } else {
8685                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8686                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8687                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8688
8689                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8690                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
8691                                  PAGE_SIZE);
8692         }
8693
8694         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8695         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8696
8697         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8698         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8699         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8700                                  WRITE_DATA_DST_SEL(8) |
8701                                  WR_CONFIRM) |
8702                                  WRITE_DATA_CACHE_POLICY(0));
8703         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8704         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8705
8706         if (resume)
8707                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8708                                            sizeof(de_payload) >> 2);
8709         else
8710                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8711                                            sizeof(de_payload) >> 2);
8712 }
8713
8714 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8715                                     bool secure)
8716 {
8717         uint32_t v = secure ? FRAME_TMZ : 0;
8718
8719         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8720         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8721 }
8722
8723 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8724                                      uint32_t reg_val_offs)
8725 {
8726         struct amdgpu_device *adev = ring->adev;
8727
8728         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8729         amdgpu_ring_write(ring, 0 |     /* src: register*/
8730                                 (5 << 8) |      /* dst: memory */
8731                                 (1 << 20));     /* write confirm */
8732         amdgpu_ring_write(ring, reg);
8733         amdgpu_ring_write(ring, 0);
8734         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8735                                 reg_val_offs * 4));
8736         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8737                                 reg_val_offs * 4));
8738 }
8739
8740 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8741                                    uint32_t val)
8742 {
8743         uint32_t cmd = 0;
8744
8745         switch (ring->funcs->type) {
8746         case AMDGPU_RING_TYPE_GFX:
8747                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8748                 break;
8749         case AMDGPU_RING_TYPE_KIQ:
8750                 cmd = (1 << 16); /* no inc addr */
8751                 break;
8752         default:
8753                 cmd = WR_CONFIRM;
8754                 break;
8755         }
8756         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8757         amdgpu_ring_write(ring, cmd);
8758         amdgpu_ring_write(ring, reg);
8759         amdgpu_ring_write(ring, 0);
8760         amdgpu_ring_write(ring, val);
8761 }
8762
8763 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8764                                         uint32_t val, uint32_t mask)
8765 {
8766         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8767 }
8768
8769 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8770                                                    uint32_t reg0, uint32_t reg1,
8771                                                    uint32_t ref, uint32_t mask)
8772 {
8773         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8774         struct amdgpu_device *adev = ring->adev;
8775         bool fw_version_ok = false;
8776
8777         fw_version_ok = adev->gfx.cp_fw_write_wait;
8778
8779         if (fw_version_ok)
8780                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8781                                        ref, mask, 0x20);
8782         else
8783                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8784                                                            ref, mask);
8785 }
8786
8787 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8788                                          unsigned int vmid)
8789 {
8790         struct amdgpu_device *adev = ring->adev;
8791         uint32_t value = 0;
8792
8793         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8794         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8795         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8796         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8797         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8798 }
8799
8800 static void
8801 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8802                                       uint32_t me, uint32_t pipe,
8803                                       enum amdgpu_interrupt_state state)
8804 {
8805         uint32_t cp_int_cntl, cp_int_cntl_reg;
8806
8807         if (!me) {
8808                 switch (pipe) {
8809                 case 0:
8810                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8811                         break;
8812                 case 1:
8813                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8814                         break;
8815                 default:
8816                         DRM_DEBUG("invalid pipe %d\n", pipe);
8817                         return;
8818                 }
8819         } else {
8820                 DRM_DEBUG("invalid me %d\n", me);
8821                 return;
8822         }
8823
8824         switch (state) {
8825         case AMDGPU_IRQ_STATE_DISABLE:
8826                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8827                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8828                                             TIME_STAMP_INT_ENABLE, 0);
8829                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8830                 break;
8831         case AMDGPU_IRQ_STATE_ENABLE:
8832                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8833                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8834                                             TIME_STAMP_INT_ENABLE, 1);
8835                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8836                 break;
8837         default:
8838                 break;
8839         }
8840 }
8841
8842 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8843                                                      int me, int pipe,
8844                                                      enum amdgpu_interrupt_state state)
8845 {
8846         u32 mec_int_cntl, mec_int_cntl_reg;
8847
8848         /*
8849          * amdgpu controls only the first MEC. That's why this function only
8850          * handles the setting of interrupts for this specific MEC. All other
8851          * pipes' interrupts are set by amdkfd.
8852          */
8853
8854         if (me == 1) {
8855                 switch (pipe) {
8856                 case 0:
8857                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8858                         break;
8859                 case 1:
8860                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8861                         break;
8862                 case 2:
8863                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8864                         break;
8865                 case 3:
8866                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8867                         break;
8868                 default:
8869                         DRM_DEBUG("invalid pipe %d\n", pipe);
8870                         return;
8871                 }
8872         } else {
8873                 DRM_DEBUG("invalid me %d\n", me);
8874                 return;
8875         }
8876
8877         switch (state) {
8878         case AMDGPU_IRQ_STATE_DISABLE:
8879                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8880                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8881                                              TIME_STAMP_INT_ENABLE, 0);
8882                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8883                 break;
8884         case AMDGPU_IRQ_STATE_ENABLE:
8885                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8886                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8887                                              TIME_STAMP_INT_ENABLE, 1);
8888                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8889                 break;
8890         default:
8891                 break;
8892         }
8893 }
8894
8895 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8896                                             struct amdgpu_irq_src *src,
8897                                             unsigned int type,
8898                                             enum amdgpu_interrupt_state state)
8899 {
8900         switch (type) {
8901         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8902                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8903                 break;
8904         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8905                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8906                 break;
8907         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8908                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8909                 break;
8910         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8911                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8912                 break;
8913         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8914                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8915                 break;
8916         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8917                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8918                 break;
8919         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8920                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8921                 break;
8922         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8923                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8924                 break;
8925         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8926                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8927                 break;
8928         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8929                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8930                 break;
8931         default:
8932                 break;
8933         }
8934         return 0;
8935 }
8936
8937 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8938                              struct amdgpu_irq_src *source,
8939                              struct amdgpu_iv_entry *entry)
8940 {
8941         int i;
8942         u8 me_id, pipe_id, queue_id;
8943         struct amdgpu_ring *ring;
8944         uint32_t mes_queue_id = entry->src_data[0];
8945
8946         DRM_DEBUG("IH: CP EOP\n");
8947
8948         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
8949                 struct amdgpu_mes_queue *queue;
8950
8951                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
8952
8953                 spin_lock(&adev->mes.queue_id_lock);
8954                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
8955                 if (queue) {
8956                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
8957                         amdgpu_fence_process(queue->ring);
8958                 }
8959                 spin_unlock(&adev->mes.queue_id_lock);
8960         } else {
8961                 me_id = (entry->ring_id & 0x0c) >> 2;
8962                 pipe_id = (entry->ring_id & 0x03) >> 0;
8963                 queue_id = (entry->ring_id & 0x70) >> 4;
8964
8965                 switch (me_id) {
8966                 case 0:
8967                         if (pipe_id == 0)
8968                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8969                         else
8970                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8971                         break;
8972                 case 1:
8973                 case 2:
8974                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8975                                 ring = &adev->gfx.compute_ring[i];
8976                                 /* Per-queue interrupt is supported for MEC starting from VI.
8977                                  * The interrupt can only be enabled/disabled per pipe instead
8978                                  * of per queue.
8979                                  */
8980                                 if ((ring->me == me_id) &&
8981                                     (ring->pipe == pipe_id) &&
8982                                     (ring->queue == queue_id))
8983                                         amdgpu_fence_process(ring);
8984                         }
8985                         break;
8986                 }
8987         }
8988
8989         return 0;
8990 }
8991
8992 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8993                                               struct amdgpu_irq_src *source,
8994                                               unsigned int type,
8995                                               enum amdgpu_interrupt_state state)
8996 {
8997         switch (state) {
8998         case AMDGPU_IRQ_STATE_DISABLE:
8999         case AMDGPU_IRQ_STATE_ENABLE:
9000                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9001                                PRIV_REG_INT_ENABLE,
9002                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9003                 break;
9004         default:
9005                 break;
9006         }
9007
9008         return 0;
9009 }
9010
9011 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9012                                                struct amdgpu_irq_src *source,
9013                                                unsigned int type,
9014                                                enum amdgpu_interrupt_state state)
9015 {
9016         switch (state) {
9017         case AMDGPU_IRQ_STATE_DISABLE:
9018         case AMDGPU_IRQ_STATE_ENABLE:
9019                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9020                                PRIV_INSTR_INT_ENABLE,
9021                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9022                 break;
9023         default:
9024                 break;
9025         }
9026
9027         return 0;
9028 }
9029
9030 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9031                                         struct amdgpu_iv_entry *entry)
9032 {
9033         u8 me_id, pipe_id, queue_id;
9034         struct amdgpu_ring *ring;
9035         int i;
9036
9037         me_id = (entry->ring_id & 0x0c) >> 2;
9038         pipe_id = (entry->ring_id & 0x03) >> 0;
9039         queue_id = (entry->ring_id & 0x70) >> 4;
9040
9041         switch (me_id) {
9042         case 0:
9043                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9044                         ring = &adev->gfx.gfx_ring[i];
9045                         /* we only enabled 1 gfx queue per pipe for now */
9046                         if (ring->me == me_id && ring->pipe == pipe_id)
9047                                 drm_sched_fault(&ring->sched);
9048                 }
9049                 break;
9050         case 1:
9051         case 2:
9052                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9053                         ring = &adev->gfx.compute_ring[i];
9054                         if (ring->me == me_id && ring->pipe == pipe_id &&
9055                             ring->queue == queue_id)
9056                                 drm_sched_fault(&ring->sched);
9057                 }
9058                 break;
9059         default:
9060                 BUG();
9061         }
9062 }
9063
9064 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9065                                   struct amdgpu_irq_src *source,
9066                                   struct amdgpu_iv_entry *entry)
9067 {
9068         DRM_ERROR("Illegal register access in command stream\n");
9069         gfx_v10_0_handle_priv_fault(adev, entry);
9070         return 0;
9071 }
9072
9073 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9074                                    struct amdgpu_irq_src *source,
9075                                    struct amdgpu_iv_entry *entry)
9076 {
9077         DRM_ERROR("Illegal instruction in command stream\n");
9078         gfx_v10_0_handle_priv_fault(adev, entry);
9079         return 0;
9080 }
9081
9082 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9083                                              struct amdgpu_irq_src *src,
9084                                              unsigned int type,
9085                                              enum amdgpu_interrupt_state state)
9086 {
9087         uint32_t tmp, target;
9088         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9089
9090         if (ring->me == 1)
9091                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9092         else
9093                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9094         target += ring->pipe;
9095
9096         switch (type) {
9097         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9098                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9099                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9100                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9101                                             GENERIC2_INT_ENABLE, 0);
9102                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9103
9104                         tmp = RREG32_SOC15_IP(GC, target);
9105                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9106                                             GENERIC2_INT_ENABLE, 0);
9107                         WREG32_SOC15_IP(GC, target, tmp);
9108                 } else {
9109                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9110                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9111                                             GENERIC2_INT_ENABLE, 1);
9112                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9113
9114                         tmp = RREG32_SOC15_IP(GC, target);
9115                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9116                                             GENERIC2_INT_ENABLE, 1);
9117                         WREG32_SOC15_IP(GC, target, tmp);
9118                 }
9119                 break;
9120         default:
9121                 BUG(); /* kiq only support GENERIC2_INT now */
9122                 break;
9123         }
9124         return 0;
9125 }
9126
9127 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9128                              struct amdgpu_irq_src *source,
9129                              struct amdgpu_iv_entry *entry)
9130 {
9131         u8 me_id, pipe_id, queue_id;
9132         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9133
9134         me_id = (entry->ring_id & 0x0c) >> 2;
9135         pipe_id = (entry->ring_id & 0x03) >> 0;
9136         queue_id = (entry->ring_id & 0x70) >> 4;
9137         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9138                    me_id, pipe_id, queue_id);
9139
9140         amdgpu_fence_process(ring);
9141         return 0;
9142 }
9143
9144 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9145 {
9146         const unsigned int gcr_cntl =
9147                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9148                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9149                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9150                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9151                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9152                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9153                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9154                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9155
9156         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9157         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9158         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9159         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9160         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9161         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9162         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9163         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9164         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9165 }
9166
9167 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9168         .name = "gfx_v10_0",
9169         .early_init = gfx_v10_0_early_init,
9170         .late_init = gfx_v10_0_late_init,
9171         .sw_init = gfx_v10_0_sw_init,
9172         .sw_fini = gfx_v10_0_sw_fini,
9173         .hw_init = gfx_v10_0_hw_init,
9174         .hw_fini = gfx_v10_0_hw_fini,
9175         .suspend = gfx_v10_0_suspend,
9176         .resume = gfx_v10_0_resume,
9177         .is_idle = gfx_v10_0_is_idle,
9178         .wait_for_idle = gfx_v10_0_wait_for_idle,
9179         .soft_reset = gfx_v10_0_soft_reset,
9180         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9181         .set_powergating_state = gfx_v10_0_set_powergating_state,
9182         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9183 };
9184
9185 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9186         .type = AMDGPU_RING_TYPE_GFX,
9187         .align_mask = 0xff,
9188         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9189         .support_64bit_ptrs = true,
9190         .secure_submission_supported = true,
9191         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9192         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9193         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9194         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9195                 5 + /* COND_EXEC */
9196                 7 + /* PIPELINE_SYNC */
9197                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9198                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9199                 2 + /* VM_FLUSH */
9200                 8 + /* FENCE for VM_FLUSH */
9201                 20 + /* GDS switch */
9202                 4 + /* double SWITCH_BUFFER,
9203                      * the first COND_EXEC jump to the place
9204                      * just prior to this double SWITCH_BUFFER
9205                      */
9206                 5 + /* COND_EXEC */
9207                 7 + /* HDP_flush */
9208                 4 + /* VGT_flush */
9209                 14 + /* CE_META */
9210                 31 + /* DE_META */
9211                 3 + /* CNTX_CTRL */
9212                 5 + /* HDP_INVL */
9213                 8 + 8 + /* FENCE x2 */
9214                 2 + /* SWITCH_BUFFER */
9215                 8, /* gfx_v10_0_emit_mem_sync */
9216         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9217         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9218         .emit_fence = gfx_v10_0_ring_emit_fence,
9219         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9220         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9221         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9222         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9223         .test_ring = gfx_v10_0_ring_test_ring,
9224         .test_ib = gfx_v10_0_ring_test_ib,
9225         .insert_nop = amdgpu_ring_insert_nop,
9226         .pad_ib = amdgpu_ring_generic_pad_ib,
9227         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9228         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9229         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9230         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9231         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9232         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9233         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9234         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9235         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9236         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9237         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9238 };
9239
9240 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9241         .type = AMDGPU_RING_TYPE_COMPUTE,
9242         .align_mask = 0xff,
9243         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9244         .support_64bit_ptrs = true,
9245         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9246         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9247         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9248         .emit_frame_size =
9249                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9250                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9251                 5 + /* hdp invalidate */
9252                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9253                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9254                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9255                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9256                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9257                 8, /* gfx_v10_0_emit_mem_sync */
9258         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9259         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9260         .emit_fence = gfx_v10_0_ring_emit_fence,
9261         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9262         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9263         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9264         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9265         .test_ring = gfx_v10_0_ring_test_ring,
9266         .test_ib = gfx_v10_0_ring_test_ib,
9267         .insert_nop = amdgpu_ring_insert_nop,
9268         .pad_ib = amdgpu_ring_generic_pad_ib,
9269         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9270         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9271         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9272         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9273 };
9274
9275 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9276         .type = AMDGPU_RING_TYPE_KIQ,
9277         .align_mask = 0xff,
9278         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9279         .support_64bit_ptrs = true,
9280         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9281         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9282         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9283         .emit_frame_size =
9284                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9285                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9286                 5 + /*hdp invalidate */
9287                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9288                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9289                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9290                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9291                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9292         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9293         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9294         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9295         .test_ring = gfx_v10_0_ring_test_ring,
9296         .test_ib = gfx_v10_0_ring_test_ib,
9297         .insert_nop = amdgpu_ring_insert_nop,
9298         .pad_ib = amdgpu_ring_generic_pad_ib,
9299         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9300         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9301         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9302         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9303 };
9304
9305 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9306 {
9307         int i;
9308
9309         adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9310
9311         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9312                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9313
9314         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9315                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9316 }
9317
9318 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9319         .set = gfx_v10_0_set_eop_interrupt_state,
9320         .process = gfx_v10_0_eop_irq,
9321 };
9322
9323 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9324         .set = gfx_v10_0_set_priv_reg_fault_state,
9325         .process = gfx_v10_0_priv_reg_irq,
9326 };
9327
9328 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9329         .set = gfx_v10_0_set_priv_inst_fault_state,
9330         .process = gfx_v10_0_priv_inst_irq,
9331 };
9332
9333 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9334         .set = gfx_v10_0_kiq_set_interrupt_state,
9335         .process = gfx_v10_0_kiq_irq,
9336 };
9337
9338 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9339 {
9340         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9341         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9342
9343         adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9344         adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9345
9346         adev->gfx.priv_reg_irq.num_types = 1;
9347         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9348
9349         adev->gfx.priv_inst_irq.num_types = 1;
9350         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9351 }
9352
9353 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9354 {
9355         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9356         case IP_VERSION(10, 1, 10):
9357         case IP_VERSION(10, 1, 1):
9358         case IP_VERSION(10, 1, 3):
9359         case IP_VERSION(10, 1, 4):
9360         case IP_VERSION(10, 3, 2):
9361         case IP_VERSION(10, 3, 1):
9362         case IP_VERSION(10, 3, 4):
9363         case IP_VERSION(10, 3, 5):
9364         case IP_VERSION(10, 3, 6):
9365         case IP_VERSION(10, 3, 3):
9366         case IP_VERSION(10, 3, 7):
9367                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9368                 break;
9369         case IP_VERSION(10, 1, 2):
9370         case IP_VERSION(10, 3, 0):
9371                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9372                 break;
9373         default:
9374                 break;
9375         }
9376 }
9377
9378 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9379 {
9380         unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9381                             adev->gfx.config.max_sh_per_se *
9382                             adev->gfx.config.max_shader_engines;
9383
9384         adev->gds.gds_size = 0x10000;
9385         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9386         adev->gds.gws_size = 64;
9387         adev->gds.oa_size = 16;
9388 }
9389
9390 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9391 {
9392         /* set gfx eng mqd */
9393         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9394                 sizeof(struct v10_gfx_mqd);
9395         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9396                 gfx_v10_0_gfx_mqd_init;
9397         /* set compute eng mqd */
9398         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9399                 sizeof(struct v10_compute_mqd);
9400         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9401                 gfx_v10_0_compute_mqd_init;
9402 }
9403
9404 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9405                                                           u32 bitmap)
9406 {
9407         u32 data;
9408
9409         if (!bitmap)
9410                 return;
9411
9412         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9413         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9414
9415         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9416 }
9417
9418 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9419 {
9420         u32 disabled_mask =
9421                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9422         u32 efuse_setting = 0;
9423         u32 vbios_setting = 0;
9424
9425         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9426         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9427         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9428
9429         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9430         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9431         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9432
9433         disabled_mask |= efuse_setting | vbios_setting;
9434
9435         return (~disabled_mask);
9436 }
9437
9438 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9439 {
9440         u32 wgp_idx, wgp_active_bitmap;
9441         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9442
9443         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9444         cu_active_bitmap = 0;
9445
9446         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9447                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9448                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9449                 if (wgp_active_bitmap & (1 << wgp_idx))
9450                         cu_active_bitmap |= cu_bitmap_per_wgp;
9451         }
9452
9453         return cu_active_bitmap;
9454 }
9455
9456 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9457                                  struct amdgpu_cu_info *cu_info)
9458 {
9459         int i, j, k, counter, active_cu_number = 0;
9460         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9461         unsigned int disable_masks[4 * 2];
9462
9463         if (!adev || !cu_info)
9464                 return -EINVAL;
9465
9466         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9467
9468         mutex_lock(&adev->grbm_idx_mutex);
9469         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9470                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9471                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9472                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
9473                               IP_VERSION(10, 3, 0)) ||
9474                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9475                               IP_VERSION(10, 3, 3)) ||
9476                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9477                               IP_VERSION(10, 3, 6)) ||
9478                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9479                               IP_VERSION(10, 3, 7))) &&
9480                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9481                                 continue;
9482                         mask = 1;
9483                         ao_bitmap = 0;
9484                         counter = 0;
9485                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9486                         if (i < 4 && j < 2)
9487                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9488                                         adev, disable_masks[i * 2 + j]);
9489                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9490                         cu_info->bitmap[0][i][j] = bitmap;
9491
9492                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9493                                 if (bitmap & mask) {
9494                                         if (counter < adev->gfx.config.max_cu_per_sh)
9495                                                 ao_bitmap |= mask;
9496                                         counter++;
9497                                 }
9498                                 mask <<= 1;
9499                         }
9500                         active_cu_number += counter;
9501                         if (i < 2 && j < 2)
9502                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9503                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9504                 }
9505         }
9506         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9507         mutex_unlock(&adev->grbm_idx_mutex);
9508
9509         cu_info->number = active_cu_number;
9510         cu_info->ao_cu_mask = ao_cu_mask;
9511         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9512
9513         return 0;
9514 }
9515
9516 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9517 {
9518         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9519
9520         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9521         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9522         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9523
9524         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9525         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9526         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9527
9528         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9529                                                 adev->gfx.config.max_shader_engines);
9530         disabled_sa = efuse_setting | vbios_setting;
9531         disabled_sa &= max_sa_mask;
9532
9533         return disabled_sa;
9534 }
9535
9536 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9537 {
9538         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9539         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9540
9541         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9542
9543         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9544         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9545         max_shader_engines = adev->gfx.config.max_shader_engines;
9546
9547         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9548                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9549                 disabled_sa_per_se &= max_sa_per_se_mask;
9550                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9551                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9552                         break;
9553                 }
9554         }
9555 }
9556
9557 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9558 {
9559         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9560                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9561                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9562                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9563
9564         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9565         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9566                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9567                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9568                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9569                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9570
9571         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9572                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9573                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9574                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9575
9576         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9577
9578         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9579                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9580 }
9581
9582 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9583         .type = AMD_IP_BLOCK_TYPE_GFX,
9584         .major = 10,
9585         .minor = 0,
9586         .rev = 0,
9587         .funcs = &gfx_v10_0_ip_funcs,
9588 };