2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "gca/gfx_7_2_enum.h"
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
49 static const u32 crtc_offsets[6] =
51 CRTC0_REGISTER_OFFSET,
52 CRTC1_REGISTER_OFFSET,
53 CRTC2_REGISTER_OFFSET,
54 CRTC3_REGISTER_OFFSET,
55 CRTC4_REGISTER_OFFSET,
59 static const uint32_t dig_offsets[] = {
60 CRTC0_REGISTER_OFFSET,
61 CRTC1_REGISTER_OFFSET,
62 CRTC2_REGISTER_OFFSET,
63 CRTC3_REGISTER_OFFSET,
64 CRTC4_REGISTER_OFFSET,
65 CRTC5_REGISTER_OFFSET,
66 (0x13830 - 0x7030) >> 2,
75 } interrupt_status_offsets[6] = { {
76 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
107 static const uint32_t hpd_int_control_offsets[6] = {
108 mmDC_HPD1_INT_CONTROL,
109 mmDC_HPD2_INT_CONTROL,
110 mmDC_HPD3_INT_CONTROL,
111 mmDC_HPD4_INT_CONTROL,
112 mmDC_HPD5_INT_CONTROL,
113 mmDC_HPD6_INT_CONTROL,
116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
117 u32 block_offset, u32 reg)
122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
131 u32 block_offset, u32 reg, u32 v)
135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
169 * Wait for vblank on the requested crtc (evergreen+).
171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
175 if (crtc >= adev->mode_info.num_crtc)
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
184 while (dce_v8_0_is_in_vblank(adev, crtc)) {
187 if (!dce_v8_0_is_counter_moving(adev, crtc))
192 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
195 if (!dce_v8_0_is_counter_moving(adev, crtc))
201 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
203 if (crtc >= adev->mode_info.num_crtc)
206 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
209 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
213 /* Enable pflip interrupts */
214 for (i = 0; i < adev->mode_info.num_crtc; i++)
215 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
218 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
222 /* Disable pflip interrupts */
223 for (i = 0; i < adev->mode_info.num_crtc; i++)
224 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
228 * dce_v8_0_page_flip - pageflip callback.
230 * @adev: amdgpu_device pointer
231 * @crtc_id: crtc to cleanup pageflip on
232 * @crtc_base: new address of the crtc (GPU MC address)
234 * Triggers the actual pageflip by updating the primary
235 * surface base address.
237 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
238 int crtc_id, u64 crtc_base, bool async)
240 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
242 /* flip at hsync for async, default is vsync */
243 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
244 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
245 /* update the primary scanout addresses */
246 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
247 upper_32_bits(crtc_base));
248 /* writing to the low address triggers the update */
249 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
250 lower_32_bits(crtc_base));
252 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
255 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
256 u32 *vbl, u32 *position)
258 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
261 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
262 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
268 * dce_v8_0_hpd_sense - hpd sense callback.
270 * @adev: amdgpu_device pointer
271 * @hpd: hpd (hotplug detect) pin
273 * Checks if a digital monitor is connected (evergreen+).
274 * Returns true if connected, false if not connected.
276 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
277 enum amdgpu_hpd_id hpd)
279 bool connected = false;
283 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
287 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
291 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
295 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
299 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
303 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
314 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
316 * @adev: amdgpu_device pointer
317 * @hpd: hpd (hotplug detect) pin
319 * Set the polarity of the hpd pin (evergreen+).
321 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
322 enum amdgpu_hpd_id hpd)
325 bool connected = dce_v8_0_hpd_sense(adev, hpd);
329 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
331 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
333 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
334 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
337 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
339 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
341 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
342 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
345 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
347 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
349 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
350 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
353 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
355 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
357 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
358 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
361 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
363 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
365 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
366 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
369 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
371 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
373 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
374 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
382 * dce_v8_0_hpd_init - hpd setup callback.
384 * @adev: amdgpu_device pointer
386 * Setup the hpd pins used by the card (evergreen+).
387 * Enable the pin, set the polarity, and enable the hpd interrupts.
389 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
391 struct drm_device *dev = adev->ddev;
392 struct drm_connector *connector;
393 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
394 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
395 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
397 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
398 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
400 switch (amdgpu_connector->hpd.hpd) {
402 WREG32(mmDC_HPD1_CONTROL, tmp);
405 WREG32(mmDC_HPD2_CONTROL, tmp);
408 WREG32(mmDC_HPD3_CONTROL, tmp);
411 WREG32(mmDC_HPD4_CONTROL, tmp);
414 WREG32(mmDC_HPD5_CONTROL, tmp);
417 WREG32(mmDC_HPD6_CONTROL, tmp);
423 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
424 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
425 /* don't try to enable hpd on eDP or LVDS avoid breaking the
426 * aux dp channel on imac and help (but not completely fix)
427 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
428 * also avoid interrupt storms during dpms.
430 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
432 switch (amdgpu_connector->hpd.hpd) {
434 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
437 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
440 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
443 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
446 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
449 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
455 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
456 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
457 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
461 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
462 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
467 * dce_v8_0_hpd_fini - hpd tear down callback.
469 * @adev: amdgpu_device pointer
471 * Tear down the hpd pins used by the card (evergreen+).
472 * Disable the hpd interrupts.
474 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
476 struct drm_device *dev = adev->ddev;
477 struct drm_connector *connector;
479 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
480 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
482 switch (amdgpu_connector->hpd.hpd) {
484 WREG32(mmDC_HPD1_CONTROL, 0);
487 WREG32(mmDC_HPD2_CONTROL, 0);
490 WREG32(mmDC_HPD3_CONTROL, 0);
493 WREG32(mmDC_HPD4_CONTROL, 0);
496 WREG32(mmDC_HPD5_CONTROL, 0);
499 WREG32(mmDC_HPD6_CONTROL, 0);
504 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
508 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
510 return mmDC_GPIO_HPD_A;
513 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
519 for (i = 0; i < adev->mode_info.num_crtc; i++) {
520 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
521 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
522 crtc_hung |= (1 << i);
526 for (j = 0; j < 10; j++) {
527 for (i = 0; i < adev->mode_info.num_crtc; i++) {
528 if (crtc_hung & (1 << i)) {
529 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
530 if (tmp != crtc_status[i])
531 crtc_hung &= ~(1 << i);
542 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
543 struct amdgpu_mode_mc_save *save)
545 u32 crtc_enabled, tmp;
548 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
549 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
551 /* disable VGA render */
552 tmp = RREG32(mmVGA_RENDER_CONTROL);
553 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
554 WREG32(mmVGA_RENDER_CONTROL, tmp);
556 /* blank the display controllers */
557 for (i = 0; i < adev->mode_info.num_crtc; i++) {
558 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
559 CRTC_CONTROL, CRTC_MASTER_EN);
562 save->crtc_enabled[i] = true;
563 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
564 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
565 /*it is correct only for RGB ; black is 0*/
566 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
567 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
568 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
572 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
573 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
574 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
575 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
576 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
577 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
578 save->crtc_enabled[i] = false;
582 save->crtc_enabled[i] = false;
587 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
588 struct amdgpu_mode_mc_save *save)
593 /* update crtc base addresses */
594 for (i = 0; i < adev->mode_info.num_crtc; i++) {
595 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
596 upper_32_bits(adev->mc.vram_start));
597 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
598 (u32)adev->mc.vram_start);
600 if (save->crtc_enabled[i]) {
601 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
602 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
603 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
608 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
609 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
611 /* Unlock vga access */
612 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
614 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
617 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
622 /* Lockout access through VGA aperture*/
623 tmp = RREG32(mmVGA_HDP_CONTROL);
625 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
627 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
628 WREG32(mmVGA_HDP_CONTROL, tmp);
630 /* disable VGA render */
631 tmp = RREG32(mmVGA_RENDER_CONTROL);
633 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
635 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
636 WREG32(mmVGA_RENDER_CONTROL, tmp);
639 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
643 switch (adev->asic_type) {
661 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
663 /*Disable VGA render and enabled crtc, if has DCE engine*/
664 if (amdgpu_atombios_has_dce_engine_info(adev)) {
668 dce_v8_0_set_vga_render_state(adev, false);
671 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
672 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
673 CRTC_CONTROL, CRTC_MASTER_EN);
675 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
676 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
677 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
678 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
679 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
685 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
687 struct drm_device *dev = encoder->dev;
688 struct amdgpu_device *adev = dev->dev_private;
689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
690 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
691 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
694 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
697 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
698 bpc = amdgpu_connector_get_monitor_bpc(connector);
699 dither = amdgpu_connector->dither;
702 /* LVDS/eDP FMT is set up by atom */
703 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
706 /* not needed for analog */
707 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
708 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
716 if (dither == AMDGPU_FMT_DITHER_ENABLE)
717 /* XXX sort out optimal dither settings */
718 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
719 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
720 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
721 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
723 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
724 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
727 if (dither == AMDGPU_FMT_DITHER_ENABLE)
728 /* XXX sort out optimal dither settings */
729 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
730 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
731 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
732 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
733 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
735 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
736 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
739 if (dither == AMDGPU_FMT_DITHER_ENABLE)
740 /* XXX sort out optimal dither settings */
741 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
742 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
743 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
744 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
745 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
747 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
748 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
755 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
759 /* display watermark setup */
761 * dce_v8_0_line_buffer_adjust - Set up the line buffer
763 * @adev: amdgpu_device pointer
764 * @amdgpu_crtc: the selected display controller
765 * @mode: the current display mode on the selected display
768 * Setup up the line buffer allocation for
769 * the selected display controller (CIK).
770 * Returns the line buffer size in pixels.
772 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
773 struct amdgpu_crtc *amdgpu_crtc,
774 struct drm_display_mode *mode)
776 u32 tmp, buffer_alloc, i;
777 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
780 * There are 6 line buffers, one for each display controllers.
781 * There are 3 partitions per LB. Select the number of partitions
782 * to enable based on the display width. For display widths larger
783 * than 4096, you need use to use 2 display controllers and combine
784 * them using the stereo blender.
786 if (amdgpu_crtc->base.enabled && mode) {
787 if (mode->crtc_hdisplay < 1920) {
790 } else if (mode->crtc_hdisplay < 2560) {
793 } else if (mode->crtc_hdisplay < 4096) {
795 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
797 DRM_DEBUG_KMS("Mode too big for LB!\n");
799 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
806 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
807 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
808 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
810 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
811 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
812 for (i = 0; i < adev->usec_timeout; i++) {
813 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
814 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
819 if (amdgpu_crtc->base.enabled && mode) {
831 /* controller not enabled, so no lb used */
836 * cik_get_number_of_dram_channels - get the number of dram channels
838 * @adev: amdgpu_device pointer
840 * Look up the number of video ram channels (CIK).
841 * Used for display watermark bandwidth calculations
842 * Returns the number of dram channels
844 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
846 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
848 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
871 struct dce8_wm_params {
872 u32 dram_channels; /* number of dram channels */
873 u32 yclk; /* bandwidth per dram data pin in kHz */
874 u32 sclk; /* engine clock in kHz */
875 u32 disp_clk; /* display clock in kHz */
876 u32 src_width; /* viewport width */
877 u32 active_time; /* active display time in ns */
878 u32 blank_time; /* blank time in ns */
879 bool interlaced; /* mode is interlaced */
880 fixed20_12 vsc; /* vertical scale ratio */
881 u32 num_heads; /* number of active crtcs */
882 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
883 u32 lb_size; /* line buffer allocated to pipe */
884 u32 vtaps; /* vertical scaler taps */
888 * dce_v8_0_dram_bandwidth - get the dram bandwidth
890 * @wm: watermark calculation data
892 * Calculate the raw dram bandwidth (CIK).
893 * Used for display watermark bandwidth calculations
894 * Returns the dram bandwidth in MBytes/s
896 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
898 /* Calculate raw DRAM Bandwidth */
899 fixed20_12 dram_efficiency; /* 0.7 */
900 fixed20_12 yclk, dram_channels, bandwidth;
903 a.full = dfixed_const(1000);
904 yclk.full = dfixed_const(wm->yclk);
905 yclk.full = dfixed_div(yclk, a);
906 dram_channels.full = dfixed_const(wm->dram_channels * 4);
907 a.full = dfixed_const(10);
908 dram_efficiency.full = dfixed_const(7);
909 dram_efficiency.full = dfixed_div(dram_efficiency, a);
910 bandwidth.full = dfixed_mul(dram_channels, yclk);
911 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
913 return dfixed_trunc(bandwidth);
917 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
919 * @wm: watermark calculation data
921 * Calculate the dram bandwidth used for display (CIK).
922 * Used for display watermark bandwidth calculations
923 * Returns the dram bandwidth for display in MBytes/s
925 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
927 /* Calculate DRAM Bandwidth and the part allocated to display. */
928 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
929 fixed20_12 yclk, dram_channels, bandwidth;
932 a.full = dfixed_const(1000);
933 yclk.full = dfixed_const(wm->yclk);
934 yclk.full = dfixed_div(yclk, a);
935 dram_channels.full = dfixed_const(wm->dram_channels * 4);
936 a.full = dfixed_const(10);
937 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
938 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
939 bandwidth.full = dfixed_mul(dram_channels, yclk);
940 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
942 return dfixed_trunc(bandwidth);
946 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
948 * @wm: watermark calculation data
950 * Calculate the data return bandwidth used for display (CIK).
951 * Used for display watermark bandwidth calculations
952 * Returns the data return bandwidth in MBytes/s
954 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
956 /* Calculate the display Data return Bandwidth */
957 fixed20_12 return_efficiency; /* 0.8 */
958 fixed20_12 sclk, bandwidth;
961 a.full = dfixed_const(1000);
962 sclk.full = dfixed_const(wm->sclk);
963 sclk.full = dfixed_div(sclk, a);
964 a.full = dfixed_const(10);
965 return_efficiency.full = dfixed_const(8);
966 return_efficiency.full = dfixed_div(return_efficiency, a);
967 a.full = dfixed_const(32);
968 bandwidth.full = dfixed_mul(a, sclk);
969 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
971 return dfixed_trunc(bandwidth);
975 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
977 * @wm: watermark calculation data
979 * Calculate the dmif bandwidth used for display (CIK).
980 * Used for display watermark bandwidth calculations
981 * Returns the dmif bandwidth in MBytes/s
983 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
985 /* Calculate the DMIF Request Bandwidth */
986 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
987 fixed20_12 disp_clk, bandwidth;
990 a.full = dfixed_const(1000);
991 disp_clk.full = dfixed_const(wm->disp_clk);
992 disp_clk.full = dfixed_div(disp_clk, a);
993 a.full = dfixed_const(32);
994 b.full = dfixed_mul(a, disp_clk);
996 a.full = dfixed_const(10);
997 disp_clk_request_efficiency.full = dfixed_const(8);
998 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1000 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1002 return dfixed_trunc(bandwidth);
1006 * dce_v8_0_available_bandwidth - get the min available bandwidth
1008 * @wm: watermark calculation data
1010 * Calculate the min available bandwidth used for display (CIK).
1011 * Used for display watermark bandwidth calculations
1012 * Returns the min available bandwidth in MBytes/s
1014 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
1016 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1017 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
1018 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
1019 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
1021 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1025 * dce_v8_0_average_bandwidth - get the average available bandwidth
1027 * @wm: watermark calculation data
1029 * Calculate the average available bandwidth used for display (CIK).
1030 * Used for display watermark bandwidth calculations
1031 * Returns the average available bandwidth in MBytes/s
1033 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
1035 /* Calculate the display mode Average Bandwidth
1036 * DisplayMode should contain the source and destination dimensions,
1040 fixed20_12 line_time;
1041 fixed20_12 src_width;
1042 fixed20_12 bandwidth;
1045 a.full = dfixed_const(1000);
1046 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1047 line_time.full = dfixed_div(line_time, a);
1048 bpp.full = dfixed_const(wm->bytes_per_pixel);
1049 src_width.full = dfixed_const(wm->src_width);
1050 bandwidth.full = dfixed_mul(src_width, bpp);
1051 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1052 bandwidth.full = dfixed_div(bandwidth, line_time);
1054 return dfixed_trunc(bandwidth);
1058 * dce_v8_0_latency_watermark - get the latency watermark
1060 * @wm: watermark calculation data
1062 * Calculate the latency watermark (CIK).
1063 * Used for display watermark bandwidth calculations
1064 * Returns the latency watermark in ns
1066 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1068 /* First calculate the latency in ns */
1069 u32 mc_latency = 2000; /* 2000 ns. */
1070 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1071 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1072 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1073 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1074 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1075 (wm->num_heads * cursor_line_pair_return_time);
1076 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1077 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1078 u32 tmp, dmif_size = 12288;
1081 if (wm->num_heads == 0)
1084 a.full = dfixed_const(2);
1085 b.full = dfixed_const(1);
1086 if ((wm->vsc.full > a.full) ||
1087 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1089 ((wm->vsc.full >= a.full) && wm->interlaced))
1090 max_src_lines_per_dst_line = 4;
1092 max_src_lines_per_dst_line = 2;
1094 a.full = dfixed_const(available_bandwidth);
1095 b.full = dfixed_const(wm->num_heads);
1096 a.full = dfixed_div(a, b);
1098 b.full = dfixed_const(mc_latency + 512);
1099 c.full = dfixed_const(wm->disp_clk);
1100 b.full = dfixed_div(b, c);
1102 c.full = dfixed_const(dmif_size);
1103 b.full = dfixed_div(c, b);
1105 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1107 b.full = dfixed_const(1000);
1108 c.full = dfixed_const(wm->disp_clk);
1109 b.full = dfixed_div(c, b);
1110 c.full = dfixed_const(wm->bytes_per_pixel);
1111 b.full = dfixed_mul(b, c);
1113 lb_fill_bw = min(tmp, dfixed_trunc(b));
1115 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1116 b.full = dfixed_const(1000);
1117 c.full = dfixed_const(lb_fill_bw);
1118 b.full = dfixed_div(c, b);
1119 a.full = dfixed_div(a, b);
1120 line_fill_time = dfixed_trunc(a);
1122 if (line_fill_time < wm->active_time)
1125 return latency + (line_fill_time - wm->active_time);
1130 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1131 * average and available dram bandwidth
1133 * @wm: watermark calculation data
1135 * Check if the display average bandwidth fits in the display
1136 * dram bandwidth (CIK).
1137 * Used for display watermark bandwidth calculations
1138 * Returns true if the display fits, false if not.
1140 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1142 if (dce_v8_0_average_bandwidth(wm) <=
1143 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1150 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1151 * average and available bandwidth
1153 * @wm: watermark calculation data
1155 * Check if the display average bandwidth fits in the display
1156 * available bandwidth (CIK).
1157 * Used for display watermark bandwidth calculations
1158 * Returns true if the display fits, false if not.
1160 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1162 if (dce_v8_0_average_bandwidth(wm) <=
1163 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1170 * dce_v8_0_check_latency_hiding - check latency hiding
1172 * @wm: watermark calculation data
1174 * Check latency hiding (CIK).
1175 * Used for display watermark bandwidth calculations
1176 * Returns true if the display fits, false if not.
1178 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1180 u32 lb_partitions = wm->lb_size / wm->src_width;
1181 u32 line_time = wm->active_time + wm->blank_time;
1182 u32 latency_tolerant_lines;
1186 a.full = dfixed_const(1);
1187 if (wm->vsc.full > a.full)
1188 latency_tolerant_lines = 1;
1190 if (lb_partitions <= (wm->vtaps + 1))
1191 latency_tolerant_lines = 1;
1193 latency_tolerant_lines = 2;
1196 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1198 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1205 * dce_v8_0_program_watermarks - program display watermarks
1207 * @adev: amdgpu_device pointer
1208 * @amdgpu_crtc: the selected display controller
1209 * @lb_size: line buffer size
1210 * @num_heads: number of display controllers in use
1212 * Calculate and program the display watermarks for the
1213 * selected display controller (CIK).
1215 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1216 struct amdgpu_crtc *amdgpu_crtc,
1217 u32 lb_size, u32 num_heads)
1219 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1220 struct dce8_wm_params wm_low, wm_high;
1223 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1224 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1226 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1227 pixel_period = 1000000 / (u32)mode->clock;
1228 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1230 /* watermark for high clocks */
1231 if (adev->pm.dpm_enabled) {
1233 amdgpu_dpm_get_mclk(adev, false) * 10;
1235 amdgpu_dpm_get_sclk(adev, false) * 10;
1237 wm_high.yclk = adev->pm.current_mclk * 10;
1238 wm_high.sclk = adev->pm.current_sclk * 10;
1241 wm_high.disp_clk = mode->clock;
1242 wm_high.src_width = mode->crtc_hdisplay;
1243 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1244 wm_high.blank_time = line_time - wm_high.active_time;
1245 wm_high.interlaced = false;
1246 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1247 wm_high.interlaced = true;
1248 wm_high.vsc = amdgpu_crtc->vsc;
1250 if (amdgpu_crtc->rmx_type != RMX_OFF)
1252 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1253 wm_high.lb_size = lb_size;
1254 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1255 wm_high.num_heads = num_heads;
1257 /* set for high clocks */
1258 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1260 /* possibly force display priority to high */
1261 /* should really do this at mode validation time... */
1262 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1263 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1264 !dce_v8_0_check_latency_hiding(&wm_high) ||
1265 (adev->mode_info.disp_priority == 2)) {
1266 DRM_DEBUG_KMS("force priority to high\n");
1269 /* watermark for low clocks */
1270 if (adev->pm.dpm_enabled) {
1272 amdgpu_dpm_get_mclk(adev, true) * 10;
1274 amdgpu_dpm_get_sclk(adev, true) * 10;
1276 wm_low.yclk = adev->pm.current_mclk * 10;
1277 wm_low.sclk = adev->pm.current_sclk * 10;
1280 wm_low.disp_clk = mode->clock;
1281 wm_low.src_width = mode->crtc_hdisplay;
1282 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1283 wm_low.blank_time = line_time - wm_low.active_time;
1284 wm_low.interlaced = false;
1285 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1286 wm_low.interlaced = true;
1287 wm_low.vsc = amdgpu_crtc->vsc;
1289 if (amdgpu_crtc->rmx_type != RMX_OFF)
1291 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1292 wm_low.lb_size = lb_size;
1293 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1294 wm_low.num_heads = num_heads;
1296 /* set for low clocks */
1297 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1299 /* possibly force display priority to high */
1300 /* should really do this at mode validation time... */
1301 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1302 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1303 !dce_v8_0_check_latency_hiding(&wm_low) ||
1304 (adev->mode_info.disp_priority == 2)) {
1305 DRM_DEBUG_KMS("force priority to high\n");
1307 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1311 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1313 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1314 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1315 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1316 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1317 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1318 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1320 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1321 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1322 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1323 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1324 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1325 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1326 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1327 /* restore original selection */
1328 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1330 /* save values for DPM */
1331 amdgpu_crtc->line_time = line_time;
1332 amdgpu_crtc->wm_high = latency_watermark_a;
1333 amdgpu_crtc->wm_low = latency_watermark_b;
1334 /* Save number of lines the linebuffer leads before the scanout */
1335 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1339 * dce_v8_0_bandwidth_update - program display watermarks
1341 * @adev: amdgpu_device pointer
1343 * Calculate and program the display watermarks and line
1344 * buffer allocation (CIK).
1346 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1348 struct drm_display_mode *mode = NULL;
1349 u32 num_heads = 0, lb_size;
1352 amdgpu_update_display_priority(adev);
1354 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1355 if (adev->mode_info.crtcs[i]->base.enabled)
1358 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1359 mode = &adev->mode_info.crtcs[i]->base.mode;
1360 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1361 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1362 lb_size, num_heads);
1366 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1371 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1372 offset = adev->mode_info.audio.pin[i].offset;
1373 tmp = RREG32_AUDIO_ENDPT(offset,
1374 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1376 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1377 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1378 adev->mode_info.audio.pin[i].connected = false;
1380 adev->mode_info.audio.pin[i].connected = true;
1384 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1388 dce_v8_0_audio_get_connected_pins(adev);
1390 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1391 if (adev->mode_info.audio.pin[i].connected)
1392 return &adev->mode_info.audio.pin[i];
1394 DRM_ERROR("No connected audio pins found!\n");
1398 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1400 struct amdgpu_device *adev = encoder->dev->dev_private;
1401 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1402 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1405 if (!dig || !dig->afmt || !dig->afmt->pin)
1408 offset = dig->afmt->offset;
1410 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1411 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1414 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1415 struct drm_display_mode *mode)
1417 struct amdgpu_device *adev = encoder->dev->dev_private;
1418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1419 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1420 struct drm_connector *connector;
1421 struct amdgpu_connector *amdgpu_connector = NULL;
1422 u32 tmp = 0, offset;
1424 if (!dig || !dig->afmt || !dig->afmt->pin)
1427 offset = dig->afmt->pin->offset;
1429 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1430 if (connector->encoder == encoder) {
1431 amdgpu_connector = to_amdgpu_connector(connector);
1436 if (!amdgpu_connector) {
1437 DRM_ERROR("Couldn't find encoder's connector\n");
1441 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1442 if (connector->latency_present[1])
1444 (connector->video_latency[1] <<
1445 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1446 (connector->audio_latency[1] <<
1447 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1451 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1453 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1455 if (connector->latency_present[0])
1457 (connector->video_latency[0] <<
1458 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1459 (connector->audio_latency[0] <<
1460 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1464 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1466 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1469 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1472 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1474 struct amdgpu_device *adev = encoder->dev->dev_private;
1475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1476 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1477 struct drm_connector *connector;
1478 struct amdgpu_connector *amdgpu_connector = NULL;
1483 if (!dig || !dig->afmt || !dig->afmt->pin)
1486 offset = dig->afmt->pin->offset;
1488 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1489 if (connector->encoder == encoder) {
1490 amdgpu_connector = to_amdgpu_connector(connector);
1495 if (!amdgpu_connector) {
1496 DRM_ERROR("Couldn't find encoder's connector\n");
1500 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1501 if (sad_count < 0) {
1502 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1506 /* program the speaker allocation */
1507 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1508 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1509 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1511 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1513 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1515 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1516 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1521 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1523 struct amdgpu_device *adev = encoder->dev->dev_private;
1524 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1525 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1527 struct drm_connector *connector;
1528 struct amdgpu_connector *amdgpu_connector = NULL;
1529 struct cea_sad *sads;
1532 static const u16 eld_reg_to_type[][2] = {
1533 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1534 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1535 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1539 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1540 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1541 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1542 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1547 if (!dig || !dig->afmt || !dig->afmt->pin)
1550 offset = dig->afmt->pin->offset;
1552 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1553 if (connector->encoder == encoder) {
1554 amdgpu_connector = to_amdgpu_connector(connector);
1559 if (!amdgpu_connector) {
1560 DRM_ERROR("Couldn't find encoder's connector\n");
1564 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1565 if (sad_count <= 0) {
1566 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1571 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1573 u8 stereo_freqs = 0;
1574 int max_channels = -1;
1577 for (j = 0; j < sad_count; j++) {
1578 struct cea_sad *sad = &sads[j];
1580 if (sad->format == eld_reg_to_type[i][1]) {
1581 if (sad->channels > max_channels) {
1582 value = (sad->channels <<
1583 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1585 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1587 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1588 max_channels = sad->channels;
1591 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1592 stereo_freqs |= sad->freq;
1598 value |= (stereo_freqs <<
1599 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1601 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1607 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1608 struct amdgpu_audio_pin *pin,
1614 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1615 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1618 static const u32 pin_offsets[7] =
1629 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1636 adev->mode_info.audio.enabled = true;
1638 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1639 adev->mode_info.audio.num_pins = 7;
1640 else if ((adev->asic_type == CHIP_KABINI) ||
1641 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1642 adev->mode_info.audio.num_pins = 3;
1643 else if ((adev->asic_type == CHIP_BONAIRE) ||
1644 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1645 adev->mode_info.audio.num_pins = 7;
1647 adev->mode_info.audio.num_pins = 3;
1649 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1650 adev->mode_info.audio.pin[i].channels = -1;
1651 adev->mode_info.audio.pin[i].rate = -1;
1652 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1653 adev->mode_info.audio.pin[i].status_bits = 0;
1654 adev->mode_info.audio.pin[i].category_code = 0;
1655 adev->mode_info.audio.pin[i].connected = false;
1656 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1657 adev->mode_info.audio.pin[i].id = i;
1658 /* disable audio. it will be set up later */
1659 /* XXX remove once we switch to ip funcs */
1660 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1666 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1673 if (!adev->mode_info.audio.enabled)
1676 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1677 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1679 adev->mode_info.audio.enabled = false;
1683 * update the N and CTS parameters for a given pixel clock rate
1685 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1687 struct drm_device *dev = encoder->dev;
1688 struct amdgpu_device *adev = dev->dev_private;
1689 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1690 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1691 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1692 uint32_t offset = dig->afmt->offset;
1694 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1695 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1697 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1698 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1700 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1701 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1705 * build a HDMI Video Info Frame
1707 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1708 void *buffer, size_t size)
1710 struct drm_device *dev = encoder->dev;
1711 struct amdgpu_device *adev = dev->dev_private;
1712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1713 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1714 uint32_t offset = dig->afmt->offset;
1715 uint8_t *frame = buffer + 3;
1716 uint8_t *header = buffer;
1718 WREG32(mmAFMT_AVI_INFO0 + offset,
1719 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1720 WREG32(mmAFMT_AVI_INFO1 + offset,
1721 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1722 WREG32(mmAFMT_AVI_INFO2 + offset,
1723 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1724 WREG32(mmAFMT_AVI_INFO3 + offset,
1725 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1728 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1730 struct drm_device *dev = encoder->dev;
1731 struct amdgpu_device *adev = dev->dev_private;
1732 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1733 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1734 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1735 u32 dto_phase = 24 * 1000;
1736 u32 dto_modulo = clock;
1738 if (!dig || !dig->afmt)
1741 /* XXX two dtos; generally use dto0 for hdmi */
1742 /* Express [24MHz / target pixel clock] as an exact rational
1743 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1744 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1746 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1747 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1748 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1752 * update the info frames with the data from the current display mode
1754 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1755 struct drm_display_mode *mode)
1757 struct drm_device *dev = encoder->dev;
1758 struct amdgpu_device *adev = dev->dev_private;
1759 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1760 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1761 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1762 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1763 struct hdmi_avi_infoframe frame;
1764 uint32_t offset, val;
1768 if (!dig || !dig->afmt)
1771 /* Silent, r600_hdmi_enable will raise WARN for us */
1772 if (!dig->afmt->enabled)
1775 offset = dig->afmt->offset;
1777 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1778 if (encoder->crtc) {
1779 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1780 bpc = amdgpu_crtc->bpc;
1783 /* disable audio prior to setting up hw */
1784 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1785 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1787 dce_v8_0_audio_set_dto(encoder, mode->clock);
1789 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1790 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1792 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1794 val = RREG32(mmHDMI_CONTROL + offset);
1795 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1796 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1804 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1805 connector->name, bpc);
1808 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1809 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1810 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1814 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1815 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1816 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1821 WREG32(mmHDMI_CONTROL + offset, val);
1823 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1824 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1825 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1826 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1828 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1829 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1830 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1832 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1833 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1835 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1836 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1838 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1840 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1841 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1842 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1844 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1845 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1847 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1850 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1851 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1853 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1854 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1855 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1857 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1859 WREG32(mmAFMT_60958_0 + offset,
1860 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1862 WREG32(mmAFMT_60958_1 + offset,
1863 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1865 WREG32(mmAFMT_60958_2 + offset,
1866 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1867 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1868 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1869 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1870 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1871 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1873 dce_v8_0_audio_write_speaker_allocation(encoder);
1876 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1877 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1879 dce_v8_0_afmt_audio_select_pin(encoder);
1880 dce_v8_0_audio_write_sad_regs(encoder);
1881 dce_v8_0_audio_write_latency_fields(encoder, mode);
1883 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1885 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1889 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1891 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1895 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1897 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1898 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1899 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1901 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1902 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1903 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1905 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1906 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1908 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1909 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1910 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1911 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1913 /* enable audio after setting up hw */
1914 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1917 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1919 struct drm_device *dev = encoder->dev;
1920 struct amdgpu_device *adev = dev->dev_private;
1921 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1922 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1924 if (!dig || !dig->afmt)
1927 /* Silent, r600_hdmi_enable will raise WARN for us */
1928 if (enable && dig->afmt->enabled)
1930 if (!enable && !dig->afmt->enabled)
1933 if (!enable && dig->afmt->pin) {
1934 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1935 dig->afmt->pin = NULL;
1938 dig->afmt->enabled = enable;
1940 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1941 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1944 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1948 for (i = 0; i < adev->mode_info.num_dig; i++)
1949 adev->mode_info.afmt[i] = NULL;
1951 /* DCE8 has audio blocks tied to DIG encoders */
1952 for (i = 0; i < adev->mode_info.num_dig; i++) {
1953 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1954 if (adev->mode_info.afmt[i]) {
1955 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1956 adev->mode_info.afmt[i]->id = i;
1959 for (j = 0; j < i; j++) {
1960 kfree(adev->mode_info.afmt[j]);
1961 adev->mode_info.afmt[j] = NULL;
1969 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1973 for (i = 0; i < adev->mode_info.num_dig; i++) {
1974 kfree(adev->mode_info.afmt[i]);
1975 adev->mode_info.afmt[i] = NULL;
1979 static const u32 vga_control_regs[6] =
1989 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1991 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992 struct drm_device *dev = crtc->dev;
1993 struct amdgpu_device *adev = dev->dev_private;
1996 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1998 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2000 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2003 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
2005 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2010 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2012 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2015 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
2016 struct drm_framebuffer *fb,
2017 int x, int y, int atomic)
2019 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020 struct drm_device *dev = crtc->dev;
2021 struct amdgpu_device *adev = dev->dev_private;
2022 struct amdgpu_framebuffer *amdgpu_fb;
2023 struct drm_framebuffer *target_fb;
2024 struct drm_gem_object *obj;
2025 struct amdgpu_bo *abo;
2026 uint64_t fb_location, tiling_flags;
2027 uint32_t fb_format, fb_pitch_pixels;
2028 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2030 u32 viewport_w, viewport_h;
2032 bool bypass_lut = false;
2036 if (!atomic && !crtc->primary->fb) {
2037 DRM_DEBUG_KMS("No FB bound\n");
2042 amdgpu_fb = to_amdgpu_framebuffer(fb);
2045 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2046 target_fb = crtc->primary->fb;
2049 /* If atomic, assume fb object is pinned & idle & fenced and
2050 * just update base pointers
2052 obj = amdgpu_fb->obj;
2053 abo = gem_to_amdgpu_bo(obj);
2054 r = amdgpu_bo_reserve(abo, false);
2055 if (unlikely(r != 0))
2059 fb_location = amdgpu_bo_gpu_offset(abo);
2061 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2062 if (unlikely(r != 0)) {
2063 amdgpu_bo_unreserve(abo);
2068 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2069 amdgpu_bo_unreserve(abo);
2071 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2073 switch (target_fb->pixel_format) {
2075 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2076 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2078 case DRM_FORMAT_XRGB4444:
2079 case DRM_FORMAT_ARGB4444:
2080 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2081 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2083 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2086 case DRM_FORMAT_XRGB1555:
2087 case DRM_FORMAT_ARGB1555:
2088 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2089 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2091 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2094 case DRM_FORMAT_BGRX5551:
2095 case DRM_FORMAT_BGRA5551:
2096 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2097 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2099 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2102 case DRM_FORMAT_RGB565:
2103 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2104 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2106 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2109 case DRM_FORMAT_XRGB8888:
2110 case DRM_FORMAT_ARGB8888:
2111 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2112 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2114 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2117 case DRM_FORMAT_XRGB2101010:
2118 case DRM_FORMAT_ARGB2101010:
2119 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2120 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2122 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2124 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2127 case DRM_FORMAT_BGRX1010102:
2128 case DRM_FORMAT_BGRA1010102:
2129 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2130 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2132 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2134 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2138 format_name = drm_get_format_name(target_fb->pixel_format);
2139 DRM_ERROR("Unsupported screen format %s\n", format_name);
2144 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2145 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2147 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2148 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2149 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2150 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2151 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2153 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2154 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2155 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2156 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2157 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2158 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2159 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2160 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2161 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2164 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2166 dce_v8_0_vga_enable(crtc, false);
2168 /* Make sure surface address is updated at vertical blank rather than
2171 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2173 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2174 upper_32_bits(fb_location));
2175 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2176 upper_32_bits(fb_location));
2177 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2178 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2179 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2180 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2181 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2182 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2185 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2186 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2187 * retain the full precision throughout the pipeline.
2189 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2190 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2191 ~LUT_10BIT_BYPASS_EN);
2194 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2196 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2197 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2198 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2199 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2200 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2201 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2203 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2206 dce_v8_0_grph_enable(crtc, true);
2208 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2213 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2215 viewport_w = crtc->mode.hdisplay;
2216 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2217 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2218 (viewport_w << 16) | viewport_h);
2220 /* set pageflip to happen anywhere in vblank interval */
2221 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2223 if (!atomic && fb && fb != crtc->primary->fb) {
2224 amdgpu_fb = to_amdgpu_framebuffer(fb);
2225 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2226 r = amdgpu_bo_reserve(abo, false);
2227 if (unlikely(r != 0))
2229 amdgpu_bo_unpin(abo);
2230 amdgpu_bo_unreserve(abo);
2233 /* Bytes per pixel may have changed */
2234 dce_v8_0_bandwidth_update(adev);
2239 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2240 struct drm_display_mode *mode)
2242 struct drm_device *dev = crtc->dev;
2243 struct amdgpu_device *adev = dev->dev_private;
2244 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2246 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2247 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2248 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2250 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2253 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2255 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2256 struct drm_device *dev = crtc->dev;
2257 struct amdgpu_device *adev = dev->dev_private;
2260 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2262 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2263 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2264 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2265 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2266 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2267 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2268 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2269 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2270 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2271 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2273 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2275 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2276 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2277 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2279 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2280 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2281 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2283 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2284 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2286 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2287 for (i = 0; i < 256; i++) {
2288 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2289 (amdgpu_crtc->lut_r[i] << 20) |
2290 (amdgpu_crtc->lut_g[i] << 10) |
2291 (amdgpu_crtc->lut_b[i] << 0));
2294 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2295 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2296 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2297 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2298 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2299 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2300 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2301 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2302 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2303 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2304 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2305 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2306 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2307 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2308 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2309 /* XXX this only needs to be programmed once per crtc at startup,
2310 * not sure where the best place for it is
2312 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2313 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2316 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2318 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2319 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2321 switch (amdgpu_encoder->encoder_id) {
2322 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2328 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2334 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2340 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2344 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2350 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2354 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2355 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2356 * monitors a dedicated PPLL must be used. If a particular board has
2357 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2358 * as there is no need to program the PLL itself. If we are not able to
2359 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2360 * avoid messing up an existing monitor.
2362 * Asic specific PLL information
2366 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2368 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2371 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374 struct drm_device *dev = crtc->dev;
2375 struct amdgpu_device *adev = dev->dev_private;
2379 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2380 if (adev->clock.dp_extclk)
2381 /* skip PPLL programming if using ext clock */
2382 return ATOM_PPLL_INVALID;
2384 /* use the same PPLL for all DP monitors */
2385 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2386 if (pll != ATOM_PPLL_INVALID)
2390 /* use the same PPLL for all monitors with the same clock */
2391 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2392 if (pll != ATOM_PPLL_INVALID)
2395 /* otherwise, pick one of the plls */
2396 if ((adev->asic_type == CHIP_KABINI) ||
2397 (adev->asic_type == CHIP_MULLINS)) {
2398 /* KB/ML has PPLL1 and PPLL2 */
2399 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2400 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2402 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2404 DRM_ERROR("unable to allocate a PPLL\n");
2405 return ATOM_PPLL_INVALID;
2407 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2408 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2409 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2411 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2413 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2415 DRM_ERROR("unable to allocate a PPLL\n");
2416 return ATOM_PPLL_INVALID;
2418 return ATOM_PPLL_INVALID;
2421 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2423 struct amdgpu_device *adev = crtc->dev->dev_private;
2424 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2427 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2429 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2431 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2432 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2435 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2437 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2438 struct amdgpu_device *adev = crtc->dev->dev_private;
2440 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2441 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2442 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2445 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2447 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2448 struct amdgpu_device *adev = crtc->dev->dev_private;
2450 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2451 upper_32_bits(amdgpu_crtc->cursor_addr));
2452 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2453 lower_32_bits(amdgpu_crtc->cursor_addr));
2455 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2456 CUR_CONTROL__CURSOR_EN_MASK |
2457 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2458 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2461 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2464 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2465 struct amdgpu_device *adev = crtc->dev->dev_private;
2466 int xorigin = 0, yorigin = 0;
2468 /* avivo cursor are offset into the total surface */
2471 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2474 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2478 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2482 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2483 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2484 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2485 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2487 amdgpu_crtc->cursor_x = x;
2488 amdgpu_crtc->cursor_y = y;
2493 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2498 dce_v8_0_lock_cursor(crtc, true);
2499 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2500 dce_v8_0_lock_cursor(crtc, false);
2505 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2506 struct drm_file *file_priv,
2513 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2514 struct drm_gem_object *obj;
2515 struct amdgpu_bo *aobj;
2519 /* turn off cursor */
2520 dce_v8_0_hide_cursor(crtc);
2525 if ((width > amdgpu_crtc->max_cursor_width) ||
2526 (height > amdgpu_crtc->max_cursor_height)) {
2527 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2531 obj = drm_gem_object_lookup(file_priv, handle);
2533 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2537 aobj = gem_to_amdgpu_bo(obj);
2538 ret = amdgpu_bo_reserve(aobj, false);
2540 drm_gem_object_unreference_unlocked(obj);
2544 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2545 amdgpu_bo_unreserve(aobj);
2547 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2548 drm_gem_object_unreference_unlocked(obj);
2552 amdgpu_crtc->cursor_width = width;
2553 amdgpu_crtc->cursor_height = height;
2555 dce_v8_0_lock_cursor(crtc, true);
2557 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2558 hot_y != amdgpu_crtc->cursor_hot_y) {
2561 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2562 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2564 dce_v8_0_cursor_move_locked(crtc, x, y);
2566 amdgpu_crtc->cursor_hot_x = hot_x;
2567 amdgpu_crtc->cursor_hot_y = hot_y;
2570 dce_v8_0_show_cursor(crtc);
2571 dce_v8_0_lock_cursor(crtc, false);
2574 if (amdgpu_crtc->cursor_bo) {
2575 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2576 ret = amdgpu_bo_reserve(aobj, false);
2577 if (likely(ret == 0)) {
2578 amdgpu_bo_unpin(aobj);
2579 amdgpu_bo_unreserve(aobj);
2581 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2584 amdgpu_crtc->cursor_bo = obj;
2588 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2592 if (amdgpu_crtc->cursor_bo) {
2593 dce_v8_0_lock_cursor(crtc, true);
2595 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2596 amdgpu_crtc->cursor_y);
2598 dce_v8_0_show_cursor(crtc);
2600 dce_v8_0_lock_cursor(crtc, false);
2604 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2605 u16 *blue, uint32_t size)
2607 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2610 /* userspace palettes are always correct as is */
2611 for (i = 0; i < size; i++) {
2612 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2613 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2614 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2616 dce_v8_0_crtc_load_lut(crtc);
2621 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2623 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2625 drm_crtc_cleanup(crtc);
2629 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2630 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2631 .cursor_move = dce_v8_0_crtc_cursor_move,
2632 .gamma_set = dce_v8_0_crtc_gamma_set,
2633 .set_config = amdgpu_crtc_set_config,
2634 .destroy = dce_v8_0_crtc_destroy,
2635 .page_flip_target = amdgpu_crtc_page_flip_target,
2638 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2640 struct drm_device *dev = crtc->dev;
2641 struct amdgpu_device *adev = dev->dev_private;
2642 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2646 case DRM_MODE_DPMS_ON:
2647 amdgpu_crtc->enabled = true;
2648 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2649 dce_v8_0_vga_enable(crtc, true);
2650 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2651 dce_v8_0_vga_enable(crtc, false);
2652 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2653 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2654 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2655 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2656 drm_crtc_vblank_on(crtc);
2657 dce_v8_0_crtc_load_lut(crtc);
2659 case DRM_MODE_DPMS_STANDBY:
2660 case DRM_MODE_DPMS_SUSPEND:
2661 case DRM_MODE_DPMS_OFF:
2662 drm_crtc_vblank_off(crtc);
2663 if (amdgpu_crtc->enabled) {
2664 dce_v8_0_vga_enable(crtc, true);
2665 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2666 dce_v8_0_vga_enable(crtc, false);
2668 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2669 amdgpu_crtc->enabled = false;
2672 /* adjust pm to dpms */
2673 amdgpu_pm_compute_clocks(adev);
2676 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2678 /* disable crtc pair power gating before programming */
2679 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2680 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2681 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2684 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2686 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2687 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2690 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2692 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2693 struct drm_device *dev = crtc->dev;
2694 struct amdgpu_device *adev = dev->dev_private;
2695 struct amdgpu_atom_ss ss;
2698 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2699 if (crtc->primary->fb) {
2701 struct amdgpu_framebuffer *amdgpu_fb;
2702 struct amdgpu_bo *abo;
2704 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2705 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2706 r = amdgpu_bo_reserve(abo, false);
2708 DRM_ERROR("failed to reserve abo before unpin\n");
2710 amdgpu_bo_unpin(abo);
2711 amdgpu_bo_unreserve(abo);
2714 /* disable the GRPH */
2715 dce_v8_0_grph_enable(crtc, false);
2717 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2719 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2720 if (adev->mode_info.crtcs[i] &&
2721 adev->mode_info.crtcs[i]->enabled &&
2722 i != amdgpu_crtc->crtc_id &&
2723 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2724 /* one other crtc is using this pll don't turn
2731 switch (amdgpu_crtc->pll_id) {
2734 /* disable the ppll */
2735 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2736 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2739 /* disable the ppll */
2740 if ((adev->asic_type == CHIP_KAVERI) ||
2741 (adev->asic_type == CHIP_BONAIRE) ||
2742 (adev->asic_type == CHIP_HAWAII))
2743 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2744 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2750 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2751 amdgpu_crtc->adjusted_clock = 0;
2752 amdgpu_crtc->encoder = NULL;
2753 amdgpu_crtc->connector = NULL;
2756 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2757 struct drm_display_mode *mode,
2758 struct drm_display_mode *adjusted_mode,
2759 int x, int y, struct drm_framebuffer *old_fb)
2761 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2763 if (!amdgpu_crtc->adjusted_clock)
2766 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2767 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2768 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2769 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2770 amdgpu_atombios_crtc_scaler_setup(crtc);
2771 dce_v8_0_cursor_reset(crtc);
2772 /* update the hw version fpr dpm */
2773 amdgpu_crtc->hw_mode = *adjusted_mode;
2778 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2779 const struct drm_display_mode *mode,
2780 struct drm_display_mode *adjusted_mode)
2782 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_encoder *encoder;
2786 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2788 if (encoder->crtc == crtc) {
2789 amdgpu_crtc->encoder = encoder;
2790 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2794 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2795 amdgpu_crtc->encoder = NULL;
2796 amdgpu_crtc->connector = NULL;
2799 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2801 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2804 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2805 /* if we can't get a PPLL for a non-DP encoder, fail */
2806 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2807 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2813 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2814 struct drm_framebuffer *old_fb)
2816 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2819 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2820 struct drm_framebuffer *fb,
2821 int x, int y, enum mode_set_atomic state)
2823 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2826 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2827 .dpms = dce_v8_0_crtc_dpms,
2828 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2829 .mode_set = dce_v8_0_crtc_mode_set,
2830 .mode_set_base = dce_v8_0_crtc_set_base,
2831 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2832 .prepare = dce_v8_0_crtc_prepare,
2833 .commit = dce_v8_0_crtc_commit,
2834 .load_lut = dce_v8_0_crtc_load_lut,
2835 .disable = dce_v8_0_crtc_disable,
2838 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2840 struct amdgpu_crtc *amdgpu_crtc;
2843 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2844 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2845 if (amdgpu_crtc == NULL)
2848 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2850 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2851 amdgpu_crtc->crtc_id = index;
2852 adev->mode_info.crtcs[index] = amdgpu_crtc;
2854 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2855 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2856 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2857 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2859 for (i = 0; i < 256; i++) {
2860 amdgpu_crtc->lut_r[i] = i << 2;
2861 amdgpu_crtc->lut_g[i] = i << 2;
2862 amdgpu_crtc->lut_b[i] = i << 2;
2865 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2867 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2868 amdgpu_crtc->adjusted_clock = 0;
2869 amdgpu_crtc->encoder = NULL;
2870 amdgpu_crtc->connector = NULL;
2871 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2876 static int dce_v8_0_early_init(void *handle)
2878 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2880 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2881 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2883 dce_v8_0_set_display_funcs(adev);
2884 dce_v8_0_set_irq_funcs(adev);
2886 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2888 switch (adev->asic_type) {
2891 adev->mode_info.num_hpd = 6;
2892 adev->mode_info.num_dig = 6;
2895 adev->mode_info.num_hpd = 6;
2896 adev->mode_info.num_dig = 7;
2900 adev->mode_info.num_hpd = 6;
2901 adev->mode_info.num_dig = 6; /* ? */
2904 /* FIXME: not supported yet */
2911 static int dce_v8_0_sw_init(void *handle)
2914 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2916 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2917 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2922 for (i = 8; i < 20; i += 2) {
2923 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2929 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2933 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2935 adev->ddev->mode_config.async_page_flip = true;
2937 adev->ddev->mode_config.max_width = 16384;
2938 adev->ddev->mode_config.max_height = 16384;
2940 adev->ddev->mode_config.preferred_depth = 24;
2941 adev->ddev->mode_config.prefer_shadow = 1;
2943 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2945 r = amdgpu_modeset_create_props(adev);
2949 adev->ddev->mode_config.max_width = 16384;
2950 adev->ddev->mode_config.max_height = 16384;
2952 /* allocate crtcs */
2953 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2954 r = dce_v8_0_crtc_init(adev, i);
2959 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2960 amdgpu_print_display_setup(adev->ddev);
2965 r = dce_v8_0_afmt_init(adev);
2969 r = dce_v8_0_audio_init(adev);
2973 drm_kms_helper_poll_init(adev->ddev);
2975 adev->mode_info.mode_config_initialized = true;
2979 static int dce_v8_0_sw_fini(void *handle)
2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2983 kfree(adev->mode_info.bios_hardcoded_edid);
2985 drm_kms_helper_poll_fini(adev->ddev);
2987 dce_v8_0_audio_fini(adev);
2989 dce_v8_0_afmt_fini(adev);
2991 drm_mode_config_cleanup(adev->ddev);
2992 adev->mode_info.mode_config_initialized = false;
2997 static int dce_v8_0_hw_init(void *handle)
3000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3002 /* init dig PHYs, disp eng pll */
3003 amdgpu_atombios_encoder_init_dig(adev);
3004 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3006 /* initialize hpd */
3007 dce_v8_0_hpd_init(adev);
3009 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3010 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3013 dce_v8_0_pageflip_interrupt_init(adev);
3018 static int dce_v8_0_hw_fini(void *handle)
3021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3023 dce_v8_0_hpd_fini(adev);
3025 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3026 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3029 dce_v8_0_pageflip_interrupt_fini(adev);
3034 static int dce_v8_0_suspend(void *handle)
3036 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3038 amdgpu_atombios_scratch_regs_save(adev);
3040 return dce_v8_0_hw_fini(handle);
3043 static int dce_v8_0_resume(void *handle)
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048 ret = dce_v8_0_hw_init(handle);
3050 amdgpu_atombios_scratch_regs_restore(adev);
3052 /* turn on the BL */
3053 if (adev->mode_info.bl_encoder) {
3054 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3055 adev->mode_info.bl_encoder);
3056 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3063 static bool dce_v8_0_is_idle(void *handle)
3068 static int dce_v8_0_wait_for_idle(void *handle)
3073 static int dce_v8_0_soft_reset(void *handle)
3075 u32 srbm_soft_reset = 0, tmp;
3076 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078 if (dce_v8_0_is_display_hung(adev))
3079 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3081 if (srbm_soft_reset) {
3082 tmp = RREG32(mmSRBM_SOFT_RESET);
3083 tmp |= srbm_soft_reset;
3084 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3085 WREG32(mmSRBM_SOFT_RESET, tmp);
3086 tmp = RREG32(mmSRBM_SOFT_RESET);
3090 tmp &= ~srbm_soft_reset;
3091 WREG32(mmSRBM_SOFT_RESET, tmp);
3092 tmp = RREG32(mmSRBM_SOFT_RESET);
3094 /* Wait a little for things to settle down */
3100 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3102 enum amdgpu_interrupt_state state)
3104 u32 reg_block, lb_interrupt_mask;
3106 if (crtc >= adev->mode_info.num_crtc) {
3107 DRM_DEBUG("invalid crtc %d\n", crtc);
3113 reg_block = CRTC0_REGISTER_OFFSET;
3116 reg_block = CRTC1_REGISTER_OFFSET;
3119 reg_block = CRTC2_REGISTER_OFFSET;
3122 reg_block = CRTC3_REGISTER_OFFSET;
3125 reg_block = CRTC4_REGISTER_OFFSET;
3128 reg_block = CRTC5_REGISTER_OFFSET;
3131 DRM_DEBUG("invalid crtc %d\n", crtc);
3136 case AMDGPU_IRQ_STATE_DISABLE:
3137 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3138 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3139 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3141 case AMDGPU_IRQ_STATE_ENABLE:
3142 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3143 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3144 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3151 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3153 enum amdgpu_interrupt_state state)
3155 u32 reg_block, lb_interrupt_mask;
3157 if (crtc >= adev->mode_info.num_crtc) {
3158 DRM_DEBUG("invalid crtc %d\n", crtc);
3164 reg_block = CRTC0_REGISTER_OFFSET;
3167 reg_block = CRTC1_REGISTER_OFFSET;
3170 reg_block = CRTC2_REGISTER_OFFSET;
3173 reg_block = CRTC3_REGISTER_OFFSET;
3176 reg_block = CRTC4_REGISTER_OFFSET;
3179 reg_block = CRTC5_REGISTER_OFFSET;
3182 DRM_DEBUG("invalid crtc %d\n", crtc);
3187 case AMDGPU_IRQ_STATE_DISABLE:
3188 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3189 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3190 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3192 case AMDGPU_IRQ_STATE_ENABLE:
3193 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3194 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3195 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3202 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3203 struct amdgpu_irq_src *src,
3205 enum amdgpu_interrupt_state state)
3207 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3211 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3214 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3217 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3220 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3223 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3226 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3229 DRM_DEBUG("invalid hdp %d\n", type);
3234 case AMDGPU_IRQ_STATE_DISABLE:
3235 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3236 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3237 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3239 case AMDGPU_IRQ_STATE_ENABLE:
3240 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3241 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3242 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3251 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3252 struct amdgpu_irq_src *src,
3254 enum amdgpu_interrupt_state state)
3257 case AMDGPU_CRTC_IRQ_VBLANK1:
3258 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3260 case AMDGPU_CRTC_IRQ_VBLANK2:
3261 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3263 case AMDGPU_CRTC_IRQ_VBLANK3:
3264 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3266 case AMDGPU_CRTC_IRQ_VBLANK4:
3267 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3269 case AMDGPU_CRTC_IRQ_VBLANK5:
3270 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3272 case AMDGPU_CRTC_IRQ_VBLANK6:
3273 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3275 case AMDGPU_CRTC_IRQ_VLINE1:
3276 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3278 case AMDGPU_CRTC_IRQ_VLINE2:
3279 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3281 case AMDGPU_CRTC_IRQ_VLINE3:
3282 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3284 case AMDGPU_CRTC_IRQ_VLINE4:
3285 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3287 case AMDGPU_CRTC_IRQ_VLINE5:
3288 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3290 case AMDGPU_CRTC_IRQ_VLINE6:
3291 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3299 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3300 struct amdgpu_irq_src *source,
3301 struct amdgpu_iv_entry *entry)
3303 unsigned crtc = entry->src_id - 1;
3304 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3305 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3307 switch (entry->src_data) {
3308 case 0: /* vblank */
3309 if (disp_int & interrupt_status_offsets[crtc].vblank)
3310 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3312 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3314 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3315 drm_handle_vblank(adev->ddev, crtc);
3317 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3320 if (disp_int & interrupt_status_offsets[crtc].vline)
3321 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3323 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3325 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3328 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3335 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3336 struct amdgpu_irq_src *src,
3338 enum amdgpu_interrupt_state state)
3342 if (type >= adev->mode_info.num_crtc) {
3343 DRM_ERROR("invalid pageflip crtc %d\n", type);
3347 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3348 if (state == AMDGPU_IRQ_STATE_DISABLE)
3349 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3350 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3352 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3353 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3358 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3362 unsigned long flags;
3364 struct amdgpu_crtc *amdgpu_crtc;
3365 struct amdgpu_flip_work *works;
3367 crtc_id = (entry->src_id - 8) >> 1;
3368 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3370 if (crtc_id >= adev->mode_info.num_crtc) {
3371 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3375 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3376 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3377 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3378 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3380 /* IRQ could occur when in initial stage */
3381 if (amdgpu_crtc == NULL)
3384 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3385 works = amdgpu_crtc->pflip_works;
3386 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3387 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3388 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3389 amdgpu_crtc->pflip_status,
3390 AMDGPU_FLIP_SUBMITTED);
3391 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3395 /* page flip completed. clean up */
3396 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3397 amdgpu_crtc->pflip_works = NULL;
3399 /* wakeup usersapce */
3401 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3403 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3405 drm_crtc_vblank_put(&amdgpu_crtc->base);
3406 schedule_work(&works->unpin_work);
3411 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3412 struct amdgpu_irq_src *source,
3413 struct amdgpu_iv_entry *entry)
3415 uint32_t disp_int, mask, int_control, tmp;
3418 if (entry->src_data >= adev->mode_info.num_hpd) {
3419 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3423 hpd = entry->src_data;
3424 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3425 mask = interrupt_status_offsets[hpd].hpd;
3426 int_control = hpd_int_control_offsets[hpd];
3428 if (disp_int & mask) {
3429 tmp = RREG32(int_control);
3430 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3431 WREG32(int_control, tmp);
3432 schedule_work(&adev->hotplug_work);
3433 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3440 static int dce_v8_0_set_clockgating_state(void *handle,
3441 enum amd_clockgating_state state)
3446 static int dce_v8_0_set_powergating_state(void *handle,
3447 enum amd_powergating_state state)
3452 const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3454 .early_init = dce_v8_0_early_init,
3456 .sw_init = dce_v8_0_sw_init,
3457 .sw_fini = dce_v8_0_sw_fini,
3458 .hw_init = dce_v8_0_hw_init,
3459 .hw_fini = dce_v8_0_hw_fini,
3460 .suspend = dce_v8_0_suspend,
3461 .resume = dce_v8_0_resume,
3462 .is_idle = dce_v8_0_is_idle,
3463 .wait_for_idle = dce_v8_0_wait_for_idle,
3464 .soft_reset = dce_v8_0_soft_reset,
3465 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3466 .set_powergating_state = dce_v8_0_set_powergating_state,
3470 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3471 struct drm_display_mode *mode,
3472 struct drm_display_mode *adjusted_mode)
3474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3476 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3478 /* need to call this here rather than in prepare() since we need some crtc info */
3479 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3481 /* set scaler clears this on some chips */
3482 dce_v8_0_set_interleave(encoder->crtc, mode);
3484 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3485 dce_v8_0_afmt_enable(encoder, true);
3486 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3490 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3492 struct amdgpu_device *adev = encoder->dev->dev_private;
3493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3494 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3496 if ((amdgpu_encoder->active_device &
3497 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3498 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3499 ENCODER_OBJECT_ID_NONE)) {
3500 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3502 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3503 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3504 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3508 amdgpu_atombios_scratch_regs_lock(adev, true);
3511 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3513 /* select the clock/data port if it uses a router */
3514 if (amdgpu_connector->router.cd_valid)
3515 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3517 /* turn eDP panel on for mode set */
3518 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3519 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3520 ATOM_TRANSMITTER_ACTION_POWER_ON);
3523 /* this is needed for the pll/ss setup to work correctly in some cases */
3524 amdgpu_atombios_encoder_set_crtc_source(encoder);
3525 /* set up the FMT blocks */
3526 dce_v8_0_program_fmt(encoder);
3529 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3531 struct drm_device *dev = encoder->dev;
3532 struct amdgpu_device *adev = dev->dev_private;
3534 /* need to call this here as we need the crtc set up */
3535 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3536 amdgpu_atombios_scratch_regs_lock(adev, false);
3539 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3542 struct amdgpu_encoder_atom_dig *dig;
3544 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3546 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3547 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3548 dce_v8_0_afmt_enable(encoder, false);
3549 dig = amdgpu_encoder->enc_priv;
3550 dig->dig_encoder = -1;
3552 amdgpu_encoder->active_device = 0;
3555 /* these are handled by the primary encoders */
3556 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3561 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3567 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3568 struct drm_display_mode *mode,
3569 struct drm_display_mode *adjusted_mode)
3574 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3580 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3585 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3586 .dpms = dce_v8_0_ext_dpms,
3587 .prepare = dce_v8_0_ext_prepare,
3588 .mode_set = dce_v8_0_ext_mode_set,
3589 .commit = dce_v8_0_ext_commit,
3590 .disable = dce_v8_0_ext_disable,
3591 /* no detect for TMDS/LVDS yet */
3594 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3595 .dpms = amdgpu_atombios_encoder_dpms,
3596 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3597 .prepare = dce_v8_0_encoder_prepare,
3598 .mode_set = dce_v8_0_encoder_mode_set,
3599 .commit = dce_v8_0_encoder_commit,
3600 .disable = dce_v8_0_encoder_disable,
3601 .detect = amdgpu_atombios_encoder_dig_detect,
3604 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3605 .dpms = amdgpu_atombios_encoder_dpms,
3606 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3607 .prepare = dce_v8_0_encoder_prepare,
3608 .mode_set = dce_v8_0_encoder_mode_set,
3609 .commit = dce_v8_0_encoder_commit,
3610 .detect = amdgpu_atombios_encoder_dac_detect,
3613 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3615 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3616 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3617 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3618 kfree(amdgpu_encoder->enc_priv);
3619 drm_encoder_cleanup(encoder);
3620 kfree(amdgpu_encoder);
3623 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3624 .destroy = dce_v8_0_encoder_destroy,
3627 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3628 uint32_t encoder_enum,
3629 uint32_t supported_device,
3632 struct drm_device *dev = adev->ddev;
3633 struct drm_encoder *encoder;
3634 struct amdgpu_encoder *amdgpu_encoder;
3636 /* see if we already added it */
3637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3638 amdgpu_encoder = to_amdgpu_encoder(encoder);
3639 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3640 amdgpu_encoder->devices |= supported_device;
3647 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3648 if (!amdgpu_encoder)
3651 encoder = &amdgpu_encoder->base;
3652 switch (adev->mode_info.num_crtc) {
3654 encoder->possible_crtcs = 0x1;
3658 encoder->possible_crtcs = 0x3;
3661 encoder->possible_crtcs = 0xf;
3664 encoder->possible_crtcs = 0x3f;
3668 amdgpu_encoder->enc_priv = NULL;
3670 amdgpu_encoder->encoder_enum = encoder_enum;
3671 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3672 amdgpu_encoder->devices = supported_device;
3673 amdgpu_encoder->rmx_type = RMX_OFF;
3674 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3675 amdgpu_encoder->is_ext_encoder = false;
3676 amdgpu_encoder->caps = caps;
3678 switch (amdgpu_encoder->encoder_id) {
3679 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3680 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3681 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3682 DRM_MODE_ENCODER_DAC, NULL);
3683 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3685 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3686 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3688 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3689 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3690 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3691 amdgpu_encoder->rmx_type = RMX_FULL;
3692 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3693 DRM_MODE_ENCODER_LVDS, NULL);
3694 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3695 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3696 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3697 DRM_MODE_ENCODER_DAC, NULL);
3698 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3700 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3701 DRM_MODE_ENCODER_TMDS, NULL);
3702 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3704 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3706 case ENCODER_OBJECT_ID_SI170B:
3707 case ENCODER_OBJECT_ID_CH7303:
3708 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3709 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3710 case ENCODER_OBJECT_ID_TITFP513:
3711 case ENCODER_OBJECT_ID_VT1623:
3712 case ENCODER_OBJECT_ID_HDMI_SI1930:
3713 case ENCODER_OBJECT_ID_TRAVIS:
3714 case ENCODER_OBJECT_ID_NUTMEG:
3715 /* these are handled by the primary encoders */
3716 amdgpu_encoder->is_ext_encoder = true;
3717 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3718 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3719 DRM_MODE_ENCODER_LVDS, NULL);
3720 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3721 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3722 DRM_MODE_ENCODER_DAC, NULL);
3724 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3725 DRM_MODE_ENCODER_TMDS, NULL);
3726 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3731 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3732 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3733 .bandwidth_update = &dce_v8_0_bandwidth_update,
3734 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3735 .vblank_wait = &dce_v8_0_vblank_wait,
3736 .is_display_hung = &dce_v8_0_is_display_hung,
3737 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3738 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3739 .hpd_sense = &dce_v8_0_hpd_sense,
3740 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3741 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3742 .page_flip = &dce_v8_0_page_flip,
3743 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3744 .add_encoder = &dce_v8_0_encoder_add,
3745 .add_connector = &amdgpu_connector_add,
3746 .stop_mc_access = &dce_v8_0_stop_mc_access,
3747 .resume_mc_access = &dce_v8_0_resume_mc_access,
3750 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3752 if (adev->mode_info.funcs == NULL)
3753 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3756 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3757 .set = dce_v8_0_set_crtc_interrupt_state,
3758 .process = dce_v8_0_crtc_irq,
3761 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3762 .set = dce_v8_0_set_pageflip_interrupt_state,
3763 .process = dce_v8_0_pageflip_irq,
3766 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3767 .set = dce_v8_0_set_hpd_interrupt_state,
3768 .process = dce_v8_0_hpd_irq,
3771 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3773 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3774 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3776 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3777 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3779 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3780 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;