2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46 static const u32 crtc_offsets[] =
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
57 static const u32 hpd_offsets[] =
67 static const uint32_t dig_offsets[] = {
85 } interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
117 static const u32 cz_golden_settings_a11[] =
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
123 static const u32 cz_mgcg_cgcg_init[] =
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
129 static const u32 stoney_golden_settings_a11[] =
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
135 static const u32 polaris11_golden_settings_a11[] =
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
140 mmFBC_MISC, 0x9f313fff, 0x14302008,
141 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
144 static const u32 polaris10_golden_settings_a11[] =
146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
148 mmFBC_MISC, 0x9f313fff, 0x14302008,
149 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154 switch (adev->asic_type) {
156 amdgpu_program_register_sequence(adev,
158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 cz_golden_settings_a11,
161 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
164 amdgpu_program_register_sequence(adev,
165 stoney_golden_settings_a11,
166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
169 amdgpu_program_register_sequence(adev,
170 polaris11_golden_settings_a11,
171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
174 amdgpu_program_register_sequence(adev,
175 polaris10_golden_settings_a11,
176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
184 u32 block_offset, u32 reg)
189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
198 u32 block_offset, u32 reg, u32 v)
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
236 * Wait for vblank on the requested crtc (evergreen+).
238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 /* depending on when we hit vblank, we may be close to active; if so,
249 * wait for another frame.
251 while (dce_v11_0_is_in_vblank(adev, crtc)) {
254 if (!dce_v11_0_is_counter_moving(adev, crtc))
259 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
262 if (!dce_v11_0_is_counter_moving(adev, crtc))
268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
280 /* Enable pflip interrupts */
281 for (i = 0; i < adev->mode_info.num_crtc; i++)
282 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
289 /* Disable pflip interrupts */
290 for (i = 0; i < adev->mode_info.num_crtc; i++)
291 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
295 * dce_v11_0_page_flip - pageflip callback.
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
305 int crtc_id, u64 crtc_base, bool async)
307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
310 /* flip immediate for async, default is vsync */
311 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
312 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
314 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
315 /* update the scanout addresses */
316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
317 upper_32_bits(crtc_base));
318 /* writing to the low address triggers the update */
319 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
320 lower_32_bits(crtc_base));
322 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
326 u32 *vbl, u32 *position)
328 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
331 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
332 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
338 * dce_v11_0_hpd_sense - hpd sense callback.
340 * @adev: amdgpu_device pointer
341 * @hpd: hpd (hotplug detect) pin
343 * Checks if a digital monitor is connected (evergreen+).
344 * Returns true if connected, false if not connected.
346 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
347 enum amdgpu_hpd_id hpd)
350 bool connected = false;
375 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
376 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
385 * @adev: amdgpu_device pointer
386 * @hpd: hpd (hotplug detect) pin
388 * Set the polarity of the hpd pin (evergreen+).
390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
391 enum amdgpu_hpd_id hpd)
394 bool connected = dce_v11_0_hpd_sense(adev, hpd);
420 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
424 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
425 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
429 * dce_v11_0_hpd_init - hpd setup callback.
431 * @adev: amdgpu_device pointer
433 * Setup the hpd pins used by the card (evergreen+).
434 * Enable the pin, set the polarity, and enable the hpd interrupts.
436 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
438 struct drm_device *dev = adev->ddev;
439 struct drm_connector *connector;
443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
446 switch (amdgpu_connector->hpd.hpd) {
469 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
470 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
471 /* don't try to enable hpd on eDP or LVDS avoid breaking the
472 * aux dp channel on imac and help (but not completely fix)
473 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
474 * also avoid interrupt storms during dpms.
476 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
477 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
478 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
482 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
483 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
484 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
486 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
487 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
488 DC_HPD_CONNECT_INT_DELAY,
489 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
490 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
491 DC_HPD_DISCONNECT_INT_DELAY,
492 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
493 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
495 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
496 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
501 * dce_v11_0_hpd_fini - hpd tear down callback.
503 * @adev: amdgpu_device pointer
505 * Tear down the hpd pins used by the card (evergreen+).
506 * Disable the hpd interrupts.
508 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
510 struct drm_device *dev = adev->ddev;
511 struct drm_connector *connector;
515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
518 switch (amdgpu_connector->hpd.hpd) {
541 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
542 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
543 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
545 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
549 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
551 return mmDC_GPIO_HPD_A;
554 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
560 for (i = 0; i < adev->mode_info.num_crtc; i++) {
561 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
562 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
563 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
564 crtc_hung |= (1 << i);
568 for (j = 0; j < 10; j++) {
569 for (i = 0; i < adev->mode_info.num_crtc; i++) {
570 if (crtc_hung & (1 << i)) {
571 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
572 if (tmp != crtc_status[i])
573 crtc_hung &= ~(1 << i);
584 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
585 struct amdgpu_mode_mc_save *save)
587 u32 crtc_enabled, tmp;
590 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
591 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
593 /* disable VGA render */
594 tmp = RREG32(mmVGA_RENDER_CONTROL);
595 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
596 WREG32(mmVGA_RENDER_CONTROL, tmp);
598 /* blank the display controllers */
599 for (i = 0; i < adev->mode_info.num_crtc; i++) {
600 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
601 CRTC_CONTROL, CRTC_MASTER_EN);
604 save->crtc_enabled[i] = true;
605 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
606 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
607 /*it is correct only for RGB ; black is 0*/
608 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
609 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
610 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
613 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
615 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
616 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
617 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
618 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
619 save->crtc_enabled[i] = false;
623 save->crtc_enabled[i] = false;
628 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
629 struct amdgpu_mode_mc_save *save)
634 /* update crtc base addresses */
635 for (i = 0; i < adev->mode_info.num_crtc; i++) {
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
637 upper_32_bits(adev->mc.vram_start));
638 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
639 (u32)adev->mc.vram_start);
641 if (save->crtc_enabled[i]) {
642 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
643 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
644 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
648 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
649 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
651 /* Unlock vga access */
652 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
654 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
657 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
662 /* Lockout access through VGA aperture*/
663 tmp = RREG32(mmVGA_HDP_CONTROL);
665 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
667 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
668 WREG32(mmVGA_HDP_CONTROL, tmp);
670 /* disable VGA render */
671 tmp = RREG32(mmVGA_RENDER_CONTROL);
673 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
675 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
676 WREG32(mmVGA_RENDER_CONTROL, tmp);
679 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
683 switch (adev->asic_type) {
702 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
704 /*Disable VGA render and enabled crtc, if has DCE engine*/
705 if (amdgpu_atombios_has_dce_engine_info(adev)) {
709 dce_v11_0_set_vga_render_state(adev, false);
712 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
713 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
714 CRTC_CONTROL, CRTC_MASTER_EN);
716 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
717 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
718 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
719 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
720 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
726 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
728 struct drm_device *dev = encoder->dev;
729 struct amdgpu_device *adev = dev->dev_private;
730 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
731 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
732 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
735 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
738 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
739 bpc = amdgpu_connector_get_monitor_bpc(connector);
740 dither = amdgpu_connector->dither;
743 /* LVDS/eDP FMT is set up by atom */
744 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
747 /* not needed for analog */
748 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
749 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
757 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
758 /* XXX sort out optimal dither settings */
759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
764 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
765 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
769 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
770 /* XXX sort out optimal dither settings */
771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
772 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
775 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
777 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
778 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
782 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
783 /* XXX sort out optimal dither settings */
784 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
785 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
786 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
787 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
788 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
790 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
791 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
799 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
803 /* display watermark setup */
805 * dce_v11_0_line_buffer_adjust - Set up the line buffer
807 * @adev: amdgpu_device pointer
808 * @amdgpu_crtc: the selected display controller
809 * @mode: the current display mode on the selected display
812 * Setup up the line buffer allocation for
813 * the selected display controller (CIK).
814 * Returns the line buffer size in pixels.
816 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
817 struct amdgpu_crtc *amdgpu_crtc,
818 struct drm_display_mode *mode)
820 u32 tmp, buffer_alloc, i, mem_cfg;
821 u32 pipe_offset = amdgpu_crtc->crtc_id;
824 * There are 6 line buffers, one for each display controllers.
825 * There are 3 partitions per LB. Select the number of partitions
826 * to enable based on the display width. For display widths larger
827 * than 4096, you need use to use 2 display controllers and combine
828 * them using the stereo blender.
830 if (amdgpu_crtc->base.enabled && mode) {
831 if (mode->crtc_hdisplay < 1920) {
834 } else if (mode->crtc_hdisplay < 2560) {
837 } else if (mode->crtc_hdisplay < 4096) {
839 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
841 DRM_DEBUG_KMS("Mode too big for LB!\n");
843 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
850 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
851 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
852 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
854 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
855 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
856 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
858 for (i = 0; i < adev->usec_timeout; i++) {
859 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
860 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
865 if (amdgpu_crtc->base.enabled && mode) {
877 /* controller not enabled, so no lb used */
882 * cik_get_number_of_dram_channels - get the number of dram channels
884 * @adev: amdgpu_device pointer
886 * Look up the number of video ram channels (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the number of dram channels
890 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
892 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
894 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
917 struct dce10_wm_params {
918 u32 dram_channels; /* number of dram channels */
919 u32 yclk; /* bandwidth per dram data pin in kHz */
920 u32 sclk; /* engine clock in kHz */
921 u32 disp_clk; /* display clock in kHz */
922 u32 src_width; /* viewport width */
923 u32 active_time; /* active display time in ns */
924 u32 blank_time; /* blank time in ns */
925 bool interlaced; /* mode is interlaced */
926 fixed20_12 vsc; /* vertical scale ratio */
927 u32 num_heads; /* number of active crtcs */
928 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
929 u32 lb_size; /* line buffer allocated to pipe */
930 u32 vtaps; /* vertical scaler taps */
934 * dce_v11_0_dram_bandwidth - get the dram bandwidth
936 * @wm: watermark calculation data
938 * Calculate the raw dram bandwidth (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns the dram bandwidth in MBytes/s
942 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
944 /* Calculate raw DRAM Bandwidth */
945 fixed20_12 dram_efficiency; /* 0.7 */
946 fixed20_12 yclk, dram_channels, bandwidth;
949 a.full = dfixed_const(1000);
950 yclk.full = dfixed_const(wm->yclk);
951 yclk.full = dfixed_div(yclk, a);
952 dram_channels.full = dfixed_const(wm->dram_channels * 4);
953 a.full = dfixed_const(10);
954 dram_efficiency.full = dfixed_const(7);
955 dram_efficiency.full = dfixed_div(dram_efficiency, a);
956 bandwidth.full = dfixed_mul(dram_channels, yclk);
957 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
959 return dfixed_trunc(bandwidth);
963 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
965 * @wm: watermark calculation data
967 * Calculate the dram bandwidth used for display (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns the dram bandwidth for display in MBytes/s
971 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
973 /* Calculate DRAM Bandwidth and the part allocated to display. */
974 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
975 fixed20_12 yclk, dram_channels, bandwidth;
978 a.full = dfixed_const(1000);
979 yclk.full = dfixed_const(wm->yclk);
980 yclk.full = dfixed_div(yclk, a);
981 dram_channels.full = dfixed_const(wm->dram_channels * 4);
982 a.full = dfixed_const(10);
983 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
984 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
985 bandwidth.full = dfixed_mul(dram_channels, yclk);
986 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
988 return dfixed_trunc(bandwidth);
992 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
994 * @wm: watermark calculation data
996 * Calculate the data return bandwidth used for display (CIK).
997 * Used for display watermark bandwidth calculations
998 * Returns the data return bandwidth in MBytes/s
1000 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
1002 /* Calculate the display Data return Bandwidth */
1003 fixed20_12 return_efficiency; /* 0.8 */
1004 fixed20_12 sclk, bandwidth;
1007 a.full = dfixed_const(1000);
1008 sclk.full = dfixed_const(wm->sclk);
1009 sclk.full = dfixed_div(sclk, a);
1010 a.full = dfixed_const(10);
1011 return_efficiency.full = dfixed_const(8);
1012 return_efficiency.full = dfixed_div(return_efficiency, a);
1013 a.full = dfixed_const(32);
1014 bandwidth.full = dfixed_mul(a, sclk);
1015 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1017 return dfixed_trunc(bandwidth);
1021 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
1023 * @wm: watermark calculation data
1025 * Calculate the dmif bandwidth used for display (CIK).
1026 * Used for display watermark bandwidth calculations
1027 * Returns the dmif bandwidth in MBytes/s
1029 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1031 /* Calculate the DMIF Request Bandwidth */
1032 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1033 fixed20_12 disp_clk, bandwidth;
1036 a.full = dfixed_const(1000);
1037 disp_clk.full = dfixed_const(wm->disp_clk);
1038 disp_clk.full = dfixed_div(disp_clk, a);
1039 a.full = dfixed_const(32);
1040 b.full = dfixed_mul(a, disp_clk);
1042 a.full = dfixed_const(10);
1043 disp_clk_request_efficiency.full = dfixed_const(8);
1044 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1046 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1048 return dfixed_trunc(bandwidth);
1052 * dce_v11_0_available_bandwidth - get the min available bandwidth
1054 * @wm: watermark calculation data
1056 * Calculate the min available bandwidth used for display (CIK).
1057 * Used for display watermark bandwidth calculations
1058 * Returns the min available bandwidth in MBytes/s
1060 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1062 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1063 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1064 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1065 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1067 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1071 * dce_v11_0_average_bandwidth - get the average available bandwidth
1073 * @wm: watermark calculation data
1075 * Calculate the average available bandwidth used for display (CIK).
1076 * Used for display watermark bandwidth calculations
1077 * Returns the average available bandwidth in MBytes/s
1079 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1081 /* Calculate the display mode Average Bandwidth
1082 * DisplayMode should contain the source and destination dimensions,
1086 fixed20_12 line_time;
1087 fixed20_12 src_width;
1088 fixed20_12 bandwidth;
1091 a.full = dfixed_const(1000);
1092 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1093 line_time.full = dfixed_div(line_time, a);
1094 bpp.full = dfixed_const(wm->bytes_per_pixel);
1095 src_width.full = dfixed_const(wm->src_width);
1096 bandwidth.full = dfixed_mul(src_width, bpp);
1097 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1098 bandwidth.full = dfixed_div(bandwidth, line_time);
1100 return dfixed_trunc(bandwidth);
1104 * dce_v11_0_latency_watermark - get the latency watermark
1106 * @wm: watermark calculation data
1108 * Calculate the latency watermark (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns the latency watermark in ns
1112 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1114 /* First calculate the latency in ns */
1115 u32 mc_latency = 2000; /* 2000 ns. */
1116 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1117 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1118 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1119 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1120 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1121 (wm->num_heads * cursor_line_pair_return_time);
1122 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1123 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1124 u32 tmp, dmif_size = 12288;
1127 if (wm->num_heads == 0)
1130 a.full = dfixed_const(2);
1131 b.full = dfixed_const(1);
1132 if ((wm->vsc.full > a.full) ||
1133 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1135 ((wm->vsc.full >= a.full) && wm->interlaced))
1136 max_src_lines_per_dst_line = 4;
1138 max_src_lines_per_dst_line = 2;
1140 a.full = dfixed_const(available_bandwidth);
1141 b.full = dfixed_const(wm->num_heads);
1142 a.full = dfixed_div(a, b);
1144 b.full = dfixed_const(mc_latency + 512);
1145 c.full = dfixed_const(wm->disp_clk);
1146 b.full = dfixed_div(b, c);
1148 c.full = dfixed_const(dmif_size);
1149 b.full = dfixed_div(c, b);
1151 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1153 b.full = dfixed_const(1000);
1154 c.full = dfixed_const(wm->disp_clk);
1155 b.full = dfixed_div(c, b);
1156 c.full = dfixed_const(wm->bytes_per_pixel);
1157 b.full = dfixed_mul(b, c);
1159 lb_fill_bw = min(tmp, dfixed_trunc(b));
1161 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1162 b.full = dfixed_const(1000);
1163 c.full = dfixed_const(lb_fill_bw);
1164 b.full = dfixed_div(c, b);
1165 a.full = dfixed_div(a, b);
1166 line_fill_time = dfixed_trunc(a);
1168 if (line_fill_time < wm->active_time)
1171 return latency + (line_fill_time - wm->active_time);
1176 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1177 * average and available dram bandwidth
1179 * @wm: watermark calculation data
1181 * Check if the display average bandwidth fits in the display
1182 * dram bandwidth (CIK).
1183 * Used for display watermark bandwidth calculations
1184 * Returns true if the display fits, false if not.
1186 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1188 if (dce_v11_0_average_bandwidth(wm) <=
1189 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1196 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1197 * average and available bandwidth
1199 * @wm: watermark calculation data
1201 * Check if the display average bandwidth fits in the display
1202 * available bandwidth (CIK).
1203 * Used for display watermark bandwidth calculations
1204 * Returns true if the display fits, false if not.
1206 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1208 if (dce_v11_0_average_bandwidth(wm) <=
1209 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1216 * dce_v11_0_check_latency_hiding - check latency hiding
1218 * @wm: watermark calculation data
1220 * Check latency hiding (CIK).
1221 * Used for display watermark bandwidth calculations
1222 * Returns true if the display fits, false if not.
1224 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1226 u32 lb_partitions = wm->lb_size / wm->src_width;
1227 u32 line_time = wm->active_time + wm->blank_time;
1228 u32 latency_tolerant_lines;
1232 a.full = dfixed_const(1);
1233 if (wm->vsc.full > a.full)
1234 latency_tolerant_lines = 1;
1236 if (lb_partitions <= (wm->vtaps + 1))
1237 latency_tolerant_lines = 1;
1239 latency_tolerant_lines = 2;
1242 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1244 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1251 * dce_v11_0_program_watermarks - program display watermarks
1253 * @adev: amdgpu_device pointer
1254 * @amdgpu_crtc: the selected display controller
1255 * @lb_size: line buffer size
1256 * @num_heads: number of display controllers in use
1258 * Calculate and program the display watermarks for the
1259 * selected display controller (CIK).
1261 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1262 struct amdgpu_crtc *amdgpu_crtc,
1263 u32 lb_size, u32 num_heads)
1265 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1266 struct dce10_wm_params wm_low, wm_high;
1269 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1270 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1272 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1273 pixel_period = 1000000 / (u32)mode->clock;
1274 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1276 /* watermark for high clocks */
1277 if (adev->pm.dpm_enabled) {
1279 amdgpu_dpm_get_mclk(adev, false) * 10;
1281 amdgpu_dpm_get_sclk(adev, false) * 10;
1283 wm_high.yclk = adev->pm.current_mclk * 10;
1284 wm_high.sclk = adev->pm.current_sclk * 10;
1287 wm_high.disp_clk = mode->clock;
1288 wm_high.src_width = mode->crtc_hdisplay;
1289 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1290 wm_high.blank_time = line_time - wm_high.active_time;
1291 wm_high.interlaced = false;
1292 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1293 wm_high.interlaced = true;
1294 wm_high.vsc = amdgpu_crtc->vsc;
1296 if (amdgpu_crtc->rmx_type != RMX_OFF)
1298 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1299 wm_high.lb_size = lb_size;
1300 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1301 wm_high.num_heads = num_heads;
1303 /* set for high clocks */
1304 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1306 /* possibly force display priority to high */
1307 /* should really do this at mode validation time... */
1308 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1309 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1310 !dce_v11_0_check_latency_hiding(&wm_high) ||
1311 (adev->mode_info.disp_priority == 2)) {
1312 DRM_DEBUG_KMS("force priority to high\n");
1315 /* watermark for low clocks */
1316 if (adev->pm.dpm_enabled) {
1318 amdgpu_dpm_get_mclk(adev, true) * 10;
1320 amdgpu_dpm_get_sclk(adev, true) * 10;
1322 wm_low.yclk = adev->pm.current_mclk * 10;
1323 wm_low.sclk = adev->pm.current_sclk * 10;
1326 wm_low.disp_clk = mode->clock;
1327 wm_low.src_width = mode->crtc_hdisplay;
1328 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1329 wm_low.blank_time = line_time - wm_low.active_time;
1330 wm_low.interlaced = false;
1331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1332 wm_low.interlaced = true;
1333 wm_low.vsc = amdgpu_crtc->vsc;
1335 if (amdgpu_crtc->rmx_type != RMX_OFF)
1337 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1338 wm_low.lb_size = lb_size;
1339 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1340 wm_low.num_heads = num_heads;
1342 /* set for low clocks */
1343 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1345 /* possibly force display priority to high */
1346 /* should really do this at mode validation time... */
1347 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1348 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1349 !dce_v11_0_check_latency_hiding(&wm_low) ||
1350 (adev->mode_info.disp_priority == 2)) {
1351 DRM_DEBUG_KMS("force priority to high\n");
1353 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1357 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1358 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1359 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1360 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1361 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1362 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1363 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1365 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1366 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1367 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1368 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1369 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1370 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1371 /* restore original selection */
1372 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1374 /* save values for DPM */
1375 amdgpu_crtc->line_time = line_time;
1376 amdgpu_crtc->wm_high = latency_watermark_a;
1377 amdgpu_crtc->wm_low = latency_watermark_b;
1378 /* Save number of lines the linebuffer leads before the scanout */
1379 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1383 * dce_v11_0_bandwidth_update - program display watermarks
1385 * @adev: amdgpu_device pointer
1387 * Calculate and program the display watermarks and line
1388 * buffer allocation (CIK).
1390 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1392 struct drm_display_mode *mode = NULL;
1393 u32 num_heads = 0, lb_size;
1396 amdgpu_update_display_priority(adev);
1398 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1399 if (adev->mode_info.crtcs[i]->base.enabled)
1402 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1403 mode = &adev->mode_info.crtcs[i]->base.mode;
1404 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1405 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1406 lb_size, num_heads);
1410 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1415 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1416 offset = adev->mode_info.audio.pin[i].offset;
1417 tmp = RREG32_AUDIO_ENDPT(offset,
1418 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1420 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1421 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1422 adev->mode_info.audio.pin[i].connected = false;
1424 adev->mode_info.audio.pin[i].connected = true;
1428 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1432 dce_v11_0_audio_get_connected_pins(adev);
1434 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1435 if (adev->mode_info.audio.pin[i].connected)
1436 return &adev->mode_info.audio.pin[i];
1438 DRM_ERROR("No connected audio pins found!\n");
1442 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1444 struct amdgpu_device *adev = encoder->dev->dev_private;
1445 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1446 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1449 if (!dig || !dig->afmt || !dig->afmt->pin)
1452 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1453 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1454 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1457 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1458 struct drm_display_mode *mode)
1460 struct amdgpu_device *adev = encoder->dev->dev_private;
1461 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1462 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1463 struct drm_connector *connector;
1464 struct amdgpu_connector *amdgpu_connector = NULL;
1468 if (!dig || !dig->afmt || !dig->afmt->pin)
1471 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1472 if (connector->encoder == encoder) {
1473 amdgpu_connector = to_amdgpu_connector(connector);
1478 if (!amdgpu_connector) {
1479 DRM_ERROR("Couldn't find encoder's connector\n");
1483 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1485 if (connector->latency_present[interlace]) {
1486 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1487 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1488 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1489 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1491 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1493 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1496 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1497 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1500 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1502 struct amdgpu_device *adev = encoder->dev->dev_private;
1503 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1504 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1505 struct drm_connector *connector;
1506 struct amdgpu_connector *amdgpu_connector = NULL;
1511 if (!dig || !dig->afmt || !dig->afmt->pin)
1514 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1515 if (connector->encoder == encoder) {
1516 amdgpu_connector = to_amdgpu_connector(connector);
1521 if (!amdgpu_connector) {
1522 DRM_ERROR("Couldn't find encoder's connector\n");
1526 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1527 if (sad_count < 0) {
1528 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1532 /* program the speaker allocation */
1533 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1534 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1535 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1538 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1539 HDMI_CONNECTION, 1);
1541 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1542 SPEAKER_ALLOCATION, sadb[0]);
1544 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1545 SPEAKER_ALLOCATION, 5); /* stereo */
1546 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1547 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1552 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1554 struct amdgpu_device *adev = encoder->dev->dev_private;
1555 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1556 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1557 struct drm_connector *connector;
1558 struct amdgpu_connector *amdgpu_connector = NULL;
1559 struct cea_sad *sads;
1562 static const u16 eld_reg_to_type[][2] = {
1563 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1564 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1565 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1566 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1567 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1568 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1569 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1570 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1571 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1572 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1573 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1574 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1577 if (!dig || !dig->afmt || !dig->afmt->pin)
1580 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1581 if (connector->encoder == encoder) {
1582 amdgpu_connector = to_amdgpu_connector(connector);
1587 if (!amdgpu_connector) {
1588 DRM_ERROR("Couldn't find encoder's connector\n");
1592 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1593 if (sad_count <= 0) {
1594 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1599 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1601 u8 stereo_freqs = 0;
1602 int max_channels = -1;
1605 for (j = 0; j < sad_count; j++) {
1606 struct cea_sad *sad = &sads[j];
1608 if (sad->format == eld_reg_to_type[i][1]) {
1609 if (sad->channels > max_channels) {
1610 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1611 MAX_CHANNELS, sad->channels);
1612 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1613 DESCRIPTOR_BYTE_2, sad->byte2);
1614 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1615 SUPPORTED_FREQUENCIES, sad->freq);
1616 max_channels = sad->channels;
1619 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1620 stereo_freqs |= sad->freq;
1626 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1627 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1628 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1634 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1635 struct amdgpu_audio_pin *pin,
1641 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1642 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1645 static const u32 pin_offsets[] =
1647 AUD0_REGISTER_OFFSET,
1648 AUD1_REGISTER_OFFSET,
1649 AUD2_REGISTER_OFFSET,
1650 AUD3_REGISTER_OFFSET,
1651 AUD4_REGISTER_OFFSET,
1652 AUD5_REGISTER_OFFSET,
1653 AUD6_REGISTER_OFFSET,
1654 AUD7_REGISTER_OFFSET,
1657 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1664 adev->mode_info.audio.enabled = true;
1666 switch (adev->asic_type) {
1669 adev->mode_info.audio.num_pins = 7;
1671 case CHIP_POLARIS10:
1672 adev->mode_info.audio.num_pins = 8;
1674 case CHIP_POLARIS11:
1675 adev->mode_info.audio.num_pins = 6;
1681 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1682 adev->mode_info.audio.pin[i].channels = -1;
1683 adev->mode_info.audio.pin[i].rate = -1;
1684 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1685 adev->mode_info.audio.pin[i].status_bits = 0;
1686 adev->mode_info.audio.pin[i].category_code = 0;
1687 adev->mode_info.audio.pin[i].connected = false;
1688 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1689 adev->mode_info.audio.pin[i].id = i;
1690 /* disable audio. it will be set up later */
1691 /* XXX remove once we switch to ip funcs */
1692 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1698 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1705 if (!adev->mode_info.audio.enabled)
1708 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1709 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1711 adev->mode_info.audio.enabled = false;
1715 * update the N and CTS parameters for a given pixel clock rate
1717 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1719 struct drm_device *dev = encoder->dev;
1720 struct amdgpu_device *adev = dev->dev_private;
1721 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1722 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1723 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1726 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1727 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1728 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1729 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1730 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1731 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1733 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1734 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1735 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1736 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1737 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1738 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1740 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1741 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1742 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1743 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1744 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1745 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1750 * build a HDMI Video Info Frame
1752 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1753 void *buffer, size_t size)
1755 struct drm_device *dev = encoder->dev;
1756 struct amdgpu_device *adev = dev->dev_private;
1757 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1758 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1759 uint8_t *frame = buffer + 3;
1760 uint8_t *header = buffer;
1762 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1763 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1764 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1765 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1766 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1767 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1768 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1769 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1772 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1774 struct drm_device *dev = encoder->dev;
1775 struct amdgpu_device *adev = dev->dev_private;
1776 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1777 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1778 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1779 u32 dto_phase = 24 * 1000;
1780 u32 dto_modulo = clock;
1783 if (!dig || !dig->afmt)
1786 /* XXX two dtos; generally use dto0 for hdmi */
1787 /* Express [24MHz / target pixel clock] as an exact rational
1788 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1789 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1791 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1792 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1793 amdgpu_crtc->crtc_id);
1794 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1795 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1796 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1800 * update the info frames with the data from the current display mode
1802 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1803 struct drm_display_mode *mode)
1805 struct drm_device *dev = encoder->dev;
1806 struct amdgpu_device *adev = dev->dev_private;
1807 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1808 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1809 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1810 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1811 struct hdmi_avi_infoframe frame;
1816 if (!dig || !dig->afmt)
1819 /* Silent, r600_hdmi_enable will raise WARN for us */
1820 if (!dig->afmt->enabled)
1823 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1824 if (encoder->crtc) {
1825 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1826 bpc = amdgpu_crtc->bpc;
1829 /* disable audio prior to setting up hw */
1830 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1831 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1833 dce_v11_0_audio_set_dto(encoder, mode->clock);
1835 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1836 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1837 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1839 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1841 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1848 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1849 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1850 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1851 connector->name, bpc);
1854 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1855 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1856 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1860 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1861 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1862 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1866 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1868 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1869 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1870 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1871 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1872 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1874 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1875 /* enable audio info frames (frames won't be set until audio is enabled) */
1876 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1877 /* required for audio info values to be updated */
1878 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1879 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1881 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1882 /* required for audio info values to be updated */
1883 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1884 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1886 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1887 /* anything other than 0 */
1888 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1889 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1891 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1893 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1894 /* set the default audio delay */
1895 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1896 /* should be suffient for all audio modes and small enough for all hblanks */
1897 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1898 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1900 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1901 /* allow 60958 channel status fields to be updated */
1902 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1903 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1905 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1907 /* clear SW CTS value */
1908 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1910 /* select SW CTS value */
1911 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1912 /* allow hw to sent ACR packets when required */
1913 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1914 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1916 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1918 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1919 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1920 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1922 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1923 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1924 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1926 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1927 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1928 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1929 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1930 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1931 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1932 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1933 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1935 dce_v11_0_audio_write_speaker_allocation(encoder);
1937 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1938 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1940 dce_v11_0_afmt_audio_select_pin(encoder);
1941 dce_v11_0_audio_write_sad_regs(encoder);
1942 dce_v11_0_audio_write_latency_fields(encoder, mode);
1944 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1946 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1950 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1952 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1956 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1958 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1959 /* enable AVI info frames */
1960 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1961 /* required for audio info values to be updated */
1962 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1963 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1965 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1966 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1967 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1969 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1970 /* send audio packets */
1971 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1972 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1974 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1975 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1976 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1977 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1979 /* enable audio after to setting up hw */
1980 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1983 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1985 struct drm_device *dev = encoder->dev;
1986 struct amdgpu_device *adev = dev->dev_private;
1987 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1988 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1990 if (!dig || !dig->afmt)
1993 /* Silent, r600_hdmi_enable will raise WARN for us */
1994 if (enable && dig->afmt->enabled)
1996 if (!enable && !dig->afmt->enabled)
1999 if (!enable && dig->afmt->pin) {
2000 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
2001 dig->afmt->pin = NULL;
2004 dig->afmt->enabled = enable;
2006 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2007 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2010 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
2014 for (i = 0; i < adev->mode_info.num_dig; i++)
2015 adev->mode_info.afmt[i] = NULL;
2017 /* DCE11 has audio blocks tied to DIG encoders */
2018 for (i = 0; i < adev->mode_info.num_dig; i++) {
2019 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2020 if (adev->mode_info.afmt[i]) {
2021 adev->mode_info.afmt[i]->offset = dig_offsets[i];
2022 adev->mode_info.afmt[i]->id = i;
2025 for (j = 0; j < i; j++) {
2026 kfree(adev->mode_info.afmt[j]);
2027 adev->mode_info.afmt[j] = NULL;
2035 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
2039 for (i = 0; i < adev->mode_info.num_dig; i++) {
2040 kfree(adev->mode_info.afmt[i]);
2041 adev->mode_info.afmt[i] = NULL;
2045 static const u32 vga_control_regs[6] =
2055 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2057 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2058 struct drm_device *dev = crtc->dev;
2059 struct amdgpu_device *adev = dev->dev_private;
2062 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2064 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2066 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2069 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2071 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2072 struct drm_device *dev = crtc->dev;
2073 struct amdgpu_device *adev = dev->dev_private;
2076 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2078 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2081 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2082 struct drm_framebuffer *fb,
2083 int x, int y, int atomic)
2085 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2086 struct drm_device *dev = crtc->dev;
2087 struct amdgpu_device *adev = dev->dev_private;
2088 struct amdgpu_framebuffer *amdgpu_fb;
2089 struct drm_framebuffer *target_fb;
2090 struct drm_gem_object *obj;
2091 struct amdgpu_bo *abo;
2092 uint64_t fb_location, tiling_flags;
2093 uint32_t fb_format, fb_pitch_pixels;
2094 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2096 u32 tmp, viewport_w, viewport_h;
2098 bool bypass_lut = false;
2102 if (!atomic && !crtc->primary->fb) {
2103 DRM_DEBUG_KMS("No FB bound\n");
2108 amdgpu_fb = to_amdgpu_framebuffer(fb);
2111 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2112 target_fb = crtc->primary->fb;
2115 /* If atomic, assume fb object is pinned & idle & fenced and
2116 * just update base pointers
2118 obj = amdgpu_fb->obj;
2119 abo = gem_to_amdgpu_bo(obj);
2120 r = amdgpu_bo_reserve(abo, false);
2121 if (unlikely(r != 0))
2125 fb_location = amdgpu_bo_gpu_offset(abo);
2127 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2128 if (unlikely(r != 0)) {
2129 amdgpu_bo_unreserve(abo);
2134 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2135 amdgpu_bo_unreserve(abo);
2137 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2139 switch (target_fb->pixel_format) {
2141 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2142 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2144 case DRM_FORMAT_XRGB4444:
2145 case DRM_FORMAT_ARGB4444:
2146 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2147 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2149 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2153 case DRM_FORMAT_XRGB1555:
2154 case DRM_FORMAT_ARGB1555:
2155 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2156 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2158 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2162 case DRM_FORMAT_BGRX5551:
2163 case DRM_FORMAT_BGRA5551:
2164 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2165 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2167 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2171 case DRM_FORMAT_RGB565:
2172 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2173 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2175 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2179 case DRM_FORMAT_XRGB8888:
2180 case DRM_FORMAT_ARGB8888:
2181 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2182 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2184 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2188 case DRM_FORMAT_XRGB2101010:
2189 case DRM_FORMAT_ARGB2101010:
2190 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2191 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2193 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2196 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2199 case DRM_FORMAT_BGRX1010102:
2200 case DRM_FORMAT_BGRA1010102:
2201 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2202 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2204 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2207 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2211 format_name = drm_get_format_name(target_fb->pixel_format);
2212 DRM_ERROR("Unsupported screen format %s\n", format_name);
2217 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2218 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2220 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2221 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2222 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2223 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2224 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2226 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2227 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2228 ARRAY_2D_TILED_THIN1);
2229 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2231 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2232 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2233 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2235 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2236 ADDR_SURF_MICRO_TILING_DISPLAY);
2237 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2238 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2239 ARRAY_1D_TILED_THIN1);
2242 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2245 dce_v11_0_vga_enable(crtc, false);
2247 /* Make sure surface address is updated at vertical blank rather than
2250 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2251 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2252 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2253 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2255 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2256 upper_32_bits(fb_location));
2257 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2258 upper_32_bits(fb_location));
2259 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2260 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2261 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2262 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2263 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2264 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2267 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2268 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2269 * retain the full precision throughout the pipeline.
2271 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2273 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2275 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2276 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2279 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2281 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2282 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2283 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2284 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2285 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2286 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2288 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2289 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2291 dce_v11_0_grph_enable(crtc, true);
2293 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2298 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2300 viewport_w = crtc->mode.hdisplay;
2301 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2302 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2303 (viewport_w << 16) | viewport_h);
2305 /* set pageflip to happen anywhere in vblank interval */
2306 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2308 if (!atomic && fb && fb != crtc->primary->fb) {
2309 amdgpu_fb = to_amdgpu_framebuffer(fb);
2310 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2311 r = amdgpu_bo_reserve(abo, false);
2312 if (unlikely(r != 0))
2314 amdgpu_bo_unpin(abo);
2315 amdgpu_bo_unreserve(abo);
2318 /* Bytes per pixel may have changed */
2319 dce_v11_0_bandwidth_update(adev);
2324 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2325 struct drm_display_mode *mode)
2327 struct drm_device *dev = crtc->dev;
2328 struct amdgpu_device *adev = dev->dev_private;
2329 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2332 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2333 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2334 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2336 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2337 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2340 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2342 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2343 struct drm_device *dev = crtc->dev;
2344 struct amdgpu_device *adev = dev->dev_private;
2348 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2350 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2351 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2352 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2354 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2355 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2356 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2358 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2359 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2360 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2362 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2364 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2365 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2366 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2368 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2369 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2370 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2372 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2373 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2375 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2376 for (i = 0; i < 256; i++) {
2377 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2378 (amdgpu_crtc->lut_r[i] << 20) |
2379 (amdgpu_crtc->lut_g[i] << 10) |
2380 (amdgpu_crtc->lut_b[i] << 0));
2383 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2384 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2385 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2386 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2387 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2389 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2390 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2391 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2393 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2394 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2395 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2397 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2398 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2399 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2401 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2402 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2403 /* XXX this only needs to be programmed once per crtc at startup,
2404 * not sure where the best place for it is
2406 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2407 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2408 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2411 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2413 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2414 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2416 switch (amdgpu_encoder->encoder_id) {
2417 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2423 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2435 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2439 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2445 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2449 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2450 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2451 * monitors a dedicated PPLL must be used. If a particular board has
2452 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2453 * as there is no need to program the PLL itself. If we are not able to
2454 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2455 * avoid messing up an existing monitor.
2457 * Asic specific PLL information
2461 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2463 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2466 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2468 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2469 struct drm_device *dev = crtc->dev;
2470 struct amdgpu_device *adev = dev->dev_private;
2474 if ((adev->asic_type == CHIP_POLARIS10) ||
2475 (adev->asic_type == CHIP_POLARIS11)) {
2476 struct amdgpu_encoder *amdgpu_encoder =
2477 to_amdgpu_encoder(amdgpu_crtc->encoder);
2478 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2480 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2483 switch (amdgpu_encoder->encoder_id) {
2484 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2486 return ATOM_COMBOPHY_PLL1;
2488 return ATOM_COMBOPHY_PLL0;
2490 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2492 return ATOM_COMBOPHY_PLL3;
2494 return ATOM_COMBOPHY_PLL2;
2496 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2498 return ATOM_COMBOPHY_PLL5;
2500 return ATOM_COMBOPHY_PLL4;
2503 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2504 return ATOM_PPLL_INVALID;
2508 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2509 if (adev->clock.dp_extclk)
2510 /* skip PPLL programming if using ext clock */
2511 return ATOM_PPLL_INVALID;
2513 /* use the same PPLL for all DP monitors */
2514 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2515 if (pll != ATOM_PPLL_INVALID)
2519 /* use the same PPLL for all monitors with the same clock */
2520 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2521 if (pll != ATOM_PPLL_INVALID)
2525 /* XXX need to determine what plls are available on each DCE11 part */
2526 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2527 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2528 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2530 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2532 DRM_ERROR("unable to allocate a PPLL\n");
2533 return ATOM_PPLL_INVALID;
2535 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2537 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2539 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2541 DRM_ERROR("unable to allocate a PPLL\n");
2542 return ATOM_PPLL_INVALID;
2544 return ATOM_PPLL_INVALID;
2547 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2549 struct amdgpu_device *adev = crtc->dev->dev_private;
2550 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2553 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2555 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2557 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2558 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2561 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2564 struct amdgpu_device *adev = crtc->dev->dev_private;
2567 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2568 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2569 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2572 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2574 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2575 struct amdgpu_device *adev = crtc->dev->dev_private;
2578 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2579 upper_32_bits(amdgpu_crtc->cursor_addr));
2580 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2581 lower_32_bits(amdgpu_crtc->cursor_addr));
2583 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2584 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2585 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2586 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2589 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2592 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2593 struct amdgpu_device *adev = crtc->dev->dev_private;
2594 int xorigin = 0, yorigin = 0;
2596 /* avivo cursor are offset into the total surface */
2599 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2602 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2606 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2610 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2611 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2612 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2613 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2615 amdgpu_crtc->cursor_x = x;
2616 amdgpu_crtc->cursor_y = y;
2621 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2626 dce_v11_0_lock_cursor(crtc, true);
2627 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2628 dce_v11_0_lock_cursor(crtc, false);
2633 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2634 struct drm_file *file_priv,
2641 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2642 struct drm_gem_object *obj;
2643 struct amdgpu_bo *aobj;
2647 /* turn off cursor */
2648 dce_v11_0_hide_cursor(crtc);
2653 if ((width > amdgpu_crtc->max_cursor_width) ||
2654 (height > amdgpu_crtc->max_cursor_height)) {
2655 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2659 obj = drm_gem_object_lookup(file_priv, handle);
2661 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2665 aobj = gem_to_amdgpu_bo(obj);
2666 ret = amdgpu_bo_reserve(aobj, false);
2668 drm_gem_object_unreference_unlocked(obj);
2672 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2673 amdgpu_bo_unreserve(aobj);
2675 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2676 drm_gem_object_unreference_unlocked(obj);
2680 amdgpu_crtc->cursor_width = width;
2681 amdgpu_crtc->cursor_height = height;
2683 dce_v11_0_lock_cursor(crtc, true);
2685 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2686 hot_y != amdgpu_crtc->cursor_hot_y) {
2689 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2690 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2692 dce_v11_0_cursor_move_locked(crtc, x, y);
2694 amdgpu_crtc->cursor_hot_x = hot_x;
2695 amdgpu_crtc->cursor_hot_y = hot_y;
2698 dce_v11_0_show_cursor(crtc);
2699 dce_v11_0_lock_cursor(crtc, false);
2702 if (amdgpu_crtc->cursor_bo) {
2703 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2704 ret = amdgpu_bo_reserve(aobj, false);
2705 if (likely(ret == 0)) {
2706 amdgpu_bo_unpin(aobj);
2707 amdgpu_bo_unreserve(aobj);
2709 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2712 amdgpu_crtc->cursor_bo = obj;
2716 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2718 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2720 if (amdgpu_crtc->cursor_bo) {
2721 dce_v11_0_lock_cursor(crtc, true);
2723 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2724 amdgpu_crtc->cursor_y);
2726 dce_v11_0_show_cursor(crtc);
2728 dce_v11_0_lock_cursor(crtc, false);
2732 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2733 u16 *blue, uint32_t size)
2735 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2738 /* userspace palettes are always correct as is */
2739 for (i = 0; i < size; i++) {
2740 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2741 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2742 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2744 dce_v11_0_crtc_load_lut(crtc);
2749 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2751 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2753 drm_crtc_cleanup(crtc);
2757 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2758 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2759 .cursor_move = dce_v11_0_crtc_cursor_move,
2760 .gamma_set = dce_v11_0_crtc_gamma_set,
2761 .set_config = amdgpu_crtc_set_config,
2762 .destroy = dce_v11_0_crtc_destroy,
2763 .page_flip_target = amdgpu_crtc_page_flip_target,
2766 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2768 struct drm_device *dev = crtc->dev;
2769 struct amdgpu_device *adev = dev->dev_private;
2770 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2774 case DRM_MODE_DPMS_ON:
2775 amdgpu_crtc->enabled = true;
2776 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2777 dce_v11_0_vga_enable(crtc, true);
2778 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2779 dce_v11_0_vga_enable(crtc, false);
2780 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2781 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2782 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2783 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2784 drm_crtc_vblank_on(crtc);
2785 dce_v11_0_crtc_load_lut(crtc);
2787 case DRM_MODE_DPMS_STANDBY:
2788 case DRM_MODE_DPMS_SUSPEND:
2789 case DRM_MODE_DPMS_OFF:
2790 drm_crtc_vblank_off(crtc);
2791 if (amdgpu_crtc->enabled) {
2792 dce_v11_0_vga_enable(crtc, true);
2793 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2794 dce_v11_0_vga_enable(crtc, false);
2796 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2797 amdgpu_crtc->enabled = false;
2800 /* adjust pm to dpms */
2801 amdgpu_pm_compute_clocks(adev);
2804 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2806 /* disable crtc pair power gating before programming */
2807 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2808 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2809 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2812 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2814 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2815 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2818 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2820 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2821 struct drm_device *dev = crtc->dev;
2822 struct amdgpu_device *adev = dev->dev_private;
2823 struct amdgpu_atom_ss ss;
2826 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2827 if (crtc->primary->fb) {
2829 struct amdgpu_framebuffer *amdgpu_fb;
2830 struct amdgpu_bo *abo;
2832 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2833 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2834 r = amdgpu_bo_reserve(abo, false);
2836 DRM_ERROR("failed to reserve abo before unpin\n");
2838 amdgpu_bo_unpin(abo);
2839 amdgpu_bo_unreserve(abo);
2842 /* disable the GRPH */
2843 dce_v11_0_grph_enable(crtc, false);
2845 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2847 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2848 if (adev->mode_info.crtcs[i] &&
2849 adev->mode_info.crtcs[i]->enabled &&
2850 i != amdgpu_crtc->crtc_id &&
2851 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2852 /* one other crtc is using this pll don't turn
2859 switch (amdgpu_crtc->pll_id) {
2863 /* disable the ppll */
2864 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2865 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2867 case ATOM_COMBOPHY_PLL0:
2868 case ATOM_COMBOPHY_PLL1:
2869 case ATOM_COMBOPHY_PLL2:
2870 case ATOM_COMBOPHY_PLL3:
2871 case ATOM_COMBOPHY_PLL4:
2872 case ATOM_COMBOPHY_PLL5:
2873 /* disable the ppll */
2874 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2875 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2881 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2882 amdgpu_crtc->adjusted_clock = 0;
2883 amdgpu_crtc->encoder = NULL;
2884 amdgpu_crtc->connector = NULL;
2887 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2888 struct drm_display_mode *mode,
2889 struct drm_display_mode *adjusted_mode,
2890 int x, int y, struct drm_framebuffer *old_fb)
2892 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2893 struct drm_device *dev = crtc->dev;
2894 struct amdgpu_device *adev = dev->dev_private;
2896 if (!amdgpu_crtc->adjusted_clock)
2899 if ((adev->asic_type == CHIP_POLARIS10) ||
2900 (adev->asic_type == CHIP_POLARIS11)) {
2901 struct amdgpu_encoder *amdgpu_encoder =
2902 to_amdgpu_encoder(amdgpu_crtc->encoder);
2904 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2906 /* SetPixelClock calculates the plls and ss values now */
2907 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2908 amdgpu_crtc->pll_id,
2909 encoder_mode, amdgpu_encoder->encoder_id,
2910 adjusted_mode->clock, 0, 0, 0, 0,
2911 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2913 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2915 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2916 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2917 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2918 amdgpu_atombios_crtc_scaler_setup(crtc);
2919 dce_v11_0_cursor_reset(crtc);
2920 /* update the hw version fpr dpm */
2921 amdgpu_crtc->hw_mode = *adjusted_mode;
2926 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2927 const struct drm_display_mode *mode,
2928 struct drm_display_mode *adjusted_mode)
2930 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2931 struct drm_device *dev = crtc->dev;
2932 struct drm_encoder *encoder;
2934 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2935 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2936 if (encoder->crtc == crtc) {
2937 amdgpu_crtc->encoder = encoder;
2938 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2942 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2943 amdgpu_crtc->encoder = NULL;
2944 amdgpu_crtc->connector = NULL;
2947 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2949 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2952 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2953 /* if we can't get a PPLL for a non-DP encoder, fail */
2954 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2955 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2961 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2962 struct drm_framebuffer *old_fb)
2964 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2967 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2968 struct drm_framebuffer *fb,
2969 int x, int y, enum mode_set_atomic state)
2971 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2974 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2975 .dpms = dce_v11_0_crtc_dpms,
2976 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2977 .mode_set = dce_v11_0_crtc_mode_set,
2978 .mode_set_base = dce_v11_0_crtc_set_base,
2979 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2980 .prepare = dce_v11_0_crtc_prepare,
2981 .commit = dce_v11_0_crtc_commit,
2982 .load_lut = dce_v11_0_crtc_load_lut,
2983 .disable = dce_v11_0_crtc_disable,
2986 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2988 struct amdgpu_crtc *amdgpu_crtc;
2991 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2992 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2993 if (amdgpu_crtc == NULL)
2996 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2998 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2999 amdgpu_crtc->crtc_id = index;
3000 adev->mode_info.crtcs[index] = amdgpu_crtc;
3002 amdgpu_crtc->max_cursor_width = 128;
3003 amdgpu_crtc->max_cursor_height = 128;
3004 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
3005 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
3007 for (i = 0; i < 256; i++) {
3008 amdgpu_crtc->lut_r[i] = i << 2;
3009 amdgpu_crtc->lut_g[i] = i << 2;
3010 amdgpu_crtc->lut_b[i] = i << 2;
3013 switch (amdgpu_crtc->crtc_id) {
3016 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
3019 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
3022 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
3025 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
3028 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
3031 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
3035 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
3036 amdgpu_crtc->adjusted_clock = 0;
3037 amdgpu_crtc->encoder = NULL;
3038 amdgpu_crtc->connector = NULL;
3039 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
3044 static int dce_v11_0_early_init(void *handle)
3046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
3049 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
3051 dce_v11_0_set_display_funcs(adev);
3052 dce_v11_0_set_irq_funcs(adev);
3054 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
3056 switch (adev->asic_type) {
3058 adev->mode_info.num_hpd = 6;
3059 adev->mode_info.num_dig = 9;
3062 adev->mode_info.num_hpd = 6;
3063 adev->mode_info.num_dig = 9;
3065 case CHIP_POLARIS10:
3066 adev->mode_info.num_hpd = 6;
3067 adev->mode_info.num_dig = 6;
3069 case CHIP_POLARIS11:
3070 adev->mode_info.num_hpd = 5;
3071 adev->mode_info.num_dig = 5;
3074 /* FIXME: not supported yet */
3081 static int dce_v11_0_sw_init(void *handle)
3084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3086 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3087 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3092 for (i = 8; i < 20; i += 2) {
3093 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3099 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3103 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3105 adev->ddev->mode_config.async_page_flip = true;
3107 adev->ddev->mode_config.max_width = 16384;
3108 adev->ddev->mode_config.max_height = 16384;
3110 adev->ddev->mode_config.preferred_depth = 24;
3111 adev->ddev->mode_config.prefer_shadow = 1;
3113 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3115 r = amdgpu_modeset_create_props(adev);
3119 adev->ddev->mode_config.max_width = 16384;
3120 adev->ddev->mode_config.max_height = 16384;
3123 /* allocate crtcs */
3124 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3125 r = dce_v11_0_crtc_init(adev, i);
3130 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3131 amdgpu_print_display_setup(adev->ddev);
3136 r = dce_v11_0_afmt_init(adev);
3140 r = dce_v11_0_audio_init(adev);
3144 drm_kms_helper_poll_init(adev->ddev);
3146 adev->mode_info.mode_config_initialized = true;
3150 static int dce_v11_0_sw_fini(void *handle)
3152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3154 kfree(adev->mode_info.bios_hardcoded_edid);
3156 drm_kms_helper_poll_fini(adev->ddev);
3158 dce_v11_0_audio_fini(adev);
3160 dce_v11_0_afmt_fini(adev);
3162 drm_mode_config_cleanup(adev->ddev);
3163 adev->mode_info.mode_config_initialized = false;
3168 static int dce_v11_0_hw_init(void *handle)
3171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3173 dce_v11_0_init_golden_registers(adev);
3175 /* init dig PHYs, disp eng pll */
3176 amdgpu_atombios_crtc_powergate_init(adev);
3177 amdgpu_atombios_encoder_init_dig(adev);
3178 if ((adev->asic_type == CHIP_POLARIS10) ||
3179 (adev->asic_type == CHIP_POLARIS11)) {
3180 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3181 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3182 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3183 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3185 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3188 /* initialize hpd */
3189 dce_v11_0_hpd_init(adev);
3191 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3192 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3195 dce_v11_0_pageflip_interrupt_init(adev);
3200 static int dce_v11_0_hw_fini(void *handle)
3203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3205 dce_v11_0_hpd_fini(adev);
3207 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3208 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3211 dce_v11_0_pageflip_interrupt_fini(adev);
3216 static int dce_v11_0_suspend(void *handle)
3218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3220 amdgpu_atombios_scratch_regs_save(adev);
3222 return dce_v11_0_hw_fini(handle);
3225 static int dce_v11_0_resume(void *handle)
3227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3230 ret = dce_v11_0_hw_init(handle);
3232 amdgpu_atombios_scratch_regs_restore(adev);
3234 /* turn on the BL */
3235 if (adev->mode_info.bl_encoder) {
3236 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3237 adev->mode_info.bl_encoder);
3238 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3245 static bool dce_v11_0_is_idle(void *handle)
3250 static int dce_v11_0_wait_for_idle(void *handle)
3255 static int dce_v11_0_soft_reset(void *handle)
3257 u32 srbm_soft_reset = 0, tmp;
3258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3260 if (dce_v11_0_is_display_hung(adev))
3261 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3263 if (srbm_soft_reset) {
3264 tmp = RREG32(mmSRBM_SOFT_RESET);
3265 tmp |= srbm_soft_reset;
3266 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3267 WREG32(mmSRBM_SOFT_RESET, tmp);
3268 tmp = RREG32(mmSRBM_SOFT_RESET);
3272 tmp &= ~srbm_soft_reset;
3273 WREG32(mmSRBM_SOFT_RESET, tmp);
3274 tmp = RREG32(mmSRBM_SOFT_RESET);
3276 /* Wait a little for things to settle down */
3282 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3284 enum amdgpu_interrupt_state state)
3286 u32 lb_interrupt_mask;
3288 if (crtc >= adev->mode_info.num_crtc) {
3289 DRM_DEBUG("invalid crtc %d\n", crtc);
3294 case AMDGPU_IRQ_STATE_DISABLE:
3295 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3296 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3297 VBLANK_INTERRUPT_MASK, 0);
3298 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3300 case AMDGPU_IRQ_STATE_ENABLE:
3301 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3302 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3303 VBLANK_INTERRUPT_MASK, 1);
3304 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3311 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3313 enum amdgpu_interrupt_state state)
3315 u32 lb_interrupt_mask;
3317 if (crtc >= adev->mode_info.num_crtc) {
3318 DRM_DEBUG("invalid crtc %d\n", crtc);
3323 case AMDGPU_IRQ_STATE_DISABLE:
3324 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3325 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3326 VLINE_INTERRUPT_MASK, 0);
3327 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3329 case AMDGPU_IRQ_STATE_ENABLE:
3330 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3331 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3332 VLINE_INTERRUPT_MASK, 1);
3333 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3340 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3341 struct amdgpu_irq_src *source,
3343 enum amdgpu_interrupt_state state)
3347 if (hpd >= adev->mode_info.num_hpd) {
3348 DRM_DEBUG("invalid hdp %d\n", hpd);
3353 case AMDGPU_IRQ_STATE_DISABLE:
3354 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3355 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3356 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3358 case AMDGPU_IRQ_STATE_ENABLE:
3359 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3360 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3361 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3370 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3371 struct amdgpu_irq_src *source,
3373 enum amdgpu_interrupt_state state)
3376 case AMDGPU_CRTC_IRQ_VBLANK1:
3377 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3379 case AMDGPU_CRTC_IRQ_VBLANK2:
3380 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3382 case AMDGPU_CRTC_IRQ_VBLANK3:
3383 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3385 case AMDGPU_CRTC_IRQ_VBLANK4:
3386 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3388 case AMDGPU_CRTC_IRQ_VBLANK5:
3389 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3391 case AMDGPU_CRTC_IRQ_VBLANK6:
3392 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3394 case AMDGPU_CRTC_IRQ_VLINE1:
3395 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3397 case AMDGPU_CRTC_IRQ_VLINE2:
3398 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3400 case AMDGPU_CRTC_IRQ_VLINE3:
3401 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3403 case AMDGPU_CRTC_IRQ_VLINE4:
3404 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3406 case AMDGPU_CRTC_IRQ_VLINE5:
3407 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3409 case AMDGPU_CRTC_IRQ_VLINE6:
3410 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3418 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3419 struct amdgpu_irq_src *src,
3421 enum amdgpu_interrupt_state state)
3425 if (type >= adev->mode_info.num_crtc) {
3426 DRM_ERROR("invalid pageflip crtc %d\n", type);
3430 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3431 if (state == AMDGPU_IRQ_STATE_DISABLE)
3432 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3433 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3435 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3436 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3441 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3442 struct amdgpu_irq_src *source,
3443 struct amdgpu_iv_entry *entry)
3445 unsigned long flags;
3447 struct amdgpu_crtc *amdgpu_crtc;
3448 struct amdgpu_flip_work *works;
3450 crtc_id = (entry->src_id - 8) >> 1;
3451 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3453 if (crtc_id >= adev->mode_info.num_crtc) {
3454 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3458 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3459 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3460 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3461 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3463 /* IRQ could occur when in initial stage */
3464 if(amdgpu_crtc == NULL)
3467 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3468 works = amdgpu_crtc->pflip_works;
3469 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3470 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3471 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3472 amdgpu_crtc->pflip_status,
3473 AMDGPU_FLIP_SUBMITTED);
3474 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3478 /* page flip completed. clean up */
3479 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3480 amdgpu_crtc->pflip_works = NULL;
3482 /* wakeup usersapce */
3484 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3486 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3488 drm_crtc_vblank_put(&amdgpu_crtc->base);
3489 schedule_work(&works->unpin_work);
3494 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3499 if (hpd >= adev->mode_info.num_hpd) {
3500 DRM_DEBUG("invalid hdp %d\n", hpd);
3504 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3505 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3506 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3509 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3514 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3515 DRM_DEBUG("invalid crtc %d\n", crtc);
3519 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3520 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3521 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3524 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3529 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3530 DRM_DEBUG("invalid crtc %d\n", crtc);
3534 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3535 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3536 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3539 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3540 struct amdgpu_irq_src *source,
3541 struct amdgpu_iv_entry *entry)
3543 unsigned crtc = entry->src_id - 1;
3544 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3545 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3547 switch (entry->src_data) {
3548 case 0: /* vblank */
3549 if (disp_int & interrupt_status_offsets[crtc].vblank)
3550 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3552 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3554 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3555 drm_handle_vblank(adev->ddev, crtc);
3557 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3561 if (disp_int & interrupt_status_offsets[crtc].vline)
3562 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3564 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3566 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3570 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3577 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3578 struct amdgpu_irq_src *source,
3579 struct amdgpu_iv_entry *entry)
3581 uint32_t disp_int, mask;
3584 if (entry->src_data >= adev->mode_info.num_hpd) {
3585 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3589 hpd = entry->src_data;
3590 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3591 mask = interrupt_status_offsets[hpd].hpd;
3593 if (disp_int & mask) {
3594 dce_v11_0_hpd_int_ack(adev, hpd);
3595 schedule_work(&adev->hotplug_work);
3596 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3602 static int dce_v11_0_set_clockgating_state(void *handle,
3603 enum amd_clockgating_state state)
3608 static int dce_v11_0_set_powergating_state(void *handle,
3609 enum amd_powergating_state state)
3614 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3615 .name = "dce_v11_0",
3616 .early_init = dce_v11_0_early_init,
3618 .sw_init = dce_v11_0_sw_init,
3619 .sw_fini = dce_v11_0_sw_fini,
3620 .hw_init = dce_v11_0_hw_init,
3621 .hw_fini = dce_v11_0_hw_fini,
3622 .suspend = dce_v11_0_suspend,
3623 .resume = dce_v11_0_resume,
3624 .is_idle = dce_v11_0_is_idle,
3625 .wait_for_idle = dce_v11_0_wait_for_idle,
3626 .soft_reset = dce_v11_0_soft_reset,
3627 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3628 .set_powergating_state = dce_v11_0_set_powergating_state,
3632 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3633 struct drm_display_mode *mode,
3634 struct drm_display_mode *adjusted_mode)
3636 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3638 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3640 /* need to call this here rather than in prepare() since we need some crtc info */
3641 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3643 /* set scaler clears this on some chips */
3644 dce_v11_0_set_interleave(encoder->crtc, mode);
3646 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3647 dce_v11_0_afmt_enable(encoder, true);
3648 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3652 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3654 struct amdgpu_device *adev = encoder->dev->dev_private;
3655 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3656 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3658 if ((amdgpu_encoder->active_device &
3659 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3660 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3661 ENCODER_OBJECT_ID_NONE)) {
3662 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3664 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3665 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3666 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3670 amdgpu_atombios_scratch_regs_lock(adev, true);
3673 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3675 /* select the clock/data port if it uses a router */
3676 if (amdgpu_connector->router.cd_valid)
3677 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3679 /* turn eDP panel on for mode set */
3680 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3681 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3682 ATOM_TRANSMITTER_ACTION_POWER_ON);
3685 /* this is needed for the pll/ss setup to work correctly in some cases */
3686 amdgpu_atombios_encoder_set_crtc_source(encoder);
3687 /* set up the FMT blocks */
3688 dce_v11_0_program_fmt(encoder);
3691 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3693 struct drm_device *dev = encoder->dev;
3694 struct amdgpu_device *adev = dev->dev_private;
3696 /* need to call this here as we need the crtc set up */
3697 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3698 amdgpu_atombios_scratch_regs_lock(adev, false);
3701 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3703 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3704 struct amdgpu_encoder_atom_dig *dig;
3706 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3708 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3709 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3710 dce_v11_0_afmt_enable(encoder, false);
3711 dig = amdgpu_encoder->enc_priv;
3712 dig->dig_encoder = -1;
3714 amdgpu_encoder->active_device = 0;
3717 /* these are handled by the primary encoders */
3718 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3723 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3729 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3730 struct drm_display_mode *mode,
3731 struct drm_display_mode *adjusted_mode)
3736 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3742 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3747 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3748 .dpms = dce_v11_0_ext_dpms,
3749 .prepare = dce_v11_0_ext_prepare,
3750 .mode_set = dce_v11_0_ext_mode_set,
3751 .commit = dce_v11_0_ext_commit,
3752 .disable = dce_v11_0_ext_disable,
3753 /* no detect for TMDS/LVDS yet */
3756 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3757 .dpms = amdgpu_atombios_encoder_dpms,
3758 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3759 .prepare = dce_v11_0_encoder_prepare,
3760 .mode_set = dce_v11_0_encoder_mode_set,
3761 .commit = dce_v11_0_encoder_commit,
3762 .disable = dce_v11_0_encoder_disable,
3763 .detect = amdgpu_atombios_encoder_dig_detect,
3766 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3767 .dpms = amdgpu_atombios_encoder_dpms,
3768 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3769 .prepare = dce_v11_0_encoder_prepare,
3770 .mode_set = dce_v11_0_encoder_mode_set,
3771 .commit = dce_v11_0_encoder_commit,
3772 .detect = amdgpu_atombios_encoder_dac_detect,
3775 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3777 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3778 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3779 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3780 kfree(amdgpu_encoder->enc_priv);
3781 drm_encoder_cleanup(encoder);
3782 kfree(amdgpu_encoder);
3785 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3786 .destroy = dce_v11_0_encoder_destroy,
3789 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3790 uint32_t encoder_enum,
3791 uint32_t supported_device,
3794 struct drm_device *dev = adev->ddev;
3795 struct drm_encoder *encoder;
3796 struct amdgpu_encoder *amdgpu_encoder;
3798 /* see if we already added it */
3799 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3800 amdgpu_encoder = to_amdgpu_encoder(encoder);
3801 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3802 amdgpu_encoder->devices |= supported_device;
3809 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3810 if (!amdgpu_encoder)
3813 encoder = &amdgpu_encoder->base;
3814 switch (adev->mode_info.num_crtc) {
3816 encoder->possible_crtcs = 0x1;
3820 encoder->possible_crtcs = 0x3;
3823 encoder->possible_crtcs = 0xf;
3826 encoder->possible_crtcs = 0x3f;
3830 amdgpu_encoder->enc_priv = NULL;
3832 amdgpu_encoder->encoder_enum = encoder_enum;
3833 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3834 amdgpu_encoder->devices = supported_device;
3835 amdgpu_encoder->rmx_type = RMX_OFF;
3836 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3837 amdgpu_encoder->is_ext_encoder = false;
3838 amdgpu_encoder->caps = caps;
3840 switch (amdgpu_encoder->encoder_id) {
3841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3843 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3844 DRM_MODE_ENCODER_DAC, NULL);
3845 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3847 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3848 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3849 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3850 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3852 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3853 amdgpu_encoder->rmx_type = RMX_FULL;
3854 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3855 DRM_MODE_ENCODER_LVDS, NULL);
3856 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3857 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3858 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3859 DRM_MODE_ENCODER_DAC, NULL);
3860 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3862 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3863 DRM_MODE_ENCODER_TMDS, NULL);
3864 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3866 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3868 case ENCODER_OBJECT_ID_SI170B:
3869 case ENCODER_OBJECT_ID_CH7303:
3870 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3871 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3872 case ENCODER_OBJECT_ID_TITFP513:
3873 case ENCODER_OBJECT_ID_VT1623:
3874 case ENCODER_OBJECT_ID_HDMI_SI1930:
3875 case ENCODER_OBJECT_ID_TRAVIS:
3876 case ENCODER_OBJECT_ID_NUTMEG:
3877 /* these are handled by the primary encoders */
3878 amdgpu_encoder->is_ext_encoder = true;
3879 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3880 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3881 DRM_MODE_ENCODER_LVDS, NULL);
3882 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3883 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3884 DRM_MODE_ENCODER_DAC, NULL);
3886 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3887 DRM_MODE_ENCODER_TMDS, NULL);
3888 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3893 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3894 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3895 .bandwidth_update = &dce_v11_0_bandwidth_update,
3896 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3897 .vblank_wait = &dce_v11_0_vblank_wait,
3898 .is_display_hung = &dce_v11_0_is_display_hung,
3899 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3900 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3901 .hpd_sense = &dce_v11_0_hpd_sense,
3902 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3903 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3904 .page_flip = &dce_v11_0_page_flip,
3905 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3906 .add_encoder = &dce_v11_0_encoder_add,
3907 .add_connector = &amdgpu_connector_add,
3908 .stop_mc_access = &dce_v11_0_stop_mc_access,
3909 .resume_mc_access = &dce_v11_0_resume_mc_access,
3912 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3914 if (adev->mode_info.funcs == NULL)
3915 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3918 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3919 .set = dce_v11_0_set_crtc_irq_state,
3920 .process = dce_v11_0_crtc_irq,
3923 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3924 .set = dce_v11_0_set_pageflip_irq_state,
3925 .process = dce_v11_0_pageflip_irq,
3928 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3929 .set = dce_v11_0_set_hpd_irq_state,
3930 .process = dce_v11_0_hpd_irq,
3933 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3935 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3936 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3938 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3939 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3941 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3942 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;