drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static const u32 tonga_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 golden_settings_fiji_a10[] =
 130 {
 131         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 132         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 133         mmFBC_MISC, 0x1f311fff, 0x12300000,
 134         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 135 };
 136
 137 static const u32 fiji_mgcg_cgcg_init[] =
 138 {
 139         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 140         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 141 };
 142
 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 144 {
 145         switch (adev->asic_type) {
 146         case CHIP_FIJI:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  fiji_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_fiji_a10,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 153                 break;
 154         case CHIP_TONGA:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  tonga_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_tonga_a11,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 168                                      u32 block_offset, u32 reg)
 169 {
 170         unsigned long flags;
 171         u32 r;
 172
 173         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 174         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 175         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 176         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 177
 178         return r;
 179 }
 180
 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 182                                       u32 block_offset, u32 reg, u32 v)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 187         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 189         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 190 }
 191
 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 193 {
 194         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 195                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 196                 return true;
 197         else
 198                 return false;
 199 }
 200
 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 202 {
 203         u32 pos1, pos2;
 204
 205         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207
 208         if (pos1 != pos2)
 209                 return true;
 210         else
 211                 return false;
 212 }
 213
 214 /**
 215  * dce_v10_0_vblank_wait - vblank wait asic callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @crtc: crtc to wait for vblank on
 219  *
 220  * Wait for vblank on the requested crtc (evergreen+).
 221  */
 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 223 {
 224         unsigned i = 0;
 225
 226         if (crtc >= adev->mode_info.num_crtc)
 227                 return;
 228
 229         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 230                 return;
 231
 232         /* depending on when we hit vblank, we may be close to active; if so,
 233          * wait for another frame.
 234          */
 235         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 236                 if (i++ % 100 == 0) {
 237                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 238                                 break;
 239                 }
 240         }
 241
 242         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 243                 if (i++ % 100 == 0) {
 244                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 245                                 break;
 246                 }
 247         }
 248 }
 249
 250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 251 {
 252         if (crtc >= adev->mode_info.num_crtc)
 253                 return 0;
 254         else
 255                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 256 }
 257
 258 /**
 259  * dce_v10_0_page_flip - pageflip callback.
 260  *
 261  * @adev: amdgpu_device pointer
 262  * @crtc_id: crtc to cleanup pageflip on
 263  * @crtc_base: new address of the crtc (GPU MC address)
 264  *
 265  * Triggers the actual pageflip by updating the primary
 266  * surface base address.
 267  */
 268 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 269                               int crtc_id, u64 crtc_base)
 270 {
 271         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 272
 273         /* update the primary scanout address */
 274         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 275                upper_32_bits(crtc_base));
 276         /* writing to the low address triggers the update */
 277         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 278                lower_32_bits(crtc_base));
 279         /* post the write */
 280         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 281 }
 282
 283 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 284                                         u32 *vbl, u32 *position)
 285 {
 286         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 287                 return -EINVAL;
 288
 289         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 290         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * dce_v10_0_hpd_sense - hpd sense callback.
 297  *
 298  * @adev: amdgpu_device pointer
 299  * @hpd: hpd (hotplug detect) pin
 300  *
 301  * Checks if a digital monitor is connected (evergreen+).
 302  * Returns true if connected, false if not connected.
 303  */
 304 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 305                                enum amdgpu_hpd_id hpd)
 306 {
 307         int idx;
 308         bool connected = false;
 309
 310         switch (hpd) {
 311         case AMDGPU_HPD_1:
 312                 idx = 0;
 313                 break;
 314         case AMDGPU_HPD_2:
 315                 idx = 1;
 316                 break;
 317         case AMDGPU_HPD_3:
 318                 idx = 2;
 319                 break;
 320         case AMDGPU_HPD_4:
 321                 idx = 3;
 322                 break;
 323         case AMDGPU_HPD_5:
 324                 idx = 4;
 325                 break;
 326         case AMDGPU_HPD_6:
 327                 idx = 5;
 328                 break;
 329         default:
 330                 return connected;
 331         }
 332
 333         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 334             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 335                 connected = true;
 336
 337         return connected;
 338 }
 339
 340 /**
 341  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 342  *
 343  * @adev: amdgpu_device pointer
 344  * @hpd: hpd (hotplug detect) pin
 345  *
 346  * Set the polarity of the hpd pin (evergreen+).
 347  */
 348 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 349                                       enum amdgpu_hpd_id hpd)
 350 {
 351         u32 tmp;
 352         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 353         int idx;
 354
 355         switch (hpd) {
 356         case AMDGPU_HPD_1:
 357                 idx = 0;
 358                 break;
 359         case AMDGPU_HPD_2:
 360                 idx = 1;
 361                 break;
 362         case AMDGPU_HPD_3:
 363                 idx = 2;
 364                 break;
 365         case AMDGPU_HPD_4:
 366                 idx = 3;
 367                 break;
 368         case AMDGPU_HPD_5:
 369                 idx = 4;
 370                 break;
 371         case AMDGPU_HPD_6:
 372                 idx = 5;
 373                 break;
 374         default:
 375                 return;
 376         }
 377
 378         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 379         if (connected)
 380                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 381         else
 382                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 383         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 384 }
 385
 386 /**
 387  * dce_v10_0_hpd_init - hpd setup callback.
 388  *
 389  * @adev: amdgpu_device pointer
 390  *
 391  * Setup the hpd pins used by the card (evergreen+).
 392  * Enable the pin, set the polarity, and enable the hpd interrupts.
 393  */
 394 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 395 {
 396         struct drm_device *dev = adev->ddev;
 397         struct drm_connector *connector;
 398         u32 tmp;
 399         int idx;
 400
 401         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 402                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 403
 404                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 405                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 406                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 407                          * aux dp channel on imac and help (but not completely fix)
 408                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 409                          * also avoid interrupt storms during dpms.
 410                          */
 411                         continue;
 412                 }
 413
 414                 switch (amdgpu_connector->hpd.hpd) {
 415                 case AMDGPU_HPD_1:
 416                         idx = 0;
 417                         break;
 418                 case AMDGPU_HPD_2:
 419                         idx = 1;
 420                         break;
 421                 case AMDGPU_HPD_3:
 422                         idx = 2;
 423                         break;
 424                 case AMDGPU_HPD_4:
 425                         idx = 3;
 426                         break;
 427                 case AMDGPU_HPD_5:
 428                         idx = 4;
 429                         break;
 430                 case AMDGPU_HPD_6:
 431                         idx = 5;
 432                         break;
 433                 default:
 434                         continue;
 435                 }
 436
 437                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 438                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 439                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 440
 441                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 442                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 443                                     DC_HPD_CONNECT_INT_DELAY,
 444                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 445                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 446                                     DC_HPD_DISCONNECT_INT_DELAY,
 447                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 448                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 449
 450                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 451                 amdgpu_irq_get(adev, &adev->hpd_irq,
 452                                amdgpu_connector->hpd.hpd);
 453         }
 454 }
 455
 456 /**
 457  * dce_v10_0_hpd_fini - hpd tear down callback.
 458  *
 459  * @adev: amdgpu_device pointer
 460  *
 461  * Tear down the hpd pins used by the card (evergreen+).
 462  * Disable the hpd interrupts.
 463  */
 464 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 465 {
 466         struct drm_device *dev = adev->ddev;
 467         struct drm_connector *connector;
 468         u32 tmp;
 469         int idx;
 470
 471         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 472                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 473
 474                 switch (amdgpu_connector->hpd.hpd) {
 475                 case AMDGPU_HPD_1:
 476                         idx = 0;
 477                         break;
 478                 case AMDGPU_HPD_2:
 479                         idx = 1;
 480                         break;
 481                 case AMDGPU_HPD_3:
 482                         idx = 2;
 483                         break;
 484                 case AMDGPU_HPD_4:
 485                         idx = 3;
 486                         break;
 487                 case AMDGPU_HPD_5:
 488                         idx = 4;
 489                         break;
 490                 case AMDGPU_HPD_6:
 491                         idx = 5;
 492                         break;
 493                 default:
 494                         continue;
 495                 }
 496
 497                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 498                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 499                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 500
 501                 amdgpu_irq_put(adev, &adev->hpd_irq,
 502                                amdgpu_connector->hpd.hpd);
 503         }
 504 }
 505
 506 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 507 {
 508         return mmDC_GPIO_HPD_A;
 509 }
 510
 511 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 512 {
 513         u32 crtc_hung = 0;
 514         u32 crtc_status[6];
 515         u32 i, j, tmp;
 516
 517         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 518                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 519                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 520                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 521                         crtc_hung |= (1 << i);
 522                 }
 523         }
 524
 525         for (j = 0; j < 10; j++) {
 526                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 527                         if (crtc_hung & (1 << i)) {
 528                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 529                                 if (tmp != crtc_status[i])
 530                                         crtc_hung &= ~(1 << i);
 531                         }
 532                 }
 533                 if (crtc_hung == 0)
 534                         return false;
 535                 udelay(100);
 536         }
 537
 538         return true;
 539 }
 540
 541 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 542                                      struct amdgpu_mode_mc_save *save)
 543 {
 544         u32 crtc_enabled, tmp;
 545         int i;
 546
 547         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 548         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 549
 550         /* disable VGA render */
 551         tmp = RREG32(mmVGA_RENDER_CONTROL);
 552         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 553         WREG32(mmVGA_RENDER_CONTROL, tmp);
 554
 555         /* blank the display controllers */
 556         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 557                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 558                                              CRTC_CONTROL, CRTC_MASTER_EN);
 559                 if (crtc_enabled) {
 560 #if 0
 561                         u32 frame_count;
 562                         int j;
 563
 564                         save->crtc_enabled[i] = true;
 565                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 566                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 567                                 amdgpu_display_vblank_wait(adev, i);
 568                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 569                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 570                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 571                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 572                         }
 573                         /* wait for the next frame */
 574                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 575                         for (j = 0; j < adev->usec_timeout; j++) {
 576                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 577                                         break;
 578                                 udelay(1);
 579                         }
 580                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 581                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 582                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 583                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 584                         }
 585                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 586                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 587                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 588                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 589                         }
 590 #else
 591                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 592                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 593                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 594                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 595                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 596                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 597                         save->crtc_enabled[i] = false;
 598                         /* ***** */
 599 #endif
 600                 } else {
 601                         save->crtc_enabled[i] = false;
 602                 }
 603         }
 604 }
 605
 606 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 607                                        struct amdgpu_mode_mc_save *save)
 608 {
 609         u32 tmp, frame_count;
 610         int i, j;
 611
 612         /* update crtc base addresses */
 613         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 614                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 615                        upper_32_bits(adev->mc.vram_start));
 616                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 617                        upper_32_bits(adev->mc.vram_start));
 618                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 619                        (u32)adev->mc.vram_start);
 620                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 621                        (u32)adev->mc.vram_start);
 622
 623                 if (save->crtc_enabled[i]) {
 624                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 625                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 626                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 627                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 628                         }
 629                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 630                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 631                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 632                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 633                         }
 634                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 635                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 636                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 637                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 638                         }
 639                         for (j = 0; j < adev->usec_timeout; j++) {
 640                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 641                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 642                                         break;
 643                                 udelay(1);
 644                         }
 645                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 646                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 647                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 648                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 649                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 650                         /* wait for the next frame */
 651                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 652                         for (j = 0; j < adev->usec_timeout; j++) {
 653                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 654                                         break;
 655                                 udelay(1);
 656                         }
 657                 }
 658         }
 659
 660         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 661         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 662
 663         /* Unlock vga access */
 664         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 665         mdelay(1);
 666         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 667 }
 668
 669 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 670                                            bool render)
 671 {
 672         u32 tmp;
 673
 674         /* Lockout access through VGA aperture*/
 675         tmp = RREG32(mmVGA_HDP_CONTROL);
 676         if (render)
 677                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 678         else
 679                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 680         WREG32(mmVGA_HDP_CONTROL, tmp);
 681
 682         /* disable VGA render */
 683         tmp = RREG32(mmVGA_RENDER_CONTROL);
 684         if (render)
 685                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 686         else
 687                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 688         WREG32(mmVGA_RENDER_CONTROL, tmp);
 689 }
 690
 691 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 692 {
 693         struct drm_device *dev = encoder->dev;
 694         struct amdgpu_device *adev = dev->dev_private;
 695         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 696         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 697         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 698         int bpc = 0;
 699         u32 tmp = 0;
 700         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 701
 702         if (connector) {
 703                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 704                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 705                 dither = amdgpu_connector->dither;
 706         }
 707
 708         /* LVDS/eDP FMT is set up by atom */
 709         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 710                 return;
 711
 712         /* not needed for analog */
 713         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 714             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 715                 return;
 716
 717         if (bpc == 0)
 718                 return;
 719
 720         switch (bpc) {
 721         case 6:
 722                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 723                         /* XXX sort out optimal dither settings */
 724                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 725                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 726                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 727                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 728                 } else {
 729                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 730                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 731                 }
 732                 break;
 733         case 8:
 734                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 735                         /* XXX sort out optimal dither settings */
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 739                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 740                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 741                 } else {
 742                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 743                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 744                 }
 745                 break;
 746         case 10:
 747                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 748                         /* XXX sort out optimal dither settings */
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 750                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 752                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 753                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 754                 } else {
 755                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 756                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 757                 }
 758                 break;
 759         default:
 760                 /* not needed */
 761                 break;
 762         }
 763
 764         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 765 }
 766
 767
 768 /* display watermark setup */
 769 /**
 770  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 771  *
 772  * @adev: amdgpu_device pointer
 773  * @amdgpu_crtc: the selected display controller
 774  * @mode: the current display mode on the selected display
 775  * controller
 776  *
 777  * Setup up the line buffer allocation for
 778  * the selected display controller (CIK).
 779  * Returns the line buffer size in pixels.
 780  */
 781 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 782                                        struct amdgpu_crtc *amdgpu_crtc,
 783                                        struct drm_display_mode *mode)
 784 {
 785         u32 tmp, buffer_alloc, i, mem_cfg;
 786         u32 pipe_offset = amdgpu_crtc->crtc_id;
 787         /*
 788          * Line Buffer Setup
 789          * There are 6 line buffers, one for each display controllers.
 790          * There are 3 partitions per LB. Select the number of partitions
 791          * to enable based on the display width.  For display widths larger
 792          * than 4096, you need use to use 2 display controllers and combine
 793          * them using the stereo blender.
 794          */
 795         if (amdgpu_crtc->base.enabled && mode) {
 796                 if (mode->crtc_hdisplay < 1920) {
 797                         mem_cfg = 1;
 798                         buffer_alloc = 2;
 799                 } else if (mode->crtc_hdisplay < 2560) {
 800                         mem_cfg = 2;
 801                         buffer_alloc = 2;
 802                 } else if (mode->crtc_hdisplay < 4096) {
 803                         mem_cfg = 0;
 804                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 805                 } else {
 806                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 807                         mem_cfg = 0;
 808                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 809                 }
 810         } else {
 811                 mem_cfg = 1;
 812                 buffer_alloc = 0;
 813         }
 814
 815         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 816         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 817         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 818
 819         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 820         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 821         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 822
 823         for (i = 0; i < adev->usec_timeout; i++) {
 824                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 825                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 826                         break;
 827                 udelay(1);
 828         }
 829
 830         if (amdgpu_crtc->base.enabled && mode) {
 831                 switch (mem_cfg) {
 832                 case 0:
 833                 default:
 834                         return 4096 * 2;
 835                 case 1:
 836                         return 1920 * 2;
 837                 case 2:
 838                         return 2560 * 2;
 839                 }
 840         }
 841
 842         /* controller not enabled, so no lb used */
 843         return 0;
 844 }
 845
 846 /**
 847  * cik_get_number_of_dram_channels - get the number of dram channels
 848  *
 849  * @adev: amdgpu_device pointer
 850  *
 851  * Look up the number of video ram channels (CIK).
 852  * Used for display watermark bandwidth calculations
 853  * Returns the number of dram channels
 854  */
 855 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 856 {
 857         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 858
 859         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 860         case 0:
 861         default:
 862                 return 1;
 863         case 1:
 864                 return 2;
 865         case 2:
 866                 return 4;
 867         case 3:
 868                 return 8;
 869         case 4:
 870                 return 3;
 871         case 5:
 872                 return 6;
 873         case 6:
 874                 return 10;
 875         case 7:
 876                 return 12;
 877         case 8:
 878                 return 16;
 879         }
 880 }
 881
 882 struct dce10_wm_params {
 883         u32 dram_channels; /* number of dram channels */
 884         u32 yclk;          /* bandwidth per dram data pin in kHz */
 885         u32 sclk;          /* engine clock in kHz */
 886         u32 disp_clk;      /* display clock in kHz */
 887         u32 src_width;     /* viewport width */
 888         u32 active_time;   /* active display time in ns */
 889         u32 blank_time;    /* blank time in ns */
 890         bool interlaced;    /* mode is interlaced */
 891         fixed20_12 vsc;    /* vertical scale ratio */
 892         u32 num_heads;     /* number of active crtcs */
 893         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 894         u32 lb_size;       /* line buffer allocated to pipe */
 895         u32 vtaps;         /* vertical scaler taps */
 896 };
 897
 898 /**
 899  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 900  *
 901  * @wm: watermark calculation data
 902  *
 903  * Calculate the raw dram bandwidth (CIK).
 904  * Used for display watermark bandwidth calculations
 905  * Returns the dram bandwidth in MBytes/s
 906  */
 907 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 908 {
 909         /* Calculate raw DRAM Bandwidth */
 910         fixed20_12 dram_efficiency; /* 0.7 */
 911         fixed20_12 yclk, dram_channels, bandwidth;
 912         fixed20_12 a;
 913
 914         a.full = dfixed_const(1000);
 915         yclk.full = dfixed_const(wm->yclk);
 916         yclk.full = dfixed_div(yclk, a);
 917         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 918         a.full = dfixed_const(10);
 919         dram_efficiency.full = dfixed_const(7);
 920         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 921         bandwidth.full = dfixed_mul(dram_channels, yclk);
 922         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 923
 924         return dfixed_trunc(bandwidth);
 925 }
 926
 927 /**
 928  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 929  *
 930  * @wm: watermark calculation data
 931  *
 932  * Calculate the dram bandwidth used for display (CIK).
 933  * Used for display watermark bandwidth calculations
 934  * Returns the dram bandwidth for display in MBytes/s
 935  */
 936 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 937 {
 938         /* Calculate DRAM Bandwidth and the part allocated to display. */
 939         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 940         fixed20_12 yclk, dram_channels, bandwidth;
 941         fixed20_12 a;
 942
 943         a.full = dfixed_const(1000);
 944         yclk.full = dfixed_const(wm->yclk);
 945         yclk.full = dfixed_div(yclk, a);
 946         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 947         a.full = dfixed_const(10);
 948         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 949         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 950         bandwidth.full = dfixed_mul(dram_channels, yclk);
 951         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 952
 953         return dfixed_trunc(bandwidth);
 954 }
 955
 956 /**
 957  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 958  *
 959  * @wm: watermark calculation data
 960  *
 961  * Calculate the data return bandwidth used for display (CIK).
 962  * Used for display watermark bandwidth calculations
 963  * Returns the data return bandwidth in MBytes/s
 964  */
 965 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 966 {
 967         /* Calculate the display Data return Bandwidth */
 968         fixed20_12 return_efficiency; /* 0.8 */
 969         fixed20_12 sclk, bandwidth;
 970         fixed20_12 a;
 971
 972         a.full = dfixed_const(1000);
 973         sclk.full = dfixed_const(wm->sclk);
 974         sclk.full = dfixed_div(sclk, a);
 975         a.full = dfixed_const(10);
 976         return_efficiency.full = dfixed_const(8);
 977         return_efficiency.full = dfixed_div(return_efficiency, a);
 978         a.full = dfixed_const(32);
 979         bandwidth.full = dfixed_mul(a, sclk);
 980         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 981
 982         return dfixed_trunc(bandwidth);
 983 }
 984
 985 /**
 986  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
 987  *
 988  * @wm: watermark calculation data
 989  *
 990  * Calculate the dmif bandwidth used for display (CIK).
 991  * Used for display watermark bandwidth calculations
 992  * Returns the dmif bandwidth in MBytes/s
 993  */
 994 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 995 {
 996         /* Calculate the DMIF Request Bandwidth */
 997         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 998         fixed20_12 disp_clk, bandwidth;
 999         fixed20_12 a, b;
1000
1001         a.full = dfixed_const(1000);
1002         disp_clk.full = dfixed_const(wm->disp_clk);
1003         disp_clk.full = dfixed_div(disp_clk, a);
1004         a.full = dfixed_const(32);
1005         b.full = dfixed_mul(a, disp_clk);
1006
1007         a.full = dfixed_const(10);
1008         disp_clk_request_efficiency.full = dfixed_const(8);
1009         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1010
1011         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1012
1013         return dfixed_trunc(bandwidth);
1014 }
1015
1016 /**
1017  * dce_v10_0_available_bandwidth - get the min available bandwidth
1018  *
1019  * @wm: watermark calculation data
1020  *
1021  * Calculate the min available bandwidth used for display (CIK).
1022  * Used for display watermark bandwidth calculations
1023  * Returns the min available bandwidth in MBytes/s
1024  */
1025 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1026 {
1027         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1028         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1029         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1030         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1031
1032         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1033 }
1034
1035 /**
1036  * dce_v10_0_average_bandwidth - get the average available bandwidth
1037  *
1038  * @wm: watermark calculation data
1039  *
1040  * Calculate the average available bandwidth used for display (CIK).
1041  * Used for display watermark bandwidth calculations
1042  * Returns the average available bandwidth in MBytes/s
1043  */
1044 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1045 {
1046         /* Calculate the display mode Average Bandwidth
1047          * DisplayMode should contain the source and destination dimensions,
1048          * timing, etc.
1049          */
1050         fixed20_12 bpp;
1051         fixed20_12 line_time;
1052         fixed20_12 src_width;
1053         fixed20_12 bandwidth;
1054         fixed20_12 a;
1055
1056         a.full = dfixed_const(1000);
1057         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1058         line_time.full = dfixed_div(line_time, a);
1059         bpp.full = dfixed_const(wm->bytes_per_pixel);
1060         src_width.full = dfixed_const(wm->src_width);
1061         bandwidth.full = dfixed_mul(src_width, bpp);
1062         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1063         bandwidth.full = dfixed_div(bandwidth, line_time);
1064
1065         return dfixed_trunc(bandwidth);
1066 }
1067
1068 /**
1069  * dce_v10_0_latency_watermark - get the latency watermark
1070  *
1071  * @wm: watermark calculation data
1072  *
1073  * Calculate the latency watermark (CIK).
1074  * Used for display watermark bandwidth calculations
1075  * Returns the latency watermark in ns
1076  */
1077 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1078 {
1079         /* First calculate the latency in ns */
1080         u32 mc_latency = 2000; /* 2000 ns. */
1081         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1082         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1083         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1084         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1085         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1086                 (wm->num_heads * cursor_line_pair_return_time);
1087         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1088         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1089         u32 tmp, dmif_size = 12288;
1090         fixed20_12 a, b, c;
1091
1092         if (wm->num_heads == 0)
1093                 return 0;
1094
1095         a.full = dfixed_const(2);
1096         b.full = dfixed_const(1);
1097         if ((wm->vsc.full > a.full) ||
1098             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1099             (wm->vtaps >= 5) ||
1100             ((wm->vsc.full >= a.full) && wm->interlaced))
1101                 max_src_lines_per_dst_line = 4;
1102         else
1103                 max_src_lines_per_dst_line = 2;
1104
1105         a.full = dfixed_const(available_bandwidth);
1106         b.full = dfixed_const(wm->num_heads);
1107         a.full = dfixed_div(a, b);
1108
1109         b.full = dfixed_const(mc_latency + 512);
1110         c.full = dfixed_const(wm->disp_clk);
1111         b.full = dfixed_div(b, c);
1112
1113         c.full = dfixed_const(dmif_size);
1114         b.full = dfixed_div(c, b);
1115
1116         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1117
1118         b.full = dfixed_const(1000);
1119         c.full = dfixed_const(wm->disp_clk);
1120         b.full = dfixed_div(c, b);
1121         c.full = dfixed_const(wm->bytes_per_pixel);
1122         b.full = dfixed_mul(b, c);
1123
1124         lb_fill_bw = min(tmp, dfixed_trunc(b));
1125
1126         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1127         b.full = dfixed_const(1000);
1128         c.full = dfixed_const(lb_fill_bw);
1129         b.full = dfixed_div(c, b);
1130         a.full = dfixed_div(a, b);
1131         line_fill_time = dfixed_trunc(a);
1132
1133         if (line_fill_time < wm->active_time)
1134                 return latency;
1135         else
1136                 return latency + (line_fill_time - wm->active_time);
1137
1138 }
1139
1140 /**
1141  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1142  * average and available dram bandwidth
1143  *
1144  * @wm: watermark calculation data
1145  *
1146  * Check if the display average bandwidth fits in the display
1147  * dram bandwidth (CIK).
1148  * Used for display watermark bandwidth calculations
1149  * Returns true if the display fits, false if not.
1150  */
1151 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1152 {
1153         if (dce_v10_0_average_bandwidth(wm) <=
1154             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1155                 return true;
1156         else
1157                 return false;
1158 }
1159
1160 /**
1161  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1162  * average and available bandwidth
1163  *
1164  * @wm: watermark calculation data
1165  *
1166  * Check if the display average bandwidth fits in the display
1167  * available bandwidth (CIK).
1168  * Used for display watermark bandwidth calculations
1169  * Returns true if the display fits, false if not.
1170  */
1171 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1172 {
1173         if (dce_v10_0_average_bandwidth(wm) <=
1174             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1175                 return true;
1176         else
1177                 return false;
1178 }
1179
1180 /**
1181  * dce_v10_0_check_latency_hiding - check latency hiding
1182  *
1183  * @wm: watermark calculation data
1184  *
1185  * Check latency hiding (CIK).
1186  * Used for display watermark bandwidth calculations
1187  * Returns true if the display fits, false if not.
1188  */
1189 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1190 {
1191         u32 lb_partitions = wm->lb_size / wm->src_width;
1192         u32 line_time = wm->active_time + wm->blank_time;
1193         u32 latency_tolerant_lines;
1194         u32 latency_hiding;
1195         fixed20_12 a;
1196
1197         a.full = dfixed_const(1);
1198         if (wm->vsc.full > a.full)
1199                 latency_tolerant_lines = 1;
1200         else {
1201                 if (lb_partitions <= (wm->vtaps + 1))
1202                         latency_tolerant_lines = 1;
1203                 else
1204                         latency_tolerant_lines = 2;
1205         }
1206
1207         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1208
1209         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1210                 return true;
1211         else
1212                 return false;
1213 }
1214
1215 /**
1216  * dce_v10_0_program_watermarks - program display watermarks
1217  *
1218  * @adev: amdgpu_device pointer
1219  * @amdgpu_crtc: the selected display controller
1220  * @lb_size: line buffer size
1221  * @num_heads: number of display controllers in use
1222  *
1223  * Calculate and program the display watermarks for the
1224  * selected display controller (CIK).
1225  */
1226 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1227                                         struct amdgpu_crtc *amdgpu_crtc,
1228                                         u32 lb_size, u32 num_heads)
1229 {
1230         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1231         struct dce10_wm_params wm_low, wm_high;
1232         u32 pixel_period;
1233         u32 line_time = 0;
1234         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1235         u32 tmp, wm_mask;
1236
1237         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1238                 pixel_period = 1000000 / (u32)mode->clock;
1239                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1240
1241                 /* watermark for high clocks */
1242                 if (adev->pm.dpm_enabled) {
1243                         wm_high.yclk =
1244                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1245                         wm_high.sclk =
1246                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1247                 } else {
1248                         wm_high.yclk = adev->pm.current_mclk * 10;
1249                         wm_high.sclk = adev->pm.current_sclk * 10;
1250                 }
1251
1252                 wm_high.disp_clk = mode->clock;
1253                 wm_high.src_width = mode->crtc_hdisplay;
1254                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1255                 wm_high.blank_time = line_time - wm_high.active_time;
1256                 wm_high.interlaced = false;
1257                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1258                         wm_high.interlaced = true;
1259                 wm_high.vsc = amdgpu_crtc->vsc;
1260                 wm_high.vtaps = 1;
1261                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1262                         wm_high.vtaps = 2;
1263                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1264                 wm_high.lb_size = lb_size;
1265                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1266                 wm_high.num_heads = num_heads;
1267
1268                 /* set for high clocks */
1269                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1270
1271                 /* possibly force display priority to high */
1272                 /* should really do this at mode validation time... */
1273                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1274                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1275                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1276                     (adev->mode_info.disp_priority == 2)) {
1277                         DRM_DEBUG_KMS("force priority to high\n");
1278                 }
1279
1280                 /* watermark for low clocks */
1281                 if (adev->pm.dpm_enabled) {
1282                         wm_low.yclk =
1283                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1284                         wm_low.sclk =
1285                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1286                 } else {
1287                         wm_low.yclk = adev->pm.current_mclk * 10;
1288                         wm_low.sclk = adev->pm.current_sclk * 10;
1289                 }
1290
1291                 wm_low.disp_clk = mode->clock;
1292                 wm_low.src_width = mode->crtc_hdisplay;
1293                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1294                 wm_low.blank_time = line_time - wm_low.active_time;
1295                 wm_low.interlaced = false;
1296                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1297                         wm_low.interlaced = true;
1298                 wm_low.vsc = amdgpu_crtc->vsc;
1299                 wm_low.vtaps = 1;
1300                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1301                         wm_low.vtaps = 2;
1302                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1303                 wm_low.lb_size = lb_size;
1304                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1305                 wm_low.num_heads = num_heads;
1306
1307                 /* set for low clocks */
1308                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1309
1310                 /* possibly force display priority to high */
1311                 /* should really do this at mode validation time... */
1312                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1313                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1314                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1315                     (adev->mode_info.disp_priority == 2)) {
1316                         DRM_DEBUG_KMS("force priority to high\n");
1317                 }
1318         }
1319
1320         /* select wm A */
1321         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1322         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1323         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1324         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1325         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1326         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1327         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1328         /* select wm B */
1329         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1330         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1331         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1332         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1333         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1334         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1335         /* restore original selection */
1336         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1337
1338         /* save values for DPM */
1339         amdgpu_crtc->line_time = line_time;
1340         amdgpu_crtc->wm_high = latency_watermark_a;
1341         amdgpu_crtc->wm_low = latency_watermark_b;
1342 }
1343
1344 /**
1345  * dce_v10_0_bandwidth_update - program display watermarks
1346  *
1347  * @adev: amdgpu_device pointer
1348  *
1349  * Calculate and program the display watermarks and line
1350  * buffer allocation (CIK).
1351  */
1352 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1353 {
1354         struct drm_display_mode *mode = NULL;
1355         u32 num_heads = 0, lb_size;
1356         int i;
1357
1358         amdgpu_update_display_priority(adev);
1359
1360         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1361                 if (adev->mode_info.crtcs[i]->base.enabled)
1362                         num_heads++;
1363         }
1364         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1365                 mode = &adev->mode_info.crtcs[i]->base.mode;
1366                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1367                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1368                                             lb_size, num_heads);
1369         }
1370 }
1371
1372 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1373 {
1374         int i;
1375         u32 offset, tmp;
1376
1377         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1378                 offset = adev->mode_info.audio.pin[i].offset;
1379                 tmp = RREG32_AUDIO_ENDPT(offset,
1380                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1381                 if (((tmp &
1382                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1383                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1384                         adev->mode_info.audio.pin[i].connected = false;
1385                 else
1386                         adev->mode_info.audio.pin[i].connected = true;
1387         }
1388 }
1389
1390 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1391 {
1392         int i;
1393
1394         dce_v10_0_audio_get_connected_pins(adev);
1395
1396         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1397                 if (adev->mode_info.audio.pin[i].connected)
1398                         return &adev->mode_info.audio.pin[i];
1399         }
1400         DRM_ERROR("No connected audio pins found!\n");
1401         return NULL;
1402 }
1403
1404 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1405 {
1406         struct amdgpu_device *adev = encoder->dev->dev_private;
1407         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1408         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1409         u32 tmp;
1410
1411         if (!dig || !dig->afmt || !dig->afmt->pin)
1412                 return;
1413
1414         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1415         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1416         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1417 }
1418
1419 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1420                                                 struct drm_display_mode *mode)
1421 {
1422         struct amdgpu_device *adev = encoder->dev->dev_private;
1423         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1424         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1425         struct drm_connector *connector;
1426         struct amdgpu_connector *amdgpu_connector = NULL;
1427         u32 tmp;
1428         int interlace = 0;
1429
1430         if (!dig || !dig->afmt || !dig->afmt->pin)
1431                 return;
1432
1433         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1434                 if (connector->encoder == encoder) {
1435                         amdgpu_connector = to_amdgpu_connector(connector);
1436                         break;
1437                 }
1438         }
1439
1440         if (!amdgpu_connector) {
1441                 DRM_ERROR("Couldn't find encoder's connector\n");
1442                 return;
1443         }
1444
1445         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1446                 interlace = 1;
1447         if (connector->latency_present[interlace]) {
1448                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1449                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1450                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1451                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1452         } else {
1453                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1454                                     VIDEO_LIPSYNC, 0);
1455                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1456                                     AUDIO_LIPSYNC, 0);
1457         }
1458         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1459                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1460 }
1461
1462 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1463 {
1464         struct amdgpu_device *adev = encoder->dev->dev_private;
1465         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1466         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1467         struct drm_connector *connector;
1468         struct amdgpu_connector *amdgpu_connector = NULL;
1469         u32 tmp;
1470         u8 *sadb = NULL;
1471         int sad_count;
1472
1473         if (!dig || !dig->afmt || !dig->afmt->pin)
1474                 return;
1475
1476         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1477                 if (connector->encoder == encoder) {
1478                         amdgpu_connector = to_amdgpu_connector(connector);
1479                         break;
1480                 }
1481         }
1482
1483         if (!amdgpu_connector) {
1484                 DRM_ERROR("Couldn't find encoder's connector\n");
1485                 return;
1486         }
1487
1488         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1489         if (sad_count < 0) {
1490                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1491                 sad_count = 0;
1492         }
1493
1494         /* program the speaker allocation */
1495         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1496                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1497         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1498                             DP_CONNECTION, 0);
1499         /* set HDMI mode */
1500         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1501                             HDMI_CONNECTION, 1);
1502         if (sad_count)
1503                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1504                                     SPEAKER_ALLOCATION, sadb[0]);
1505         else
1506                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1507                                     SPEAKER_ALLOCATION, 5); /* stereo */
1508         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1509                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1510
1511         kfree(sadb);
1512 }
1513
1514 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1515 {
1516         struct amdgpu_device *adev = encoder->dev->dev_private;
1517         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1518         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1519         struct drm_connector *connector;
1520         struct amdgpu_connector *amdgpu_connector = NULL;
1521         struct cea_sad *sads;
1522         int i, sad_count;
1523
1524         static const u16 eld_reg_to_type[][2] = {
1525                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1526                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1527                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1528                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1529                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1530                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1531                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1532                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1533                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1534                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1535                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1536                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1537         };
1538
1539         if (!dig || !dig->afmt || !dig->afmt->pin)
1540                 return;
1541
1542         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1543                 if (connector->encoder == encoder) {
1544                         amdgpu_connector = to_amdgpu_connector(connector);
1545                         break;
1546                 }
1547         }
1548
1549         if (!amdgpu_connector) {
1550                 DRM_ERROR("Couldn't find encoder's connector\n");
1551                 return;
1552         }
1553
1554         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1555         if (sad_count <= 0) {
1556                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1557                 return;
1558         }
1559         BUG_ON(!sads);
1560
1561         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1562                 u32 tmp = 0;
1563                 u8 stereo_freqs = 0;
1564                 int max_channels = -1;
1565                 int j;
1566
1567                 for (j = 0; j < sad_count; j++) {
1568                         struct cea_sad *sad = &sads[j];
1569
1570                         if (sad->format == eld_reg_to_type[i][1]) {
1571                                 if (sad->channels > max_channels) {
1572                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1573                                                             MAX_CHANNELS, sad->channels);
1574                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1575                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1576                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1577                                                             SUPPORTED_FREQUENCIES, sad->freq);
1578                                         max_channels = sad->channels;
1579                                 }
1580
1581                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1582                                         stereo_freqs |= sad->freq;
1583                                 else
1584                                         break;
1585                         }
1586                 }
1587
1588                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1589                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1590                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1591         }
1592
1593         kfree(sads);
1594 }
1595
1596 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1597                                   struct amdgpu_audio_pin *pin,
1598                                   bool enable)
1599 {
1600         if (!pin)
1601                 return;
1602
1603         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1604                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1605 }
1606
1607 static const u32 pin_offsets[] =
1608 {
1609         AUD0_REGISTER_OFFSET,
1610         AUD1_REGISTER_OFFSET,
1611         AUD2_REGISTER_OFFSET,
1612         AUD3_REGISTER_OFFSET,
1613         AUD4_REGISTER_OFFSET,
1614         AUD5_REGISTER_OFFSET,
1615         AUD6_REGISTER_OFFSET,
1616 };
1617
1618 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1619 {
1620         int i;
1621
1622         if (!amdgpu_audio)
1623                 return 0;
1624
1625         adev->mode_info.audio.enabled = true;
1626
1627         adev->mode_info.audio.num_pins = 7;
1628
1629         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1630                 adev->mode_info.audio.pin[i].channels = -1;
1631                 adev->mode_info.audio.pin[i].rate = -1;
1632                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1633                 adev->mode_info.audio.pin[i].status_bits = 0;
1634                 adev->mode_info.audio.pin[i].category_code = 0;
1635                 adev->mode_info.audio.pin[i].connected = false;
1636                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1637                 adev->mode_info.audio.pin[i].id = i;
1638                 /* disable audio.  it will be set up later */
1639                 /* XXX remove once we switch to ip funcs */
1640                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1641         }
1642
1643         return 0;
1644 }
1645
1646 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1647 {
1648         int i;
1649
1650         if (!adev->mode_info.audio.enabled)
1651                 return;
1652
1653         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1654                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1655
1656         adev->mode_info.audio.enabled = false;
1657 }
1658
1659 /*
1660  * update the N and CTS parameters for a given pixel clock rate
1661  */
1662 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1663 {
1664         struct drm_device *dev = encoder->dev;
1665         struct amdgpu_device *adev = dev->dev_private;
1666         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1667         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1668         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1669         u32 tmp;
1670
1671         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1672         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1673         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1674         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1675         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1676         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1677
1678         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1679         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1680         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1681         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1682         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1683         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1684
1685         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1686         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1687         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1688         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1689         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1690         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1691
1692 }
1693
1694 /*
1695  * build a HDMI Video Info Frame
1696  */
1697 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1698                                                void *buffer, size_t size)
1699 {
1700         struct drm_device *dev = encoder->dev;
1701         struct amdgpu_device *adev = dev->dev_private;
1702         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1703         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1704         uint8_t *frame = buffer + 3;
1705         uint8_t *header = buffer;
1706
1707         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1708                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1709         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1710                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1711         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1712                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1713         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1714                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1715 }
1716
1717 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1718 {
1719         struct drm_device *dev = encoder->dev;
1720         struct amdgpu_device *adev = dev->dev_private;
1721         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1722         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1723         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1724         u32 dto_phase = 24 * 1000;
1725         u32 dto_modulo = clock;
1726         u32 tmp;
1727
1728         if (!dig || !dig->afmt)
1729                 return;
1730
1731         /* XXX two dtos; generally use dto0 for hdmi */
1732         /* Express [24MHz / target pixel clock] as an exact rational
1733          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1734          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1735          */
1736         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1737         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1738                             amdgpu_crtc->crtc_id);
1739         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1740         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1741         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1742 }
1743
1744 /*
1745  * update the info frames with the data from the current display mode
1746  */
1747 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1748                                   struct drm_display_mode *mode)
1749 {
1750         struct drm_device *dev = encoder->dev;
1751         struct amdgpu_device *adev = dev->dev_private;
1752         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1753         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1754         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1755         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1756         struct hdmi_avi_infoframe frame;
1757         ssize_t err;
1758         u32 tmp;
1759         int bpc = 8;
1760
1761         if (!dig || !dig->afmt)
1762                 return;
1763
1764         /* Silent, r600_hdmi_enable will raise WARN for us */
1765         if (!dig->afmt->enabled)
1766                 return;
1767
1768         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1769         if (encoder->crtc) {
1770                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1771                 bpc = amdgpu_crtc->bpc;
1772         }
1773
1774         /* disable audio prior to setting up hw */
1775         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1776         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1777
1778         dce_v10_0_audio_set_dto(encoder, mode->clock);
1779
1780         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1781         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1782         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1783
1784         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1785
1786         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1787         switch (bpc) {
1788         case 0:
1789         case 6:
1790         case 8:
1791         case 16:
1792         default:
1793                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1794                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1795                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1796                           connector->name, bpc);
1797                 break;
1798         case 10:
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1800                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1801                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1802                           connector->name);
1803                 break;
1804         case 12:
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1806                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1807                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1808                           connector->name);
1809                 break;
1810         }
1811         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1812
1813         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1814         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1815         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1816         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1817         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1818
1819         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1820         /* enable audio info frames (frames won't be set until audio is enabled) */
1821         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1822         /* required for audio info values to be updated */
1823         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1824         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1825
1826         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1827         /* required for audio info values to be updated */
1828         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1829         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1830
1831         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1832         /* anything other than 0 */
1833         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1834         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1835
1836         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1837
1838         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1839         /* set the default audio delay */
1840         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1841         /* should be suffient for all audio modes and small enough for all hblanks */
1842         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1843         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1844
1845         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1846         /* allow 60958 channel status fields to be updated */
1847         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1848         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1849
1850         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1851         if (bpc > 8)
1852                 /* clear SW CTS value */
1853                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1854         else
1855                 /* select SW CTS value */
1856                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1857         /* allow hw to sent ACR packets when required */
1858         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1859         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1860
1861         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1862
1863         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1864         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1865         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1866
1867         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1868         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1869         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1870
1871         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1872         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1873         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1874         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1875         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1876         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1877         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1878         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1879
1880         dce_v10_0_audio_write_speaker_allocation(encoder);
1881
1882         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1883                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1884
1885         dce_v10_0_afmt_audio_select_pin(encoder);
1886         dce_v10_0_audio_write_sad_regs(encoder);
1887         dce_v10_0_audio_write_latency_fields(encoder, mode);
1888
1889         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1890         if (err < 0) {
1891                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1892                 return;
1893         }
1894
1895         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1896         if (err < 0) {
1897                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1898                 return;
1899         }
1900
1901         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1902
1903         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1904         /* enable AVI info frames */
1905         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1906         /* required for audio info values to be updated */
1907         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1908         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1909
1910         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1911         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1912         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1913
1914         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1915         /* send audio packets */
1916         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1917         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1918
1919         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1920         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1921         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1922         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1923
1924         /* enable audio after to setting up hw */
1925         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1926 }
1927
1928 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1929 {
1930         struct drm_device *dev = encoder->dev;
1931         struct amdgpu_device *adev = dev->dev_private;
1932         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1933         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1934
1935         if (!dig || !dig->afmt)
1936                 return;
1937
1938         /* Silent, r600_hdmi_enable will raise WARN for us */
1939         if (enable && dig->afmt->enabled)
1940                 return;
1941         if (!enable && !dig->afmt->enabled)
1942                 return;
1943
1944         if (!enable && dig->afmt->pin) {
1945                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1946                 dig->afmt->pin = NULL;
1947         }
1948
1949         dig->afmt->enabled = enable;
1950
1951         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1952                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1953 }
1954
1955 static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
1956 {
1957         int i;
1958
1959         for (i = 0; i < adev->mode_info.num_dig; i++)
1960                 adev->mode_info.afmt[i] = NULL;
1961
1962         /* DCE10 has audio blocks tied to DIG encoders */
1963         for (i = 0; i < adev->mode_info.num_dig; i++) {
1964                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1965                 if (adev->mode_info.afmt[i]) {
1966                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1967                         adev->mode_info.afmt[i]->id = i;
1968                 }
1969         }
1970 }
1971
1972 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1973 {
1974         int i;
1975
1976         for (i = 0; i < adev->mode_info.num_dig; i++) {
1977                 kfree(adev->mode_info.afmt[i]);
1978                 adev->mode_info.afmt[i] = NULL;
1979         }
1980 }
1981
1982 static const u32 vga_control_regs[6] =
1983 {
1984         mmD1VGA_CONTROL,
1985         mmD2VGA_CONTROL,
1986         mmD3VGA_CONTROL,
1987         mmD4VGA_CONTROL,
1988         mmD5VGA_CONTROL,
1989         mmD6VGA_CONTROL,
1990 };
1991
1992 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1993 {
1994         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1995         struct drm_device *dev = crtc->dev;
1996         struct amdgpu_device *adev = dev->dev_private;
1997         u32 vga_control;
1998
1999         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2000         if (enable)
2001                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2002         else
2003                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2004 }
2005
2006 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2007 {
2008         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009         struct drm_device *dev = crtc->dev;
2010         struct amdgpu_device *adev = dev->dev_private;
2011
2012         if (enable)
2013                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2014         else
2015                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2016 }
2017
2018 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2019                                      struct drm_framebuffer *fb,
2020                                      int x, int y, int atomic)
2021 {
2022         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2023         struct drm_device *dev = crtc->dev;
2024         struct amdgpu_device *adev = dev->dev_private;
2025         struct amdgpu_framebuffer *amdgpu_fb;
2026         struct drm_framebuffer *target_fb;
2027         struct drm_gem_object *obj;
2028         struct amdgpu_bo *rbo;
2029         uint64_t fb_location, tiling_flags;
2030         uint32_t fb_format, fb_pitch_pixels;
2031         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2032         u32 pipe_config;
2033         u32 tmp, viewport_w, viewport_h;
2034         int r;
2035         bool bypass_lut = false;
2036
2037         /* no fb bound */
2038         if (!atomic && !crtc->primary->fb) {
2039                 DRM_DEBUG_KMS("No FB bound\n");
2040                 return 0;
2041         }
2042
2043         if (atomic) {
2044                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2045                 target_fb = fb;
2046         }
2047         else {
2048                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2049                 target_fb = crtc->primary->fb;
2050         }
2051
2052         /* If atomic, assume fb object is pinned & idle & fenced and
2053          * just update base pointers
2054          */
2055         obj = amdgpu_fb->obj;
2056         rbo = gem_to_amdgpu_bo(obj);
2057         r = amdgpu_bo_reserve(rbo, false);
2058         if (unlikely(r != 0))
2059                 return r;
2060
2061         if (atomic)
2062                 fb_location = amdgpu_bo_gpu_offset(rbo);
2063         else {
2064                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2065                 if (unlikely(r != 0)) {
2066                         amdgpu_bo_unreserve(rbo);
2067                         return -EINVAL;
2068                 }
2069         }
2070
2071         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2072         amdgpu_bo_unreserve(rbo);
2073
2074         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2075
2076         switch (target_fb->pixel_format) {
2077         case DRM_FORMAT_C8:
2078                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2079                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2080                 break;
2081         case DRM_FORMAT_XRGB4444:
2082         case DRM_FORMAT_ARGB4444:
2083                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2084                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2085 #ifdef __BIG_ENDIAN
2086                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2087                                         ENDIAN_8IN16);
2088 #endif
2089                 break;
2090         case DRM_FORMAT_XRGB1555:
2091         case DRM_FORMAT_ARGB1555:
2092                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2093                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2094 #ifdef __BIG_ENDIAN
2095                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2096                                         ENDIAN_8IN16);
2097 #endif
2098                 break;
2099         case DRM_FORMAT_BGRX5551:
2100         case DRM_FORMAT_BGRA5551:
2101                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2102                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2103 #ifdef __BIG_ENDIAN
2104                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2105                                         ENDIAN_8IN16);
2106 #endif
2107                 break;
2108         case DRM_FORMAT_RGB565:
2109                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2110                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2111 #ifdef __BIG_ENDIAN
2112                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2113                                         ENDIAN_8IN16);
2114 #endif
2115                 break;
2116         case DRM_FORMAT_XRGB8888:
2117         case DRM_FORMAT_ARGB8888:
2118                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2119                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2120 #ifdef __BIG_ENDIAN
2121                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2122                                         ENDIAN_8IN32);
2123 #endif
2124                 break;
2125         case DRM_FORMAT_XRGB2101010:
2126         case DRM_FORMAT_ARGB2101010:
2127                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2128                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2129 #ifdef __BIG_ENDIAN
2130                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2131                                         ENDIAN_8IN32);
2132 #endif
2133                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2134                 bypass_lut = true;
2135                 break;
2136         case DRM_FORMAT_BGRX1010102:
2137         case DRM_FORMAT_BGRA1010102:
2138                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2139                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2140 #ifdef __BIG_ENDIAN
2141                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2142                                         ENDIAN_8IN32);
2143 #endif
2144                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2145                 bypass_lut = true;
2146                 break;
2147         default:
2148                 DRM_ERROR("Unsupported screen format %s\n",
2149                         drm_get_format_name(target_fb->pixel_format));
2150                 return -EINVAL;
2151         }
2152
2153         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2154                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2155
2156                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2157                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2158                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2159                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2160                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2161
2162                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2163                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2164                                           ARRAY_2D_TILED_THIN1);
2165                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2166                                           tile_split);
2167                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2168                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2169                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2170                                           mtaspect);
2171                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2172                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2173         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2175                                           ARRAY_1D_TILED_THIN1);
2176         }
2177
2178         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2179                                   pipe_config);
2180
2181         dce_v10_0_vga_enable(crtc, false);
2182
2183         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2184                upper_32_bits(fb_location));
2185         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2186                upper_32_bits(fb_location));
2187         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2188                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2189         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2190                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2191         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2192         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2193
2194         /*
2195          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2196          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2197          * retain the full precision throughout the pipeline.
2198          */
2199         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2200         if (bypass_lut)
2201                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2202         else
2203                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2204         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2205
2206         if (bypass_lut)
2207                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2208
2209         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2210         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2211         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2212         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2213         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2214         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2215
2216         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2217         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2218
2219         dce_v10_0_grph_enable(crtc, true);
2220
2221         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2222                target_fb->height);
2223
2224         x &= ~3;
2225         y &= ~1;
2226         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2227                (x << 16) | y);
2228         viewport_w = crtc->mode.hdisplay;
2229         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2230         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2231                (viewport_w << 16) | viewport_h);
2232
2233         /* pageflip setup */
2234         /* make sure flip is at vb rather than hb */
2235         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2236         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2237                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2238         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2239
2240         /* set pageflip to happen only at start of vblank interval (front porch) */
2241         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2242
2243         if (!atomic && fb && fb != crtc->primary->fb) {
2244                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2245                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2246                 r = amdgpu_bo_reserve(rbo, false);
2247                 if (unlikely(r != 0))
2248                         return r;
2249                 amdgpu_bo_unpin(rbo);
2250                 amdgpu_bo_unreserve(rbo);
2251         }
2252
2253         /* Bytes per pixel may have changed */
2254         dce_v10_0_bandwidth_update(adev);
2255
2256         return 0;
2257 }
2258
2259 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2260                                      struct drm_display_mode *mode)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct amdgpu_device *adev = dev->dev_private;
2264         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2265         u32 tmp;
2266
2267         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2268         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2269                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2270         else
2271                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2272         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2273 }
2274
2275 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2276 {
2277         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2278         struct drm_device *dev = crtc->dev;
2279         struct amdgpu_device *adev = dev->dev_private;
2280         int i;
2281         u32 tmp;
2282
2283         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2284
2285         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2286         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2287         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2288         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2289
2290         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2291         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2292         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2293
2294         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2295         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2296         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2297
2298         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2299         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2300         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2301         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302
2303         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2304
2305         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2306         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2307         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2308
2309         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2310         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2311         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2312
2313         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2314         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2315
2316         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2317         for (i = 0; i < 256; i++) {
2318                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2319                        (amdgpu_crtc->lut_r[i] << 20) |
2320                        (amdgpu_crtc->lut_g[i] << 10) |
2321                        (amdgpu_crtc->lut_b[i] << 0));
2322         }
2323
2324         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2325         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2326         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2327         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2328         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2329
2330         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2331         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2332         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2333         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2334
2335         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2336         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2337         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2338         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2339
2340         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2341         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2342         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2343         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2344
2345         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2346         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2347         /* XXX this only needs to be programmed once per crtc at startup,
2348          * not sure where the best place for it is
2349          */
2350         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2351         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2352         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353 }
2354
2355 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2356 {
2357         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2358         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2359
2360         switch (amdgpu_encoder->encoder_id) {
2361         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2362                 if (dig->linkb)
2363                         return 1;
2364                 else
2365                         return 0;
2366                 break;
2367         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2368                 if (dig->linkb)
2369                         return 3;
2370                 else
2371                         return 2;
2372                 break;
2373         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2374                 if (dig->linkb)
2375                         return 5;
2376                 else
2377                         return 4;
2378                 break;
2379         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2380                 return 6;
2381                 break;
2382         default:
2383                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2384                 return 0;
2385         }
2386 }
2387
2388 /**
2389  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2390  *
2391  * @crtc: drm crtc
2392  *
2393  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2394  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2395  * monitors a dedicated PPLL must be used.  If a particular board has
2396  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2397  * as there is no need to program the PLL itself.  If we are not able to
2398  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2399  * avoid messing up an existing monitor.
2400  *
2401  * Asic specific PLL information
2402  *
2403  * DCE 10.x
2404  * Tonga
2405  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2406  * CI
2407  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2408  *
2409  */
2410 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2411 {
2412         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2413         struct drm_device *dev = crtc->dev;
2414         struct amdgpu_device *adev = dev->dev_private;
2415         u32 pll_in_use;
2416         int pll;
2417
2418         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2419                 if (adev->clock.dp_extclk)
2420                         /* skip PPLL programming if using ext clock */
2421                         return ATOM_PPLL_INVALID;
2422                 else {
2423                         /* use the same PPLL for all DP monitors */
2424                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2425                         if (pll != ATOM_PPLL_INVALID)
2426                                 return pll;
2427                 }
2428         } else {
2429                 /* use the same PPLL for all monitors with the same clock */
2430                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2431                 if (pll != ATOM_PPLL_INVALID)
2432                         return pll;
2433         }
2434
2435         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2436         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2437         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2438                 return ATOM_PPLL2;
2439         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2440                 return ATOM_PPLL1;
2441         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2442                 return ATOM_PPLL0;
2443         DRM_ERROR("unable to allocate a PPLL\n");
2444         return ATOM_PPLL_INVALID;
2445 }
2446
2447 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2448 {
2449         struct amdgpu_device *adev = crtc->dev->dev_private;
2450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451         uint32_t cur_lock;
2452
2453         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2454         if (lock)
2455                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2456         else
2457                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2458         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2459 }
2460
2461 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2462 {
2463         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464         struct amdgpu_device *adev = crtc->dev->dev_private;
2465         u32 tmp;
2466
2467         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2468         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2469         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2470 }
2471
2472 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2473 {
2474         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475         struct amdgpu_device *adev = crtc->dev->dev_private;
2476         u32 tmp;
2477
2478         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2479                upper_32_bits(amdgpu_crtc->cursor_addr));
2480         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2481                lower_32_bits(amdgpu_crtc->cursor_addr));
2482
2483         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2484         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2485         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2486         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2487 }
2488
2489 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2490                                         int x, int y)
2491 {
2492         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2493         struct amdgpu_device *adev = crtc->dev->dev_private;
2494         int xorigin = 0, yorigin = 0;
2495
2496         /* avivo cursor are offset into the total surface */
2497         x += crtc->x;
2498         y += crtc->y;
2499         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2500
2501         if (x < 0) {
2502                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2503                 x = 0;
2504         }
2505         if (y < 0) {
2506                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2507                 y = 0;
2508         }
2509
2510         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2511         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2512         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2513                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2514
2515         amdgpu_crtc->cursor_x = x;
2516         amdgpu_crtc->cursor_y = y;
2517
2518         return 0;
2519 }
2520
2521 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2522                                       int x, int y)
2523 {
2524         int ret;
2525
2526         dce_v10_0_lock_cursor(crtc, true);
2527         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2528         dce_v10_0_lock_cursor(crtc, false);
2529
2530         return ret;
2531 }
2532
2533 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2534                                       struct drm_file *file_priv,
2535                                       uint32_t handle,
2536                                       uint32_t width,
2537                                       uint32_t height,
2538                                       int32_t hot_x,
2539                                       int32_t hot_y)
2540 {
2541         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542         struct drm_gem_object *obj;
2543         struct amdgpu_bo *aobj;
2544         int ret;
2545
2546         if (!handle) {
2547                 /* turn off cursor */
2548                 dce_v10_0_hide_cursor(crtc);
2549                 obj = NULL;
2550                 goto unpin;
2551         }
2552
2553         if ((width > amdgpu_crtc->max_cursor_width) ||
2554             (height > amdgpu_crtc->max_cursor_height)) {
2555                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2556                 return -EINVAL;
2557         }
2558
2559         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2560         if (!obj) {
2561                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2562                 return -ENOENT;
2563         }
2564
2565         aobj = gem_to_amdgpu_bo(obj);
2566         ret = amdgpu_bo_reserve(aobj, false);
2567         if (ret != 0) {
2568                 drm_gem_object_unreference_unlocked(obj);
2569                 return ret;
2570         }
2571
2572         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2573         amdgpu_bo_unreserve(aobj);
2574         if (ret) {
2575                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2576                 drm_gem_object_unreference_unlocked(obj);
2577                 return ret;
2578         }
2579
2580         amdgpu_crtc->cursor_width = width;
2581         amdgpu_crtc->cursor_height = height;
2582
2583         dce_v10_0_lock_cursor(crtc, true);
2584
2585         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2586             hot_y != amdgpu_crtc->cursor_hot_y) {
2587                 int x, y;
2588
2589                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2590                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2591
2592                 dce_v10_0_cursor_move_locked(crtc, x, y);
2593
2594                 amdgpu_crtc->cursor_hot_x = hot_x;
2595                 amdgpu_crtc->cursor_hot_y = hot_y;
2596         }
2597
2598         dce_v10_0_show_cursor(crtc);
2599         dce_v10_0_lock_cursor(crtc, false);
2600
2601 unpin:
2602         if (amdgpu_crtc->cursor_bo) {
2603                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2604                 ret = amdgpu_bo_reserve(aobj, false);
2605                 if (likely(ret == 0)) {
2606                         amdgpu_bo_unpin(aobj);
2607                         amdgpu_bo_unreserve(aobj);
2608                 }
2609                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2610         }
2611
2612         amdgpu_crtc->cursor_bo = obj;
2613         return 0;
2614 }
2615
2616 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2617 {
2618         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2619
2620         if (amdgpu_crtc->cursor_bo) {
2621                 dce_v10_0_lock_cursor(crtc, true);
2622
2623                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2624                                              amdgpu_crtc->cursor_y);
2625
2626                 dce_v10_0_show_cursor(crtc);
2627
2628                 dce_v10_0_lock_cursor(crtc, false);
2629         }
2630 }
2631
2632 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2633                                     u16 *blue, uint32_t start, uint32_t size)
2634 {
2635         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2636         int end = (start + size > 256) ? 256 : start + size, i;
2637
2638         /* userspace palettes are always correct as is */
2639         for (i = start; i < end; i++) {
2640                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2641                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2642                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2643         }
2644         dce_v10_0_crtc_load_lut(crtc);
2645 }
2646
2647 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2648 {
2649         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2650
2651         drm_crtc_cleanup(crtc);
2652         destroy_workqueue(amdgpu_crtc->pflip_queue);
2653         kfree(amdgpu_crtc);
2654 }
2655
2656 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2657         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2658         .cursor_move = dce_v10_0_crtc_cursor_move,
2659         .gamma_set = dce_v10_0_crtc_gamma_set,
2660         .set_config = amdgpu_crtc_set_config,
2661         .destroy = dce_v10_0_crtc_destroy,
2662         .page_flip = amdgpu_crtc_page_flip,
2663 };
2664
2665 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2666 {
2667         struct drm_device *dev = crtc->dev;
2668         struct amdgpu_device *adev = dev->dev_private;
2669         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2670         unsigned type;
2671
2672         switch (mode) {
2673         case DRM_MODE_DPMS_ON:
2674                 amdgpu_crtc->enabled = true;
2675                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2676                 dce_v10_0_vga_enable(crtc, true);
2677                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2678                 dce_v10_0_vga_enable(crtc, false);
2679                 /* Make sure VBLANK interrupt is still enabled */
2680                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2681                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2682                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2683                 dce_v10_0_crtc_load_lut(crtc);
2684                 break;
2685         case DRM_MODE_DPMS_STANDBY:
2686         case DRM_MODE_DPMS_SUSPEND:
2687         case DRM_MODE_DPMS_OFF:
2688                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2689                 if (amdgpu_crtc->enabled) {
2690                         dce_v10_0_vga_enable(crtc, true);
2691                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2692                         dce_v10_0_vga_enable(crtc, false);
2693                 }
2694                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2695                 amdgpu_crtc->enabled = false;
2696                 break;
2697         }
2698         /* adjust pm to dpms */
2699         amdgpu_pm_compute_clocks(adev);
2700 }
2701
2702 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2703 {
2704         /* disable crtc pair power gating before programming */
2705         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2706         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2707         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2708 }
2709
2710 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2711 {
2712         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2713         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2714 }
2715
2716 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2717 {
2718         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2719         struct drm_device *dev = crtc->dev;
2720         struct amdgpu_device *adev = dev->dev_private;
2721         struct amdgpu_atom_ss ss;
2722         int i;
2723
2724         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2725         if (crtc->primary->fb) {
2726                 int r;
2727                 struct amdgpu_framebuffer *amdgpu_fb;
2728                 struct amdgpu_bo *rbo;
2729
2730                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2731                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2732                 r = amdgpu_bo_reserve(rbo, false);
2733                 if (unlikely(r))
2734                         DRM_ERROR("failed to reserve rbo before unpin\n");
2735                 else {
2736                         amdgpu_bo_unpin(rbo);
2737                         amdgpu_bo_unreserve(rbo);
2738                 }
2739         }
2740         /* disable the GRPH */
2741         dce_v10_0_grph_enable(crtc, false);
2742
2743         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2744
2745         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2746                 if (adev->mode_info.crtcs[i] &&
2747                     adev->mode_info.crtcs[i]->enabled &&
2748                     i != amdgpu_crtc->crtc_id &&
2749                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2750                         /* one other crtc is using this pll don't turn
2751                          * off the pll
2752                          */
2753                         goto done;
2754                 }
2755         }
2756
2757         switch (amdgpu_crtc->pll_id) {
2758         case ATOM_PPLL0:
2759         case ATOM_PPLL1:
2760         case ATOM_PPLL2:
2761                 /* disable the ppll */
2762                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2763                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2764                 break;
2765         default:
2766                 break;
2767         }
2768 done:
2769         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2770         amdgpu_crtc->adjusted_clock = 0;
2771         amdgpu_crtc->encoder = NULL;
2772         amdgpu_crtc->connector = NULL;
2773 }
2774
2775 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2776                                   struct drm_display_mode *mode,
2777                                   struct drm_display_mode *adjusted_mode,
2778                                   int x, int y, struct drm_framebuffer *old_fb)
2779 {
2780         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2781
2782         if (!amdgpu_crtc->adjusted_clock)
2783                 return -EINVAL;
2784
2785         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2786         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2787         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2788         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2789         amdgpu_atombios_crtc_scaler_setup(crtc);
2790         dce_v10_0_cursor_reset(crtc);
2791         /* update the hw version fpr dpm */
2792         amdgpu_crtc->hw_mode = *adjusted_mode;
2793
2794         return 0;
2795 }
2796
2797 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2798                                      const struct drm_display_mode *mode,
2799                                      struct drm_display_mode *adjusted_mode)
2800 {
2801         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_encoder *encoder;
2804
2805         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2806         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2807                 if (encoder->crtc == crtc) {
2808                         amdgpu_crtc->encoder = encoder;
2809                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2810                         break;
2811                 }
2812         }
2813         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2814                 amdgpu_crtc->encoder = NULL;
2815                 amdgpu_crtc->connector = NULL;
2816                 return false;
2817         }
2818         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2819                 return false;
2820         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2821                 return false;
2822         /* pick pll */
2823         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2824         /* if we can't get a PPLL for a non-DP encoder, fail */
2825         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2826             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2827                 return false;
2828
2829         return true;
2830 }
2831
2832 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2833                                   struct drm_framebuffer *old_fb)
2834 {
2835         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2836 }
2837
2838 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2839                                          struct drm_framebuffer *fb,
2840                                          int x, int y, enum mode_set_atomic state)
2841 {
2842        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2843 }
2844
2845 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2846         .dpms = dce_v10_0_crtc_dpms,
2847         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2848         .mode_set = dce_v10_0_crtc_mode_set,
2849         .mode_set_base = dce_v10_0_crtc_set_base,
2850         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2851         .prepare = dce_v10_0_crtc_prepare,
2852         .commit = dce_v10_0_crtc_commit,
2853         .load_lut = dce_v10_0_crtc_load_lut,
2854         .disable = dce_v10_0_crtc_disable,
2855 };
2856
2857 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2858 {
2859         struct amdgpu_crtc *amdgpu_crtc;
2860         int i;
2861
2862         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2863                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2864         if (amdgpu_crtc == NULL)
2865                 return -ENOMEM;
2866
2867         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2868
2869         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2870         amdgpu_crtc->crtc_id = index;
2871         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2872         adev->mode_info.crtcs[index] = amdgpu_crtc;
2873
2874         amdgpu_crtc->max_cursor_width = 128;
2875         amdgpu_crtc->max_cursor_height = 128;
2876         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2877         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2878
2879         for (i = 0; i < 256; i++) {
2880                 amdgpu_crtc->lut_r[i] = i << 2;
2881                 amdgpu_crtc->lut_g[i] = i << 2;
2882                 amdgpu_crtc->lut_b[i] = i << 2;
2883         }
2884
2885         switch (amdgpu_crtc->crtc_id) {
2886         case 0:
2887         default:
2888                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2889                 break;
2890         case 1:
2891                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2892                 break;
2893         case 2:
2894                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2895                 break;
2896         case 3:
2897                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2898                 break;
2899         case 4:
2900                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2901                 break;
2902         case 5:
2903                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2904                 break;
2905         }
2906
2907         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2908         amdgpu_crtc->adjusted_clock = 0;
2909         amdgpu_crtc->encoder = NULL;
2910         amdgpu_crtc->connector = NULL;
2911         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2912
2913         return 0;
2914 }
2915
2916 static int dce_v10_0_early_init(void *handle)
2917 {
2918         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2919
2920         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2921         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2922
2923         dce_v10_0_set_display_funcs(adev);
2924         dce_v10_0_set_irq_funcs(adev);
2925
2926         switch (adev->asic_type) {
2927         case CHIP_FIJI:
2928         case CHIP_TONGA:
2929                 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2930                 adev->mode_info.num_hpd = 6;
2931                 adev->mode_info.num_dig = 7;
2932                 break;
2933         default:
2934                 /* FIXME: not supported yet */
2935                 return -EINVAL;
2936         }
2937
2938         return 0;
2939 }
2940
2941 static int dce_v10_0_sw_init(void *handle)
2942 {
2943         int r, i;
2944         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2945
2946         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2947                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2948                 if (r)
2949                         return r;
2950         }
2951
2952         for (i = 8; i < 20; i += 2) {
2953                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2954                 if (r)
2955                         return r;
2956         }
2957
2958         /* HPD hotplug */
2959         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2960         if (r)
2961                 return r;
2962
2963         adev->mode_info.mode_config_initialized = true;
2964
2965         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2966
2967         adev->ddev->mode_config.max_width = 16384;
2968         adev->ddev->mode_config.max_height = 16384;
2969
2970         adev->ddev->mode_config.preferred_depth = 24;
2971         adev->ddev->mode_config.prefer_shadow = 1;
2972
2973         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2974
2975         r = amdgpu_modeset_create_props(adev);
2976         if (r)
2977                 return r;
2978
2979         adev->ddev->mode_config.max_width = 16384;
2980         adev->ddev->mode_config.max_height = 16384;
2981
2982         /* allocate crtcs */
2983         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2984                 r = dce_v10_0_crtc_init(adev, i);
2985                 if (r)
2986                         return r;
2987         }
2988
2989         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2990                 amdgpu_print_display_setup(adev->ddev);
2991         else
2992                 return -EINVAL;
2993
2994         /* setup afmt */
2995         dce_v10_0_afmt_init(adev);
2996
2997         r = dce_v10_0_audio_init(adev);
2998         if (r)
2999                 return r;
3000
3001         drm_kms_helper_poll_init(adev->ddev);
3002
3003         return r;
3004 }
3005
3006 static int dce_v10_0_sw_fini(void *handle)
3007 {
3008         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3009
3010         kfree(adev->mode_info.bios_hardcoded_edid);
3011
3012         drm_kms_helper_poll_fini(adev->ddev);
3013
3014         dce_v10_0_audio_fini(adev);
3015
3016         dce_v10_0_afmt_fini(adev);
3017
3018         drm_mode_config_cleanup(adev->ddev);
3019         adev->mode_info.mode_config_initialized = false;
3020
3021         return 0;
3022 }
3023
3024 static int dce_v10_0_hw_init(void *handle)
3025 {
3026         int i;
3027         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3028
3029         dce_v10_0_init_golden_registers(adev);
3030
3031         /* init dig PHYs, disp eng pll */
3032         amdgpu_atombios_encoder_init_dig(adev);
3033         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3034
3035         /* initialize hpd */
3036         dce_v10_0_hpd_init(adev);
3037
3038         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3039                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3040         }
3041
3042         return 0;
3043 }
3044
3045 static int dce_v10_0_hw_fini(void *handle)
3046 {
3047         int i;
3048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3049
3050         dce_v10_0_hpd_fini(adev);
3051
3052         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3053                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3054         }
3055
3056         return 0;
3057 }
3058
3059 static int dce_v10_0_suspend(void *handle)
3060 {
3061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3062
3063         amdgpu_atombios_scratch_regs_save(adev);
3064
3065         return dce_v10_0_hw_fini(handle);
3066 }
3067
3068 static int dce_v10_0_resume(void *handle)
3069 {
3070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3071         int ret;
3072
3073         ret = dce_v10_0_hw_init(handle);
3074
3075         amdgpu_atombios_scratch_regs_restore(adev);
3076
3077         /* turn on the BL */
3078         if (adev->mode_info.bl_encoder) {
3079                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3080                                                                   adev->mode_info.bl_encoder);
3081                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3082                                                     bl_level);
3083         }
3084
3085         return ret;
3086 }
3087
3088 static bool dce_v10_0_is_idle(void *handle)
3089 {
3090         return true;
3091 }
3092
3093 static int dce_v10_0_wait_for_idle(void *handle)
3094 {
3095         return 0;
3096 }
3097
3098 static void dce_v10_0_print_status(void *handle)
3099 {
3100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3101
3102         dev_info(adev->dev, "DCE 10.x registers\n");
3103         /* XXX todo */
3104 }
3105
3106 static int dce_v10_0_soft_reset(void *handle)
3107 {
3108         u32 srbm_soft_reset = 0, tmp;
3109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3110
3111         if (dce_v10_0_is_display_hung(adev))
3112                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3113
3114         if (srbm_soft_reset) {
3115                 dce_v10_0_print_status((void *)adev);
3116
3117                 tmp = RREG32(mmSRBM_SOFT_RESET);
3118                 tmp |= srbm_soft_reset;
3119                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3120                 WREG32(mmSRBM_SOFT_RESET, tmp);
3121                 tmp = RREG32(mmSRBM_SOFT_RESET);
3122
3123                 udelay(50);
3124
3125                 tmp &= ~srbm_soft_reset;
3126                 WREG32(mmSRBM_SOFT_RESET, tmp);
3127                 tmp = RREG32(mmSRBM_SOFT_RESET);
3128
3129                 /* Wait a little for things to settle down */
3130                 udelay(50);
3131                 dce_v10_0_print_status((void *)adev);
3132         }
3133         return 0;
3134 }
3135
3136 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3137                                                      int crtc,
3138                                                      enum amdgpu_interrupt_state state)
3139 {
3140         u32 lb_interrupt_mask;
3141
3142         if (crtc >= adev->mode_info.num_crtc) {
3143                 DRM_DEBUG("invalid crtc %d\n", crtc);
3144                 return;
3145         }
3146
3147         switch (state) {
3148         case AMDGPU_IRQ_STATE_DISABLE:
3149                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3150                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3151                                                   VBLANK_INTERRUPT_MASK, 0);
3152                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3153                 break;
3154         case AMDGPU_IRQ_STATE_ENABLE:
3155                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3156                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3157                                                   VBLANK_INTERRUPT_MASK, 1);
3158                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3159                 break;
3160         default:
3161                 break;
3162         }
3163 }
3164
3165 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3166                                                     int crtc,
3167                                                     enum amdgpu_interrupt_state state)
3168 {
3169         u32 lb_interrupt_mask;
3170
3171         if (crtc >= adev->mode_info.num_crtc) {
3172                 DRM_DEBUG("invalid crtc %d\n", crtc);
3173                 return;
3174         }
3175
3176         switch (state) {
3177         case AMDGPU_IRQ_STATE_DISABLE:
3178                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3179                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3180                                                   VLINE_INTERRUPT_MASK, 0);
3181                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3182                 break;
3183         case AMDGPU_IRQ_STATE_ENABLE:
3184                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3185                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3186                                                   VLINE_INTERRUPT_MASK, 1);
3187                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3188                 break;
3189         default:
3190                 break;
3191         }
3192 }
3193
3194 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3195                                        struct amdgpu_irq_src *source,
3196                                        unsigned hpd,
3197                                        enum amdgpu_interrupt_state state)
3198 {
3199         u32 tmp;
3200
3201         if (hpd >= adev->mode_info.num_hpd) {
3202                 DRM_DEBUG("invalid hdp %d\n", hpd);
3203                 return 0;
3204         }
3205
3206         switch (state) {
3207         case AMDGPU_IRQ_STATE_DISABLE:
3208                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3209                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3210                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3211                 break;
3212         case AMDGPU_IRQ_STATE_ENABLE:
3213                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3214                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3215                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3216                 break;
3217         default:
3218                 break;
3219         }
3220
3221         return 0;
3222 }
3223
3224 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3225                                         struct amdgpu_irq_src *source,
3226                                         unsigned type,
3227                                         enum amdgpu_interrupt_state state)
3228 {
3229         switch (type) {
3230         case AMDGPU_CRTC_IRQ_VBLANK1:
3231                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3232                 break;
3233         case AMDGPU_CRTC_IRQ_VBLANK2:
3234                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3235                 break;
3236         case AMDGPU_CRTC_IRQ_VBLANK3:
3237                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3238                 break;
3239         case AMDGPU_CRTC_IRQ_VBLANK4:
3240                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3241                 break;
3242         case AMDGPU_CRTC_IRQ_VBLANK5:
3243                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3244                 break;
3245         case AMDGPU_CRTC_IRQ_VBLANK6:
3246                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3247                 break;
3248         case AMDGPU_CRTC_IRQ_VLINE1:
3249                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3250                 break;
3251         case AMDGPU_CRTC_IRQ_VLINE2:
3252                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3253                 break;
3254         case AMDGPU_CRTC_IRQ_VLINE3:
3255                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3256                 break;
3257         case AMDGPU_CRTC_IRQ_VLINE4:
3258                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3259                 break;
3260         case AMDGPU_CRTC_IRQ_VLINE5:
3261                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3262                 break;
3263         case AMDGPU_CRTC_IRQ_VLINE6:
3264                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3265                 break;
3266         default:
3267                 break;
3268         }
3269         return 0;
3270 }
3271
3272 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3273                                             struct amdgpu_irq_src *src,
3274                                             unsigned type,
3275                                             enum amdgpu_interrupt_state state)
3276 {
3277         u32 reg;
3278
3279         if (type >= adev->mode_info.num_crtc) {
3280                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3281                 return -EINVAL;
3282         }
3283
3284         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3285         if (state == AMDGPU_IRQ_STATE_DISABLE)
3286                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3287                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3288         else
3289                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3290                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3291
3292         return 0;
3293 }
3294
3295 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3296                                   struct amdgpu_irq_src *source,
3297                                   struct amdgpu_iv_entry *entry)
3298 {
3299         unsigned long flags;
3300         unsigned crtc_id;
3301         struct amdgpu_crtc *amdgpu_crtc;
3302         struct amdgpu_flip_work *works;
3303
3304         crtc_id = (entry->src_id - 8) >> 1;
3305         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3306
3307         if (crtc_id >= adev->mode_info.num_crtc) {
3308                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3309                 return -EINVAL;
3310         }
3311
3312         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3313             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3314                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3315                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3316
3317         /* IRQ could occur when in initial stage */
3318         if (amdgpu_crtc == NULL)
3319                 return 0;
3320
3321         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3322         works = amdgpu_crtc->pflip_works;
3323         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3324                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3325                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3326                                                  amdgpu_crtc->pflip_status,
3327                                                  AMDGPU_FLIP_SUBMITTED);
3328                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3329                 return 0;
3330         }
3331
3332         /* page flip completed. clean up */
3333         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3334         amdgpu_crtc->pflip_works = NULL;
3335
3336         /* wakeup usersapce */
3337         if (works->event)
3338                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3339
3340         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3341
3342         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3343         amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
3344         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3345
3346         return 0;
3347 }
3348
3349 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3350                                   int hpd)
3351 {
3352         u32 tmp;
3353
3354         if (hpd >= adev->mode_info.num_hpd) {
3355                 DRM_DEBUG("invalid hdp %d\n", hpd);
3356                 return;
3357         }
3358
3359         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3360         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3361         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3362 }
3363
3364 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3365                                           int crtc)
3366 {
3367         u32 tmp;
3368
3369         if (crtc >= adev->mode_info.num_crtc) {
3370                 DRM_DEBUG("invalid crtc %d\n", crtc);
3371                 return;
3372         }
3373
3374         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3375         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3376         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3377 }
3378
3379 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3380                                          int crtc)
3381 {
3382         u32 tmp;
3383
3384         if (crtc >= adev->mode_info.num_crtc) {
3385                 DRM_DEBUG("invalid crtc %d\n", crtc);
3386                 return;
3387         }
3388
3389         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3390         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3391         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3392 }
3393
3394 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3395                               struct amdgpu_irq_src *source,
3396                               struct amdgpu_iv_entry *entry)
3397 {
3398         unsigned crtc = entry->src_id - 1;
3399         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3400         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3401
3402         switch (entry->src_data) {
3403         case 0: /* vblank */
3404                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3405                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3406                 else
3407                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3408
3409                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3410                         drm_handle_vblank(adev->ddev, crtc);
3411                 }
3412                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3413
3414                 break;
3415         case 1: /* vline */
3416                 if (disp_int & interrupt_status_offsets[crtc].vline)
3417                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3418                 else
3419                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3420
3421                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3422
3423                 break;
3424         default:
3425                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3426                 break;
3427         }
3428
3429         return 0;
3430 }
3431
3432 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3433                              struct amdgpu_irq_src *source,
3434                              struct amdgpu_iv_entry *entry)
3435 {
3436         uint32_t disp_int, mask;
3437         unsigned hpd;
3438
3439         if (entry->src_data >= adev->mode_info.num_hpd) {
3440                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3441                 return 0;
3442         }
3443
3444         hpd = entry->src_data;
3445         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3446         mask = interrupt_status_offsets[hpd].hpd;
3447
3448         if (disp_int & mask) {
3449                 dce_v10_0_hpd_int_ack(adev, hpd);
3450                 schedule_work(&adev->hotplug_work);
3451                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int dce_v10_0_set_clockgating_state(void *handle,
3458                                           enum amd_clockgating_state state)
3459 {
3460         return 0;
3461 }
3462
3463 static int dce_v10_0_set_powergating_state(void *handle,
3464                                           enum amd_powergating_state state)
3465 {
3466         return 0;
3467 }
3468
3469 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3470         .early_init = dce_v10_0_early_init,
3471         .late_init = NULL,
3472         .sw_init = dce_v10_0_sw_init,
3473         .sw_fini = dce_v10_0_sw_fini,
3474         .hw_init = dce_v10_0_hw_init,
3475         .hw_fini = dce_v10_0_hw_fini,
3476         .suspend = dce_v10_0_suspend,
3477         .resume = dce_v10_0_resume,
3478         .is_idle = dce_v10_0_is_idle,
3479         .wait_for_idle = dce_v10_0_wait_for_idle,
3480         .soft_reset = dce_v10_0_soft_reset,
3481         .print_status = dce_v10_0_print_status,
3482         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3483         .set_powergating_state = dce_v10_0_set_powergating_state,
3484 };
3485
3486 static void
3487 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3488                           struct drm_display_mode *mode,
3489                           struct drm_display_mode *adjusted_mode)
3490 {
3491         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3492
3493         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3494
3495         /* need to call this here rather than in prepare() since we need some crtc info */
3496         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3497
3498         /* set scaler clears this on some chips */
3499         dce_v10_0_set_interleave(encoder->crtc, mode);
3500
3501         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3502                 dce_v10_0_afmt_enable(encoder, true);
3503                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3504         }
3505 }
3506
3507 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3508 {
3509         struct amdgpu_device *adev = encoder->dev->dev_private;
3510         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3511         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3512
3513         if ((amdgpu_encoder->active_device &
3514              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3515             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3516              ENCODER_OBJECT_ID_NONE)) {
3517                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3518                 if (dig) {
3519                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3520                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3521                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3522                 }
3523         }
3524
3525         amdgpu_atombios_scratch_regs_lock(adev, true);
3526
3527         if (connector) {
3528                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3529
3530                 /* select the clock/data port if it uses a router */
3531                 if (amdgpu_connector->router.cd_valid)
3532                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3533
3534                 /* turn eDP panel on for mode set */
3535                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3536                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3537                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3538         }
3539
3540         /* this is needed for the pll/ss setup to work correctly in some cases */
3541         amdgpu_atombios_encoder_set_crtc_source(encoder);
3542         /* set up the FMT blocks */
3543         dce_v10_0_program_fmt(encoder);
3544 }
3545
3546 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3547 {
3548         struct drm_device *dev = encoder->dev;
3549         struct amdgpu_device *adev = dev->dev_private;
3550
3551         /* need to call this here as we need the crtc set up */
3552         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3553         amdgpu_atombios_scratch_regs_lock(adev, false);
3554 }
3555
3556 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3557 {
3558         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3559         struct amdgpu_encoder_atom_dig *dig;
3560
3561         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3562
3563         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3564                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3565                         dce_v10_0_afmt_enable(encoder, false);
3566                 dig = amdgpu_encoder->enc_priv;
3567                 dig->dig_encoder = -1;
3568         }
3569         amdgpu_encoder->active_device = 0;
3570 }
3571
3572 /* these are handled by the primary encoders */
3573 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3574 {
3575
3576 }
3577
3578 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3579 {
3580
3581 }
3582
3583 static void
3584 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3585                       struct drm_display_mode *mode,
3586                       struct drm_display_mode *adjusted_mode)
3587 {
3588
3589 }
3590
3591 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3592 {
3593
3594 }
3595
3596 static void
3597 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3598 {
3599
3600 }
3601
3602 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder,
3603                                     const struct drm_display_mode *mode,
3604                                     struct drm_display_mode *adjusted_mode)
3605 {
3606         return true;
3607 }
3608
3609 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3610         .dpms = dce_v10_0_ext_dpms,
3611         .mode_fixup = dce_v10_0_ext_mode_fixup,
3612         .prepare = dce_v10_0_ext_prepare,
3613         .mode_set = dce_v10_0_ext_mode_set,
3614         .commit = dce_v10_0_ext_commit,
3615         .disable = dce_v10_0_ext_disable,
3616         /* no detect for TMDS/LVDS yet */
3617 };
3618
3619 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3620         .dpms = amdgpu_atombios_encoder_dpms,
3621         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3622         .prepare = dce_v10_0_encoder_prepare,
3623         .mode_set = dce_v10_0_encoder_mode_set,
3624         .commit = dce_v10_0_encoder_commit,
3625         .disable = dce_v10_0_encoder_disable,
3626         .detect = amdgpu_atombios_encoder_dig_detect,
3627 };
3628
3629 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3630         .dpms = amdgpu_atombios_encoder_dpms,
3631         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3632         .prepare = dce_v10_0_encoder_prepare,
3633         .mode_set = dce_v10_0_encoder_mode_set,
3634         .commit = dce_v10_0_encoder_commit,
3635         .detect = amdgpu_atombios_encoder_dac_detect,
3636 };
3637
3638 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3639 {
3640         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3641         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3642                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3643         kfree(amdgpu_encoder->enc_priv);
3644         drm_encoder_cleanup(encoder);
3645         kfree(amdgpu_encoder);
3646 }
3647
3648 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3649         .destroy = dce_v10_0_encoder_destroy,
3650 };
3651
3652 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3653                                  uint32_t encoder_enum,
3654                                  uint32_t supported_device,
3655                                  u16 caps)
3656 {
3657         struct drm_device *dev = adev->ddev;
3658         struct drm_encoder *encoder;
3659         struct amdgpu_encoder *amdgpu_encoder;
3660
3661         /* see if we already added it */
3662         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3663                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3664                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3665                         amdgpu_encoder->devices |= supported_device;
3666                         return;
3667                 }
3668
3669         }
3670
3671         /* add a new one */
3672         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3673         if (!amdgpu_encoder)
3674                 return;
3675
3676         encoder = &amdgpu_encoder->base;
3677         switch (adev->mode_info.num_crtc) {
3678         case 1:
3679                 encoder->possible_crtcs = 0x1;
3680                 break;
3681         case 2:
3682         default:
3683                 encoder->possible_crtcs = 0x3;
3684                 break;
3685         case 4:
3686                 encoder->possible_crtcs = 0xf;
3687                 break;
3688         case 6:
3689                 encoder->possible_crtcs = 0x3f;
3690                 break;
3691         }
3692
3693         amdgpu_encoder->enc_priv = NULL;
3694
3695         amdgpu_encoder->encoder_enum = encoder_enum;
3696         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3697         amdgpu_encoder->devices = supported_device;
3698         amdgpu_encoder->rmx_type = RMX_OFF;
3699         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3700         amdgpu_encoder->is_ext_encoder = false;
3701         amdgpu_encoder->caps = caps;
3702
3703         switch (amdgpu_encoder->encoder_id) {
3704         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3705         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3706                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3707                                  DRM_MODE_ENCODER_DAC);
3708                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3709                 break;
3710         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3711         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3712         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3713         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3714         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3715                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3716                         amdgpu_encoder->rmx_type = RMX_FULL;
3717                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3718                                          DRM_MODE_ENCODER_LVDS);
3719                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3720                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3721                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3722                                          DRM_MODE_ENCODER_DAC);
3723                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3724                 } else {
3725                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3726                                          DRM_MODE_ENCODER_TMDS);
3727                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3728                 }
3729                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3730                 break;
3731         case ENCODER_OBJECT_ID_SI170B:
3732         case ENCODER_OBJECT_ID_CH7303:
3733         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3734         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3735         case ENCODER_OBJECT_ID_TITFP513:
3736         case ENCODER_OBJECT_ID_VT1623:
3737         case ENCODER_OBJECT_ID_HDMI_SI1930:
3738         case ENCODER_OBJECT_ID_TRAVIS:
3739         case ENCODER_OBJECT_ID_NUTMEG:
3740                 /* these are handled by the primary encoders */
3741                 amdgpu_encoder->is_ext_encoder = true;
3742                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3743                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3744                                          DRM_MODE_ENCODER_LVDS);
3745                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3746                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3747                                          DRM_MODE_ENCODER_DAC);
3748                 else
3749                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3750                                          DRM_MODE_ENCODER_TMDS);
3751                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3752                 break;
3753         }
3754 }
3755
3756 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3757         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3758         .bandwidth_update = &dce_v10_0_bandwidth_update,
3759         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3760         .vblank_wait = &dce_v10_0_vblank_wait,
3761         .is_display_hung = &dce_v10_0_is_display_hung,
3762         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3763         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3764         .hpd_sense = &dce_v10_0_hpd_sense,
3765         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3766         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3767         .page_flip = &dce_v10_0_page_flip,
3768         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3769         .add_encoder = &dce_v10_0_encoder_add,
3770         .add_connector = &amdgpu_connector_add,
3771         .stop_mc_access = &dce_v10_0_stop_mc_access,
3772         .resume_mc_access = &dce_v10_0_resume_mc_access,
3773 };
3774
3775 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3776 {
3777         if (adev->mode_info.funcs == NULL)
3778                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3779 }
3780
3781 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3782         .set = dce_v10_0_set_crtc_irq_state,
3783         .process = dce_v10_0_crtc_irq,
3784 };
3785
3786 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3787         .set = dce_v10_0_set_pageflip_irq_state,
3788         .process = dce_v10_0_pageflip_irq,
3789 };
3790
3791 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3792         .set = dce_v10_0_set_hpd_irq_state,
3793         .process = dce_v10_0_hpd_irq,
3794 };
3795
3796 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3797 {
3798         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3799         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3800
3801         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3802         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3803
3804         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3805         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3806 }