drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55
  56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  66
  67 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  68
  69 /*
  70  * sDMA - System DMA
  71  * Starting with CIK, the GPU has new asynchronous
  72  * DMA engines.  These engines are used for compute
  73  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  74  * and each one supports 1 ring buffer used for gfx
  75  * and 2 queues used for compute.
  76  *
  77  * The programming model is very similar to the CP
  78  * (ring buffer, IBs, etc.), but sDMA has it's own
  79  * packet format that is different from the PM4 format
  80  * used by the CP. sDMA supports copying data, writing
  81  * embedded data, solid fills, and a number of other
  82  * things.  It also has support for tiling/detiling of
  83  * buffers.
  84  */
  85
  86 /**
  87  * cik_sdma_init_microcode - load ucode images from disk
  88  *
  89  * @adev: amdgpu_device pointer
  90  *
  91  * Use the firmware interface to load the ucode images into
  92  * the driver (not loaded into hw).
  93  * Returns 0 on success, error on failure.
  94  */
  95 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  96 {
  97         const char *chip_name;
  98         char fw_name[30];
  99         int err = 0, i;
 100
 101         DRM_DEBUG("\n");
 102
 103         switch (adev->asic_type) {
 104         case CHIP_BONAIRE:
 105                 chip_name = "bonaire";
 106                 break;
 107         case CHIP_HAWAII:
 108                 chip_name = "hawaii";
 109                 break;
 110         case CHIP_KAVERI:
 111                 chip_name = "kaveri";
 112                 break;
 113         case CHIP_KABINI:
 114                 chip_name = "kabini";
 115                 break;
 116         case CHIP_MULLINS:
 117                 chip_name = "mullins";
 118                 break;
 119         default: BUG();
 120         }
 121
 122         for (i = 0; i < adev->sdma.num_instances; i++) {
 123                 if (i == 0)
 124                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 125                 else
 126                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 127                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 128                 if (err)
 129                         goto out;
 130                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 131         }
 132 out:
 133         if (err) {
 134                 printk(KERN_ERR
 135                        "cik_sdma: Failed to load firmware \"%s\"\n",
 136                        fw_name);
 137                 for (i = 0; i < adev->sdma.num_instances; i++) {
 138                         release_firmware(adev->sdma.instance[i].fw);
 139                         adev->sdma.instance[i].fw = NULL;
 140                 }
 141         }
 142         return err;
 143 }
 144
 145 /**
 146  * cik_sdma_ring_get_rptr - get the current read pointer
 147  *
 148  * @ring: amdgpu ring pointer
 149  *
 150  * Get the current rptr from the hardware (CIK+).
 151  */
 152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 153 {
 154         u32 rptr;
 155
 156         rptr = ring->adev->wb.wb[ring->rptr_offs];
 157
 158         return (rptr & 0x3fffc) >> 2;
 159 }
 160
 161 /**
 162  * cik_sdma_ring_get_wptr - get the current write pointer
 163  *
 164  * @ring: amdgpu ring pointer
 165  *
 166  * Get the current wptr from the hardware (CIK+).
 167  */
 168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 172
 173         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 174 }
 175
 176 /**
 177  * cik_sdma_ring_set_wptr - commit the write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Write the wptr back to the hardware (CIK+).
 182  */
 183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 184 {
 185         struct amdgpu_device *adev = ring->adev;
 186         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 187
 188         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 189 }
 190
 191 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 192 {
 193         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 194         int i;
 195
 196         for (i = 0; i < count; i++)
 197                 if (sdma && sdma->burst_nop && (i == 0))
 198                         amdgpu_ring_write(ring, ring->nop |
 199                                           SDMA_NOP_COUNT(count - 1));
 200                 else
 201                         amdgpu_ring_write(ring, ring->nop);
 202 }
 203
 204 /**
 205  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 206  *
 207  * @ring: amdgpu ring pointer
 208  * @ib: IB object to schedule
 209  *
 210  * Schedule an IB in the DMA ring (CIK).
 211  */
 212 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 213                            struct amdgpu_ib *ib)
 214 {
 215         u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 216         u32 next_rptr = ring->wptr + 5;
 217
 218         while ((next_rptr & 7) != 4)
 219                 next_rptr++;
 220
 221         next_rptr += 4;
 222         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 223         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 224         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 225         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 226         amdgpu_ring_write(ring, next_rptr);
 227
 228         /* IB packet must end on a 8 DW boundary */
 229         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 230
 231         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 232         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 234         amdgpu_ring_write(ring, ib->length_dw);
 235
 236 }
 237
 238 /**
 239  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Emit an hdp flush packet on the requested DMA ring.
 244  */
 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 246 {
 247         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 248                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 249         u32 ref_and_mask;
 250
 251         if (ring == &ring->adev->sdma.instance[0].ring)
 252                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 253         else
 254                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 255
 256         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 257         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 259         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 260         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 261         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 262 }
 263
 264 /**
 265  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 266  *
 267  * @ring: amdgpu ring pointer
 268  * @fence: amdgpu fence object
 269  *
 270  * Add a DMA fence packet to the ring to write
 271  * the fence seq number and DMA trap packet to generate
 272  * an interrupt if needed (CIK).
 273  */
 274 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 275                                      unsigned flags)
 276 {
 277         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 278         /* write the fence */
 279         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 280         amdgpu_ring_write(ring, lower_32_bits(addr));
 281         amdgpu_ring_write(ring, upper_32_bits(addr));
 282         amdgpu_ring_write(ring, lower_32_bits(seq));
 283
 284         /* optionally write high bits as well */
 285         if (write64bit) {
 286                 addr += 4;
 287                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 288                 amdgpu_ring_write(ring, lower_32_bits(addr));
 289                 amdgpu_ring_write(ring, upper_32_bits(addr));
 290                 amdgpu_ring_write(ring, upper_32_bits(seq));
 291         }
 292
 293         /* generate an interrupt */
 294         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 295 }
 296
 297 /**
 298  * cik_sdma_gfx_stop - stop the gfx async dma engines
 299  *
 300  * @adev: amdgpu_device pointer
 301  *
 302  * Stop the gfx async dma ring buffers (CIK).
 303  */
 304 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 305 {
 306         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 307         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 308         u32 rb_cntl;
 309         int i;
 310
 311         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 312             (adev->mman.buffer_funcs_ring == sdma1))
 313                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 314
 315         for (i = 0; i < adev->sdma.num_instances; i++) {
 316                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 317                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 318                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 319                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 320         }
 321         sdma0->ready = false;
 322         sdma1->ready = false;
 323 }
 324
 325 /**
 326  * cik_sdma_rlc_stop - stop the compute async dma engines
 327  *
 328  * @adev: amdgpu_device pointer
 329  *
 330  * Stop the compute async dma queues (CIK).
 331  */
 332 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 333 {
 334         /* XXX todo */
 335 }
 336
 337 /**
 338  * cik_sdma_enable - stop the async dma engines
 339  *
 340  * @adev: amdgpu_device pointer
 341  * @enable: enable/disable the DMA MEs.
 342  *
 343  * Halt or unhalt the async dma engines (CIK).
 344  */
 345 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 346 {
 347         u32 me_cntl;
 348         int i;
 349
 350         if (enable == false) {
 351                 cik_sdma_gfx_stop(adev);
 352                 cik_sdma_rlc_stop(adev);
 353         }
 354
 355         for (i = 0; i < adev->sdma.num_instances; i++) {
 356                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 357                 if (enable)
 358                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 359                 else
 360                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 361                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 362         }
 363 }
 364
 365 /**
 366  * cik_sdma_gfx_resume - setup and start the async dma engines
 367  *
 368  * @adev: amdgpu_device pointer
 369  *
 370  * Set up the gfx DMA ring buffers and enable them (CIK).
 371  * Returns 0 for success, error for failure.
 372  */
 373 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 374 {
 375         struct amdgpu_ring *ring;
 376         u32 rb_cntl, ib_cntl;
 377         u32 rb_bufsz;
 378         u32 wb_offset;
 379         int i, j, r;
 380
 381         for (i = 0; i < adev->sdma.num_instances; i++) {
 382                 ring = &adev->sdma.instance[i].ring;
 383                 wb_offset = (ring->rptr_offs * 4);
 384
 385                 mutex_lock(&adev->srbm_mutex);
 386                 for (j = 0; j < 16; j++) {
 387                         cik_srbm_select(adev, 0, 0, 0, j);
 388                         /* SDMA GFX */
 389                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 390                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 391                         /* XXX SDMA RLC - todo */
 392                 }
 393                 cik_srbm_select(adev, 0, 0, 0, 0);
 394                 mutex_unlock(&adev->srbm_mutex);
 395
 396                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 397                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 398
 399                 /* Set ring buffer size in dwords */
 400                 rb_bufsz = order_base_2(ring->ring_size / 4);
 401                 rb_cntl = rb_bufsz << 1;
 402 #ifdef __BIG_ENDIAN
 403                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 404                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 405 #endif
 406                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 407
 408                 /* Initialize the ring buffer's read and write pointers */
 409                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 410                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 411
 412                 /* set the wb address whether it's enabled or not */
 413                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 414                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 415                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 416                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 417
 418                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 419
 420                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 421                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 422
 423                 ring->wptr = 0;
 424                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 425
 426                 /* enable DMA RB */
 427                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 428                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 429
 430                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 431 #ifdef __BIG_ENDIAN
 432                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 433 #endif
 434                 /* enable DMA IBs */
 435                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 436
 437                 ring->ready = true;
 438
 439                 r = amdgpu_ring_test_ring(ring);
 440                 if (r) {
 441                         ring->ready = false;
 442                         return r;
 443                 }
 444
 445                 if (adev->mman.buffer_funcs_ring == ring)
 446                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 447         }
 448
 449         return 0;
 450 }
 451
 452 /**
 453  * cik_sdma_rlc_resume - setup and start the async dma engines
 454  *
 455  * @adev: amdgpu_device pointer
 456  *
 457  * Set up the compute DMA queues and enable them (CIK).
 458  * Returns 0 for success, error for failure.
 459  */
 460 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 461 {
 462         /* XXX todo */
 463         return 0;
 464 }
 465
 466 /**
 467  * cik_sdma_load_microcode - load the sDMA ME ucode
 468  *
 469  * @adev: amdgpu_device pointer
 470  *
 471  * Loads the sDMA0/1 ucode.
 472  * Returns 0 for success, -EINVAL if the ucode is not available.
 473  */
 474 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 475 {
 476         const struct sdma_firmware_header_v1_0 *hdr;
 477         const __le32 *fw_data;
 478         u32 fw_size;
 479         int i, j;
 480
 481         /* halt the MEs */
 482         cik_sdma_enable(adev, false);
 483
 484         for (i = 0; i < adev->sdma.num_instances; i++) {
 485                 if (!adev->sdma.instance[i].fw)
 486                         return -EINVAL;
 487                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 488                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 489                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 490                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 491                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 492                 if (adev->sdma.instance[i].feature_version >= 20)
 493                         adev->sdma.instance[i].burst_nop = true;
 494                 fw_data = (const __le32 *)
 495                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 496                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 497                 for (j = 0; j < fw_size; j++)
 498                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 499                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 500         }
 501
 502         return 0;
 503 }
 504
 505 /**
 506  * cik_sdma_start - setup and start the async dma engines
 507  *
 508  * @adev: amdgpu_device pointer
 509  *
 510  * Set up the DMA engines and enable them (CIK).
 511  * Returns 0 for success, error for failure.
 512  */
 513 static int cik_sdma_start(struct amdgpu_device *adev)
 514 {
 515         int r;
 516
 517         r = cik_sdma_load_microcode(adev);
 518         if (r)
 519                 return r;
 520
 521         /* unhalt the MEs */
 522         cik_sdma_enable(adev, true);
 523
 524         /* start the gfx rings and rlc compute queues */
 525         r = cik_sdma_gfx_resume(adev);
 526         if (r)
 527                 return r;
 528         r = cik_sdma_rlc_resume(adev);
 529         if (r)
 530                 return r;
 531
 532         return 0;
 533 }
 534
 535 /**
 536  * cik_sdma_ring_test_ring - simple async dma engine test
 537  *
 538  * @ring: amdgpu_ring structure holding ring information
 539  *
 540  * Test the DMA engine by writing using it to write an
 541  * value to memory. (CIK).
 542  * Returns 0 for success, error for failure.
 543  */
 544 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 545 {
 546         struct amdgpu_device *adev = ring->adev;
 547         unsigned i;
 548         unsigned index;
 549         int r;
 550         u32 tmp;
 551         u64 gpu_addr;
 552
 553         r = amdgpu_wb_get(adev, &index);
 554         if (r) {
 555                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 556                 return r;
 557         }
 558
 559         gpu_addr = adev->wb.gpu_addr + (index * 4);
 560         tmp = 0xCAFEDEAD;
 561         adev->wb.wb[index] = cpu_to_le32(tmp);
 562
 563         r = amdgpu_ring_alloc(ring, 5);
 564         if (r) {
 565                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 566                 amdgpu_wb_free(adev, index);
 567                 return r;
 568         }
 569         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 570         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 571         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 572         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 573         amdgpu_ring_write(ring, 0xDEADBEEF);
 574         amdgpu_ring_commit(ring);
 575
 576         for (i = 0; i < adev->usec_timeout; i++) {
 577                 tmp = le32_to_cpu(adev->wb.wb[index]);
 578                 if (tmp == 0xDEADBEEF)
 579                         break;
 580                 DRM_UDELAY(1);
 581         }
 582
 583         if (i < adev->usec_timeout) {
 584                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 585         } else {
 586                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 587                           ring->idx, tmp);
 588                 r = -EINVAL;
 589         }
 590         amdgpu_wb_free(adev, index);
 591
 592         return r;
 593 }
 594
 595 /**
 596  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 597  *
 598  * @ring: amdgpu_ring structure holding ring information
 599  *
 600  * Test a simple IB in the DMA ring (CIK).
 601  * Returns 0 on success, error on failure.
 602  */
 603 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 604 {
 605         struct amdgpu_device *adev = ring->adev;
 606         struct amdgpu_ib ib;
 607         struct fence *f = NULL;
 608         unsigned i;
 609         unsigned index;
 610         int r;
 611         u32 tmp = 0;
 612         u64 gpu_addr;
 613
 614         r = amdgpu_wb_get(adev, &index);
 615         if (r) {
 616                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 617                 return r;
 618         }
 619
 620         gpu_addr = adev->wb.gpu_addr + (index * 4);
 621         tmp = 0xCAFEDEAD;
 622         adev->wb.wb[index] = cpu_to_le32(tmp);
 623         memset(&ib, 0, sizeof(ib));
 624         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 625         if (r) {
 626                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 627                 goto err0;
 628         }
 629
 630         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 631         ib.ptr[1] = lower_32_bits(gpu_addr);
 632         ib.ptr[2] = upper_32_bits(gpu_addr);
 633         ib.ptr[3] = 1;
 634         ib.ptr[4] = 0xDEADBEEF;
 635         ib.length_dw = 5;
 636         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 637                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 638                                                  &f);
 639         if (r)
 640                 goto err1;
 641
 642         r = fence_wait(f, false);
 643         if (r) {
 644                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 645                 goto err1;
 646         }
 647         for (i = 0; i < adev->usec_timeout; i++) {
 648                 tmp = le32_to_cpu(adev->wb.wb[index]);
 649                 if (tmp == 0xDEADBEEF)
 650                         break;
 651                 DRM_UDELAY(1);
 652         }
 653         if (i < adev->usec_timeout) {
 654                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 655                          ring->idx, i);
 656                 goto err1;
 657         } else {
 658                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 659                 r = -EINVAL;
 660         }
 661
 662 err1:
 663         fence_put(f);
 664         amdgpu_ib_free(adev, &ib);
 665 err0:
 666         amdgpu_wb_free(adev, index);
 667         return r;
 668 }
 669
 670 /**
 671  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 672  *
 673  * @ib: indirect buffer to fill with commands
 674  * @pe: addr of the page entry
 675  * @src: src addr to copy from
 676  * @count: number of page entries to update
 677  *
 678  * Update PTEs by copying them from the GART using sDMA (CIK).
 679  */
 680 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 681                                  uint64_t pe, uint64_t src,
 682                                  unsigned count)
 683 {
 684         while (count) {
 685                 unsigned bytes = count * 8;
 686                 if (bytes > 0x1FFFF8)
 687                         bytes = 0x1FFFF8;
 688
 689                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 690                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 691                 ib->ptr[ib->length_dw++] = bytes;
 692                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 693                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 694                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 695                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 696                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 697
 698                 pe += bytes;
 699                 src += bytes;
 700                 count -= bytes / 8;
 701         }
 702 }
 703
 704 /**
 705  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 706  *
 707  * @ib: indirect buffer to fill with commands
 708  * @pe: addr of the page entry
 709  * @addr: dst addr to write into pe
 710  * @count: number of page entries to update
 711  * @incr: increase next addr by incr bytes
 712  * @flags: access flags
 713  *
 714  * Update PTEs by writing them manually using sDMA (CIK).
 715  */
 716 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 717                                   const dma_addr_t *pages_addr, uint64_t pe,
 718                                   uint64_t addr, unsigned count,
 719                                   uint32_t incr, uint32_t flags)
 720 {
 721         uint64_t value;
 722         unsigned ndw;
 723
 724         while (count) {
 725                 ndw = count * 2;
 726                 if (ndw > 0xFFFFE)
 727                         ndw = 0xFFFFE;
 728
 729                 /* for non-physically contiguous pages (system) */
 730                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 731                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 732                 ib->ptr[ib->length_dw++] = pe;
 733                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 734                 ib->ptr[ib->length_dw++] = ndw;
 735                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 736                         value = amdgpu_vm_map_gart(pages_addr, addr);
 737                         addr += incr;
 738                         value |= flags;
 739                         ib->ptr[ib->length_dw++] = value;
 740                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 741                 }
 742         }
 743 }
 744
 745 /**
 746  * cik_sdma_vm_set_pages - update the page tables using sDMA
 747  *
 748  * @ib: indirect buffer to fill with commands
 749  * @pe: addr of the page entry
 750  * @addr: dst addr to write into pe
 751  * @count: number of page entries to update
 752  * @incr: increase next addr by incr bytes
 753  * @flags: access flags
 754  *
 755  * Update the page tables using sDMA (CIK).
 756  */
 757 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 758                                     uint64_t pe,
 759                                     uint64_t addr, unsigned count,
 760                                     uint32_t incr, uint32_t flags)
 761 {
 762         uint64_t value;
 763         unsigned ndw;
 764
 765         while (count) {
 766                 ndw = count;
 767                 if (ndw > 0x7FFFF)
 768                         ndw = 0x7FFFF;
 769
 770                 if (flags & AMDGPU_PTE_VALID)
 771                         value = addr;
 772                 else
 773                         value = 0;
 774
 775                 /* for physically contiguous pages (vram) */
 776                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 777                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 778                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 779                 ib->ptr[ib->length_dw++] = flags; /* mask */
 780                 ib->ptr[ib->length_dw++] = 0;
 781                 ib->ptr[ib->length_dw++] = value; /* value */
 782                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 783                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 784                 ib->ptr[ib->length_dw++] = 0;
 785                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 786
 787                 pe += ndw * 8;
 788                 addr += ndw * incr;
 789                 count -= ndw;
 790         }
 791 }
 792
 793 /**
 794  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 795  *
 796  * @ib: indirect buffer to fill with padding
 797  *
 798  */
 799 static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
 800 {
 801         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
 802         u32 pad_count;
 803         int i;
 804
 805         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 806         for (i = 0; i < pad_count; i++)
 807                 if (sdma && sdma->burst_nop && (i == 0))
 808                         ib->ptr[ib->length_dw++] =
 809                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 810                                         SDMA_NOP_COUNT(pad_count - 1);
 811                 else
 812                         ib->ptr[ib->length_dw++] =
 813                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 814 }
 815
 816 /**
 817  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 818  *
 819  * @ring: amdgpu_ring pointer
 820  * @vm: amdgpu_vm pointer
 821  *
 822  * Update the page table base and flush the VM TLB
 823  * using sDMA (CIK).
 824  */
 825 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 826                                         unsigned vm_id, uint64_t pd_addr)
 827 {
 828         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 829                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 830
 831         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 832         if (vm_id < 8) {
 833                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 834         } else {
 835                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 836         }
 837         amdgpu_ring_write(ring, pd_addr >> 12);
 838
 839         /* flush TLB */
 840         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 841         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 842         amdgpu_ring_write(ring, 1 << vm_id);
 843
 844         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 845         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 846         amdgpu_ring_write(ring, 0);
 847         amdgpu_ring_write(ring, 0); /* reference */
 848         amdgpu_ring_write(ring, 0); /* mask */
 849         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 850 }
 851
 852 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 853                                  bool enable)
 854 {
 855         u32 orig, data;
 856
 857         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
 858                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 859                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 860         } else {
 861                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 862                 data |= 0xff000000;
 863                 if (data != orig)
 864                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 865
 866                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 867                 data |= 0xff000000;
 868                 if (data != orig)
 869                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 870         }
 871 }
 872
 873 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 874                                  bool enable)
 875 {
 876         u32 orig, data;
 877
 878         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
 879                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 880                 data |= 0x100;
 881                 if (orig != data)
 882                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 883
 884                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 885                 data |= 0x100;
 886                 if (orig != data)
 887                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 888         } else {
 889                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 890                 data &= ~0x100;
 891                 if (orig != data)
 892                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 893
 894                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 895                 data &= ~0x100;
 896                 if (orig != data)
 897                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 898         }
 899 }
 900
 901 static int cik_sdma_early_init(void *handle)
 902 {
 903         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 904
 905         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 906
 907         cik_sdma_set_ring_funcs(adev);
 908         cik_sdma_set_irq_funcs(adev);
 909         cik_sdma_set_buffer_funcs(adev);
 910         cik_sdma_set_vm_pte_funcs(adev);
 911
 912         return 0;
 913 }
 914
 915 static int cik_sdma_sw_init(void *handle)
 916 {
 917         struct amdgpu_ring *ring;
 918         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 919         int r, i;
 920
 921         r = cik_sdma_init_microcode(adev);
 922         if (r) {
 923                 DRM_ERROR("Failed to load sdma firmware!\n");
 924                 return r;
 925         }
 926
 927         /* SDMA trap event */
 928         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 929         if (r)
 930                 return r;
 931
 932         /* SDMA Privileged inst */
 933         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 934         if (r)
 935                 return r;
 936
 937         /* SDMA Privileged inst */
 938         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 939         if (r)
 940                 return r;
 941
 942         for (i = 0; i < adev->sdma.num_instances; i++) {
 943                 ring = &adev->sdma.instance[i].ring;
 944                 ring->ring_obj = NULL;
 945                 sprintf(ring->name, "sdma%d", i);
 946                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 947                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 948                                      &adev->sdma.trap_irq,
 949                                      (i == 0) ?
 950                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 951                                      AMDGPU_RING_TYPE_SDMA);
 952                 if (r)
 953                         return r;
 954         }
 955
 956         return r;
 957 }
 958
 959 static int cik_sdma_sw_fini(void *handle)
 960 {
 961         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 962         int i;
 963
 964         for (i = 0; i < adev->sdma.num_instances; i++)
 965                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 966
 967         return 0;
 968 }
 969
 970 static int cik_sdma_hw_init(void *handle)
 971 {
 972         int r;
 973         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 974
 975         r = cik_sdma_start(adev);
 976         if (r)
 977                 return r;
 978
 979         return r;
 980 }
 981
 982 static int cik_sdma_hw_fini(void *handle)
 983 {
 984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 985
 986         cik_sdma_enable(adev, false);
 987
 988         return 0;
 989 }
 990
 991 static int cik_sdma_suspend(void *handle)
 992 {
 993         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 994
 995         return cik_sdma_hw_fini(adev);
 996 }
 997
 998 static int cik_sdma_resume(void *handle)
 999 {
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         return cik_sdma_hw_init(adev);
1003 }
1004
1005 static bool cik_sdma_is_idle(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008         u32 tmp = RREG32(mmSRBM_STATUS2);
1009
1010         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1011                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1012             return false;
1013
1014         return true;
1015 }
1016
1017 static int cik_sdma_wait_for_idle(void *handle)
1018 {
1019         unsigned i;
1020         u32 tmp;
1021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023         for (i = 0; i < adev->usec_timeout; i++) {
1024                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1025                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1026
1027                 if (!tmp)
1028                         return 0;
1029                 udelay(1);
1030         }
1031         return -ETIMEDOUT;
1032 }
1033
1034 static void cik_sdma_print_status(void *handle)
1035 {
1036         int i, j;
1037         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1038
1039         dev_info(adev->dev, "CIK SDMA registers\n");
1040         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1041                  RREG32(mmSRBM_STATUS2));
1042         for (i = 0; i < adev->sdma.num_instances; i++) {
1043                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1044                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1045                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
1046                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1047                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1048                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1049                 dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1050                          i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1051                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1052                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1053                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1054                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1055                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1056                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1057                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1058                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1059                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1060                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1061                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1062                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1063                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1064                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1065                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1066                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1067                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1068                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1069                 mutex_lock(&adev->srbm_mutex);
1070                 for (j = 0; j < 16; j++) {
1071                         cik_srbm_select(adev, 0, 0, 0, j);
1072                         dev_info(adev->dev, "  VM %d:\n", j);
1073                         dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1074                                  RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1075                         dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
1076                                  RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1077                 }
1078                 cik_srbm_select(adev, 0, 0, 0, 0);
1079                 mutex_unlock(&adev->srbm_mutex);
1080         }
1081 }
1082
1083 static int cik_sdma_soft_reset(void *handle)
1084 {
1085         u32 srbm_soft_reset = 0;
1086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087         u32 tmp = RREG32(mmSRBM_STATUS2);
1088
1089         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1090                 /* sdma0 */
1091                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1092                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1093                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1094                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1095         }
1096         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1097                 /* sdma1 */
1098                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1099                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1100                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1101                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1102         }
1103
1104         if (srbm_soft_reset) {
1105                 cik_sdma_print_status((void *)adev);
1106
1107                 tmp = RREG32(mmSRBM_SOFT_RESET);
1108                 tmp |= srbm_soft_reset;
1109                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1110                 WREG32(mmSRBM_SOFT_RESET, tmp);
1111                 tmp = RREG32(mmSRBM_SOFT_RESET);
1112
1113                 udelay(50);
1114
1115                 tmp &= ~srbm_soft_reset;
1116                 WREG32(mmSRBM_SOFT_RESET, tmp);
1117                 tmp = RREG32(mmSRBM_SOFT_RESET);
1118
1119                 /* Wait a little for things to settle down */
1120                 udelay(50);
1121
1122                 cik_sdma_print_status((void *)adev);
1123         }
1124
1125         return 0;
1126 }
1127
1128 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1129                                        struct amdgpu_irq_src *src,
1130                                        unsigned type,
1131                                        enum amdgpu_interrupt_state state)
1132 {
1133         u32 sdma_cntl;
1134
1135         switch (type) {
1136         case AMDGPU_SDMA_IRQ_TRAP0:
1137                 switch (state) {
1138                 case AMDGPU_IRQ_STATE_DISABLE:
1139                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1140                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1141                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1142                         break;
1143                 case AMDGPU_IRQ_STATE_ENABLE:
1144                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1145                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1146                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1147                         break;
1148                 default:
1149                         break;
1150                 }
1151                 break;
1152         case AMDGPU_SDMA_IRQ_TRAP1:
1153                 switch (state) {
1154                 case AMDGPU_IRQ_STATE_DISABLE:
1155                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1156                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1157                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1158                         break;
1159                 case AMDGPU_IRQ_STATE_ENABLE:
1160                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1161                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1162                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1163                         break;
1164                 default:
1165                         break;
1166                 }
1167                 break;
1168         default:
1169                 break;
1170         }
1171         return 0;
1172 }
1173
1174 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1175                                      struct amdgpu_irq_src *source,
1176                                      struct amdgpu_iv_entry *entry)
1177 {
1178         u8 instance_id, queue_id;
1179
1180         instance_id = (entry->ring_id & 0x3) >> 0;
1181         queue_id = (entry->ring_id & 0xc) >> 2;
1182         DRM_DEBUG("IH: SDMA trap\n");
1183         switch (instance_id) {
1184         case 0:
1185                 switch (queue_id) {
1186                 case 0:
1187                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1188                         break;
1189                 case 1:
1190                         /* XXX compute */
1191                         break;
1192                 case 2:
1193                         /* XXX compute */
1194                         break;
1195                 }
1196                 break;
1197         case 1:
1198                 switch (queue_id) {
1199                 case 0:
1200                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1201                         break;
1202                 case 1:
1203                         /* XXX compute */
1204                         break;
1205                 case 2:
1206                         /* XXX compute */
1207                         break;
1208                 }
1209                 break;
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1216                                              struct amdgpu_irq_src *source,
1217                                              struct amdgpu_iv_entry *entry)
1218 {
1219         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1220         schedule_work(&adev->reset_work);
1221         return 0;
1222 }
1223
1224 static int cik_sdma_set_clockgating_state(void *handle,
1225                                           enum amd_clockgating_state state)
1226 {
1227         bool gate = false;
1228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
1230         if (state == AMD_CG_STATE_GATE)
1231                 gate = true;
1232
1233         cik_enable_sdma_mgcg(adev, gate);
1234         cik_enable_sdma_mgls(adev, gate);
1235
1236         return 0;
1237 }
1238
1239 static int cik_sdma_set_powergating_state(void *handle,
1240                                           enum amd_powergating_state state)
1241 {
1242         return 0;
1243 }
1244
1245 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1246         .early_init = cik_sdma_early_init,
1247         .late_init = NULL,
1248         .sw_init = cik_sdma_sw_init,
1249         .sw_fini = cik_sdma_sw_fini,
1250         .hw_init = cik_sdma_hw_init,
1251         .hw_fini = cik_sdma_hw_fini,
1252         .suspend = cik_sdma_suspend,
1253         .resume = cik_sdma_resume,
1254         .is_idle = cik_sdma_is_idle,
1255         .wait_for_idle = cik_sdma_wait_for_idle,
1256         .soft_reset = cik_sdma_soft_reset,
1257         .print_status = cik_sdma_print_status,
1258         .set_clockgating_state = cik_sdma_set_clockgating_state,
1259         .set_powergating_state = cik_sdma_set_powergating_state,
1260 };
1261
1262 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1263         .get_rptr = cik_sdma_ring_get_rptr,
1264         .get_wptr = cik_sdma_ring_get_wptr,
1265         .set_wptr = cik_sdma_ring_set_wptr,
1266         .parse_cs = NULL,
1267         .emit_ib = cik_sdma_ring_emit_ib,
1268         .emit_fence = cik_sdma_ring_emit_fence,
1269         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1270         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1271         .test_ring = cik_sdma_ring_test_ring,
1272         .test_ib = cik_sdma_ring_test_ib,
1273         .insert_nop = cik_sdma_ring_insert_nop,
1274 };
1275
1276 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1277 {
1278         int i;
1279
1280         for (i = 0; i < adev->sdma.num_instances; i++)
1281                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1282 }
1283
1284 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1285         .set = cik_sdma_set_trap_irq_state,
1286         .process = cik_sdma_process_trap_irq,
1287 };
1288
1289 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1290         .process = cik_sdma_process_illegal_inst_irq,
1291 };
1292
1293 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1294 {
1295         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1296         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1297         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1298 }
1299
1300 /**
1301  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1302  *
1303  * @ring: amdgpu_ring structure holding ring information
1304  * @src_offset: src GPU address
1305  * @dst_offset: dst GPU address
1306  * @byte_count: number of bytes to xfer
1307  *
1308  * Copy GPU buffers using the DMA engine (CIK).
1309  * Used by the amdgpu ttm implementation to move pages if
1310  * registered as the asic copy callback.
1311  */
1312 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1313                                       uint64_t src_offset,
1314                                       uint64_t dst_offset,
1315                                       uint32_t byte_count)
1316 {
1317         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1318         ib->ptr[ib->length_dw++] = byte_count;
1319         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1320         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1321         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1322         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1323         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1324 }
1325
1326 /**
1327  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1328  *
1329  * @ring: amdgpu_ring structure holding ring information
1330  * @src_data: value to write to buffer
1331  * @dst_offset: dst GPU address
1332  * @byte_count: number of bytes to xfer
1333  *
1334  * Fill GPU buffers using the DMA engine (CIK).
1335  */
1336 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1337                                       uint32_t src_data,
1338                                       uint64_t dst_offset,
1339                                       uint32_t byte_count)
1340 {
1341         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1342         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1343         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1344         ib->ptr[ib->length_dw++] = src_data;
1345         ib->ptr[ib->length_dw++] = byte_count;
1346 }
1347
1348 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1349         .copy_max_bytes = 0x1fffff,
1350         .copy_num_dw = 7,
1351         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1352
1353         .fill_max_bytes = 0x1fffff,
1354         .fill_num_dw = 5,
1355         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1356 };
1357
1358 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1359 {
1360         if (adev->mman.buffer_funcs == NULL) {
1361                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1362                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1363         }
1364 }
1365
1366 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1367         .copy_pte = cik_sdma_vm_copy_pte,
1368         .write_pte = cik_sdma_vm_write_pte,
1369         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1370         .pad_ib = cik_sdma_vm_pad_ib,
1371 };
1372
1373 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1374 {
1375         if (adev->vm_manager.vm_pte_funcs == NULL) {
1376                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1377                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1378                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1379         }
1380 }