2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/amdgpu_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
33 #include "atombios_encoders.h"
34 #include "atombios_crtc.h"
35 #include "amdgpu_atombios.h"
36 #include "amdgpu_pll.h"
37 #include "amdgpu_connectors.h"
39 void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
40 struct drm_display_mode *mode,
41 struct drm_display_mode *adjusted_mode)
43 struct drm_device *dev = crtc->dev;
44 struct amdgpu_device *adev = drm_to_adev(dev);
45 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
46 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
47 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
50 memset(&args, 0, sizeof(args));
52 args.ucCRTC = amdgpu_crtc->crtc_id;
54 switch (amdgpu_crtc->rmx_type) {
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
66 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
67 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
69 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
75 args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);
76 args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);
77 args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);
78 args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);
81 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
84 void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc)
86 struct drm_device *dev = crtc->dev;
87 struct amdgpu_device *adev = drm_to_adev(dev);
88 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
89 ENABLE_SCALER_PS_ALLOCATION args;
90 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
92 memset(&args, 0, sizeof(args));
94 args.ucScaler = amdgpu_crtc->crtc_id;
96 switch (amdgpu_crtc->rmx_type) {
98 args.ucEnable = ATOM_SCALER_EXPANSION;
101 args.ucEnable = ATOM_SCALER_CENTER;
104 args.ucEnable = ATOM_SCALER_EXPANSION;
107 args.ucEnable = ATOM_SCALER_DISABLE;
110 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
113 void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock)
115 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
116 struct drm_device *dev = crtc->dev;
117 struct amdgpu_device *adev = drm_to_adev(dev);
119 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
120 ENABLE_CRTC_PS_ALLOCATION args;
122 memset(&args, 0, sizeof(args));
124 args.ucCRTC = amdgpu_crtc->crtc_id;
125 args.ucEnable = lock;
127 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
130 void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state)
132 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
133 struct drm_device *dev = crtc->dev;
134 struct amdgpu_device *adev = drm_to_adev(dev);
135 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
136 ENABLE_CRTC_PS_ALLOCATION args;
138 memset(&args, 0, sizeof(args));
140 args.ucCRTC = amdgpu_crtc->crtc_id;
141 args.ucEnable = state;
143 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
146 void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state)
148 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
149 struct drm_device *dev = crtc->dev;
150 struct amdgpu_device *adev = drm_to_adev(dev);
151 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
152 BLANK_CRTC_PS_ALLOCATION args;
154 memset(&args, 0, sizeof(args));
156 args.ucCRTC = amdgpu_crtc->crtc_id;
157 args.ucBlanking = state;
159 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
162 void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
164 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
165 struct drm_device *dev = crtc->dev;
166 struct amdgpu_device *adev = drm_to_adev(dev);
167 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
168 ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
170 memset(&args, 0, sizeof(args));
172 args.ucDispPipeId = amdgpu_crtc->crtc_id;
173 args.ucEnable = state;
175 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
178 void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
180 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
181 ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
183 memset(&args, 0, sizeof(args));
185 args.ucEnable = ATOM_INIT;
187 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
190 void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
191 struct drm_display_mode *mode)
193 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
194 struct drm_device *dev = crtc->dev;
195 struct amdgpu_device *adev = drm_to_adev(dev);
196 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
197 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
200 memset(&args, 0, sizeof(args));
201 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
202 args.usH_Blanking_Time =
203 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
204 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
205 args.usV_Blanking_Time =
206 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
207 args.usH_SyncOffset =
208 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
210 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
211 args.usV_SyncOffset =
212 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
214 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
215 args.ucH_Border = amdgpu_crtc->h_border;
216 args.ucV_Border = amdgpu_crtc->v_border;
218 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
219 misc |= ATOM_VSYNC_POLARITY;
220 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
221 misc |= ATOM_HSYNC_POLARITY;
222 if (mode->flags & DRM_MODE_FLAG_CSYNC)
223 misc |= ATOM_COMPOSITESYNC;
224 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
225 misc |= ATOM_INTERLACE;
226 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
227 misc |= ATOM_DOUBLE_CLOCK_MODE;
229 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
230 args.ucCRTC = amdgpu_crtc->crtc_id;
232 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
235 union atom_enable_ss {
236 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
237 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
238 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
241 static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
245 struct amdgpu_atom_ss *ss)
248 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
249 union atom_enable_ss args;
252 /* Don't mess with SS if percentage is 0 or external ss.
253 * SS is already disabled previously, and disabling it
254 * again can cause display problems if the pll is already
257 if (ss->percentage == 0)
259 if (ss->type & ATOM_EXTERNAL_SS_MASK)
262 for (i = 0; i < adev->mode_info.num_crtc; i++) {
263 if (adev->mode_info.crtcs[i] &&
264 adev->mode_info.crtcs[i]->enabled &&
266 pll_id == adev->mode_info.crtcs[i]->pll_id) {
267 /* one other crtc is using this pll don't turn
268 * off spread spectrum as it might turn off
269 * display on active crtc
276 memset(&args, 0, sizeof(args));
278 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
279 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
282 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
285 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
288 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
290 case ATOM_PPLL_INVALID:
293 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
294 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
295 args.v3.ucEnable = enable;
297 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
300 union adjust_pixel_clock {
301 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
302 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
305 static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
306 struct drm_display_mode *mode)
308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
309 struct drm_device *dev = crtc->dev;
310 struct amdgpu_device *adev = drm_to_adev(dev);
311 struct drm_encoder *encoder = amdgpu_crtc->encoder;
312 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
313 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
314 u32 adjusted_clock = mode->clock;
315 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
316 u32 dp_clock = mode->clock;
317 u32 clock = mode->clock;
318 int bpc = amdgpu_crtc->bpc;
319 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
320 union adjust_pixel_clock args;
324 amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
326 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
327 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
329 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
330 struct amdgpu_connector_atom_dig *dig_connector =
331 amdgpu_connector->con_priv;
333 dp_clock = dig_connector->dp_clock;
337 /* use recommended ref_div for ss */
338 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
339 if (amdgpu_crtc->ss_enabled) {
340 if (amdgpu_crtc->ss.refdiv) {
341 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
342 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;
343 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
348 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
349 if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
350 adjusted_clock = mode->clock * 2;
351 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
352 amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;
353 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
354 amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;
357 /* adjust pll for deep color modes */
358 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
364 clock = (clock * 5) / 4;
367 clock = (clock * 3) / 2;
375 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
376 * accordingly based on the encoder/transmitter to work around
377 * special hw requirements.
379 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
380 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
382 return adjusted_clock;
384 memset(&args, 0, sizeof(args));
391 args.v1.usPixelClock = cpu_to_le16(clock / 10);
392 args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;
393 args.v1.ucEncodeMode = encoder_mode;
394 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
396 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
398 amdgpu_atom_execute_table(adev->mode_info.atom_context,
399 index, (uint32_t *)&args);
400 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
403 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
404 args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id;
405 args.v3.sInput.ucEncodeMode = encoder_mode;
406 args.v3.sInput.ucDispPllConfig = 0;
407 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
408 args.v3.sInput.ucDispPllConfig |=
409 DISPPLL_CONFIG_SS_ENABLE;
410 if (ENCODER_MODE_IS_DP(encoder_mode)) {
411 args.v3.sInput.ucDispPllConfig |=
412 DISPPLL_CONFIG_COHERENT_MODE;
414 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
415 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
416 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
417 if (dig->coherent_mode)
418 args.v3.sInput.ucDispPllConfig |=
419 DISPPLL_CONFIG_COHERENT_MODE;
421 args.v3.sInput.ucDispPllConfig |=
422 DISPPLL_CONFIG_DUAL_LINK;
424 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
425 ENCODER_OBJECT_ID_NONE)
426 args.v3.sInput.ucExtTransmitterID =
427 amdgpu_encoder_get_dp_bridge_encoder_id(encoder);
429 args.v3.sInput.ucExtTransmitterID = 0;
431 amdgpu_atom_execute_table(adev->mode_info.atom_context,
432 index, (uint32_t *)&args);
433 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
434 if (args.v3.sOutput.ucRefDiv) {
435 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
436 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
437 amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
439 if (args.v3.sOutput.ucPostDiv) {
440 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
441 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;
442 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
446 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
447 return adjusted_clock;
451 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
452 return adjusted_clock;
455 return adjusted_clock;
458 union set_pixel_clock {
459 SET_PIXEL_CLOCK_PS_ALLOCATION base;
460 PIXEL_CLOCK_PARAMETERS v1;
461 PIXEL_CLOCK_PARAMETERS_V2 v2;
462 PIXEL_CLOCK_PARAMETERS_V3 v3;
463 PIXEL_CLOCK_PARAMETERS_V5 v5;
464 PIXEL_CLOCK_PARAMETERS_V6 v6;
465 PIXEL_CLOCK_PARAMETERS_V7 v7;
468 /* on DCE5, make sure the voltage is high enough to support the
471 void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
476 union set_pixel_clock args;
478 memset(&args, 0, sizeof(args));
480 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
481 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
489 /* if the default dcpll clock is specified,
490 * SetPixelClock provides the dividers
492 args.v5.ucCRTC = ATOM_CRTC_INVALID;
493 args.v5.usPixelClock = cpu_to_le16(dispclk);
494 args.v5.ucPpll = ATOM_DCPLL;
497 /* if the default dcpll clock is specified,
498 * SetPixelClock provides the dividers
500 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
501 if (adev->asic_type == CHIP_TAHITI ||
502 adev->asic_type == CHIP_PITCAIRN ||
503 adev->asic_type == CHIP_VERDE ||
504 adev->asic_type == CHIP_OLAND)
505 args.v6.ucPpll = ATOM_PPLL0;
507 args.v6.ucPpll = ATOM_EXT_PLL1;
510 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
515 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
518 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
521 union set_dce_clock {
522 SET_DCE_CLOCK_PS_ALLOCATION_V1_1 v1_1;
523 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1;
526 u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,
527 u32 freq, u8 clk_type, u8 clk_src)
531 union set_dce_clock args;
534 memset(&args, 0, sizeof(args));
536 index = GetIndexIntoMasterTable(COMMAND, SetDCEClock);
537 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
545 args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */
546 args.v2_1.asParam.ucDCEClkType = clk_type;
547 args.v2_1.asParam.ucDCEClkSrc = clk_src;
548 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
549 ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10;
552 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
557 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
564 static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
566 if (ENCODER_MODE_IS_DP(encoder_mode)) {
567 if (pll_id < ATOM_EXT_PLL1)
576 void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
588 struct amdgpu_atom_ss *ss)
590 struct drm_device *dev = crtc->dev;
591 struct amdgpu_device *adev = drm_to_adev(dev);
593 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
594 union set_pixel_clock args;
596 memset(&args, 0, sizeof(args));
598 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
606 if (clock == ATOM_DISABLE)
608 args.v1.usPixelClock = cpu_to_le16(clock / 10);
609 args.v1.usRefDiv = cpu_to_le16(ref_div);
610 args.v1.usFbDiv = cpu_to_le16(fb_div);
611 args.v1.ucFracFbDiv = frac_fb_div;
612 args.v1.ucPostDiv = post_div;
613 args.v1.ucPpll = pll_id;
614 args.v1.ucCRTC = crtc_id;
615 args.v1.ucRefDivSrc = 1;
618 args.v2.usPixelClock = cpu_to_le16(clock / 10);
619 args.v2.usRefDiv = cpu_to_le16(ref_div);
620 args.v2.usFbDiv = cpu_to_le16(fb_div);
621 args.v2.ucFracFbDiv = frac_fb_div;
622 args.v2.ucPostDiv = post_div;
623 args.v2.ucPpll = pll_id;
624 args.v2.ucCRTC = crtc_id;
625 args.v2.ucRefDivSrc = 1;
628 args.v3.usPixelClock = cpu_to_le16(clock / 10);
629 args.v3.usRefDiv = cpu_to_le16(ref_div);
630 args.v3.usFbDiv = cpu_to_le16(fb_div);
631 args.v3.ucFracFbDiv = frac_fb_div;
632 args.v3.ucPostDiv = post_div;
633 args.v3.ucPpll = pll_id;
634 if (crtc_id == ATOM_CRTC2)
635 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
637 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
638 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
639 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
640 args.v3.ucTransmitterId = encoder_id;
641 args.v3.ucEncoderMode = encoder_mode;
644 args.v5.ucCRTC = crtc_id;
645 args.v5.usPixelClock = cpu_to_le16(clock / 10);
646 args.v5.ucRefDiv = ref_div;
647 args.v5.usFbDiv = cpu_to_le16(fb_div);
648 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
649 args.v5.ucPostDiv = post_div;
650 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
651 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
652 (pll_id < ATOM_EXT_PLL1))
653 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
654 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
658 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
661 /* yes this is correct, the atom define is wrong */
662 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
665 /* yes this is correct, the atom define is wrong */
666 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
670 args.v5.ucTransmitterID = encoder_id;
671 args.v5.ucEncoderMode = encoder_mode;
672 args.v5.ucPpll = pll_id;
675 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
676 args.v6.ucRefDiv = ref_div;
677 args.v6.usFbDiv = cpu_to_le16(fb_div);
678 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
679 args.v6.ucPostDiv = post_div;
680 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
681 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
682 (pll_id < ATOM_EXT_PLL1) &&
683 !is_pixel_clock_source_from_pll(encoder_mode, pll_id))
684 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
685 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
689 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
692 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
695 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
698 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
702 args.v6.ucTransmitterID = encoder_id;
703 args.v6.ucEncoderMode = encoder_mode;
704 args.v6.ucPpll = pll_id;
707 args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */
708 args.v7.ucMiscInfo = 0;
709 if ((encoder_mode == ATOM_ENCODER_MODE_DVI) &&
711 args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
712 args.v7.ucCRTC = crtc_id;
713 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
717 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
720 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
723 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
726 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
730 args.v7.ucTransmitterID = encoder_id;
731 args.v7.ucEncoderMode = encoder_mode;
732 args.v7.ucPpll = pll_id;
735 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
740 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
744 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
747 int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
748 struct drm_display_mode *mode)
750 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
751 struct drm_device *dev = crtc->dev;
752 struct amdgpu_device *adev = drm_to_adev(dev);
753 struct amdgpu_encoder *amdgpu_encoder =
754 to_amdgpu_encoder(amdgpu_crtc->encoder);
755 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
757 amdgpu_crtc->bpc = 8;
758 amdgpu_crtc->ss_enabled = false;
760 if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
761 (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
762 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
763 struct drm_connector *connector =
764 amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
765 struct amdgpu_connector *amdgpu_connector =
766 to_amdgpu_connector(connector);
767 struct amdgpu_connector_atom_dig *dig_connector =
768 amdgpu_connector->con_priv;
771 /* Assign mode clock for hdmi deep color max clock limit check */
772 amdgpu_connector->pixelclock_for_modeset = mode->clock;
773 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
775 switch (encoder_mode) {
776 case ATOM_ENCODER_MODE_DP_MST:
777 case ATOM_ENCODER_MODE_DP:
779 dp_clock = dig_connector->dp_clock / 10;
780 amdgpu_crtc->ss_enabled =
781 amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,
782 ASIC_INTERNAL_SS_ON_DP,
785 case ATOM_ENCODER_MODE_LVDS:
786 amdgpu_crtc->ss_enabled =
787 amdgpu_atombios_get_asic_ss_info(adev,
792 case ATOM_ENCODER_MODE_DVI:
793 amdgpu_crtc->ss_enabled =
794 amdgpu_atombios_get_asic_ss_info(adev,
796 ASIC_INTERNAL_SS_ON_TMDS,
799 case ATOM_ENCODER_MODE_HDMI:
800 amdgpu_crtc->ss_enabled =
801 amdgpu_atombios_get_asic_ss_info(adev,
803 ASIC_INTERNAL_SS_ON_HDMI,
811 /* adjust pixel clock as needed */
812 amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
817 void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
819 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
820 struct drm_device *dev = crtc->dev;
821 struct amdgpu_device *adev = drm_to_adev(dev);
822 struct amdgpu_encoder *amdgpu_encoder =
823 to_amdgpu_encoder(amdgpu_crtc->encoder);
824 u32 pll_clock = mode->clock;
825 u32 clock = mode->clock;
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
827 struct amdgpu_pll *pll;
828 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
830 /* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */
831 if ((encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
832 (amdgpu_crtc->bpc > 8))
833 clock = amdgpu_crtc->adjusted_clock;
835 switch (amdgpu_crtc->pll_id) {
837 pll = &adev->clock.ppll[0];
840 pll = &adev->clock.ppll[1];
843 case ATOM_PPLL_INVALID:
845 pll = &adev->clock.ppll[2];
849 /* update pll params */
850 pll->flags = amdgpu_crtc->pll_flags;
851 pll->reference_div = amdgpu_crtc->pll_reference_div;
852 pll->post_div = amdgpu_crtc->pll_post_div;
854 amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
855 &fb_div, &frac_fb_div, &ref_div, &post_div);
857 amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
858 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
860 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
861 encoder_mode, amdgpu_encoder->encoder_id, clock,
862 ref_div, fb_div, frac_fb_div, post_div,
863 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
865 if (amdgpu_crtc->ss_enabled) {
866 /* calculate ss amount and step size */
868 u32 amount = (((fb_div * 10) + frac_fb_div) *
869 (u32)amdgpu_crtc->ss.percentage) /
870 (100 * (u32)amdgpu_crtc->ss.percentage_divider);
871 amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
872 amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
873 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
874 if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
875 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
876 (125 * 25 * pll->reference_freq / 100);
878 step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
879 (125 * 25 * pll->reference_freq / 100);
880 amdgpu_crtc->ss.step = step_size;
882 amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
883 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);