2 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Stanislaw Skowronek
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <asm/unaligned.h>
33 #include "atom-names.h"
34 #include "atom-bits.h"
37 #define ATOM_COND_ABOVE 0
38 #define ATOM_COND_ABOVEOREQUAL 1
39 #define ATOM_COND_ALWAYS 2
40 #define ATOM_COND_BELOW 3
41 #define ATOM_COND_BELOWOREQUAL 4
42 #define ATOM_COND_EQUAL 5
43 #define ATOM_COND_NOTEQUAL 6
45 #define ATOM_PORT_ATI 0
46 #define ATOM_PORT_PCI 1
47 #define ATOM_PORT_SYSIO 2
49 #define ATOM_UNIT_MICROSEC 0
50 #define ATOM_UNIT_MILLISEC 1
56 struct atom_context *ctx;
61 unsigned long last_jump_jiffies;
65 int amdgpu_atom_debug = 0;
66 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
67 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
69 static uint32_t atom_arg_mask[8] =
70 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
72 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
74 static int atom_dst_to_src[8][4] = {
75 /* translate destination alignment field to the source alignment encoding */
85 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
87 static int debug_depth = 0;
89 static void debug_print_spaces(int n)
95 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
96 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
98 #define DEBUG(...) do { } while (0)
99 #define SDEBUG(...) do { } while (0)
102 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
103 uint32_t index, uint32_t data)
105 uint32_t temp = 0xCDCDCDCD;
113 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
117 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
122 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
128 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
132 case ATOM_IIO_MOVE_INDEX:
134 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
137 ((index >> CU8(base + 2)) &
138 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
142 case ATOM_IIO_MOVE_DATA:
144 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
147 ((data >> CU8(base + 2)) &
148 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
152 case ATOM_IIO_MOVE_ATTR:
154 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
158 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
169 printk(KERN_INFO "Unknown IIO opcode.\n");
174 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
175 int *ptr, uint32_t *saved, int print)
177 uint32_t idx, val = 0xCDCDCDCD, align, arg;
178 struct atom_context *gctx = ctx->ctx;
180 align = (attr >> 3) & 7;
186 DEBUG("REG[0x%04X]", idx);
187 idx += gctx->reg_block;
188 switch (gctx->io_mode) {
190 val = gctx->card->reg_read(gctx->card, idx);
194 "PCI registers are not implemented.\n");
198 "SYSIO registers are not implemented.\n");
201 if (!(gctx->io_mode & 0x80)) {
202 printk(KERN_INFO "Bad IO mode.\n");
205 if (!gctx->iio[gctx->io_mode & 0x7F]) {
207 "Undefined indirect IO read method %d.\n",
208 gctx->io_mode & 0x7F);
212 atom_iio_execute(gctx,
213 gctx->iio[gctx->io_mode & 0x7F],
220 /* get_unaligned_le32 avoids unaligned accesses from atombios
221 * tables, noticed on a DEC Alpha. */
222 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
224 DEBUG("PS[0x%02X,0x%04X]", idx, val);
230 DEBUG("WS[0x%02X]", idx);
232 case ATOM_WS_QUOTIENT:
233 val = gctx->divmul[0];
235 case ATOM_WS_REMAINDER:
236 val = gctx->divmul[1];
238 case ATOM_WS_DATAPTR:
239 val = gctx->data_block;
244 case ATOM_WS_OR_MASK:
245 val = 1 << gctx->shift;
247 case ATOM_WS_AND_MASK:
248 val = ~(1 << gctx->shift);
250 case ATOM_WS_FB_WINDOW:
253 case ATOM_WS_ATTRIBUTES:
257 val = gctx->reg_block;
267 if (gctx->data_block)
268 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
270 DEBUG("ID[0x%04X]", idx);
272 val = U32(idx + gctx->data_block);
277 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
278 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
279 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
282 val = gctx->scratch[(gctx->fb_base / 4) + idx];
284 DEBUG("FB[0x%02X]", idx);
292 DEBUG("IMM 0x%08X\n", val);
296 case ATOM_SRC_WORD16:
300 DEBUG("IMM 0x%04X\n", val);
304 case ATOM_SRC_BYTE16:
305 case ATOM_SRC_BYTE24:
309 DEBUG("IMM 0x%02X\n", val);
317 DEBUG("PLL[0x%02X]", idx);
318 val = gctx->card->pll_read(gctx->card, idx);
324 DEBUG("MC[0x%02X]", idx);
325 val = gctx->card->mc_read(gctx->card, idx);
330 val &= atom_arg_mask[align];
331 val >>= atom_arg_shift[align];
335 DEBUG(".[31:0] -> 0x%08X\n", val);
338 DEBUG(".[15:0] -> 0x%04X\n", val);
341 DEBUG(".[23:8] -> 0x%04X\n", val);
343 case ATOM_SRC_WORD16:
344 DEBUG(".[31:16] -> 0x%04X\n", val);
347 DEBUG(".[7:0] -> 0x%02X\n", val);
350 DEBUG(".[15:8] -> 0x%02X\n", val);
352 case ATOM_SRC_BYTE16:
353 DEBUG(".[23:16] -> 0x%02X\n", val);
355 case ATOM_SRC_BYTE24:
356 DEBUG(".[31:24] -> 0x%02X\n", val);
362 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
364 uint32_t align = (attr >> 3) & 7, arg = attr & 7;
384 case ATOM_SRC_WORD16:
389 case ATOM_SRC_BYTE16:
390 case ATOM_SRC_BYTE24:
398 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
400 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
403 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
405 uint32_t val = 0xCDCDCDCD;
414 case ATOM_SRC_WORD16:
420 case ATOM_SRC_BYTE16:
421 case ATOM_SRC_BYTE24:
429 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
430 int *ptr, uint32_t *saved, int print)
432 return atom_get_src_int(ctx,
433 arg | atom_dst_to_src[(attr >> 3) &
434 7][(attr >> 6) & 3] << 3,
438 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
440 atom_skip_src_int(ctx,
441 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
445 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
446 int *ptr, uint32_t val, uint32_t saved)
449 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
451 struct atom_context *gctx = ctx->ctx;
452 old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
453 val <<= atom_arg_shift[align];
454 val &= atom_arg_mask[align];
455 saved &= ~atom_arg_mask[align];
461 DEBUG("REG[0x%04X]", idx);
462 idx += gctx->reg_block;
463 switch (gctx->io_mode) {
466 gctx->card->reg_write(gctx->card, idx,
469 gctx->card->reg_write(gctx->card, idx, val);
473 "PCI registers are not implemented.\n");
477 "SYSIO registers are not implemented.\n");
480 if (!(gctx->io_mode & 0x80)) {
481 printk(KERN_INFO "Bad IO mode.\n");
484 if (!gctx->iio[gctx->io_mode & 0xFF]) {
486 "Undefined indirect IO write method %d.\n",
487 gctx->io_mode & 0x7F);
490 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
497 DEBUG("PS[0x%02X]", idx);
498 ctx->ps[idx] = cpu_to_le32(val);
503 DEBUG("WS[0x%02X]", idx);
505 case ATOM_WS_QUOTIENT:
506 gctx->divmul[0] = val;
508 case ATOM_WS_REMAINDER:
509 gctx->divmul[1] = val;
511 case ATOM_WS_DATAPTR:
512 gctx->data_block = val;
517 case ATOM_WS_OR_MASK:
518 case ATOM_WS_AND_MASK:
520 case ATOM_WS_FB_WINDOW:
523 case ATOM_WS_ATTRIBUTES:
527 gctx->reg_block = val;
536 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
537 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
538 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
540 gctx->scratch[(gctx->fb_base / 4) + idx] = val;
541 DEBUG("FB[0x%02X]", idx);
546 DEBUG("PLL[0x%02X]", idx);
547 gctx->card->pll_write(gctx->card, idx, val);
552 DEBUG("MC[0x%02X]", idx);
553 gctx->card->mc_write(gctx->card, idx, val);
558 DEBUG(".[31:0] <- 0x%08X\n", old_val);
561 DEBUG(".[15:0] <- 0x%04X\n", old_val);
564 DEBUG(".[23:8] <- 0x%04X\n", old_val);
566 case ATOM_SRC_WORD16:
567 DEBUG(".[31:16] <- 0x%04X\n", old_val);
570 DEBUG(".[7:0] <- 0x%02X\n", old_val);
573 DEBUG(".[15:8] <- 0x%02X\n", old_val);
575 case ATOM_SRC_BYTE16:
576 DEBUG(".[23:16] <- 0x%02X\n", old_val);
578 case ATOM_SRC_BYTE24:
579 DEBUG(".[31:24] <- 0x%02X\n", old_val);
584 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
586 uint8_t attr = U8((*ptr)++);
587 uint32_t dst, src, saved;
590 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
592 src = atom_get_src(ctx, attr, ptr);
595 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
598 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
600 uint8_t attr = U8((*ptr)++);
601 uint32_t dst, src, saved;
604 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
606 src = atom_get_src(ctx, attr, ptr);
609 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
612 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
614 printk("ATOM BIOS beeped!\n");
617 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
619 int idx = U8((*ptr)++);
622 if (idx < ATOM_TABLE_NAMES_CNT)
623 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]);
625 SDEBUG(" table: %d\n", idx);
626 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
627 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
633 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
635 uint8_t attr = U8((*ptr)++);
639 attr |= atom_def_dst[attr >> 3] << 6;
640 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
642 atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
645 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
647 uint8_t attr = U8((*ptr)++);
650 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
652 src = atom_get_src(ctx, attr, ptr);
653 ctx->ctx->cs_equal = (dst == src);
654 ctx->ctx->cs_above = (dst > src);
655 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
656 ctx->ctx->cs_above ? "GT" : "LE");
659 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
661 unsigned count = U8((*ptr)++);
662 SDEBUG(" count: %d\n", count);
663 if (arg == ATOM_UNIT_MICROSEC)
665 else if (!drm_can_sleep())
671 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
673 uint8_t attr = U8((*ptr)++);
676 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
678 src = atom_get_src(ctx, attr, ptr);
680 ctx->ctx->divmul[0] = dst / src;
681 ctx->ctx->divmul[1] = dst % src;
683 ctx->ctx->divmul[0] = 0;
684 ctx->ctx->divmul[1] = 0;
688 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
690 /* functionally, a nop */
693 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
695 int execute = 0, target = U16(*ptr);
696 unsigned long cjiffies;
700 case ATOM_COND_ABOVE:
701 execute = ctx->ctx->cs_above;
703 case ATOM_COND_ABOVEOREQUAL:
704 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
706 case ATOM_COND_ALWAYS:
709 case ATOM_COND_BELOW:
710 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
712 case ATOM_COND_BELOWOREQUAL:
713 execute = !ctx->ctx->cs_above;
715 case ATOM_COND_EQUAL:
716 execute = ctx->ctx->cs_equal;
718 case ATOM_COND_NOTEQUAL:
719 execute = !ctx->ctx->cs_equal;
722 if (arg != ATOM_COND_ALWAYS)
723 SDEBUG(" taken: %s\n", execute ? "yes" : "no");
724 SDEBUG(" target: 0x%04X\n", target);
726 if (ctx->last_jump == (ctx->start + target)) {
728 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
729 cjiffies -= ctx->last_jump_jiffies;
730 if ((jiffies_to_msecs(cjiffies) > 5000)) {
731 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
735 /* jiffies wrap around we will just wait a little longer */
736 ctx->last_jump_jiffies = jiffies;
739 ctx->last_jump = ctx->start + target;
740 ctx->last_jump_jiffies = jiffies;
742 *ptr = ctx->start + target;
746 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
748 uint8_t attr = U8((*ptr)++);
749 uint32_t dst, mask, src, saved;
752 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
753 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
754 SDEBUG(" mask: 0x%08x", mask);
756 src = atom_get_src(ctx, attr, ptr);
760 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
763 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
765 uint8_t attr = U8((*ptr)++);
768 if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
769 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
771 atom_skip_dst(ctx, arg, attr, ptr);
775 src = atom_get_src(ctx, attr, ptr);
777 atom_put_dst(ctx, arg, attr, &dptr, src, saved);
780 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
782 uint8_t attr = U8((*ptr)++);
785 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
787 src = atom_get_src(ctx, attr, ptr);
788 ctx->ctx->divmul[0] = dst * src;
791 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
796 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
798 uint8_t attr = U8((*ptr)++);
799 uint32_t dst, src, saved;
802 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
804 src = atom_get_src(ctx, attr, ptr);
807 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
810 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
812 uint8_t val = U8((*ptr)++);
813 SDEBUG("POST card output: 0x%02X\n", val);
816 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
818 printk(KERN_INFO "unimplemented!\n");
821 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
823 printk(KERN_INFO "unimplemented!\n");
826 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
828 printk(KERN_INFO "unimplemented!\n");
831 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
835 SDEBUG(" block: %d\n", idx);
837 ctx->ctx->data_block = 0;
839 ctx->ctx->data_block = ctx->start;
841 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
842 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block);
845 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
847 uint8_t attr = U8((*ptr)++);
848 SDEBUG(" fb_base: ");
849 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
852 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
858 if (port < ATOM_IO_NAMES_CNT)
859 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]);
861 SDEBUG(" port: %d\n", port);
863 ctx->ctx->io_mode = ATOM_IO_MM;
865 ctx->ctx->io_mode = ATOM_IO_IIO | port;
869 ctx->ctx->io_mode = ATOM_IO_PCI;
872 case ATOM_PORT_SYSIO:
873 ctx->ctx->io_mode = ATOM_IO_SYSIO;
879 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
881 ctx->ctx->reg_block = U16(*ptr);
883 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
886 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
888 uint8_t attr = U8((*ptr)++), shift;
892 attr |= atom_def_dst[attr >> 3] << 6;
894 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
895 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
896 SDEBUG(" shift: %d\n", shift);
899 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
902 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
904 uint8_t attr = U8((*ptr)++), shift;
908 attr |= atom_def_dst[attr >> 3] << 6;
910 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
911 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
912 SDEBUG(" shift: %d\n", shift);
915 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
918 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
920 uint8_t attr = U8((*ptr)++), shift;
923 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
925 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
926 /* op needs to full dst value */
928 shift = atom_get_src(ctx, attr, ptr);
929 SDEBUG(" shift: %d\n", shift);
931 dst &= atom_arg_mask[dst_align];
932 dst >>= atom_arg_shift[dst_align];
934 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
937 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
939 uint8_t attr = U8((*ptr)++), shift;
942 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
944 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
945 /* op needs to full dst value */
947 shift = atom_get_src(ctx, attr, ptr);
948 SDEBUG(" shift: %d\n", shift);
950 dst &= atom_arg_mask[dst_align];
951 dst >>= atom_arg_shift[dst_align];
953 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
956 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
958 uint8_t attr = U8((*ptr)++);
959 uint32_t dst, src, saved;
962 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
964 src = atom_get_src(ctx, attr, ptr);
967 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
970 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
972 uint8_t attr = U8((*ptr)++);
973 uint32_t src, val, target;
975 src = atom_get_src(ctx, attr, ptr);
976 while (U16(*ptr) != ATOM_CASE_END)
977 if (U8(*ptr) == ATOM_CASE_MAGIC) {
981 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
985 SDEBUG(" target: %04X\n", target);
986 *ptr = ctx->start + target;
991 printk(KERN_INFO "Bad case.\n");
997 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
999 uint8_t attr = U8((*ptr)++);
1002 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1004 src = atom_get_src(ctx, attr, ptr);
1005 ctx->ctx->cs_equal = ((dst & src) == 0);
1006 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1009 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1011 uint8_t attr = U8((*ptr)++);
1012 uint32_t dst, src, saved;
1015 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1017 src = atom_get_src(ctx, attr, ptr);
1020 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1023 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1025 uint8_t val = U8((*ptr)++);
1026 SDEBUG("DEBUG output: 0x%02X\n", val);
1030 void (*func) (atom_exec_context *, int *, int);
1032 } opcode_table[ATOM_OP_CNT] = {
1035 atom_op_move, ATOM_ARG_REG}, {
1036 atom_op_move, ATOM_ARG_PS}, {
1037 atom_op_move, ATOM_ARG_WS}, {
1038 atom_op_move, ATOM_ARG_FB}, {
1039 atom_op_move, ATOM_ARG_PLL}, {
1040 atom_op_move, ATOM_ARG_MC}, {
1041 atom_op_and, ATOM_ARG_REG}, {
1042 atom_op_and, ATOM_ARG_PS}, {
1043 atom_op_and, ATOM_ARG_WS}, {
1044 atom_op_and, ATOM_ARG_FB}, {
1045 atom_op_and, ATOM_ARG_PLL}, {
1046 atom_op_and, ATOM_ARG_MC}, {
1047 atom_op_or, ATOM_ARG_REG}, {
1048 atom_op_or, ATOM_ARG_PS}, {
1049 atom_op_or, ATOM_ARG_WS}, {
1050 atom_op_or, ATOM_ARG_FB}, {
1051 atom_op_or, ATOM_ARG_PLL}, {
1052 atom_op_or, ATOM_ARG_MC}, {
1053 atom_op_shift_left, ATOM_ARG_REG}, {
1054 atom_op_shift_left, ATOM_ARG_PS}, {
1055 atom_op_shift_left, ATOM_ARG_WS}, {
1056 atom_op_shift_left, ATOM_ARG_FB}, {
1057 atom_op_shift_left, ATOM_ARG_PLL}, {
1058 atom_op_shift_left, ATOM_ARG_MC}, {
1059 atom_op_shift_right, ATOM_ARG_REG}, {
1060 atom_op_shift_right, ATOM_ARG_PS}, {
1061 atom_op_shift_right, ATOM_ARG_WS}, {
1062 atom_op_shift_right, ATOM_ARG_FB}, {
1063 atom_op_shift_right, ATOM_ARG_PLL}, {
1064 atom_op_shift_right, ATOM_ARG_MC}, {
1065 atom_op_mul, ATOM_ARG_REG}, {
1066 atom_op_mul, ATOM_ARG_PS}, {
1067 atom_op_mul, ATOM_ARG_WS}, {
1068 atom_op_mul, ATOM_ARG_FB}, {
1069 atom_op_mul, ATOM_ARG_PLL}, {
1070 atom_op_mul, ATOM_ARG_MC}, {
1071 atom_op_div, ATOM_ARG_REG}, {
1072 atom_op_div, ATOM_ARG_PS}, {
1073 atom_op_div, ATOM_ARG_WS}, {
1074 atom_op_div, ATOM_ARG_FB}, {
1075 atom_op_div, ATOM_ARG_PLL}, {
1076 atom_op_div, ATOM_ARG_MC}, {
1077 atom_op_add, ATOM_ARG_REG}, {
1078 atom_op_add, ATOM_ARG_PS}, {
1079 atom_op_add, ATOM_ARG_WS}, {
1080 atom_op_add, ATOM_ARG_FB}, {
1081 atom_op_add, ATOM_ARG_PLL}, {
1082 atom_op_add, ATOM_ARG_MC}, {
1083 atom_op_sub, ATOM_ARG_REG}, {
1084 atom_op_sub, ATOM_ARG_PS}, {
1085 atom_op_sub, ATOM_ARG_WS}, {
1086 atom_op_sub, ATOM_ARG_FB}, {
1087 atom_op_sub, ATOM_ARG_PLL}, {
1088 atom_op_sub, ATOM_ARG_MC}, {
1089 atom_op_setport, ATOM_PORT_ATI}, {
1090 atom_op_setport, ATOM_PORT_PCI}, {
1091 atom_op_setport, ATOM_PORT_SYSIO}, {
1092 atom_op_setregblock, 0}, {
1093 atom_op_setfbbase, 0}, {
1094 atom_op_compare, ATOM_ARG_REG}, {
1095 atom_op_compare, ATOM_ARG_PS}, {
1096 atom_op_compare, ATOM_ARG_WS}, {
1097 atom_op_compare, ATOM_ARG_FB}, {
1098 atom_op_compare, ATOM_ARG_PLL}, {
1099 atom_op_compare, ATOM_ARG_MC}, {
1100 atom_op_switch, 0}, {
1101 atom_op_jump, ATOM_COND_ALWAYS}, {
1102 atom_op_jump, ATOM_COND_EQUAL}, {
1103 atom_op_jump, ATOM_COND_BELOW}, {
1104 atom_op_jump, ATOM_COND_ABOVE}, {
1105 atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
1106 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
1107 atom_op_jump, ATOM_COND_NOTEQUAL}, {
1108 atom_op_test, ATOM_ARG_REG}, {
1109 atom_op_test, ATOM_ARG_PS}, {
1110 atom_op_test, ATOM_ARG_WS}, {
1111 atom_op_test, ATOM_ARG_FB}, {
1112 atom_op_test, ATOM_ARG_PLL}, {
1113 atom_op_test, ATOM_ARG_MC}, {
1114 atom_op_delay, ATOM_UNIT_MILLISEC}, {
1115 atom_op_delay, ATOM_UNIT_MICROSEC}, {
1116 atom_op_calltable, 0}, {
1117 atom_op_repeat, 0}, {
1118 atom_op_clear, ATOM_ARG_REG}, {
1119 atom_op_clear, ATOM_ARG_PS}, {
1120 atom_op_clear, ATOM_ARG_WS}, {
1121 atom_op_clear, ATOM_ARG_FB}, {
1122 atom_op_clear, ATOM_ARG_PLL}, {
1123 atom_op_clear, ATOM_ARG_MC}, {
1126 atom_op_mask, ATOM_ARG_REG}, {
1127 atom_op_mask, ATOM_ARG_PS}, {
1128 atom_op_mask, ATOM_ARG_WS}, {
1129 atom_op_mask, ATOM_ARG_FB}, {
1130 atom_op_mask, ATOM_ARG_PLL}, {
1131 atom_op_mask, ATOM_ARG_MC}, {
1132 atom_op_postcard, 0}, {
1134 atom_op_savereg, 0}, {
1135 atom_op_restorereg, 0}, {
1136 atom_op_setdatablock, 0}, {
1137 atom_op_xor, ATOM_ARG_REG}, {
1138 atom_op_xor, ATOM_ARG_PS}, {
1139 atom_op_xor, ATOM_ARG_WS}, {
1140 atom_op_xor, ATOM_ARG_FB}, {
1141 atom_op_xor, ATOM_ARG_PLL}, {
1142 atom_op_xor, ATOM_ARG_MC}, {
1143 atom_op_shl, ATOM_ARG_REG}, {
1144 atom_op_shl, ATOM_ARG_PS}, {
1145 atom_op_shl, ATOM_ARG_WS}, {
1146 atom_op_shl, ATOM_ARG_FB}, {
1147 atom_op_shl, ATOM_ARG_PLL}, {
1148 atom_op_shl, ATOM_ARG_MC}, {
1149 atom_op_shr, ATOM_ARG_REG}, {
1150 atom_op_shr, ATOM_ARG_PS}, {
1151 atom_op_shr, ATOM_ARG_WS}, {
1152 atom_op_shr, ATOM_ARG_FB}, {
1153 atom_op_shr, ATOM_ARG_PLL}, {
1154 atom_op_shr, ATOM_ARG_MC}, {
1155 atom_op_debug, 0},};
1157 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
1159 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1160 int len, ws, ps, ptr;
1162 atom_exec_context ectx;
1168 len = CU16(base + ATOM_CT_SIZE_PTR);
1169 ws = CU8(base + ATOM_CT_WS_PTR);
1170 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1171 ptr = base + ATOM_CT_CODE_PTR;
1173 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1176 ectx.ps_shift = ps / 4;
1182 ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
1189 if (op < ATOM_OP_NAMES_CNT)
1190 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1192 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1194 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1195 base, len, ws, ps, ptr - 1);
1200 if (op < ATOM_OP_CNT && op > 0)
1201 opcode_table[op].func(&ectx, &ptr,
1202 opcode_table[op].arg);
1206 if (op == ATOM_OP_EOT)
1218 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1222 mutex_lock(&ctx->mutex);
1223 /* reset data block */
1224 ctx->data_block = 0;
1225 /* reset reg block */
1227 /* reset fb window */
1230 ctx->io_mode = ATOM_IO_MM;
1234 r = amdgpu_atom_execute_table_locked(ctx, index, params);
1235 mutex_unlock(&ctx->mutex);
1239 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1241 static void atom_index_iio(struct atom_context *ctx, int base)
1243 ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1246 while (CU8(base) == ATOM_IIO_START) {
1247 ctx->iio[CU8(base + 1)] = base + 2;
1249 while (CU8(base) != ATOM_IIO_END)
1250 base += atom_iio_len[CU8(base)];
1255 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
1258 struct atom_context *ctx =
1259 kzalloc(sizeof(struct atom_context), GFP_KERNEL);
1270 if (CU16(0) != ATOM_BIOS_MAGIC) {
1271 printk(KERN_INFO "Invalid BIOS magic.\n");
1276 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
1277 strlen(ATOM_ATI_MAGIC))) {
1278 printk(KERN_INFO "Invalid ATI magic.\n");
1283 base = CU16(ATOM_ROM_TABLE_PTR);
1285 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1286 strlen(ATOM_ROM_MAGIC))) {
1287 printk(KERN_INFO "Invalid ATOM magic.\n");
1292 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1293 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1294 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1296 amdgpu_atom_destroy(ctx);
1300 str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
1301 while (*str && ((*str == '\n') || (*str == '\r')))
1303 /* name string isn't always 0 terminated */
1304 for (i = 0; i < 511; i++) {
1306 if (name[i] < '.' || name[i] > 'z') {
1311 printk(KERN_INFO "ATOM BIOS: %s\n", name);
1316 int amdgpu_atom_asic_init(struct atom_context *ctx)
1318 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1324 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
1325 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
1326 if (!ps[0] || !ps[1])
1329 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1331 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
1340 void amdgpu_atom_destroy(struct atom_context *ctx)
1346 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1347 uint16_t * size, uint8_t * frev, uint8_t * crev,
1348 uint16_t * data_start)
1350 int offset = index * 2 + 4;
1351 int idx = CU16(ctx->data_table + offset);
1352 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1360 *frev = CU8(idx + 2);
1362 *crev = CU8(idx + 3);
1367 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
1370 int offset = index * 2 + 4;
1371 int idx = CU16(ctx->cmd_table + offset);
1372 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
1378 *frev = CU8(idx + 2);
1380 *crev = CU8(idx + 3);
1384 int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx)
1386 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1387 uint16_t data_offset;
1388 int usage_bytes = 0;
1389 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1391 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1392 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1394 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1395 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1396 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1398 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1400 ctx->scratch_size_bytes = 0;
1401 if (usage_bytes == 0)
1402 usage_bytes = 20 * 1024;
1403 /* allocate some scratch memory */
1404 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1407 ctx->scratch_size_bytes = usage_bytes;