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23 #ifndef AMDGV_SRIOV_MSG__H_
24 #define AMDGV_SRIOV_MSG__H_
26 /* unit in kilobytes */
27 #define AMD_SRIOV_MSG_VBIOS_OFFSET 0
28 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
29 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
30 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
35 * | VBIOS | PF2VF | VF2PF | Bad Page | ...
36 * | 64KB | 1KB | 1KB |
38 #define AMD_SRIOV_MSG_SIZE_KB 1
39 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
40 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
41 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
45 * v1 defined in amdgim
49 * v1 defined in amdgim
50 * v2 defined in amdgim
53 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
54 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
56 #define AMD_SRIOV_MSG_RESERVE_UCODE 24
58 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
60 enum amd_sriov_ucode_engine_id {
61 AMD_SRIOV_UCODE_ID_VCE = 0,
62 AMD_SRIOV_UCODE_ID_UVD,
63 AMD_SRIOV_UCODE_ID_MC,
64 AMD_SRIOV_UCODE_ID_ME,
65 AMD_SRIOV_UCODE_ID_PFP,
66 AMD_SRIOV_UCODE_ID_CE,
67 AMD_SRIOV_UCODE_ID_RLC,
68 AMD_SRIOV_UCODE_ID_RLC_SRLC,
69 AMD_SRIOV_UCODE_ID_RLC_SRLG,
70 AMD_SRIOV_UCODE_ID_RLC_SRLS,
71 AMD_SRIOV_UCODE_ID_MEC,
72 AMD_SRIOV_UCODE_ID_MEC2,
73 AMD_SRIOV_UCODE_ID_SOS,
74 AMD_SRIOV_UCODE_ID_ASD,
75 AMD_SRIOV_UCODE_ID_TA_RAS,
76 AMD_SRIOV_UCODE_ID_TA_XGMI,
77 AMD_SRIOV_UCODE_ID_SMC,
78 AMD_SRIOV_UCODE_ID_SDMA,
79 AMD_SRIOV_UCODE_ID_SDMA2,
80 AMD_SRIOV_UCODE_ID_VCN,
81 AMD_SRIOV_UCODE_ID_DMCU,
82 AMD_SRIOV_UCODE_ID__MAX
85 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
87 union amd_sriov_msg_feature_flags {
89 uint32_t error_log_collect : 1;
90 uint32_t host_load_ucodes : 1;
91 uint32_t host_flr_vramlost : 1;
92 uint32_t mm_bw_management : 1;
93 uint32_t pp_one_vf_mode : 1;
94 uint32_t reg_indirect_acc : 1;
95 uint32_t reserved : 26;
100 union amd_sriov_reg_access_flags {
102 uint32_t vf_reg_access_ih : 1;
103 uint32_t vf_reg_access_mmhub : 1;
104 uint32_t vf_reg_access_gc : 1;
105 uint32_t reserved : 29;
110 union amd_sriov_msg_os_info {
112 uint32_t windows : 1;
113 uint32_t reserved : 31;
118 struct amd_sriov_msg_uuid_info {
129 uint32_t time_mid : 16;
130 uint32_t time_high : 12;
131 uint32_t version : 4;
136 uint8_t clk_seq_hi : 6;
149 struct amd_sriov_msg_pf2vf_info_header {
150 /* the total structure size in byte */
152 /* version of this structure, written by the HOST */
155 uint32_t reserved[2];
158 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48)
159 struct amd_sriov_msg_pf2vf_info {
160 /* header contains size and version */
161 struct amd_sriov_msg_pf2vf_info_header header;
162 /* use private key from mailbox 2 to create checksum */
164 /* The features flags of the HOST driver supports */
165 union amd_sriov_msg_feature_flags feature_flags;
166 /* (max_width * max_height * fps) / (16 * 16) */
167 uint32_t hevc_enc_max_mb_per_second;
168 /* (max_width * max_height) / (16 * 16) */
169 uint32_t hevc_enc_max_mb_per_frame;
170 /* (max_width * max_height * fps) / (16 * 16) */
171 uint32_t avc_enc_max_mb_per_second;
172 /* (max_width * max_height) / (16 * 16) */
173 uint32_t avc_enc_max_mb_per_frame;
174 /* MEC FW position in BYTE from the start of VF visible frame buffer */
175 uint64_t mecfw_offset;
176 /* MEC FW size in BYTE */
178 /* UVD FW position in BYTE from the start of VF visible frame buffer */
179 uint64_t uvdfw_offset;
180 /* UVD FW size in BYTE */
182 /* VCE FW position in BYTE from the start of VF visible frame buffer */
183 uint64_t vcefw_offset;
184 /* VCE FW size in BYTE */
186 /* Bad pages block position in BYTE */
187 uint32_t bp_block_offset_low;
188 uint32_t bp_block_offset_high;
189 /* Bad pages block size in BYTE */
190 uint32_t bp_block_size;
191 /* frequency for VF to update the VF2PF area in msec, 0 = manual */
192 uint32_t vf2pf_update_interval_ms;
193 /* identification in ROCm SMI */
196 /* flags to indicate which register access method VF should use */
197 union amd_sriov_reg_access_flags reg_access_flags;
198 /* MM BW management */
200 uint32_t decode_max_dimension_pixels;
201 uint32_t decode_max_frame_pixels;
202 uint32_t encode_max_dimension_pixels;
203 uint32_t encode_max_frame_pixels;
204 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
206 struct amd_sriov_msg_uuid_info uuid_info;
207 /* PCIE atomic ops support flag */
208 uint32_t pcie_atomic_ops_support_flags;
210 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
213 struct amd_sriov_msg_vf2pf_info_header {
214 /* the total structure size in byte */
216 /* version of this structure, written by the guest */
219 uint32_t reserved[2];
222 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70)
223 struct amd_sriov_msg_vf2pf_info {
224 /* header contains size and version */
225 struct amd_sriov_msg_vf2pf_info_header header;
228 uint8_t driver_version[64];
229 /* driver certification, 1=WHQL, 0=None */
230 uint32_t driver_cert;
231 /* guest OS type and version */
232 union amd_sriov_msg_os_info os_info;
233 /* guest fb information in the unit of MB */
235 /* guest gfx engine usage percentage */
237 /* guest gfx engine health percentage */
239 /* guest compute engine usage percentage */
240 uint32_t compute_usage;
241 /* guest compute engine health percentage */
242 uint32_t compute_health;
243 /* guest avc engine usage percentage. 0xffff means N/A */
244 uint32_t avc_enc_usage;
245 /* guest avc engine health percentage. 0xffff means N/A */
246 uint32_t avc_enc_health;
247 /* guest hevc engine usage percentage. 0xffff means N/A */
248 uint32_t hevc_enc_usage;
249 /* guest hevc engine usage percentage. 0xffff means N/A */
250 uint32_t hevc_enc_health;
251 /* combined encode/decode usage */
252 uint32_t encode_usage;
253 uint32_t decode_usage;
254 /* Version of PF2VF that VF understands */
255 uint32_t pf2vf_version_required;
256 /* additional FB usage */
257 uint32_t fb_vis_usage;
258 uint32_t fb_vis_size;
260 /* guest ucode data, each one is 1.25 Dword */
264 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
265 uint64_t dummy_page_addr;
268 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
271 /* mailbox message send from guest to host */
272 enum amd_sriov_mailbox_request_message {
273 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
274 MB_REQ_MSG_REL_GPU_INIT_ACCESS,
275 MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
276 MB_REQ_MSG_REL_GPU_FINI_ACCESS,
277 MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
278 MB_REQ_MSG_REQ_GPU_INIT_DATA,
280 MB_REQ_MSG_LOG_VF_ERROR = 200,
283 /* mailbox message send from host to guest */
284 enum amd_sriov_mailbox_response_message {
285 MB_RES_MSG_CLR_MSG_BUF = 0,
286 MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
287 MB_RES_MSG_FLR_NOTIFICATION,
288 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
291 MB_RES_MSG_QUERY_ALIVE,
292 MB_RES_MSG_GPU_INIT_DATA_READY,
294 MB_RES_MSG_TEXT_MESSAGE = 255
297 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
298 enum amd_sriov_gpu_init_data_version {
299 GPU_INIT_DATA_READY_V1 = 1,
302 #pragma pack(pop) // Restore previous packing option
304 /* checksum function between host and guest */
305 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
306 unsigned int checksum);
308 /* assertion at compile time */
310 #define stringification(s) _stringification(s)
311 #define _stringification(s) #s
314 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
315 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
318 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
319 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
321 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
322 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
324 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
325 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
327 #undef _stringification
328 #undef stringification
331 #endif /* AMDGV_SRIOV_MSG__H_ */