drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_xgmi.h"
  27 #include "amdgpu_smu.h"
  28 #include "amdgpu_ras.h"
  29 #include "soc15.h"
  30 #include "df/df_3_6_offset.h"
  31 #include "xgmi/xgmi_4_0_0_smn.h"
  32 #include "xgmi/xgmi_4_0_0_sh_mask.h"
  33 #include "wafl/wafl2_4_0_0_smn.h"
  34 #include "wafl/wafl2_4_0_0_sh_mask.h"
  35
  36 static DEFINE_MUTEX(xgmi_mutex);
  37
  38 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE         4
  39
  40 static LIST_HEAD(xgmi_hive_list);
  41
  42 static const int xgmi_pcs_err_status_reg_vg20[] = {
  43         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  44         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  45 };
  46
  47 static const int wafl_pcs_err_status_reg_vg20[] = {
  48         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  49         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  50 };
  51
  52 static const int xgmi_pcs_err_status_reg_arct[] = {
  53         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  54         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  55         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
  56         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
  57         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
  58         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
  59 };
  60
  61 /* same as vg20*/
  62 static const int wafl_pcs_err_status_reg_arct[] = {
  63         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  64         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  65 };
  66
  67 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
  68         {"XGMI PCS DataLossErr",
  69          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
  70         {"XGMI PCS TrainingErr",
  71          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
  72         {"XGMI PCS CRCErr",
  73          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
  74         {"XGMI PCS BERExceededErr",
  75          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
  76         {"XGMI PCS TxMetaDataErr",
  77          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
  78         {"XGMI PCS ReplayBufParityErr",
  79          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
  80         {"XGMI PCS DataParityErr",
  81          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
  82         {"XGMI PCS ReplayFifoOverflowErr",
  83          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
  84         {"XGMI PCS ReplayFifoUnderflowErr",
  85          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
  86         {"XGMI PCS ElasticFifoOverflowErr",
  87          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
  88         {"XGMI PCS DeskewErr",
  89          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
  90         {"XGMI PCS DataStartupLimitErr",
  91          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
  92         {"XGMI PCS FCInitTimeoutErr",
  93          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
  94         {"XGMI PCS RecoveryTimeoutErr",
  95          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
  96         {"XGMI PCS ReadySerialTimeoutErr",
  97          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
  98         {"XGMI PCS ReadySerialAttemptErr",
  99          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 100         {"XGMI PCS RecoveryAttemptErr",
 101          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 102         {"XGMI PCS RecoveryRelockAttemptErr",
 103          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 104 };
 105
 106 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
 107         {"WAFL PCS DataLossErr",
 108          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
 109         {"WAFL PCS TrainingErr",
 110          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
 111         {"WAFL PCS CRCErr",
 112          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
 113         {"WAFL PCS BERExceededErr",
 114          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
 115         {"WAFL PCS TxMetaDataErr",
 116          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
 117         {"WAFL PCS ReplayBufParityErr",
 118          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
 119         {"WAFL PCS DataParityErr",
 120          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
 121         {"WAFL PCS ReplayFifoOverflowErr",
 122          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 123         {"WAFL PCS ReplayFifoUnderflowErr",
 124          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 125         {"WAFL PCS ElasticFifoOverflowErr",
 126          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 127         {"WAFL PCS DeskewErr",
 128          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
 129         {"WAFL PCS DataStartupLimitErr",
 130          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
 131         {"WAFL PCS FCInitTimeoutErr",
 132          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 133         {"WAFL PCS RecoveryTimeoutErr",
 134          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 135         {"WAFL PCS ReadySerialTimeoutErr",
 136          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 137         {"WAFL PCS ReadySerialAttemptErr",
 138          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 139         {"WAFL PCS RecoveryAttemptErr",
 140          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 141         {"WAFL PCS RecoveryRelockAttemptErr",
 142          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 143 };
 144
 145 /**
 146  * DOC: AMDGPU XGMI Support
 147  *
 148  * XGMI is a high speed interconnect that joins multiple GPU cards
 149  * into a homogeneous memory space that is organized by a collective
 150  * hive ID and individual node IDs, both of which are 64-bit numbers.
 151  *
 152  * The file xgmi_device_id contains the unique per GPU device ID and
 153  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
 154  *
 155  * Inside the device directory a sub-directory 'xgmi_hive_info' is
 156  * created which contains the hive ID and the list of nodes.
 157  *
 158  * The hive ID is stored in:
 159  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
 160  *
 161  * The node information is stored in numbered directories:
 162  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
 163  *
 164  * Each device has their own xgmi_hive_info direction with a mirror
 165  * set of node sub-directories.
 166  *
 167  * The XGMI memory space is built by contiguously adding the power of
 168  * two padded VRAM space from each node to each other.
 169  *
 170  */
 171
 172 static struct attribute amdgpu_xgmi_hive_id = {
 173         .name = "xgmi_hive_id",
 174         .mode = S_IRUGO
 175 };
 176
 177 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
 178         &amdgpu_xgmi_hive_id,
 179         NULL
 180 };
 181
 182 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
 183         struct attribute *attr, char *buf)
 184 {
 185         struct amdgpu_hive_info *hive = container_of(
 186                 kobj, struct amdgpu_hive_info, kobj);
 187
 188         if (attr == &amdgpu_xgmi_hive_id)
 189                 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
 190
 191         return 0;
 192 }
 193
 194 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
 195 {
 196         struct amdgpu_hive_info *hive = container_of(
 197                 kobj, struct amdgpu_hive_info, kobj);
 198
 199         mutex_destroy(&hive->hive_lock);
 200         kfree(hive);
 201 }
 202
 203 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
 204         .show = amdgpu_xgmi_show_attrs,
 205 };
 206
 207 struct kobj_type amdgpu_xgmi_hive_type = {
 208         .release = amdgpu_xgmi_hive_release,
 209         .sysfs_ops = &amdgpu_xgmi_hive_ops,
 210         .default_attrs = amdgpu_xgmi_hive_attrs,
 211 };
 212
 213 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
 214                                      struct device_attribute *attr,
 215                                      char *buf)
 216 {
 217         struct drm_device *ddev = dev_get_drvdata(dev);
 218         struct amdgpu_device *adev = drm_to_adev(ddev);
 219
 220         return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id);
 221
 222 }
 223
 224 #define AMDGPU_XGMI_SET_FICAA(o)        ((o) | 0x456801)
 225 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
 226                                       struct device_attribute *attr,
 227                                       char *buf)
 228 {
 229         struct drm_device *ddev = dev_get_drvdata(dev);
 230         struct amdgpu_device *adev = drm_to_adev(ddev);
 231         uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
 232         uint64_t fica_out;
 233         unsigned int error_count = 0;
 234
 235         ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
 236         ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 237
 238         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
 239         if (fica_out != 0x1f)
 240                 pr_err("xGMI error counters not enabled!\n");
 241
 242         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
 243
 244         if ((fica_out & 0xffff) == 2)
 245                 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 246
 247         adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
 248
 249         return snprintf(buf, PAGE_SIZE, "%u\n", error_count);
 250 }
 251
 252
 253 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
 254 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
 255
 256 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
 257                                          struct amdgpu_hive_info *hive)
 258 {
 259         int ret = 0;
 260         char node[10] = { 0 };
 261
 262         /* Create xgmi device id file */
 263         ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
 264         if (ret) {
 265                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
 266                 return ret;
 267         }
 268
 269         /* Create xgmi error file */
 270         ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
 271         if (ret)
 272                 pr_err("failed to create xgmi_error\n");
 273
 274
 275         /* Create sysfs link to hive info folder on the first device */
 276         if (hive->kobj.parent != (&adev->dev->kobj)) {
 277                 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
 278                                         "xgmi_hive_info");
 279                 if (ret) {
 280                         dev_err(adev->dev, "XGMI: Failed to create link to hive info");
 281                         goto remove_file;
 282                 }
 283         }
 284
 285         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 286         /* Create sysfs link form the hive folder to yourself */
 287         ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
 288         if (ret) {
 289                 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
 290                 goto remove_link;
 291         }
 292
 293         goto success;
 294
 295
 296 remove_link:
 297         sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
 298
 299 remove_file:
 300         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 301
 302 success:
 303         return ret;
 304 }
 305
 306 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
 307                                           struct amdgpu_hive_info *hive)
 308 {
 309         char node[10];
 310         memset(node, 0, sizeof(node));
 311
 312         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 313         device_remove_file(adev->dev, &dev_attr_xgmi_error);
 314
 315         if (hive->kobj.parent != (&adev->dev->kobj))
 316                 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
 317
 318         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 319         sysfs_remove_link(&hive->kobj, node);
 320
 321 }
 322
 323
 324
 325 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
 326 {
 327         struct amdgpu_hive_info *hive = NULL;
 328         int ret;
 329
 330         if (!adev->gmc.xgmi.hive_id)
 331                 return NULL;
 332
 333         if (adev->hive) {
 334                 kobject_get(&adev->hive->kobj);
 335                 return adev->hive;
 336         }
 337
 338         mutex_lock(&xgmi_mutex);
 339
 340         list_for_each_entry(hive, &xgmi_hive_list, node)  {
 341                 if (hive->hive_id == adev->gmc.xgmi.hive_id)
 342                         goto pro_end;
 343         }
 344
 345         hive = kzalloc(sizeof(*hive), GFP_KERNEL);
 346         if (!hive) {
 347                 dev_err(adev->dev, "XGMI: allocation failed\n");
 348                 hive = NULL;
 349                 goto pro_end;
 350         }
 351
 352         /* initialize new hive if not exist */
 353         ret = kobject_init_and_add(&hive->kobj,
 354                         &amdgpu_xgmi_hive_type,
 355                         &adev->dev->kobj,
 356                         "%s", "xgmi_hive_info");
 357         if (ret) {
 358                 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
 359                 kfree(hive);
 360                 hive = NULL;
 361                 goto pro_end;
 362         }
 363
 364         hive->hive_id = adev->gmc.xgmi.hive_id;
 365         INIT_LIST_HEAD(&hive->device_list);
 366         INIT_LIST_HEAD(&hive->node);
 367         mutex_init(&hive->hive_lock);
 368         atomic_set(&hive->in_reset, 0);
 369         atomic_set(&hive->number_devices, 0);
 370         task_barrier_init(&hive->tb);
 371         hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
 372         hive->hi_req_gpu = NULL;
 373         /*
 374          * hive pstate on boot is high in vega20 so we have to go to low
 375          * pstate on after boot.
 376          */
 377         hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
 378         list_add_tail(&hive->node, &xgmi_hive_list);
 379
 380 pro_end:
 381         if (hive)
 382                 kobject_get(&hive->kobj);
 383         mutex_unlock(&xgmi_mutex);
 384         return hive;
 385 }
 386
 387 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
 388 {
 389         if (hive)
 390                 kobject_put(&hive->kobj);
 391 }
 392
 393 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
 394 {
 395         int ret = 0;
 396         struct amdgpu_hive_info *hive;
 397         struct amdgpu_device *request_adev;
 398         bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
 399         bool init_low;
 400
 401         hive = amdgpu_get_xgmi_hive(adev);
 402         if (!hive)
 403                 return 0;
 404
 405         request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
 406         init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
 407         amdgpu_put_xgmi_hive(hive);
 408         /* fw bug so temporarily disable pstate switching */
 409         return 0;
 410
 411         if (!hive || adev->asic_type != CHIP_VEGA20)
 412                 return 0;
 413
 414         mutex_lock(&hive->hive_lock);
 415
 416         if (is_hi_req)
 417                 hive->hi_req_count++;
 418         else
 419                 hive->hi_req_count--;
 420
 421         /*
 422          * Vega20 only needs single peer to request pstate high for the hive to
 423          * go high but all peers must request pstate low for the hive to go low
 424          */
 425         if (hive->pstate == pstate ||
 426                         (!is_hi_req && hive->hi_req_count && !init_low))
 427                 goto out;
 428
 429         dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
 430
 431         ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
 432         if (ret) {
 433                 dev_err(request_adev->dev,
 434                         "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
 435                         request_adev->gmc.xgmi.node_id,
 436                         request_adev->gmc.xgmi.hive_id, ret);
 437                 goto out;
 438         }
 439
 440         if (init_low)
 441                 hive->pstate = hive->hi_req_count ?
 442                                         hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
 443         else {
 444                 hive->pstate = pstate;
 445                 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
 446                                                         adev : NULL;
 447         }
 448 out:
 449         mutex_unlock(&hive->hive_lock);
 450         return ret;
 451 }
 452
 453 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
 454 {
 455         int ret;
 456
 457         /* Each psp need to set the latest topology */
 458         ret = psp_xgmi_set_topology_info(&adev->psp,
 459                                          atomic_read(&hive->number_devices),
 460                                          &adev->psp.xgmi_context.top_info);
 461         if (ret)
 462                 dev_err(adev->dev,
 463                         "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
 464                         adev->gmc.xgmi.node_id,
 465                         adev->gmc.xgmi.hive_id, ret);
 466
 467         return ret;
 468 }
 469
 470
 471 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
 472                 struct amdgpu_device *peer_adev)
 473 {
 474         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 475         int i;
 476
 477         for (i = 0 ; i < top->num_nodes; ++i)
 478                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 479                         return top->nodes[i].num_hops;
 480         return  -EINVAL;
 481 }
 482
 483 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 484 {
 485         struct psp_xgmi_topology_info *top_info;
 486         struct amdgpu_hive_info *hive;
 487         struct amdgpu_xgmi      *entry;
 488         struct amdgpu_device *tmp_adev = NULL;
 489
 490         int count = 0, ret = 0;
 491
 492         if (!adev->gmc.xgmi.supported)
 493                 return 0;
 494
 495         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 496                 ret = psp_xgmi_initialize(&adev->psp);
 497                 if (ret) {
 498                         dev_err(adev->dev,
 499                                 "XGMI: Failed to initialize xgmi session\n");
 500                         return ret;
 501                 }
 502
 503                 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
 504                 if (ret) {
 505                         dev_err(adev->dev,
 506                                 "XGMI: Failed to get hive id\n");
 507                         return ret;
 508                 }
 509
 510                 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
 511                 if (ret) {
 512                         dev_err(adev->dev,
 513                                 "XGMI: Failed to get node id\n");
 514                         return ret;
 515                 }
 516         } else {
 517                 adev->gmc.xgmi.hive_id = 16;
 518                 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
 519         }
 520
 521         hive = amdgpu_get_xgmi_hive(adev);
 522         if (!hive) {
 523                 ret = -EINVAL;
 524                 dev_err(adev->dev,
 525                         "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
 526                         adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
 527                 goto exit;
 528         }
 529         mutex_lock(&hive->hive_lock);
 530
 531         top_info = &adev->psp.xgmi_context.top_info;
 532
 533         list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
 534         list_for_each_entry(entry, &hive->device_list, head)
 535                 top_info->nodes[count++].node_id = entry->node_id;
 536         top_info->num_nodes = count;
 537         atomic_set(&hive->number_devices, count);
 538
 539         task_barrier_add_task(&hive->tb);
 540
 541         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 542                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 543                         /* update node list for other device in the hive */
 544                         if (tmp_adev != adev) {
 545                                 top_info = &tmp_adev->psp.xgmi_context.top_info;
 546                                 top_info->nodes[count - 1].node_id =
 547                                         adev->gmc.xgmi.node_id;
 548                                 top_info->num_nodes = count;
 549                         }
 550                         ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
 551                         if (ret)
 552                                 goto exit_unlock;
 553                 }
 554
 555                 /* get latest topology info for each device from psp */
 556                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 557                         ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 558                                         &tmp_adev->psp.xgmi_context.top_info);
 559                         if (ret) {
 560                                 dev_err(tmp_adev->dev,
 561                                         "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
 562                                         tmp_adev->gmc.xgmi.node_id,
 563                                         tmp_adev->gmc.xgmi.hive_id, ret);
 564                                 /* To do : continue with some node failed or disable the whole hive */
 565                                 goto exit_unlock;
 566                         }
 567                 }
 568         }
 569
 570         if (!ret)
 571                 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
 572
 573 exit_unlock:
 574         mutex_unlock(&hive->hive_lock);
 575 exit:
 576         if (!ret) {
 577                 adev->hive = hive;
 578                 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
 579                          adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
 580         } else {
 581                 amdgpu_put_xgmi_hive(hive);
 582                 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
 583                         adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
 584                         ret);
 585         }
 586
 587         return ret;
 588 }
 589
 590 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
 591 {
 592         struct amdgpu_hive_info *hive = adev->hive;
 593
 594         if (!adev->gmc.xgmi.supported)
 595                 return -EINVAL;
 596
 597         if (!hive)
 598                 return -EINVAL;
 599
 600         mutex_lock(&hive->hive_lock);
 601         task_barrier_rem_task(&hive->tb);
 602         amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
 603         if (hive->hi_req_gpu == adev)
 604                 hive->hi_req_gpu = NULL;
 605         list_del(&adev->gmc.xgmi.head);
 606         mutex_unlock(&hive->hive_lock);
 607
 608         amdgpu_put_xgmi_hive(hive);
 609         adev->hive = NULL;
 610
 611         if (atomic_dec_return(&hive->number_devices) == 0) {
 612                 /* Remove the hive from global hive list */
 613                 mutex_lock(&xgmi_mutex);
 614                 list_del(&hive->node);
 615                 mutex_unlock(&xgmi_mutex);
 616
 617                 amdgpu_put_xgmi_hive(hive);
 618         }
 619
 620         return psp_xgmi_terminate(&adev->psp);
 621 }
 622
 623 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
 624 {
 625         int r;
 626         struct ras_ih_if ih_info = {
 627                 .cb = NULL,
 628         };
 629         struct ras_fs_if fs_info = {
 630                 .sysfs_name = "xgmi_wafl_err_count",
 631         };
 632
 633         if (!adev->gmc.xgmi.supported ||
 634             adev->gmc.xgmi.num_physical_nodes == 0)
 635                 return 0;
 636
 637         amdgpu_xgmi_reset_ras_error_count(adev);
 638
 639         if (!adev->gmc.xgmi.ras_if) {
 640                 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
 641                 if (!adev->gmc.xgmi.ras_if)
 642                         return -ENOMEM;
 643                 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
 644                 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 645                 adev->gmc.xgmi.ras_if->sub_block_index = 0;
 646                 strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
 647         }
 648         ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
 649         r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
 650                                  &fs_info, &ih_info);
 651         if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
 652                 kfree(adev->gmc.xgmi.ras_if);
 653                 adev->gmc.xgmi.ras_if = NULL;
 654         }
 655
 656         return r;
 657 }
 658
 659 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
 660 {
 661         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
 662                         adev->gmc.xgmi.ras_if) {
 663                 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
 664                 struct ras_ih_if ih_info = {
 665                         .cb = NULL,
 666                 };
 667
 668                 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
 669                 kfree(ras_if);
 670         }
 671 }
 672
 673 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
 674                                            uint64_t addr)
 675 {
 676         struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
 677         return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
 678 }
 679
 680 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
 681 {
 682         WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
 683         WREG32_PCIE(pcs_status_reg, 0);
 684 }
 685
 686 void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
 687 {
 688         uint32_t i;
 689
 690         switch (adev->asic_type) {
 691         case CHIP_ARCTURUS:
 692                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
 693                         pcs_clear_status(adev,
 694                                          xgmi_pcs_err_status_reg_arct[i]);
 695                 break;
 696         case CHIP_VEGA20:
 697                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
 698                         pcs_clear_status(adev,
 699                                          xgmi_pcs_err_status_reg_vg20[i]);
 700                 break;
 701         default:
 702                 break;
 703         }
 704 }
 705
 706 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
 707                                               uint32_t value,
 708                                               uint32_t *ue_count,
 709                                               uint32_t *ce_count,
 710                                               bool is_xgmi_pcs)
 711 {
 712         int i;
 713         int ue_cnt;
 714
 715         if (is_xgmi_pcs) {
 716                 /* query xgmi pcs error status,
 717                  * only ue is supported */
 718                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
 719                         ue_cnt = (value &
 720                                   xgmi_pcs_ras_fields[i].pcs_err_mask) >>
 721                                   xgmi_pcs_ras_fields[i].pcs_err_shift;
 722                         if (ue_cnt) {
 723                                 dev_info(adev->dev, "%s detected\n",
 724                                          xgmi_pcs_ras_fields[i].err_name);
 725                                 *ue_count += ue_cnt;
 726                         }
 727                 }
 728         } else {
 729                 /* query wafl pcs error status,
 730                  * only ue is supported */
 731                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
 732                         ue_cnt = (value &
 733                                   wafl_pcs_ras_fields[i].pcs_err_mask) >>
 734                                   wafl_pcs_ras_fields[i].pcs_err_shift;
 735                         if (ue_cnt) {
 736                                 dev_info(adev->dev, "%s detected\n",
 737                                          wafl_pcs_ras_fields[i].err_name);
 738                                 *ue_count += ue_cnt;
 739                         }
 740                 }
 741         }
 742
 743         return 0;
 744 }
 745
 746 int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
 747                                       void *ras_error_status)
 748 {
 749         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 750         int i;
 751         uint32_t data;
 752         uint32_t ue_cnt = 0, ce_cnt = 0;
 753
 754         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
 755                 return -EINVAL;
 756
 757         err_data->ue_count = 0;
 758         err_data->ce_count = 0;
 759
 760         switch (adev->asic_type) {
 761         case CHIP_ARCTURUS:
 762                 /* check xgmi pcs error */
 763                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
 764                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
 765                         if (data)
 766                                 amdgpu_xgmi_query_pcs_error_status(adev,
 767                                                 data, &ue_cnt, &ce_cnt, true);
 768                 }
 769                 /* check wafl pcs error */
 770                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
 771                         data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
 772                         if (data)
 773                                 amdgpu_xgmi_query_pcs_error_status(adev,
 774                                                 data, &ue_cnt, &ce_cnt, false);
 775                 }
 776                 break;
 777         case CHIP_VEGA20:
 778         default:
 779                 /* check xgmi pcs error */
 780                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
 781                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
 782                         if (data)
 783                                 amdgpu_xgmi_query_pcs_error_status(adev,
 784                                                 data, &ue_cnt, &ce_cnt, true);
 785                 }
 786                 /* check wafl pcs error */
 787                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
 788                         data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
 789                         if (data)
 790                                 amdgpu_xgmi_query_pcs_error_status(adev,
 791                                                 data, &ue_cnt, &ce_cnt, false);
 792                 }
 793                 break;
 794         }
 795
 796         amdgpu_xgmi_reset_ras_error_count(adev);
 797
 798         err_data->ue_count += ue_cnt;
 799         err_data->ce_count += ce_cnt;
 800
 801         return 0;
 802 }