2 * Copyright 2019 Advanced Micro Devices, Inc.
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23 #include "amdgpu_vm.h"
24 #include "amdgpu_job.h"
25 #include "amdgpu_object.h"
26 #include "amdgpu_trace.h"
28 #define AMDGPU_VM_SDMA_MIN_NUM_DW 256u
29 #define AMDGPU_VM_SDMA_MAX_NUM_DW (16u * 1024u)
32 * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped
34 * @table: newly allocated or validated PD/PT
36 static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
40 r = amdgpu_ttm_alloc_gart(&table->tbo);
45 r = amdgpu_ttm_alloc_gart(&table->shadow->tbo);
51 * amdgpu_vm_sdma_prepare - prepare SDMA command submission
53 * @p: see amdgpu_vm_update_params definition
54 * @owner: owner we need to sync to
55 * @exclusive: exclusive move fence we need to sync to
58 * Negativ errno, 0 for success.
60 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
61 struct dma_resv *resv,
62 enum amdgpu_sync_mode sync_mode)
64 unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
67 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
76 return amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode, p->vm);
80 * amdgpu_vm_sdma_commit - commit SDMA command submission
82 * @p: see amdgpu_vm_update_params definition
83 * @fence: resulting fence
86 * Negativ errno, 0 for success.
88 static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
89 struct dma_fence **fence)
91 struct amdgpu_ib *ib = p->job->ibs;
92 struct drm_sched_entity *entity;
93 struct dma_fence *f, *tmp;
94 struct amdgpu_ring *ring;
97 entity = p->direct ? &p->vm->direct : &p->vm->delayed;
98 ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
100 WARN_ON(ib->length_dw == 0);
101 amdgpu_ring_pad_ib(ring, ib);
102 WARN_ON(ib->length_dw > p->num_dw_left);
103 r = amdgpu_job_submit(p->job, entity, AMDGPU_FENCE_OWNER_VM, &f);
108 tmp = dma_fence_get(f);
109 swap(p->vm->last_direct, tmp);
112 dma_resv_add_shared_fence(p->vm->root.base.bo->tbo.base.resv, f);
115 if (fence && !p->direct)
121 amdgpu_job_free(p->job);
126 * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
128 * @p: see amdgpu_vm_update_params definition
129 * @bo: PD/PT to update
130 * @pe: addr of the page entry
131 * @count: number of page entries to copy
133 * Traces the parameters and calls the DMA function to copy the PTEs.
135 static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
136 struct amdgpu_bo *bo, uint64_t pe,
139 struct amdgpu_ib *ib = p->job->ibs;
140 uint64_t src = ib->gpu_addr;
142 src += p->num_dw_left * 4;
144 pe += amdgpu_bo_gpu_offset_no_check(bo);
145 trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct);
147 amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
151 * amdgpu_vm_sdma_set_ptes - helper to call the right asic function
153 * @p: see amdgpu_vm_update_params definition
154 * @bo: PD/PT to update
155 * @pe: addr of the page entry
156 * @addr: dst addr to write into pe
157 * @count: number of page entries to update
158 * @incr: increase next addr by incr bytes
159 * @flags: hw access flags
161 * Traces the parameters and calls the right asic functions
162 * to setup the page table using the DMA.
164 static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
165 struct amdgpu_bo *bo, uint64_t pe,
166 uint64_t addr, unsigned count,
167 uint32_t incr, uint64_t flags)
169 struct amdgpu_ib *ib = p->job->ibs;
171 pe += amdgpu_bo_gpu_offset_no_check(bo);
172 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
174 amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
177 amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,
183 * amdgpu_vm_sdma_update - execute VM update
185 * @p: see amdgpu_vm_update_params definition
186 * @bo: PD/PT to update
187 * @pe: addr of the page entry
188 * @addr: dst addr to write into pe
189 * @count: number of page entries to update
190 * @incr: increase next addr by incr bytes
191 * @flags: hw access flags
193 * Reserve space in the IB, setup mapping buffer on demand and write commands to
196 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
197 struct amdgpu_bo *bo, uint64_t pe,
198 uint64_t addr, unsigned count, uint32_t incr,
201 unsigned int i, ndw, nptes;
205 /* Wait for PD/PT moves to be completed */
206 r = amdgpu_sync_fence(&p->job->sync, bo->tbo.moving, false);
211 ndw = p->num_dw_left;
212 ndw -= p->job->ibs->length_dw;
215 r = amdgpu_vm_sdma_commit(p, NULL);
219 /* estimate how many dw we need */
223 ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW);
224 ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
226 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
230 p->num_dw_left = ndw;
233 if (!p->pages_addr) {
234 /* set page commands needed */
236 amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr,
238 amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
243 /* copy commands needed */
244 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
245 (bo->shadow ? 2 : 1);
250 nptes = min(count, ndw / 2);
252 /* Put the PTEs at the end of the IB. */
253 p->num_dw_left -= nptes * 2;
254 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]);
255 for (i = 0; i < nptes; ++i, addr += incr) {
256 pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr);
261 amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes);
262 amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
271 const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = {
272 .map_table = amdgpu_vm_sdma_map_table,
273 .prepare = amdgpu_vm_sdma_prepare,
274 .update = amdgpu_vm_sdma_update,
275 .commit = amdgpu_vm_sdma_commit