2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo_driver.h>
34 #include "amdgpu_sync.h"
35 #include "amdgpu_ring.h"
36 #include "amdgpu_ids.h"
40 struct amdgpu_bo_list_entry;
46 /* Maximum number of PTEs the hardware can write with one command */
47 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
49 /* number of entries in page table */
50 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
52 #define AMDGPU_PTE_VALID (1ULL << 0)
53 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
54 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
57 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
59 #define AMDGPU_PTE_READABLE (1ULL << 5)
60 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
62 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
64 /* TILED for VEGA10, reserved for older ASICs */
65 #define AMDGPU_PTE_PRT (1ULL << 51)
67 /* PDE is handled as PTE for VEGA10 */
68 #define AMDGPU_PDE_PTE (1ULL << 54)
70 /* PTE is handled as PDE for VEGA10 (Translate Further) */
71 #define AMDGPU_PTE_TF (1ULL << 56)
73 /* PDE Block Fragment Size for VEGA10 */
74 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
78 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
79 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
81 #define AMDGPU_MTYPE_NC 0
82 #define AMDGPU_MTYPE_CC 2
84 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
85 | AMDGPU_PTE_SNOOPED \
86 | AMDGPU_PTE_EXECUTABLE \
87 | AMDGPU_PTE_READABLE \
88 | AMDGPU_PTE_WRITEABLE \
89 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
91 /* How to programm VM fault handling */
92 #define AMDGPU_VM_FAULT_STOP_NEVER 0
93 #define AMDGPU_VM_FAULT_STOP_FIRST 1
94 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
96 /* max number of VMHUB */
97 #define AMDGPU_MAX_VMHUBS 2
98 #define AMDGPU_GFXHUB 0
99 #define AMDGPU_MMHUB 1
101 /* hardcode that limit for now */
102 #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
104 /* max vmids dedicated for process */
105 #define AMDGPU_VM_MAX_RESERVED_VMID 1
107 #define AMDGPU_VM_CONTEXT_GFX 0
108 #define AMDGPU_VM_CONTEXT_COMPUTE 1
110 /* See vm_update_mode */
111 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
112 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
114 /* VMPT level enumerate, and the hiberachy is:
115 * PDB2->PDB1->PDB0->PTB
117 enum amdgpu_vm_level {
124 /* base structure for tracking BO usage in a VM */
125 struct amdgpu_vm_bo_base {
126 /* constant after initialization */
127 struct amdgpu_vm *vm;
128 struct amdgpu_bo *bo;
130 /* protected by bo being reserved */
131 struct amdgpu_vm_bo_base *next;
133 /* protected by spinlock */
134 struct list_head vm_status;
136 /* protected by the BO being reserved */
140 struct amdgpu_vm_pt {
141 struct amdgpu_vm_bo_base base;
143 /* array of page tables, one for each directory entry */
144 struct amdgpu_vm_pt *entries;
147 /* provided by hw blocks that can write ptes, e.g., sdma */
148 struct amdgpu_vm_pte_funcs {
149 /* number of dw to reserve per operation */
150 unsigned copy_pte_num_dw;
152 /* copy pte entries from GART */
153 void (*copy_pte)(struct amdgpu_ib *ib,
154 uint64_t pe, uint64_t src,
157 /* write pte one entry at a time with addr mapping */
158 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
159 uint64_t value, unsigned count,
161 /* for linear pte/pde updates without addr mapping */
162 void (*set_pte_pde)(struct amdgpu_ib *ib,
164 uint64_t addr, unsigned count,
165 uint32_t incr, uint64_t flags);
168 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
169 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
170 #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
173 struct amdgpu_task_info {
174 char process_name[TASK_COMM_LEN];
175 char task_name[TASK_COMM_LEN];
181 /* tree of virtual addresses mapped */
182 struct rb_root_cached va;
184 /* BOs who needs a validation */
185 struct list_head evicted;
187 /* PT BOs which relocated and their parent need an update */
188 struct list_head relocated;
190 /* per VM BOs moved, but not yet updated in the PT */
191 struct list_head moved;
193 /* All BOs of this VM not currently in the state machine */
194 struct list_head idle;
196 /* regular invalidated BOs, but not yet updated in the PT */
197 struct list_head invalidated;
198 spinlock_t invalidated_lock;
200 /* BO mappings freed, but not yet updated in the PT */
201 struct list_head freed;
203 /* contains the page directory */
204 struct amdgpu_vm_pt root;
205 struct dma_fence *last_update;
207 /* Scheduler entity for page table updates */
208 struct drm_sched_entity entity;
211 /* dedicated to vm */
212 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
214 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
215 bool use_cpu_for_update;
217 /* Flag to indicate ATS support from PTE for GFX9 */
218 bool pte_support_ats;
220 /* Up to 128 pending retry page faults */
221 DECLARE_KFIFO(faults, u64, 128);
223 /* Points to the KFD process VM info */
224 struct amdkfd_process_info *process_info;
226 /* List node in amdkfd_process_info.vm_list_head */
227 struct list_head vm_list_node;
229 /* Valid while the PD is reserved or fenced */
230 uint64_t pd_phys_addr;
232 /* Some basic info about the task */
233 struct amdgpu_task_info task_info;
235 /* Store positions of group of BOs */
236 struct ttm_lru_bulk_move lru_bulk_move;
237 /* mark whether can do the bulk move */
241 struct amdgpu_vm_manager {
242 /* Handling of VMIDs */
243 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
245 /* Handling of VM fences */
247 unsigned seqno[AMDGPU_MAX_RINGS];
252 uint32_t fragment_size;
253 enum amdgpu_vm_level root_level;
254 /* vram base address for page table entry */
255 u64 vram_base_offset;
256 /* vm pte handling */
257 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
258 struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
259 unsigned vm_pte_num_rqs;
261 /* partial resident texture handling */
263 atomic_t num_prt_users;
265 /* controls how VM page tables are updated for Graphics and Compute.
266 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
267 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
271 /* PASID to VM mapping, will be used in interrupt context to
272 * look up VM of a page fault
274 struct idr pasid_idr;
275 spinlock_t pasid_lock;
278 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
279 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
280 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
282 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
283 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
285 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
286 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
287 int vm_context, unsigned int pasid);
288 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
289 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
290 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
291 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
292 struct list_head *validated,
293 struct amdgpu_bo_list_entry *entry);
294 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
295 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
296 int (*callback)(void *p, struct amdgpu_bo *bo),
298 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
299 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
300 struct amdgpu_vm *vm);
301 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
302 struct amdgpu_vm *vm,
303 struct dma_fence **fence);
304 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
305 struct amdgpu_vm *vm);
306 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
307 struct amdgpu_bo_va *bo_va,
309 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
310 struct amdgpu_bo *bo, bool evicted);
311 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
312 struct amdgpu_bo *bo);
313 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
314 struct amdgpu_vm *vm,
315 struct amdgpu_bo *bo);
316 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
317 struct amdgpu_bo_va *bo_va,
318 uint64_t addr, uint64_t offset,
319 uint64_t size, uint64_t flags);
320 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
321 struct amdgpu_bo_va *bo_va,
322 uint64_t addr, uint64_t offset,
323 uint64_t size, uint64_t flags);
324 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
325 struct amdgpu_bo_va *bo_va,
327 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
328 struct amdgpu_vm *vm,
329 uint64_t saddr, uint64_t size);
330 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
332 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
333 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
334 struct amdgpu_bo_va *bo_va);
335 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
336 uint32_t fragment_size_default, unsigned max_level,
338 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
339 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
340 struct amdgpu_job *job);
341 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
343 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
344 struct amdgpu_task_info *task_info);
346 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
348 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
349 struct amdgpu_vm *vm);
350 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);