2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
41 * GPUVM is similar to the legacy gart on older asics, however
42 * rather than there being a single global gart table
43 * for the entire GPU, there are multiple VM page tables active
44 * at any given time. The VM page tables can contain a mix
45 * vram pages and system memory pages and system memory pages
46 * can be mapped as snooped (cached system pages) or unsnooped
47 * (uncached system pages).
48 * Each VM has an ID associated with it and there is a page table
49 * associated with each VMID. When execting a command buffer,
50 * the kernel tells the the ring what VMID to use for that command
51 * buffer. VMIDs are allocated dynamically as commands are submitted.
52 * The userspace drivers maintain their own address space and the kernel
53 * sets up their pages tables accordingly when they submit their
54 * command buffers and a VMID is assigned.
55 * Cayman/Trinity support up to 8 active VMs at any given time;
59 #define START(node) ((node)->start)
60 #define LAST(node) ((node)->last)
62 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
63 START, LAST, static, amdgpu_vm_it)
69 * struct amdgpu_pte_update_params - Local structure
71 * Encapsulate some VM table update parameters to reduce
72 * the number of function parameters
75 struct amdgpu_pte_update_params {
78 * @adev: amdgpu device we do this update for
80 struct amdgpu_device *adev;
83 * @vm: optional amdgpu_vm we do this update for
88 * @src: address where to copy page table entries from
93 * @ib: indirect buffer to fill with commands
98 * @func: Function which actually does the update
100 void (*func)(struct amdgpu_pte_update_params *params,
101 struct amdgpu_bo *bo, uint64_t pe,
102 uint64_t addr, unsigned count, uint32_t incr,
107 * DMA addresses to use for mapping, used during VM update by CPU
109 dma_addr_t *pages_addr;
114 * Kernel pointer of PD/PT BO that needs to be updated,
115 * used during VM update by CPU
121 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
123 struct amdgpu_prt_cb {
126 * @adev: amdgpu device
128 struct amdgpu_device *adev;
133 struct dma_fence_cb cb;
137 * amdgpu_vm_level_shift - return the addr shift for each level
139 * @adev: amdgpu_device pointer
143 * The number of bits the pfn needs to be right shifted for a level.
145 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
148 unsigned shift = 0xff;
154 shift = 9 * (AMDGPU_VM_PDB0 - level) +
155 adev->vm_manager.block_size;
161 dev_err(adev->dev, "the level%d isn't supported.\n", level);
168 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
170 * @adev: amdgpu_device pointer
174 * The number of entries in a page directory or page table.
176 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
179 unsigned shift = amdgpu_vm_level_shift(adev,
180 adev->vm_manager.root_level);
182 if (level == adev->vm_manager.root_level)
183 /* For the root directory */
184 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
185 else if (level != AMDGPU_VM_PTB)
186 /* Everything in between */
189 /* For the page tables on the leaves */
190 return AMDGPU_VM_PTE_COUNT(adev);
194 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
196 * @adev: amdgpu_device pointer
200 * The mask to extract the entry number of a PD/PT from an address.
202 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
205 if (level <= adev->vm_manager.root_level)
207 else if (level != AMDGPU_VM_PTB)
210 return AMDGPU_VM_PTE_COUNT(adev) - 1;
214 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
216 * @adev: amdgpu_device pointer
220 * The size of the BO for a page directory or page table in bytes.
222 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
224 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
228 * amdgpu_vm_bo_evicted - vm_bo is evicted
230 * @vm_bo: vm_bo which is evicted
232 * State for PDs/PTs and per VM BOs which are not at the location they should
235 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
237 struct amdgpu_vm *vm = vm_bo->vm;
238 struct amdgpu_bo *bo = vm_bo->bo;
241 if (bo->tbo.type == ttm_bo_type_kernel)
242 list_move(&vm_bo->vm_status, &vm->evicted);
244 list_move_tail(&vm_bo->vm_status, &vm->evicted);
248 * amdgpu_vm_bo_relocated - vm_bo is reloacted
250 * @vm_bo: vm_bo which is relocated
252 * State for PDs/PTs which needs to update their parent PD.
254 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
256 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
260 * amdgpu_vm_bo_moved - vm_bo is moved
262 * @vm_bo: vm_bo which is moved
264 * State for per VM BOs which are moved, but that change is not yet reflected
265 * in the page tables.
267 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
269 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
273 * amdgpu_vm_bo_idle - vm_bo is idle
275 * @vm_bo: vm_bo which is now idle
277 * State for PDs/PTs and per VM BOs which have gone through the state machine
280 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
282 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
283 vm_bo->moved = false;
287 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
289 * @vm_bo: vm_bo which is now invalidated
291 * State for normal BOs which are invalidated and that change not yet reflected
294 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
296 spin_lock(&vm_bo->vm->invalidated_lock);
297 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
298 spin_unlock(&vm_bo->vm->invalidated_lock);
302 * amdgpu_vm_bo_done - vm_bo is done
304 * @vm_bo: vm_bo which is now done
306 * State for normal BOs which are invalidated and that change has been updated
309 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
311 spin_lock(&vm_bo->vm->invalidated_lock);
312 list_del_init(&vm_bo->vm_status);
313 spin_unlock(&vm_bo->vm->invalidated_lock);
317 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
319 * @base: base structure for tracking BO usage in a VM
320 * @vm: vm to which bo is to be added
321 * @bo: amdgpu buffer object
323 * Initialize a bo_va_base structure and add it to the appropriate lists
326 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
327 struct amdgpu_vm *vm,
328 struct amdgpu_bo *bo)
333 INIT_LIST_HEAD(&base->vm_status);
337 base->next = bo->vm_bo;
340 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
343 vm->bulk_moveable = false;
344 if (bo->tbo.type == ttm_bo_type_kernel)
345 amdgpu_vm_bo_relocated(base);
347 amdgpu_vm_bo_idle(base);
349 if (bo->preferred_domains &
350 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
354 * we checked all the prerequisites, but it looks like this per vm bo
355 * is currently evicted. add the bo to the evicted list to make sure it
356 * is validated on next vm use to avoid fault.
358 amdgpu_vm_bo_evicted(base);
362 * amdgpu_vm_pt_parent - get the parent page directory
364 * @pt: child page table
366 * Helper to get the parent entry for the child page table. NULL if we are at
367 * the root page directory.
369 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
371 struct amdgpu_bo *parent = pt->base.bo->parent;
376 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
380 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
382 struct amdgpu_vm_pt_cursor {
384 struct amdgpu_vm_pt *parent;
385 struct amdgpu_vm_pt *entry;
390 * amdgpu_vm_pt_start - start PD/PT walk
392 * @adev: amdgpu_device pointer
393 * @vm: amdgpu_vm structure
394 * @start: start address of the walk
395 * @cursor: state to initialize
397 * Initialize a amdgpu_vm_pt_cursor to start a walk.
399 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
400 struct amdgpu_vm *vm, uint64_t start,
401 struct amdgpu_vm_pt_cursor *cursor)
404 cursor->parent = NULL;
405 cursor->entry = &vm->root;
406 cursor->level = adev->vm_manager.root_level;
410 * amdgpu_vm_pt_descendant - go to child node
412 * @adev: amdgpu_device pointer
413 * @cursor: current state
415 * Walk to the child node of the current node.
417 * True if the walk was possible, false otherwise.
419 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
420 struct amdgpu_vm_pt_cursor *cursor)
422 unsigned mask, shift, idx;
424 if (!cursor->entry->entries)
427 BUG_ON(!cursor->entry->base.bo);
428 mask = amdgpu_vm_entries_mask(adev, cursor->level);
429 shift = amdgpu_vm_level_shift(adev, cursor->level);
432 idx = (cursor->pfn >> shift) & mask;
433 cursor->parent = cursor->entry;
434 cursor->entry = &cursor->entry->entries[idx];
439 * amdgpu_vm_pt_sibling - go to sibling node
441 * @adev: amdgpu_device pointer
442 * @cursor: current state
444 * Walk to the sibling node of the current node.
446 * True if the walk was possible, false otherwise.
448 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
449 struct amdgpu_vm_pt_cursor *cursor)
451 unsigned shift, num_entries;
453 /* Root doesn't have a sibling */
457 /* Go to our parents and see if we got a sibling */
458 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
459 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
461 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
464 cursor->pfn += 1ULL << shift;
465 cursor->pfn &= ~((1ULL << shift) - 1);
471 * amdgpu_vm_pt_ancestor - go to parent node
473 * @cursor: current state
475 * Walk to the parent node of the current node.
477 * True if the walk was possible, false otherwise.
479 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
485 cursor->entry = cursor->parent;
486 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
491 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
493 * @adev: amdgpu_device pointer
494 * @cursor: current state
496 * Walk the PD/PT tree to the next node.
498 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
499 struct amdgpu_vm_pt_cursor *cursor)
501 /* First try a newborn child */
502 if (amdgpu_vm_pt_descendant(adev, cursor))
505 /* If that didn't worked try to find a sibling */
506 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
507 /* No sibling, go to our parents and grandparents */
508 if (!amdgpu_vm_pt_ancestor(cursor)) {
516 * amdgpu_vm_pt_first_leaf - get first leaf PD/PT
518 * @adev: amdgpu_device pointer
519 * @vm: amdgpu_vm structure
520 * @start: start addr of the walk
521 * @cursor: state to initialize
523 * Start a walk and go directly to the leaf node.
525 static void amdgpu_vm_pt_first_leaf(struct amdgpu_device *adev,
526 struct amdgpu_vm *vm, uint64_t start,
527 struct amdgpu_vm_pt_cursor *cursor)
529 amdgpu_vm_pt_start(adev, vm, start, cursor);
530 while (amdgpu_vm_pt_descendant(adev, cursor));
534 * amdgpu_vm_pt_next_leaf - get next leaf PD/PT
536 * @adev: amdgpu_device pointer
537 * @cursor: current state
539 * Walk the PD/PT tree to the next leaf node.
541 static void amdgpu_vm_pt_next_leaf(struct amdgpu_device *adev,
542 struct amdgpu_vm_pt_cursor *cursor)
544 amdgpu_vm_pt_next(adev, cursor);
545 if (cursor->pfn != ~0ll)
546 while (amdgpu_vm_pt_descendant(adev, cursor));
550 * for_each_amdgpu_vm_pt_leaf - walk over all leaf PDs/PTs in the hierarchy
552 #define for_each_amdgpu_vm_pt_leaf(adev, vm, start, end, cursor) \
553 for (amdgpu_vm_pt_first_leaf((adev), (vm), (start), &(cursor)); \
554 (cursor).pfn <= end; amdgpu_vm_pt_next_leaf((adev), &(cursor)))
557 * amdgpu_vm_pt_first_dfs - start a deep first search
559 * @adev: amdgpu_device structure
560 * @vm: amdgpu_vm structure
561 * @cursor: state to initialize
563 * Starts a deep first traversal of the PD/PT tree.
565 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
566 struct amdgpu_vm *vm,
567 struct amdgpu_vm_pt_cursor *cursor)
569 amdgpu_vm_pt_start(adev, vm, 0, cursor);
570 while (amdgpu_vm_pt_descendant(adev, cursor));
574 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
576 * @adev: amdgpu_device structure
577 * @cursor: current state
579 * Move the cursor to the next node in a deep first search.
581 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
582 struct amdgpu_vm_pt_cursor *cursor)
588 cursor->entry = NULL;
589 else if (amdgpu_vm_pt_sibling(adev, cursor))
590 while (amdgpu_vm_pt_descendant(adev, cursor));
592 amdgpu_vm_pt_ancestor(cursor);
596 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
598 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) \
599 for (amdgpu_vm_pt_first_dfs((adev), (vm), &(cursor)), \
600 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
601 (entry); (entry) = (cursor).entry, \
602 amdgpu_vm_pt_next_dfs((adev), &(cursor)))
605 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
607 * @vm: vm providing the BOs
608 * @validated: head of validation list
609 * @entry: entry to add
611 * Add the page directory to the list of BOs to
612 * validate for command submission.
614 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
615 struct list_head *validated,
616 struct amdgpu_bo_list_entry *entry)
619 entry->tv.bo = &vm->root.base.bo->tbo;
620 /* One for the VM updates, one for TTM and one for the CS job */
621 entry->tv.num_shared = 3;
622 entry->user_pages = NULL;
623 list_add(&entry->tv.head, validated);
627 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
629 * @adev: amdgpu device pointer
630 * @vm: vm providing the BOs
632 * Move all BOs to the end of LRU and remember their positions to put them
635 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
636 struct amdgpu_vm *vm)
638 struct ttm_bo_global *glob = adev->mman.bdev.glob;
639 struct amdgpu_vm_bo_base *bo_base;
641 if (vm->bulk_moveable) {
642 spin_lock(&glob->lru_lock);
643 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
644 spin_unlock(&glob->lru_lock);
648 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
650 spin_lock(&glob->lru_lock);
651 list_for_each_entry(bo_base, &vm->idle, vm_status) {
652 struct amdgpu_bo *bo = bo_base->bo;
657 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
659 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
662 spin_unlock(&glob->lru_lock);
664 vm->bulk_moveable = true;
668 * amdgpu_vm_validate_pt_bos - validate the page table BOs
670 * @adev: amdgpu device pointer
671 * @vm: vm providing the BOs
672 * @validate: callback to do the validation
673 * @param: parameter for the validation callback
675 * Validate the page table BOs on command submission if neccessary.
680 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
681 int (*validate)(void *p, struct amdgpu_bo *bo),
684 struct amdgpu_vm_bo_base *bo_base, *tmp;
687 vm->bulk_moveable &= list_empty(&vm->evicted);
689 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
690 struct amdgpu_bo *bo = bo_base->bo;
692 r = validate(param, bo);
696 if (bo->tbo.type != ttm_bo_type_kernel) {
697 amdgpu_vm_bo_moved(bo_base);
699 if (vm->use_cpu_for_update)
700 r = amdgpu_bo_kmap(bo, NULL);
702 r = amdgpu_ttm_alloc_gart(&bo->tbo);
706 r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
710 amdgpu_vm_bo_relocated(bo_base);
718 * amdgpu_vm_ready - check VM is ready for updates
722 * Check if all VM PDs/PTs are ready for updates
725 * True if eviction list is empty.
727 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
729 return list_empty(&vm->evicted);
733 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
735 * @adev: amdgpu_device pointer
736 * @vm: VM to clear BO from
738 * @level: level this BO is at
739 * @pte_support_ats: indicate ATS support from PTE
741 * Root PD needs to be reserved when calling this.
744 * 0 on success, errno otherwise.
746 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
747 struct amdgpu_vm *vm, struct amdgpu_bo *bo,
748 unsigned level, bool pte_support_ats)
750 struct ttm_operation_ctx ctx = { true, false };
751 struct dma_fence *fence = NULL;
752 unsigned entries, ats_entries;
753 struct amdgpu_ring *ring;
754 struct amdgpu_job *job;
758 entries = amdgpu_bo_size(bo) / 8;
760 if (pte_support_ats) {
761 if (level == adev->vm_manager.root_level) {
762 ats_entries = amdgpu_vm_level_shift(adev, level);
763 ats_entries += AMDGPU_GPU_PAGE_SHIFT;
764 ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries;
765 ats_entries = min(ats_entries, entries);
766 entries -= ats_entries;
768 ats_entries = entries;
775 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
777 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
781 r = amdgpu_ttm_alloc_gart(&bo->tbo);
785 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
789 addr = amdgpu_bo_gpu_offset(bo);
793 ats_value = AMDGPU_PTE_DEFAULT_ATC;
794 if (level != AMDGPU_VM_PTB)
795 ats_value |= AMDGPU_PDE_PTE;
797 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
798 ats_entries, 0, ats_value);
799 addr += ats_entries * 8;
803 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
806 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
808 WARN_ON(job->ibs[0].length_dw > 64);
809 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
810 AMDGPU_FENCE_OWNER_UNDEFINED, false);
814 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED,
819 amdgpu_bo_fence(bo, fence, true);
820 dma_fence_put(fence);
823 return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
824 level, pte_support_ats);
829 amdgpu_job_free(job);
836 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
838 * @adev: amdgpu_device pointer
840 * @bp: resulting BO allocation parameters
842 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
843 int level, struct amdgpu_bo_param *bp)
845 memset(bp, 0, sizeof(*bp));
847 bp->size = amdgpu_vm_bo_size(adev, level);
848 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
849 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
850 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
851 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
852 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
853 if (vm->use_cpu_for_update)
854 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
855 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
856 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
857 bp->type = ttm_bo_type_kernel;
858 if (vm->root.base.bo)
859 bp->resv = vm->root.base.bo->tbo.resv;
863 * amdgpu_vm_alloc_pts - Allocate page tables.
865 * @adev: amdgpu_device pointer
866 * @vm: VM to allocate page tables for
867 * @saddr: Start address which needs to be allocated
868 * @size: Size from start address we need.
870 * Make sure the page directories and page tables are allocated
873 * 0 on success, errno otherwise.
875 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
876 struct amdgpu_vm *vm,
877 uint64_t saddr, uint64_t size)
879 struct amdgpu_vm_pt_cursor cursor;
880 struct amdgpu_bo *pt;
885 /* validate the parameters */
886 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
889 eaddr = saddr + size - 1;
891 if (vm->pte_support_ats)
892 ats = saddr < AMDGPU_GMC_HOLE_START;
894 saddr /= AMDGPU_GPU_PAGE_SIZE;
895 eaddr /= AMDGPU_GPU_PAGE_SIZE;
897 if (eaddr >= adev->vm_manager.max_pfn) {
898 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
899 eaddr, adev->vm_manager.max_pfn);
903 for_each_amdgpu_vm_pt_leaf(adev, vm, saddr, eaddr, cursor) {
904 struct amdgpu_vm_pt *entry = cursor.entry;
905 struct amdgpu_bo_param bp;
907 if (cursor.level < AMDGPU_VM_PTB) {
908 unsigned num_entries;
910 num_entries = amdgpu_vm_num_entries(adev, cursor.level);
911 entry->entries = kvmalloc_array(num_entries,
912 sizeof(*entry->entries),
923 amdgpu_vm_bo_param(adev, vm, cursor.level, &bp);
925 r = amdgpu_bo_create(adev, &bp, &pt);
929 r = amdgpu_vm_clear_bo(adev, vm, pt, cursor.level, ats);
933 if (vm->use_cpu_for_update) {
934 r = amdgpu_bo_kmap(pt, NULL);
939 /* Keep a reference to the root directory to avoid
940 * freeing them up in the wrong order.
942 pt->parent = amdgpu_bo_ref(cursor.parent->base.bo);
944 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
950 amdgpu_bo_unref(&pt->shadow);
951 amdgpu_bo_unref(&pt);
956 * amdgpu_vm_free_pts - free PD/PT levels
958 * @adev: amdgpu device structure
959 * @vm: amdgpu vm structure
961 * Free the page directory or page table level and all sub levels.
963 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
964 struct amdgpu_vm *vm)
966 struct amdgpu_vm_pt_cursor cursor;
967 struct amdgpu_vm_pt *entry;
969 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) {
971 if (entry->base.bo) {
972 entry->base.bo->vm_bo = NULL;
973 list_del(&entry->base.vm_status);
974 amdgpu_bo_unref(&entry->base.bo->shadow);
975 amdgpu_bo_unref(&entry->base.bo);
977 kvfree(entry->entries);
980 BUG_ON(vm->root.base.bo);
984 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
986 * @adev: amdgpu_device pointer
988 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
990 const struct amdgpu_ip_block *ip_block;
991 bool has_compute_vm_bug;
992 struct amdgpu_ring *ring;
995 has_compute_vm_bug = false;
997 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
999 /* Compute has a VM bug for GFX version < 7.
1000 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1001 if (ip_block->version->major <= 7)
1002 has_compute_vm_bug = true;
1003 else if (ip_block->version->major == 8)
1004 if (adev->gfx.mec_fw_version < 673)
1005 has_compute_vm_bug = true;
1008 for (i = 0; i < adev->num_rings; i++) {
1009 ring = adev->rings[i];
1010 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1011 /* only compute rings */
1012 ring->has_compute_vm_bug = has_compute_vm_bug;
1014 ring->has_compute_vm_bug = false;
1019 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1021 * @ring: ring on which the job will be submitted
1022 * @job: job to submit
1025 * True if sync is needed.
1027 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1028 struct amdgpu_job *job)
1030 struct amdgpu_device *adev = ring->adev;
1031 unsigned vmhub = ring->funcs->vmhub;
1032 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1033 struct amdgpu_vmid *id;
1034 bool gds_switch_needed;
1035 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1039 id = &id_mgr->ids[job->vmid];
1040 gds_switch_needed = ring->funcs->emit_gds_switch && (
1041 id->gds_base != job->gds_base ||
1042 id->gds_size != job->gds_size ||
1043 id->gws_base != job->gws_base ||
1044 id->gws_size != job->gws_size ||
1045 id->oa_base != job->oa_base ||
1046 id->oa_size != job->oa_size);
1048 if (amdgpu_vmid_had_gpu_reset(adev, id))
1051 return vm_flush_needed || gds_switch_needed;
1055 * amdgpu_vm_flush - hardware flush the vm
1057 * @ring: ring to use for flush
1059 * @need_pipe_sync: is pipe sync needed
1061 * Emit a VM flush when it is necessary.
1064 * 0 on success, errno otherwise.
1066 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1068 struct amdgpu_device *adev = ring->adev;
1069 unsigned vmhub = ring->funcs->vmhub;
1070 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1071 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1072 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1073 id->gds_base != job->gds_base ||
1074 id->gds_size != job->gds_size ||
1075 id->gws_base != job->gws_base ||
1076 id->gws_size != job->gws_size ||
1077 id->oa_base != job->oa_base ||
1078 id->oa_size != job->oa_size);
1079 bool vm_flush_needed = job->vm_needs_flush;
1080 bool pasid_mapping_needed = id->pasid != job->pasid ||
1081 !id->pasid_mapping ||
1082 !dma_fence_is_signaled(id->pasid_mapping);
1083 struct dma_fence *fence = NULL;
1084 unsigned patch_offset = 0;
1087 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1088 gds_switch_needed = true;
1089 vm_flush_needed = true;
1090 pasid_mapping_needed = true;
1093 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1094 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1095 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1096 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1097 ring->funcs->emit_wreg;
1099 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1102 if (ring->funcs->init_cond_exec)
1103 patch_offset = amdgpu_ring_init_cond_exec(ring);
1106 amdgpu_ring_emit_pipeline_sync(ring);
1108 if (vm_flush_needed) {
1109 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1110 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1113 if (pasid_mapping_needed)
1114 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1116 if (vm_flush_needed || pasid_mapping_needed) {
1117 r = amdgpu_fence_emit(ring, &fence, 0);
1122 if (vm_flush_needed) {
1123 mutex_lock(&id_mgr->lock);
1124 dma_fence_put(id->last_flush);
1125 id->last_flush = dma_fence_get(fence);
1126 id->current_gpu_reset_count =
1127 atomic_read(&adev->gpu_reset_counter);
1128 mutex_unlock(&id_mgr->lock);
1131 if (pasid_mapping_needed) {
1132 id->pasid = job->pasid;
1133 dma_fence_put(id->pasid_mapping);
1134 id->pasid_mapping = dma_fence_get(fence);
1136 dma_fence_put(fence);
1138 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1139 id->gds_base = job->gds_base;
1140 id->gds_size = job->gds_size;
1141 id->gws_base = job->gws_base;
1142 id->gws_size = job->gws_size;
1143 id->oa_base = job->oa_base;
1144 id->oa_size = job->oa_size;
1145 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1146 job->gds_size, job->gws_base,
1147 job->gws_size, job->oa_base,
1151 if (ring->funcs->patch_cond_exec)
1152 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1154 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1155 if (ring->funcs->emit_switch_buffer) {
1156 amdgpu_ring_emit_switch_buffer(ring);
1157 amdgpu_ring_emit_switch_buffer(ring);
1163 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1166 * @bo: requested buffer object
1168 * Find @bo inside the requested vm.
1169 * Search inside the @bos vm list for the requested vm
1170 * Returns the found bo_va or NULL if none is found
1172 * Object has to be reserved!
1175 * Found bo_va or NULL.
1177 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1178 struct amdgpu_bo *bo)
1180 struct amdgpu_vm_bo_base *base;
1182 for (base = bo->vm_bo; base; base = base->next) {
1186 return container_of(base, struct amdgpu_bo_va, base);
1192 * amdgpu_vm_do_set_ptes - helper to call the right asic function
1194 * @params: see amdgpu_pte_update_params definition
1195 * @bo: PD/PT to update
1196 * @pe: addr of the page entry
1197 * @addr: dst addr to write into pe
1198 * @count: number of page entries to update
1199 * @incr: increase next addr by incr bytes
1200 * @flags: hw access flags
1202 * Traces the parameters and calls the right asic functions
1203 * to setup the page table using the DMA.
1205 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
1206 struct amdgpu_bo *bo,
1207 uint64_t pe, uint64_t addr,
1208 unsigned count, uint32_t incr,
1211 pe += amdgpu_bo_gpu_offset(bo);
1212 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1215 amdgpu_vm_write_pte(params->adev, params->ib, pe,
1216 addr | flags, count, incr);
1219 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
1220 count, incr, flags);
1225 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
1227 * @params: see amdgpu_pte_update_params definition
1228 * @bo: PD/PT to update
1229 * @pe: addr of the page entry
1230 * @addr: dst addr to write into pe
1231 * @count: number of page entries to update
1232 * @incr: increase next addr by incr bytes
1233 * @flags: hw access flags
1235 * Traces the parameters and calls the DMA function to copy the PTEs.
1237 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
1238 struct amdgpu_bo *bo,
1239 uint64_t pe, uint64_t addr,
1240 unsigned count, uint32_t incr,
1243 uint64_t src = (params->src + (addr >> 12) * 8);
1245 pe += amdgpu_bo_gpu_offset(bo);
1246 trace_amdgpu_vm_copy_ptes(pe, src, count);
1248 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
1252 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1254 * @pages_addr: optional DMA address to use for lookup
1255 * @addr: the unmapped addr
1257 * Look up the physical address of the page that the pte resolves
1261 * The pointer for the page table entry.
1263 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1267 /* page table offset */
1268 result = pages_addr[addr >> PAGE_SHIFT];
1270 /* in case cpu page size != gpu page size*/
1271 result |= addr & (~PAGE_MASK);
1273 result &= 0xFFFFFFFFFFFFF000ULL;
1279 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1281 * @params: see amdgpu_pte_update_params definition
1282 * @bo: PD/PT to update
1283 * @pe: kmap addr of the page entry
1284 * @addr: dst addr to write into pe
1285 * @count: number of page entries to update
1286 * @incr: increase next addr by incr bytes
1287 * @flags: hw access flags
1289 * Write count number of PT/PD entries directly.
1291 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
1292 struct amdgpu_bo *bo,
1293 uint64_t pe, uint64_t addr,
1294 unsigned count, uint32_t incr,
1300 pe += (unsigned long)amdgpu_bo_kptr(bo);
1302 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1304 for (i = 0; i < count; i++) {
1305 value = params->pages_addr ?
1306 amdgpu_vm_map_gart(params->pages_addr, addr) :
1308 amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
1316 * amdgpu_vm_wait_pd - Wait for PT BOs to be free.
1318 * @adev: amdgpu_device pointer
1320 * @owner: fence owner
1323 * 0 on success, errno otherwise.
1325 static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1328 struct amdgpu_sync sync;
1331 amdgpu_sync_create(&sync);
1332 amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
1333 r = amdgpu_sync_wait(&sync, true);
1334 amdgpu_sync_free(&sync);
1340 * amdgpu_vm_update_func - helper to call update function
1342 * Calls the update function for both the given BO as well as its shadow.
1344 static void amdgpu_vm_update_func(struct amdgpu_pte_update_params *params,
1345 struct amdgpu_bo *bo,
1346 uint64_t pe, uint64_t addr,
1347 unsigned count, uint32_t incr,
1351 params->func(params, bo->shadow, pe, addr, count, incr, flags);
1352 params->func(params, bo, pe, addr, count, incr, flags);
1356 * amdgpu_vm_update_pde - update a single level in the hierarchy
1358 * @param: parameters for the update
1360 * @parent: parent directory
1361 * @entry: entry to update
1363 * Makes sure the requested entry in parent is up to date.
1365 static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
1366 struct amdgpu_vm *vm,
1367 struct amdgpu_vm_pt *parent,
1368 struct amdgpu_vm_pt *entry)
1370 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1371 uint64_t pde, pt, flags;
1374 /* Don't update huge pages here */
1378 for (level = 0, pbo = bo->parent; pbo; ++level)
1381 level += params->adev->vm_manager.root_level;
1382 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1383 pde = (entry - parent->entries) * 8;
1384 amdgpu_vm_update_func(params, bo, pde, pt, 1, 0, flags);
1388 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1390 * @adev: amdgpu_device pointer
1393 * Mark all PD level as invalid after an error.
1395 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1396 struct amdgpu_vm *vm)
1398 struct amdgpu_vm_pt_cursor cursor;
1399 struct amdgpu_vm_pt *entry;
1401 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry)
1402 if (entry->base.bo && !entry->base.moved)
1403 amdgpu_vm_bo_relocated(&entry->base);
1407 * amdgpu_vm_update_directories - make sure that all directories are valid
1409 * @adev: amdgpu_device pointer
1412 * Makes sure all directories are up to date.
1415 * 0 for success, error for failure.
1417 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1418 struct amdgpu_vm *vm)
1420 struct amdgpu_pte_update_params params;
1421 struct amdgpu_job *job;
1425 if (list_empty(&vm->relocated))
1429 memset(¶ms, 0, sizeof(params));
1432 if (vm->use_cpu_for_update) {
1433 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
1437 params.func = amdgpu_vm_cpu_set_ptes;
1440 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1444 params.ib = &job->ibs[0];
1445 params.func = amdgpu_vm_do_set_ptes;
1448 while (!list_empty(&vm->relocated)) {
1449 struct amdgpu_vm_pt *pt, *entry;
1451 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1453 amdgpu_vm_bo_idle(&entry->base);
1455 pt = amdgpu_vm_pt_parent(entry);
1459 amdgpu_vm_update_pde(¶ms, vm, pt, entry);
1461 if (!vm->use_cpu_for_update &&
1462 (ndw - params.ib->length_dw) < 32)
1466 if (vm->use_cpu_for_update) {
1469 amdgpu_asic_flush_hdp(adev, NULL);
1470 } else if (params.ib->length_dw == 0) {
1471 amdgpu_job_free(job);
1473 struct amdgpu_bo *root = vm->root.base.bo;
1474 struct amdgpu_ring *ring;
1475 struct dma_fence *fence;
1477 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring,
1480 amdgpu_ring_pad_ib(ring, params.ib);
1481 amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
1482 AMDGPU_FENCE_OWNER_VM, false);
1483 WARN_ON(params.ib->length_dw > ndw);
1484 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM,
1489 amdgpu_bo_fence(root, fence, true);
1490 dma_fence_put(vm->last_update);
1491 vm->last_update = fence;
1494 if (!list_empty(&vm->relocated))
1500 amdgpu_vm_invalidate_pds(adev, vm);
1501 amdgpu_job_free(job);
1506 * amdgpu_vm_update_huge - figure out parameters for PTE updates
1508 * Make sure to set the right flags for the PTEs at the desired level.
1510 static void amdgpu_vm_update_huge(struct amdgpu_pte_update_params *params,
1511 struct amdgpu_bo *bo, unsigned level,
1512 uint64_t pe, uint64_t addr,
1513 unsigned count, uint32_t incr,
1517 if (level != AMDGPU_VM_PTB) {
1518 flags |= AMDGPU_PDE_PTE;
1519 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1522 amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags);
1526 * amdgpu_vm_fragment - get fragment for PTEs
1528 * @params: see amdgpu_pte_update_params definition
1529 * @start: first PTE to handle
1530 * @end: last PTE to handle
1531 * @flags: hw mapping flags
1532 * @frag: resulting fragment size
1533 * @frag_end: end of this fragment
1535 * Returns the first possible fragment for the start and end address.
1537 static void amdgpu_vm_fragment(struct amdgpu_pte_update_params *params,
1538 uint64_t start, uint64_t end, uint64_t flags,
1539 unsigned int *frag, uint64_t *frag_end)
1542 * The MC L1 TLB supports variable sized pages, based on a fragment
1543 * field in the PTE. When this field is set to a non-zero value, page
1544 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1545 * flags are considered valid for all PTEs within the fragment range
1546 * and corresponding mappings are assumed to be physically contiguous.
1548 * The L1 TLB can store a single PTE for the whole fragment,
1549 * significantly increasing the space available for translation
1550 * caching. This leads to large improvements in throughput when the
1551 * TLB is under pressure.
1553 * The L2 TLB distributes small and large fragments into two
1554 * asymmetric partitions. The large fragment cache is significantly
1555 * larger. Thus, we try to use large fragments wherever possible.
1556 * Userspace can support this by aligning virtual base address and
1557 * allocation size to the fragment size.
1559 * Starting with Vega10 the fragment size only controls the L1. The L2
1560 * is now directly feed with small/huge/giant pages from the walker.
1564 if (params->adev->asic_type < CHIP_VEGA10)
1565 max_frag = params->adev->vm_manager.fragment_size;
1569 /* system pages are non continuously */
1576 /* This intentionally wraps around if no bit is set */
1577 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1578 if (*frag >= max_frag) {
1580 *frag_end = end & ~((1ULL << max_frag) - 1);
1582 *frag_end = start + (1 << *frag);
1587 * amdgpu_vm_update_ptes - make sure that page tables are valid
1589 * @params: see amdgpu_pte_update_params definition
1590 * @start: start of GPU address range
1591 * @end: end of GPU address range
1592 * @dst: destination address to map to, the next dst inside the function
1593 * @flags: mapping flags
1595 * Update the page tables in the range @start - @end.
1598 * 0 for success, -EINVAL for failure.
1600 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1601 uint64_t start, uint64_t end,
1602 uint64_t dst, uint64_t flags)
1604 struct amdgpu_device *adev = params->adev;
1605 struct amdgpu_vm_pt_cursor cursor;
1606 uint64_t frag_start = start, frag_end;
1609 /* figure out the initial fragment */
1610 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1612 /* walk over the address space and update the PTs */
1613 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1614 while (cursor.pfn < end) {
1615 struct amdgpu_bo *pt = cursor.entry->base.bo;
1616 unsigned shift, parent_shift, mask;
1617 uint64_t incr, entry_end, pe_start;
1622 /* The root level can't be a huge page */
1623 if (cursor.level == adev->vm_manager.root_level) {
1624 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1629 /* If it isn't already handled it can't be a huge page */
1630 if (cursor.entry->huge) {
1631 /* Add the entry to the relocated list to update it. */
1632 cursor.entry->huge = false;
1633 amdgpu_vm_bo_relocated(&cursor.entry->base);
1636 shift = amdgpu_vm_level_shift(adev, cursor.level);
1637 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1638 if (adev->asic_type < CHIP_VEGA10) {
1639 /* No huge page support before GMC v9 */
1640 if (cursor.level != AMDGPU_VM_PTB) {
1641 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1645 } else if (frag < shift) {
1646 /* We can't use this level when the fragment size is
1647 * smaller than the address shift. Go to the next
1648 * child entry and try again.
1650 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1653 } else if (frag >= parent_shift &&
1654 cursor.level - 1 != adev->vm_manager.root_level) {
1655 /* If the fragment size is even larger than the parent
1656 * shift we should go up one level and check it again
1657 * unless one level up is the root level.
1659 if (!amdgpu_vm_pt_ancestor(&cursor))
1664 /* Looks good so far, calculate parameters for the update */
1665 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1666 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1667 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1668 entry_end = (uint64_t)(mask + 1) << shift;
1669 entry_end += cursor.pfn & ~(entry_end - 1);
1670 entry_end = min(entry_end, end);
1673 uint64_t upd_end = min(entry_end, frag_end);
1674 unsigned nptes = (upd_end - frag_start) >> shift;
1676 amdgpu_vm_update_huge(params, pt, cursor.level,
1677 pe_start, dst, nptes, incr,
1678 flags | AMDGPU_PTE_FRAG(frag));
1680 pe_start += nptes * 8;
1681 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1683 frag_start = upd_end;
1684 if (frag_start >= frag_end) {
1685 /* figure out the next fragment */
1686 amdgpu_vm_fragment(params, frag_start, end,
1687 flags, &frag, &frag_end);
1691 } while (frag_start < entry_end);
1693 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1694 /* Mark all child entries as huge */
1695 while (cursor.pfn < frag_start) {
1696 cursor.entry->huge = true;
1697 amdgpu_vm_pt_next(adev, &cursor);
1700 } else if (frag >= shift) {
1701 /* or just move on to the next on the same level. */
1702 amdgpu_vm_pt_next(adev, &cursor);
1710 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1712 * @adev: amdgpu_device pointer
1713 * @exclusive: fence we need to sync to
1714 * @pages_addr: DMA addresses to use for mapping
1716 * @start: start of mapped range
1717 * @last: last mapped entry
1718 * @flags: flags for the entries
1719 * @addr: addr to set the area to
1720 * @fence: optional resulting fence
1722 * Fill in the page table entries between @start and @last.
1725 * 0 for success, -EINVAL for failure.
1727 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1728 struct dma_fence *exclusive,
1729 dma_addr_t *pages_addr,
1730 struct amdgpu_vm *vm,
1731 uint64_t start, uint64_t last,
1732 uint64_t flags, uint64_t addr,
1733 struct dma_fence **fence)
1735 struct amdgpu_ring *ring;
1736 void *owner = AMDGPU_FENCE_OWNER_VM;
1737 unsigned nptes, ncmds, ndw;
1738 struct amdgpu_job *job;
1739 struct amdgpu_pte_update_params params;
1740 struct dma_fence *f = NULL;
1743 memset(¶ms, 0, sizeof(params));
1747 /* sync to everything on unmapping */
1748 if (!(flags & AMDGPU_PTE_VALID))
1749 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1751 if (vm->use_cpu_for_update) {
1752 /* params.src is used as flag to indicate system Memory */
1756 /* Wait for PT BOs to be free. PTs share the same resv. object
1759 r = amdgpu_vm_wait_pd(adev, vm, owner);
1763 params.func = amdgpu_vm_cpu_set_ptes;
1764 params.pages_addr = pages_addr;
1765 return amdgpu_vm_update_ptes(¶ms, start, last + 1,
1769 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
1771 nptes = last - start + 1;
1774 * reserve space for two commands every (1 << BLOCK_SIZE)
1775 * entries or 2k dwords (whatever is smaller)
1777 * The second command is for the shadow pagetables.
1779 if (vm->root.base.bo->shadow)
1780 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1782 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1788 /* copy commands needed */
1789 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1794 params.func = amdgpu_vm_do_copy_ptes;
1797 /* set page commands needed */
1800 /* extra commands for begin/end fragments */
1801 if (vm->root.base.bo->shadow)
1802 ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
1804 ndw += 2 * 10 * adev->vm_manager.fragment_size;
1806 params.func = amdgpu_vm_do_set_ptes;
1809 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1813 params.ib = &job->ibs[0];
1819 /* Put the PTEs at the end of the IB. */
1820 i = ndw - nptes * 2;
1821 pte= (uint64_t *)&(job->ibs->ptr[i]);
1822 params.src = job->ibs->gpu_addr + i * 4;
1824 for (i = 0; i < nptes; ++i) {
1825 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1826 AMDGPU_GPU_PAGE_SIZE);
1832 r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1836 r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1841 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1845 amdgpu_ring_pad_ib(ring, params.ib);
1846 WARN_ON(params.ib->length_dw > ndw);
1847 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
1851 amdgpu_bo_fence(vm->root.base.bo, f, true);
1852 dma_fence_put(*fence);
1857 amdgpu_job_free(job);
1862 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1864 * @adev: amdgpu_device pointer
1865 * @exclusive: fence we need to sync to
1866 * @pages_addr: DMA addresses to use for mapping
1868 * @mapping: mapped range and flags to use for the update
1869 * @flags: HW flags for the mapping
1870 * @nodes: array of drm_mm_nodes with the MC addresses
1871 * @fence: optional resulting fence
1873 * Split the mapping into smaller chunks so that each update fits
1877 * 0 for success, -EINVAL for failure.
1879 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1880 struct dma_fence *exclusive,
1881 dma_addr_t *pages_addr,
1882 struct amdgpu_vm *vm,
1883 struct amdgpu_bo_va_mapping *mapping,
1885 struct drm_mm_node *nodes,
1886 struct dma_fence **fence)
1888 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1889 uint64_t pfn, start = mapping->start;
1892 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1893 * but in case of something, we filter the flags in first place
1895 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1896 flags &= ~AMDGPU_PTE_READABLE;
1897 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1898 flags &= ~AMDGPU_PTE_WRITEABLE;
1900 flags &= ~AMDGPU_PTE_EXECUTABLE;
1901 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1903 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1904 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1906 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1907 (adev->asic_type >= CHIP_VEGA10)) {
1908 flags |= AMDGPU_PTE_PRT;
1909 flags &= ~AMDGPU_PTE_VALID;
1912 trace_amdgpu_vm_bo_update(mapping);
1914 pfn = mapping->offset >> PAGE_SHIFT;
1916 while (pfn >= nodes->size) {
1923 dma_addr_t *dma_addr = NULL;
1924 uint64_t max_entries;
1925 uint64_t addr, last;
1928 addr = nodes->start << PAGE_SHIFT;
1929 max_entries = (nodes->size - pfn) *
1930 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1933 max_entries = S64_MAX;
1939 max_entries = min(max_entries, 16ull * 1024ull);
1941 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1943 uint64_t idx = pfn + count;
1945 if (pages_addr[idx] !=
1946 (pages_addr[idx - 1] + PAGE_SIZE))
1950 if (count < min_linear_pages) {
1951 addr = pfn << PAGE_SHIFT;
1952 dma_addr = pages_addr;
1954 addr = pages_addr[pfn];
1955 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1958 } else if (flags & AMDGPU_PTE_VALID) {
1959 addr += adev->vm_manager.vram_base_offset;
1960 addr += pfn << PAGE_SHIFT;
1963 last = min((uint64_t)mapping->last, start + max_entries - 1);
1964 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1965 start, last, flags, addr,
1970 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1971 if (nodes && nodes->size == pfn) {
1977 } while (unlikely(start != mapping->last + 1));
1983 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1985 * @adev: amdgpu_device pointer
1986 * @bo_va: requested BO and VM object
1987 * @clear: if true clear the entries
1989 * Fill in the page table entries for @bo_va.
1992 * 0 for success, -EINVAL for failure.
1994 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1995 struct amdgpu_bo_va *bo_va,
1998 struct amdgpu_bo *bo = bo_va->base.bo;
1999 struct amdgpu_vm *vm = bo_va->base.vm;
2000 struct amdgpu_bo_va_mapping *mapping;
2001 dma_addr_t *pages_addr = NULL;
2002 struct ttm_mem_reg *mem;
2003 struct drm_mm_node *nodes;
2004 struct dma_fence *exclusive, **last_update;
2013 struct ttm_dma_tt *ttm;
2016 nodes = mem->mm_node;
2017 if (mem->mem_type == TTM_PL_TT) {
2018 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
2019 pages_addr = ttm->dma_address;
2021 exclusive = reservation_object_get_excl(bo->tbo.resv);
2025 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
2029 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
2030 last_update = &vm->last_update;
2032 last_update = &bo_va->last_pt_update;
2034 if (!clear && bo_va->base.moved) {
2035 bo_va->base.moved = false;
2036 list_splice_init(&bo_va->valids, &bo_va->invalids);
2038 } else if (bo_va->cleared != clear) {
2039 list_splice_init(&bo_va->valids, &bo_va->invalids);
2042 list_for_each_entry(mapping, &bo_va->invalids, list) {
2043 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
2044 mapping, flags, nodes,
2050 if (vm->use_cpu_for_update) {
2053 amdgpu_asic_flush_hdp(adev, NULL);
2056 /* If the BO is not in its preferred location add it back to
2057 * the evicted list so that it gets validated again on the
2058 * next command submission.
2060 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2061 uint32_t mem_type = bo->tbo.mem.mem_type;
2063 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
2064 amdgpu_vm_bo_evicted(&bo_va->base);
2066 amdgpu_vm_bo_idle(&bo_va->base);
2068 amdgpu_vm_bo_done(&bo_va->base);
2071 list_splice_init(&bo_va->invalids, &bo_va->valids);
2072 bo_va->cleared = clear;
2074 if (trace_amdgpu_vm_bo_mapping_enabled()) {
2075 list_for_each_entry(mapping, &bo_va->valids, list)
2076 trace_amdgpu_vm_bo_mapping(mapping);
2083 * amdgpu_vm_update_prt_state - update the global PRT state
2085 * @adev: amdgpu_device pointer
2087 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
2089 unsigned long flags;
2092 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
2093 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
2094 adev->gmc.gmc_funcs->set_prt(adev, enable);
2095 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
2099 * amdgpu_vm_prt_get - add a PRT user
2101 * @adev: amdgpu_device pointer
2103 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
2105 if (!adev->gmc.gmc_funcs->set_prt)
2108 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
2109 amdgpu_vm_update_prt_state(adev);
2113 * amdgpu_vm_prt_put - drop a PRT user
2115 * @adev: amdgpu_device pointer
2117 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
2119 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
2120 amdgpu_vm_update_prt_state(adev);
2124 * amdgpu_vm_prt_cb - callback for updating the PRT status
2126 * @fence: fence for the callback
2127 * @_cb: the callback function
2129 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
2131 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
2133 amdgpu_vm_prt_put(cb->adev);
2138 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
2140 * @adev: amdgpu_device pointer
2141 * @fence: fence for the callback
2143 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
2144 struct dma_fence *fence)
2146 struct amdgpu_prt_cb *cb;
2148 if (!adev->gmc.gmc_funcs->set_prt)
2151 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2153 /* Last resort when we are OOM */
2155 dma_fence_wait(fence, false);
2157 amdgpu_vm_prt_put(adev);
2160 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2162 amdgpu_vm_prt_cb(fence, &cb->cb);
2167 * amdgpu_vm_free_mapping - free a mapping
2169 * @adev: amdgpu_device pointer
2171 * @mapping: mapping to be freed
2172 * @fence: fence of the unmap operation
2174 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2176 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2177 struct amdgpu_vm *vm,
2178 struct amdgpu_bo_va_mapping *mapping,
2179 struct dma_fence *fence)
2181 if (mapping->flags & AMDGPU_PTE_PRT)
2182 amdgpu_vm_add_prt_cb(adev, fence);
2187 * amdgpu_vm_prt_fini - finish all prt mappings
2189 * @adev: amdgpu_device pointer
2192 * Register a cleanup callback to disable PRT support after VM dies.
2194 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2196 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
2197 struct dma_fence *excl, **shared;
2198 unsigned i, shared_count;
2201 r = reservation_object_get_fences_rcu(resv, &excl,
2202 &shared_count, &shared);
2204 /* Not enough memory to grab the fence list, as last resort
2205 * block for all the fences to complete.
2207 reservation_object_wait_timeout_rcu(resv, true, false,
2208 MAX_SCHEDULE_TIMEOUT);
2212 /* Add a callback for each fence in the reservation object */
2213 amdgpu_vm_prt_get(adev);
2214 amdgpu_vm_add_prt_cb(adev, excl);
2216 for (i = 0; i < shared_count; ++i) {
2217 amdgpu_vm_prt_get(adev);
2218 amdgpu_vm_add_prt_cb(adev, shared[i]);
2225 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2227 * @adev: amdgpu_device pointer
2229 * @fence: optional resulting fence (unchanged if no work needed to be done
2230 * or if an error occurred)
2232 * Make sure all freed BOs are cleared in the PT.
2233 * PTs have to be reserved and mutex must be locked!
2239 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2240 struct amdgpu_vm *vm,
2241 struct dma_fence **fence)
2243 struct amdgpu_bo_va_mapping *mapping;
2244 uint64_t init_pte_value = 0;
2245 struct dma_fence *f = NULL;
2248 while (!list_empty(&vm->freed)) {
2249 mapping = list_first_entry(&vm->freed,
2250 struct amdgpu_bo_va_mapping, list);
2251 list_del(&mapping->list);
2253 if (vm->pte_support_ats &&
2254 mapping->start < AMDGPU_GMC_HOLE_START)
2255 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2257 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
2258 mapping->start, mapping->last,
2259 init_pte_value, 0, &f);
2260 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2268 dma_fence_put(*fence);
2279 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2281 * @adev: amdgpu_device pointer
2284 * Make sure all BOs which are moved are updated in the PTs.
2289 * PTs have to be reserved!
2291 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2292 struct amdgpu_vm *vm)
2294 struct amdgpu_bo_va *bo_va, *tmp;
2295 struct reservation_object *resv;
2299 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2300 /* Per VM BOs never need to bo cleared in the page tables */
2301 r = amdgpu_vm_bo_update(adev, bo_va, false);
2306 spin_lock(&vm->invalidated_lock);
2307 while (!list_empty(&vm->invalidated)) {
2308 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2310 resv = bo_va->base.bo->tbo.resv;
2311 spin_unlock(&vm->invalidated_lock);
2313 /* Try to reserve the BO to avoid clearing its ptes */
2314 if (!amdgpu_vm_debug && reservation_object_trylock(resv))
2316 /* Somebody else is using the BO right now */
2320 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2325 reservation_object_unlock(resv);
2326 spin_lock(&vm->invalidated_lock);
2328 spin_unlock(&vm->invalidated_lock);
2334 * amdgpu_vm_bo_add - add a bo to a specific vm
2336 * @adev: amdgpu_device pointer
2338 * @bo: amdgpu buffer object
2340 * Add @bo into the requested vm.
2341 * Add @bo to the list of bos associated with the vm
2344 * Newly added bo_va or NULL for failure
2346 * Object has to be reserved!
2348 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2349 struct amdgpu_vm *vm,
2350 struct amdgpu_bo *bo)
2352 struct amdgpu_bo_va *bo_va;
2354 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2355 if (bo_va == NULL) {
2358 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2360 bo_va->ref_count = 1;
2361 INIT_LIST_HEAD(&bo_va->valids);
2362 INIT_LIST_HEAD(&bo_va->invalids);
2369 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2371 * @adev: amdgpu_device pointer
2372 * @bo_va: bo_va to store the address
2373 * @mapping: the mapping to insert
2375 * Insert a new mapping into all structures.
2377 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2378 struct amdgpu_bo_va *bo_va,
2379 struct amdgpu_bo_va_mapping *mapping)
2381 struct amdgpu_vm *vm = bo_va->base.vm;
2382 struct amdgpu_bo *bo = bo_va->base.bo;
2384 mapping->bo_va = bo_va;
2385 list_add(&mapping->list, &bo_va->invalids);
2386 amdgpu_vm_it_insert(mapping, &vm->va);
2388 if (mapping->flags & AMDGPU_PTE_PRT)
2389 amdgpu_vm_prt_get(adev);
2391 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
2392 !bo_va->base.moved) {
2393 list_move(&bo_va->base.vm_status, &vm->moved);
2395 trace_amdgpu_vm_bo_map(bo_va, mapping);
2399 * amdgpu_vm_bo_map - map bo inside a vm
2401 * @adev: amdgpu_device pointer
2402 * @bo_va: bo_va to store the address
2403 * @saddr: where to map the BO
2404 * @offset: requested offset in the BO
2405 * @size: BO size in bytes
2406 * @flags: attributes of pages (read/write/valid/etc.)
2408 * Add a mapping of the BO at the specefied addr into the VM.
2411 * 0 for success, error for failure.
2413 * Object has to be reserved and unreserved outside!
2415 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2416 struct amdgpu_bo_va *bo_va,
2417 uint64_t saddr, uint64_t offset,
2418 uint64_t size, uint64_t flags)
2420 struct amdgpu_bo_va_mapping *mapping, *tmp;
2421 struct amdgpu_bo *bo = bo_va->base.bo;
2422 struct amdgpu_vm *vm = bo_va->base.vm;
2425 /* validate the parameters */
2426 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2427 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2430 /* make sure object fit at this offset */
2431 eaddr = saddr + size - 1;
2432 if (saddr >= eaddr ||
2433 (bo && offset + size > amdgpu_bo_size(bo)))
2436 saddr /= AMDGPU_GPU_PAGE_SIZE;
2437 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2439 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2441 /* bo and tmp overlap, invalid addr */
2442 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2443 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2444 tmp->start, tmp->last + 1);
2448 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2452 mapping->start = saddr;
2453 mapping->last = eaddr;
2454 mapping->offset = offset;
2455 mapping->flags = flags;
2457 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2463 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2465 * @adev: amdgpu_device pointer
2466 * @bo_va: bo_va to store the address
2467 * @saddr: where to map the BO
2468 * @offset: requested offset in the BO
2469 * @size: BO size in bytes
2470 * @flags: attributes of pages (read/write/valid/etc.)
2472 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2473 * mappings as we do so.
2476 * 0 for success, error for failure.
2478 * Object has to be reserved and unreserved outside!
2480 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2481 struct amdgpu_bo_va *bo_va,
2482 uint64_t saddr, uint64_t offset,
2483 uint64_t size, uint64_t flags)
2485 struct amdgpu_bo_va_mapping *mapping;
2486 struct amdgpu_bo *bo = bo_va->base.bo;
2490 /* validate the parameters */
2491 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2492 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2495 /* make sure object fit at this offset */
2496 eaddr = saddr + size - 1;
2497 if (saddr >= eaddr ||
2498 (bo && offset + size > amdgpu_bo_size(bo)))
2501 /* Allocate all the needed memory */
2502 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2506 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2512 saddr /= AMDGPU_GPU_PAGE_SIZE;
2513 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2515 mapping->start = saddr;
2516 mapping->last = eaddr;
2517 mapping->offset = offset;
2518 mapping->flags = flags;
2520 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2526 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2528 * @adev: amdgpu_device pointer
2529 * @bo_va: bo_va to remove the address from
2530 * @saddr: where to the BO is mapped
2532 * Remove a mapping of the BO at the specefied addr from the VM.
2535 * 0 for success, error for failure.
2537 * Object has to be reserved and unreserved outside!
2539 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2540 struct amdgpu_bo_va *bo_va,
2543 struct amdgpu_bo_va_mapping *mapping;
2544 struct amdgpu_vm *vm = bo_va->base.vm;
2547 saddr /= AMDGPU_GPU_PAGE_SIZE;
2549 list_for_each_entry(mapping, &bo_va->valids, list) {
2550 if (mapping->start == saddr)
2554 if (&mapping->list == &bo_va->valids) {
2557 list_for_each_entry(mapping, &bo_va->invalids, list) {
2558 if (mapping->start == saddr)
2562 if (&mapping->list == &bo_va->invalids)
2566 list_del(&mapping->list);
2567 amdgpu_vm_it_remove(mapping, &vm->va);
2568 mapping->bo_va = NULL;
2569 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2572 list_add(&mapping->list, &vm->freed);
2574 amdgpu_vm_free_mapping(adev, vm, mapping,
2575 bo_va->last_pt_update);
2581 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2583 * @adev: amdgpu_device pointer
2584 * @vm: VM structure to use
2585 * @saddr: start of the range
2586 * @size: size of the range
2588 * Remove all mappings in a range, split them as appropriate.
2591 * 0 for success, error for failure.
2593 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2594 struct amdgpu_vm *vm,
2595 uint64_t saddr, uint64_t size)
2597 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2601 eaddr = saddr + size - 1;
2602 saddr /= AMDGPU_GPU_PAGE_SIZE;
2603 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2605 /* Allocate all the needed memory */
2606 before = kzalloc(sizeof(*before), GFP_KERNEL);
2609 INIT_LIST_HEAD(&before->list);
2611 after = kzalloc(sizeof(*after), GFP_KERNEL);
2616 INIT_LIST_HEAD(&after->list);
2618 /* Now gather all removed mappings */
2619 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2621 /* Remember mapping split at the start */
2622 if (tmp->start < saddr) {
2623 before->start = tmp->start;
2624 before->last = saddr - 1;
2625 before->offset = tmp->offset;
2626 before->flags = tmp->flags;
2627 before->bo_va = tmp->bo_va;
2628 list_add(&before->list, &tmp->bo_va->invalids);
2631 /* Remember mapping split at the end */
2632 if (tmp->last > eaddr) {
2633 after->start = eaddr + 1;
2634 after->last = tmp->last;
2635 after->offset = tmp->offset;
2636 after->offset += after->start - tmp->start;
2637 after->flags = tmp->flags;
2638 after->bo_va = tmp->bo_va;
2639 list_add(&after->list, &tmp->bo_va->invalids);
2642 list_del(&tmp->list);
2643 list_add(&tmp->list, &removed);
2645 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2648 /* And free them up */
2649 list_for_each_entry_safe(tmp, next, &removed, list) {
2650 amdgpu_vm_it_remove(tmp, &vm->va);
2651 list_del(&tmp->list);
2653 if (tmp->start < saddr)
2655 if (tmp->last > eaddr)
2659 list_add(&tmp->list, &vm->freed);
2660 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2663 /* Insert partial mapping before the range */
2664 if (!list_empty(&before->list)) {
2665 amdgpu_vm_it_insert(before, &vm->va);
2666 if (before->flags & AMDGPU_PTE_PRT)
2667 amdgpu_vm_prt_get(adev);
2672 /* Insert partial mapping after the range */
2673 if (!list_empty(&after->list)) {
2674 amdgpu_vm_it_insert(after, &vm->va);
2675 if (after->flags & AMDGPU_PTE_PRT)
2676 amdgpu_vm_prt_get(adev);
2685 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2687 * @vm: the requested VM
2688 * @addr: the address
2690 * Find a mapping by it's address.
2693 * The amdgpu_bo_va_mapping matching for addr or NULL
2696 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2699 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2703 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2705 * @vm: the requested vm
2706 * @ticket: CS ticket
2708 * Trace all mappings of BOs reserved during a command submission.
2710 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2712 struct amdgpu_bo_va_mapping *mapping;
2714 if (!trace_amdgpu_vm_bo_cs_enabled())
2717 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2718 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2719 if (mapping->bo_va && mapping->bo_va->base.bo) {
2720 struct amdgpu_bo *bo;
2722 bo = mapping->bo_va->base.bo;
2723 if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
2727 trace_amdgpu_vm_bo_cs(mapping);
2732 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2734 * @adev: amdgpu_device pointer
2735 * @bo_va: requested bo_va
2737 * Remove @bo_va->bo from the requested vm.
2739 * Object have to be reserved!
2741 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2742 struct amdgpu_bo_va *bo_va)
2744 struct amdgpu_bo_va_mapping *mapping, *next;
2745 struct amdgpu_bo *bo = bo_va->base.bo;
2746 struct amdgpu_vm *vm = bo_va->base.vm;
2747 struct amdgpu_vm_bo_base **base;
2750 if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2751 vm->bulk_moveable = false;
2753 for (base = &bo_va->base.bo->vm_bo; *base;
2754 base = &(*base)->next) {
2755 if (*base != &bo_va->base)
2758 *base = bo_va->base.next;
2763 spin_lock(&vm->invalidated_lock);
2764 list_del(&bo_va->base.vm_status);
2765 spin_unlock(&vm->invalidated_lock);
2767 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2768 list_del(&mapping->list);
2769 amdgpu_vm_it_remove(mapping, &vm->va);
2770 mapping->bo_va = NULL;
2771 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2772 list_add(&mapping->list, &vm->freed);
2774 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2775 list_del(&mapping->list);
2776 amdgpu_vm_it_remove(mapping, &vm->va);
2777 amdgpu_vm_free_mapping(adev, vm, mapping,
2778 bo_va->last_pt_update);
2781 dma_fence_put(bo_va->last_pt_update);
2786 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2788 * @adev: amdgpu_device pointer
2789 * @bo: amdgpu buffer object
2790 * @evicted: is the BO evicted
2792 * Mark @bo as invalid.
2794 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2795 struct amdgpu_bo *bo, bool evicted)
2797 struct amdgpu_vm_bo_base *bo_base;
2799 /* shadow bo doesn't have bo base, its validation needs its parent */
2800 if (bo->parent && bo->parent->shadow == bo)
2803 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2804 struct amdgpu_vm *vm = bo_base->vm;
2806 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2807 amdgpu_vm_bo_evicted(bo_base);
2813 bo_base->moved = true;
2815 if (bo->tbo.type == ttm_bo_type_kernel)
2816 amdgpu_vm_bo_relocated(bo_base);
2817 else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2818 amdgpu_vm_bo_moved(bo_base);
2820 amdgpu_vm_bo_invalidated(bo_base);
2825 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2830 * VM page table as power of two
2832 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2834 /* Total bits covered by PD + PTs */
2835 unsigned bits = ilog2(vm_size) + 18;
2837 /* Make sure the PD is 4K in size up to 8GB address space.
2838 Above that split equal between PD and PTs */
2842 return ((bits + 3) / 2);
2846 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2848 * @adev: amdgpu_device pointer
2849 * @min_vm_size: the minimum vm size in GB if it's set auto
2850 * @fragment_size_default: Default PTE fragment size
2851 * @max_level: max VMPT level
2852 * @max_bits: max address space size in bits
2855 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2856 uint32_t fragment_size_default, unsigned max_level,
2859 unsigned int max_size = 1 << (max_bits - 30);
2860 unsigned int vm_size;
2863 /* adjust vm size first */
2864 if (amdgpu_vm_size != -1) {
2865 vm_size = amdgpu_vm_size;
2866 if (vm_size > max_size) {
2867 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2868 amdgpu_vm_size, max_size);
2873 unsigned int phys_ram_gb;
2875 /* Optimal VM size depends on the amount of physical
2876 * RAM available. Underlying requirements and
2879 * - Need to map system memory and VRAM from all GPUs
2880 * - VRAM from other GPUs not known here
2881 * - Assume VRAM <= system memory
2882 * - On GFX8 and older, VM space can be segmented for
2884 * - Need to allow room for fragmentation, guard pages etc.
2886 * This adds up to a rough guess of system memory x3.
2887 * Round up to power of two to maximize the available
2888 * VM size with the given page table size.
2891 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2892 (1 << 30) - 1) >> 30;
2893 vm_size = roundup_pow_of_two(
2894 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2897 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2899 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2900 if (amdgpu_vm_block_size != -1)
2901 tmp >>= amdgpu_vm_block_size - 9;
2902 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2903 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2904 switch (adev->vm_manager.num_level) {
2906 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2909 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2912 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2915 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2917 /* block size depends on vm size and hw setup*/
2918 if (amdgpu_vm_block_size != -1)
2919 adev->vm_manager.block_size =
2920 min((unsigned)amdgpu_vm_block_size, max_bits
2921 - AMDGPU_GPU_PAGE_SHIFT
2922 - 9 * adev->vm_manager.num_level);
2923 else if (adev->vm_manager.num_level > 1)
2924 adev->vm_manager.block_size = 9;
2926 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2928 if (amdgpu_vm_fragment_size == -1)
2929 adev->vm_manager.fragment_size = fragment_size_default;
2931 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2933 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2934 vm_size, adev->vm_manager.num_level + 1,
2935 adev->vm_manager.block_size,
2936 adev->vm_manager.fragment_size);
2939 static struct amdgpu_retryfault_hashtable *init_fault_hash(void)
2941 struct amdgpu_retryfault_hashtable *fault_hash;
2943 fault_hash = kmalloc(sizeof(*fault_hash), GFP_KERNEL);
2947 INIT_CHASH_TABLE(fault_hash->hash,
2948 AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
2949 spin_lock_init(&fault_hash->lock);
2950 fault_hash->count = 0;
2956 * amdgpu_vm_init - initialize a vm instance
2958 * @adev: amdgpu_device pointer
2960 * @vm_context: Indicates if it GFX or Compute context
2961 * @pasid: Process address space identifier
2966 * 0 for success, error for failure.
2968 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2969 int vm_context, unsigned int pasid)
2971 struct amdgpu_bo_param bp;
2972 struct amdgpu_bo *root;
2975 vm->va = RB_ROOT_CACHED;
2976 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2977 vm->reserved_vmid[i] = NULL;
2978 INIT_LIST_HEAD(&vm->evicted);
2979 INIT_LIST_HEAD(&vm->relocated);
2980 INIT_LIST_HEAD(&vm->moved);
2981 INIT_LIST_HEAD(&vm->idle);
2982 INIT_LIST_HEAD(&vm->invalidated);
2983 spin_lock_init(&vm->invalidated_lock);
2984 INIT_LIST_HEAD(&vm->freed);
2986 /* create scheduler entity for page table updates */
2987 r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
2988 adev->vm_manager.vm_pte_num_rqs, NULL);
2992 vm->pte_support_ats = false;
2994 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2995 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2996 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2998 if (adev->asic_type == CHIP_RAVEN)
2999 vm->pte_support_ats = true;
3001 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3002 AMDGPU_VM_USE_CPU_FOR_GFX);
3004 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3005 vm->use_cpu_for_update ? "CPU" : "SDMA");
3006 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3007 "CPU update of VM recommended only for large BAR system\n");
3008 vm->last_update = NULL;
3010 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
3011 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
3012 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
3013 r = amdgpu_bo_create(adev, &bp, &root);
3015 goto error_free_sched_entity;
3017 r = amdgpu_bo_reserve(root, true);
3019 goto error_free_root;
3021 r = reservation_object_reserve_shared(root->tbo.resv, 1);
3023 goto error_unreserve;
3025 r = amdgpu_vm_clear_bo(adev, vm, root,
3026 adev->vm_manager.root_level,
3027 vm->pte_support_ats);
3029 goto error_unreserve;
3031 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
3032 amdgpu_bo_unreserve(vm->root.base.bo);
3035 unsigned long flags;
3037 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3038 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3040 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3042 goto error_free_root;
3047 vm->fault_hash = init_fault_hash();
3048 if (!vm->fault_hash) {
3050 goto error_free_root;
3053 INIT_KFIFO(vm->faults);
3058 amdgpu_bo_unreserve(vm->root.base.bo);
3061 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3062 amdgpu_bo_unref(&vm->root.base.bo);
3063 vm->root.base.bo = NULL;
3065 error_free_sched_entity:
3066 drm_sched_entity_destroy(&vm->entity);
3072 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3074 * @adev: amdgpu_device pointer
3077 * This only works on GFX VMs that don't have any BOs added and no
3078 * page tables allocated yet.
3080 * Changes the following VM parameters:
3081 * - use_cpu_for_update
3082 * - pte_supports_ats
3083 * - pasid (old PASID is released, because compute manages its own PASIDs)
3085 * Reinitializes the page directory to reflect the changed ATS
3089 * 0 for success, -errno for errors.
3091 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
3093 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3096 r = amdgpu_bo_reserve(vm->root.base.bo, true);
3101 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
3107 unsigned long flags;
3109 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3110 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3112 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3119 /* Check if PD needs to be reinitialized and do it before
3120 * changing any other state, in case it fails.
3122 if (pte_support_ats != vm->pte_support_ats) {
3123 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
3124 adev->vm_manager.root_level,
3130 /* Update VM state */
3131 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3132 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3133 vm->pte_support_ats = pte_support_ats;
3134 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3135 vm->use_cpu_for_update ? "CPU" : "SDMA");
3136 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3137 "CPU update of VM recommended only for large BAR system\n");
3140 unsigned long flags;
3142 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3143 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3144 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3146 /* Free the original amdgpu allocated pasid
3147 * Will be replaced with kfd allocated pasid
3149 amdgpu_pasid_free(vm->pasid);
3153 /* Free the shadow bo for compute VM */
3154 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3163 unsigned long flags;
3165 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3166 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3167 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3170 amdgpu_bo_unreserve(vm->root.base.bo);
3175 * amdgpu_vm_release_compute - release a compute vm
3176 * @adev: amdgpu_device pointer
3177 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3179 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3180 * pasid from vm. Compute should stop use of vm after this call.
3182 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3185 unsigned long flags;
3187 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3188 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3189 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3195 * amdgpu_vm_fini - tear down a vm instance
3197 * @adev: amdgpu_device pointer
3201 * Unbind the VM and remove all bos from the vm bo list
3203 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3205 struct amdgpu_bo_va_mapping *mapping, *tmp;
3206 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3207 struct amdgpu_bo *root;
3211 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3213 /* Clear pending page faults from IH when the VM is destroyed */
3214 while (kfifo_get(&vm->faults, &fault))
3215 amdgpu_vm_clear_fault(vm->fault_hash, fault);
3218 unsigned long flags;
3220 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3221 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3222 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3225 kfree(vm->fault_hash);
3226 vm->fault_hash = NULL;
3228 drm_sched_entity_destroy(&vm->entity);
3230 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3231 dev_err(adev->dev, "still active bo inside vm\n");
3233 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3234 &vm->va.rb_root, rb) {
3235 /* Don't remove the mapping here, we don't want to trigger a
3236 * rebalance and the tree is about to be destroyed anyway.
3238 list_del(&mapping->list);
3241 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3242 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3243 amdgpu_vm_prt_fini(adev, vm);
3244 prt_fini_needed = false;
3247 list_del(&mapping->list);
3248 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3251 root = amdgpu_bo_ref(vm->root.base.bo);
3252 r = amdgpu_bo_reserve(root, true);
3254 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
3256 amdgpu_vm_free_pts(adev, vm);
3257 amdgpu_bo_unreserve(root);
3259 amdgpu_bo_unref(&root);
3260 dma_fence_put(vm->last_update);
3261 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3262 amdgpu_vmid_free_reserved(adev, vm, i);
3266 * amdgpu_vm_manager_init - init the VM manager
3268 * @adev: amdgpu_device pointer
3270 * Initialize the VM manager structures
3272 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3276 amdgpu_vmid_mgr_init(adev);
3278 adev->vm_manager.fence_context =
3279 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3280 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3281 adev->vm_manager.seqno[i] = 0;
3283 spin_lock_init(&adev->vm_manager.prt_lock);
3284 atomic_set(&adev->vm_manager.num_prt_users, 0);
3286 /* If not overridden by the user, by default, only in large BAR systems
3287 * Compute VM tables will be updated by CPU
3289 #ifdef CONFIG_X86_64
3290 if (amdgpu_vm_update_mode == -1) {
3291 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3292 adev->vm_manager.vm_update_mode =
3293 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3295 adev->vm_manager.vm_update_mode = 0;
3297 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3299 adev->vm_manager.vm_update_mode = 0;
3302 idr_init(&adev->vm_manager.pasid_idr);
3303 spin_lock_init(&adev->vm_manager.pasid_lock);
3307 * amdgpu_vm_manager_fini - cleanup VM manager
3309 * @adev: amdgpu_device pointer
3311 * Cleanup the VM manager and free resources.
3313 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3315 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3316 idr_destroy(&adev->vm_manager.pasid_idr);
3318 amdgpu_vmid_mgr_fini(adev);
3322 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3324 * @dev: drm device pointer
3325 * @data: drm_amdgpu_vm
3326 * @filp: drm file pointer
3329 * 0 for success, -errno for errors.
3331 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3333 union drm_amdgpu_vm *args = data;
3334 struct amdgpu_device *adev = dev->dev_private;
3335 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3338 switch (args->in.op) {
3339 case AMDGPU_VM_OP_RESERVE_VMID:
3340 /* current, we only have requirement to reserve vmid from gfxhub */
3341 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3345 case AMDGPU_VM_OP_UNRESERVE_VMID:
3346 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3356 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3358 * @adev: drm device pointer
3359 * @pasid: PASID identifier for VM
3360 * @task_info: task_info to fill.
3362 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3363 struct amdgpu_task_info *task_info)
3365 struct amdgpu_vm *vm;
3367 spin_lock(&adev->vm_manager.pasid_lock);
3369 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3371 *task_info = vm->task_info;
3373 spin_unlock(&adev->vm_manager.pasid_lock);
3377 * amdgpu_vm_set_task_info - Sets VMs task info.
3379 * @vm: vm for which to set the info
3381 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3383 if (!vm->task_info.pid) {
3384 vm->task_info.pid = current->pid;
3385 get_task_comm(vm->task_info.task_name, current);
3387 if (current->group_leader->mm == current->mm) {
3388 vm->task_info.tgid = current->group_leader->pid;
3389 get_task_comm(vm->task_info.process_name, current->group_leader);
3395 * amdgpu_vm_add_fault - Add a page fault record to fault hash table
3397 * @fault_hash: fault hash table
3398 * @key: 64-bit encoding of PASID and address
3400 * This should be called when a retry page fault interrupt is
3401 * received. If this is a new page fault, it will be added to a hash
3402 * table. The return value indicates whether this is a new fault, or
3403 * a fault that was already known and is already being handled.
3405 * If there are too many pending page faults, this will fail. Retry
3406 * interrupts should be ignored in this case until there is enough
3409 * Returns 0 if the fault was added, 1 if the fault was already known,
3410 * -ENOSPC if there are too many pending faults.
3412 int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
3414 unsigned long flags;
3417 if (WARN_ON_ONCE(!fault_hash))
3418 /* Should be allocated in amdgpu_vm_init
3422 spin_lock_irqsave(&fault_hash->lock, flags);
3424 /* Only let the hash table fill up to 50% for best performance */
3425 if (fault_hash->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1)))
3428 r = chash_table_copy_in(&fault_hash->hash, key, NULL);
3430 fault_hash->count++;
3432 /* chash_table_copy_in should never fail unless we're losing count */
3433 WARN_ON_ONCE(r < 0);
3436 spin_unlock_irqrestore(&fault_hash->lock, flags);
3441 * amdgpu_vm_clear_fault - Remove a page fault record
3443 * @fault_hash: fault hash table
3444 * @key: 64-bit encoding of PASID and address
3446 * This should be called when a page fault has been handled. Any
3447 * future interrupt with this key will be processed as a new
3450 void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
3452 unsigned long flags;
3458 spin_lock_irqsave(&fault_hash->lock, flags);
3460 r = chash_table_remove(&fault_hash->hash, key, NULL);
3461 if (!WARN_ON_ONCE(r < 0)) {
3462 fault_hash->count--;
3463 WARN_ON_ONCE(fault_hash->count < 0);
3466 spin_unlock_irqrestore(&fault_hash->lock, flags);