2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
41 * GPUVM is similar to the legacy gart on older asics, however
42 * rather than there being a single global gart table
43 * for the entire GPU, there are multiple VM page tables active
44 * at any given time. The VM page tables can contain a mix
45 * vram pages and system memory pages and system memory pages
46 * can be mapped as snooped (cached system pages) or unsnooped
47 * (uncached system pages).
48 * Each VM has an ID associated with it and there is a page table
49 * associated with each VMID. When execting a command buffer,
50 * the kernel tells the the ring what VMID to use for that command
51 * buffer. VMIDs are allocated dynamically as commands are submitted.
52 * The userspace drivers maintain their own address space and the kernel
53 * sets up their pages tables accordingly when they submit their
54 * command buffers and a VMID is assigned.
55 * Cayman/Trinity support up to 8 active VMs at any given time;
59 #define START(node) ((node)->start)
60 #define LAST(node) ((node)->last)
62 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
63 START, LAST, static, amdgpu_vm_it)
69 * struct amdgpu_pte_update_params - Local structure
71 * Encapsulate some VM table update parameters to reduce
72 * the number of function parameters
75 struct amdgpu_pte_update_params {
78 * @adev: amdgpu device we do this update for
80 struct amdgpu_device *adev;
83 * @vm: optional amdgpu_vm we do this update for
88 * @src: address where to copy page table entries from
93 * @ib: indirect buffer to fill with commands
98 * @func: Function which actually does the update
100 void (*func)(struct amdgpu_pte_update_params *params,
101 struct amdgpu_bo *bo, uint64_t pe,
102 uint64_t addr, unsigned count, uint32_t incr,
107 * DMA addresses to use for mapping, used during VM update by CPU
109 dma_addr_t *pages_addr;
113 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
115 struct amdgpu_prt_cb {
118 * @adev: amdgpu device
120 struct amdgpu_device *adev;
125 struct dma_fence_cb cb;
129 * amdgpu_vm_level_shift - return the addr shift for each level
131 * @adev: amdgpu_device pointer
135 * The number of bits the pfn needs to be right shifted for a level.
137 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
140 unsigned shift = 0xff;
146 shift = 9 * (AMDGPU_VM_PDB0 - level) +
147 adev->vm_manager.block_size;
153 dev_err(adev->dev, "the level%d isn't supported.\n", level);
160 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
162 * @adev: amdgpu_device pointer
166 * The number of entries in a page directory or page table.
168 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
171 unsigned shift = amdgpu_vm_level_shift(adev,
172 adev->vm_manager.root_level);
174 if (level == adev->vm_manager.root_level)
175 /* For the root directory */
176 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
177 else if (level != AMDGPU_VM_PTB)
178 /* Everything in between */
181 /* For the page tables on the leaves */
182 return AMDGPU_VM_PTE_COUNT(adev);
186 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
188 * @adev: amdgpu_device pointer
192 * The mask to extract the entry number of a PD/PT from an address.
194 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
197 if (level <= adev->vm_manager.root_level)
199 else if (level != AMDGPU_VM_PTB)
202 return AMDGPU_VM_PTE_COUNT(adev) - 1;
206 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
208 * @adev: amdgpu_device pointer
212 * The size of the BO for a page directory or page table in bytes.
214 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
220 * amdgpu_vm_bo_evicted - vm_bo is evicted
222 * @vm_bo: vm_bo which is evicted
224 * State for PDs/PTs and per VM BOs which are not at the location they should
227 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
229 struct amdgpu_vm *vm = vm_bo->vm;
230 struct amdgpu_bo *bo = vm_bo->bo;
233 if (bo->tbo.type == ttm_bo_type_kernel)
234 list_move(&vm_bo->vm_status, &vm->evicted);
236 list_move_tail(&vm_bo->vm_status, &vm->evicted);
240 * amdgpu_vm_bo_relocated - vm_bo is reloacted
242 * @vm_bo: vm_bo which is relocated
244 * State for PDs/PTs which needs to update their parent PD.
246 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
248 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
252 * amdgpu_vm_bo_moved - vm_bo is moved
254 * @vm_bo: vm_bo which is moved
256 * State for per VM BOs which are moved, but that change is not yet reflected
257 * in the page tables.
259 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
261 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
265 * amdgpu_vm_bo_idle - vm_bo is idle
267 * @vm_bo: vm_bo which is now idle
269 * State for PDs/PTs and per VM BOs which have gone through the state machine
272 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
274 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
275 vm_bo->moved = false;
279 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
281 * @vm_bo: vm_bo which is now invalidated
283 * State for normal BOs which are invalidated and that change not yet reflected
286 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
288 spin_lock(&vm_bo->vm->invalidated_lock);
289 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
290 spin_unlock(&vm_bo->vm->invalidated_lock);
294 * amdgpu_vm_bo_done - vm_bo is done
296 * @vm_bo: vm_bo which is now done
298 * State for normal BOs which are invalidated and that change has been updated
301 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
303 spin_lock(&vm_bo->vm->invalidated_lock);
304 list_del_init(&vm_bo->vm_status);
305 spin_unlock(&vm_bo->vm->invalidated_lock);
309 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
311 * @base: base structure for tracking BO usage in a VM
312 * @vm: vm to which bo is to be added
313 * @bo: amdgpu buffer object
315 * Initialize a bo_va_base structure and add it to the appropriate lists
318 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
319 struct amdgpu_vm *vm,
320 struct amdgpu_bo *bo)
325 INIT_LIST_HEAD(&base->vm_status);
329 base->next = bo->vm_bo;
332 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
335 vm->bulk_moveable = false;
336 if (bo->tbo.type == ttm_bo_type_kernel)
337 amdgpu_vm_bo_relocated(base);
339 amdgpu_vm_bo_idle(base);
341 if (bo->preferred_domains &
342 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
346 * we checked all the prerequisites, but it looks like this per vm bo
347 * is currently evicted. add the bo to the evicted list to make sure it
348 * is validated on next vm use to avoid fault.
350 amdgpu_vm_bo_evicted(base);
354 * amdgpu_vm_pt_parent - get the parent page directory
356 * @pt: child page table
358 * Helper to get the parent entry for the child page table. NULL if we are at
359 * the root page directory.
361 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
363 struct amdgpu_bo *parent = pt->base.bo->parent;
368 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
372 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
374 struct amdgpu_vm_pt_cursor {
376 struct amdgpu_vm_pt *parent;
377 struct amdgpu_vm_pt *entry;
382 * amdgpu_vm_pt_start - start PD/PT walk
384 * @adev: amdgpu_device pointer
385 * @vm: amdgpu_vm structure
386 * @start: start address of the walk
387 * @cursor: state to initialize
389 * Initialize a amdgpu_vm_pt_cursor to start a walk.
391 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
392 struct amdgpu_vm *vm, uint64_t start,
393 struct amdgpu_vm_pt_cursor *cursor)
396 cursor->parent = NULL;
397 cursor->entry = &vm->root;
398 cursor->level = adev->vm_manager.root_level;
402 * amdgpu_vm_pt_descendant - go to child node
404 * @adev: amdgpu_device pointer
405 * @cursor: current state
407 * Walk to the child node of the current node.
409 * True if the walk was possible, false otherwise.
411 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
412 struct amdgpu_vm_pt_cursor *cursor)
414 unsigned mask, shift, idx;
416 if (!cursor->entry->entries)
419 BUG_ON(!cursor->entry->base.bo);
420 mask = amdgpu_vm_entries_mask(adev, cursor->level);
421 shift = amdgpu_vm_level_shift(adev, cursor->level);
424 idx = (cursor->pfn >> shift) & mask;
425 cursor->parent = cursor->entry;
426 cursor->entry = &cursor->entry->entries[idx];
431 * amdgpu_vm_pt_sibling - go to sibling node
433 * @adev: amdgpu_device pointer
434 * @cursor: current state
436 * Walk to the sibling node of the current node.
438 * True if the walk was possible, false otherwise.
440 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
441 struct amdgpu_vm_pt_cursor *cursor)
443 unsigned shift, num_entries;
445 /* Root doesn't have a sibling */
449 /* Go to our parents and see if we got a sibling */
450 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
451 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
453 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
456 cursor->pfn += 1ULL << shift;
457 cursor->pfn &= ~((1ULL << shift) - 1);
463 * amdgpu_vm_pt_ancestor - go to parent node
465 * @cursor: current state
467 * Walk to the parent node of the current node.
469 * True if the walk was possible, false otherwise.
471 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
477 cursor->entry = cursor->parent;
478 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
483 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
485 * @adev: amdgpu_device pointer
486 * @cursor: current state
488 * Walk the PD/PT tree to the next node.
490 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
491 struct amdgpu_vm_pt_cursor *cursor)
493 /* First try a newborn child */
494 if (amdgpu_vm_pt_descendant(adev, cursor))
497 /* If that didn't worked try to find a sibling */
498 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
499 /* No sibling, go to our parents and grandparents */
500 if (!amdgpu_vm_pt_ancestor(cursor)) {
508 * amdgpu_vm_pt_first_leaf - get first leaf PD/PT
510 * @adev: amdgpu_device pointer
511 * @vm: amdgpu_vm structure
512 * @start: start addr of the walk
513 * @cursor: state to initialize
515 * Start a walk and go directly to the leaf node.
517 static void amdgpu_vm_pt_first_leaf(struct amdgpu_device *adev,
518 struct amdgpu_vm *vm, uint64_t start,
519 struct amdgpu_vm_pt_cursor *cursor)
521 amdgpu_vm_pt_start(adev, vm, start, cursor);
522 while (amdgpu_vm_pt_descendant(adev, cursor));
526 * amdgpu_vm_pt_next_leaf - get next leaf PD/PT
528 * @adev: amdgpu_device pointer
529 * @cursor: current state
531 * Walk the PD/PT tree to the next leaf node.
533 static void amdgpu_vm_pt_next_leaf(struct amdgpu_device *adev,
534 struct amdgpu_vm_pt_cursor *cursor)
536 amdgpu_vm_pt_next(adev, cursor);
537 if (cursor->pfn != ~0ll)
538 while (amdgpu_vm_pt_descendant(adev, cursor));
542 * for_each_amdgpu_vm_pt_leaf - walk over all leaf PDs/PTs in the hierarchy
544 #define for_each_amdgpu_vm_pt_leaf(adev, vm, start, end, cursor) \
545 for (amdgpu_vm_pt_first_leaf((adev), (vm), (start), &(cursor)); \
546 (cursor).pfn <= end; amdgpu_vm_pt_next_leaf((adev), &(cursor)))
549 * amdgpu_vm_pt_first_dfs - start a deep first search
551 * @adev: amdgpu_device structure
552 * @vm: amdgpu_vm structure
553 * @cursor: state to initialize
555 * Starts a deep first traversal of the PD/PT tree.
557 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
558 struct amdgpu_vm *vm,
559 struct amdgpu_vm_pt_cursor *cursor)
561 amdgpu_vm_pt_start(adev, vm, 0, cursor);
562 while (amdgpu_vm_pt_descendant(adev, cursor));
566 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
568 * @adev: amdgpu_device structure
569 * @cursor: current state
571 * Move the cursor to the next node in a deep first search.
573 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
574 struct amdgpu_vm_pt_cursor *cursor)
580 cursor->entry = NULL;
581 else if (amdgpu_vm_pt_sibling(adev, cursor))
582 while (amdgpu_vm_pt_descendant(adev, cursor));
584 amdgpu_vm_pt_ancestor(cursor);
588 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
590 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) \
591 for (amdgpu_vm_pt_first_dfs((adev), (vm), &(cursor)), \
592 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
593 (entry); (entry) = (cursor).entry, \
594 amdgpu_vm_pt_next_dfs((adev), &(cursor)))
597 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
599 * @vm: vm providing the BOs
600 * @validated: head of validation list
601 * @entry: entry to add
603 * Add the page directory to the list of BOs to
604 * validate for command submission.
606 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
607 struct list_head *validated,
608 struct amdgpu_bo_list_entry *entry)
611 entry->tv.bo = &vm->root.base.bo->tbo;
612 /* One for the VM updates, one for TTM and one for the CS job */
613 entry->tv.num_shared = 3;
614 entry->user_pages = NULL;
615 list_add(&entry->tv.head, validated);
618 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
620 struct amdgpu_bo *abo;
621 struct amdgpu_vm_bo_base *bo_base;
623 if (!amdgpu_bo_is_amdgpu_bo(bo))
626 if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
629 abo = ttm_to_amdgpu_bo(bo);
632 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
633 struct amdgpu_vm *vm = bo_base->vm;
635 if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
636 vm->bulk_moveable = false;
641 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
643 * @adev: amdgpu device pointer
644 * @vm: vm providing the BOs
646 * Move all BOs to the end of LRU and remember their positions to put them
649 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
650 struct amdgpu_vm *vm)
652 struct ttm_bo_global *glob = adev->mman.bdev.glob;
653 struct amdgpu_vm_bo_base *bo_base;
655 if (vm->bulk_moveable) {
656 spin_lock(&glob->lru_lock);
657 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
658 spin_unlock(&glob->lru_lock);
662 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
664 spin_lock(&glob->lru_lock);
665 list_for_each_entry(bo_base, &vm->idle, vm_status) {
666 struct amdgpu_bo *bo = bo_base->bo;
671 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
673 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
676 spin_unlock(&glob->lru_lock);
678 vm->bulk_moveable = true;
682 * amdgpu_vm_validate_pt_bos - validate the page table BOs
684 * @adev: amdgpu device pointer
685 * @vm: vm providing the BOs
686 * @validate: callback to do the validation
687 * @param: parameter for the validation callback
689 * Validate the page table BOs on command submission if neccessary.
694 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
695 int (*validate)(void *p, struct amdgpu_bo *bo),
698 struct amdgpu_vm_bo_base *bo_base, *tmp;
701 vm->bulk_moveable &= list_empty(&vm->evicted);
703 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
704 struct amdgpu_bo *bo = bo_base->bo;
706 r = validate(param, bo);
710 if (bo->tbo.type != ttm_bo_type_kernel) {
711 amdgpu_vm_bo_moved(bo_base);
713 if (vm->use_cpu_for_update)
714 r = amdgpu_bo_kmap(bo, NULL);
716 r = amdgpu_ttm_alloc_gart(&bo->tbo);
720 r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
724 amdgpu_vm_bo_relocated(bo_base);
732 * amdgpu_vm_ready - check VM is ready for updates
736 * Check if all VM PDs/PTs are ready for updates
739 * True if eviction list is empty.
741 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
743 return list_empty(&vm->evicted);
747 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
749 * @adev: amdgpu_device pointer
750 * @vm: VM to clear BO from
752 * @level: level this BO is at
753 * @pte_support_ats: indicate ATS support from PTE
755 * Root PD needs to be reserved when calling this.
758 * 0 on success, errno otherwise.
760 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
761 struct amdgpu_vm *vm, struct amdgpu_bo *bo,
762 unsigned level, bool pte_support_ats)
764 struct ttm_operation_ctx ctx = { true, false };
765 struct dma_fence *fence = NULL;
766 unsigned entries, ats_entries;
767 struct amdgpu_ring *ring;
768 struct amdgpu_job *job;
772 entries = amdgpu_bo_size(bo) / 8;
774 if (pte_support_ats) {
775 if (level == adev->vm_manager.root_level) {
776 ats_entries = amdgpu_vm_level_shift(adev, level);
777 ats_entries += AMDGPU_GPU_PAGE_SHIFT;
778 ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries;
779 ats_entries = min(ats_entries, entries);
780 entries -= ats_entries;
782 ats_entries = entries;
789 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
791 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
795 r = amdgpu_ttm_alloc_gart(&bo->tbo);
799 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
803 addr = amdgpu_bo_gpu_offset(bo);
807 ats_value = AMDGPU_PTE_DEFAULT_ATC;
808 if (level != AMDGPU_VM_PTB)
809 ats_value |= AMDGPU_PDE_PTE;
811 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
812 ats_entries, 0, ats_value);
813 addr += ats_entries * 8;
819 /* Workaround for fault priority problem on GMC9 */
820 if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
821 value = AMDGPU_PTE_EXECUTABLE;
823 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
827 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
829 WARN_ON(job->ibs[0].length_dw > 64);
830 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
831 AMDGPU_FENCE_OWNER_UNDEFINED, false);
835 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED,
840 amdgpu_bo_fence(bo, fence, true);
841 dma_fence_put(fence);
844 return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
845 level, pte_support_ats);
850 amdgpu_job_free(job);
857 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
859 * @adev: amdgpu_device pointer
861 * @bp: resulting BO allocation parameters
863 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
864 int level, struct amdgpu_bo_param *bp)
866 memset(bp, 0, sizeof(*bp));
868 bp->size = amdgpu_vm_bo_size(adev, level);
869 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
870 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
871 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
872 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
873 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
874 if (vm->use_cpu_for_update)
875 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
876 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
877 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
878 bp->type = ttm_bo_type_kernel;
879 if (vm->root.base.bo)
880 bp->resv = vm->root.base.bo->tbo.resv;
884 * amdgpu_vm_alloc_pts - Allocate page tables.
886 * @adev: amdgpu_device pointer
887 * @vm: VM to allocate page tables for
888 * @saddr: Start address which needs to be allocated
889 * @size: Size from start address we need.
891 * Make sure the page directories and page tables are allocated
894 * 0 on success, errno otherwise.
896 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
897 struct amdgpu_vm *vm,
898 uint64_t saddr, uint64_t size)
900 struct amdgpu_vm_pt_cursor cursor;
901 struct amdgpu_bo *pt;
906 /* validate the parameters */
907 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
910 eaddr = saddr + size - 1;
912 if (vm->pte_support_ats)
913 ats = saddr < AMDGPU_GMC_HOLE_START;
915 saddr /= AMDGPU_GPU_PAGE_SIZE;
916 eaddr /= AMDGPU_GPU_PAGE_SIZE;
918 if (eaddr >= adev->vm_manager.max_pfn) {
919 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
920 eaddr, adev->vm_manager.max_pfn);
924 for_each_amdgpu_vm_pt_leaf(adev, vm, saddr, eaddr, cursor) {
925 struct amdgpu_vm_pt *entry = cursor.entry;
926 struct amdgpu_bo_param bp;
928 if (cursor.level < AMDGPU_VM_PTB) {
929 unsigned num_entries;
931 num_entries = amdgpu_vm_num_entries(adev, cursor.level);
932 entry->entries = kvmalloc_array(num_entries,
933 sizeof(*entry->entries),
944 amdgpu_vm_bo_param(adev, vm, cursor.level, &bp);
946 r = amdgpu_bo_create(adev, &bp, &pt);
950 r = amdgpu_vm_clear_bo(adev, vm, pt, cursor.level, ats);
954 if (vm->use_cpu_for_update) {
955 r = amdgpu_bo_kmap(pt, NULL);
960 /* Keep a reference to the root directory to avoid
961 * freeing them up in the wrong order.
963 pt->parent = amdgpu_bo_ref(cursor.parent->base.bo);
965 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
971 amdgpu_bo_unref(&pt->shadow);
972 amdgpu_bo_unref(&pt);
977 * amdgpu_vm_free_pts - free PD/PT levels
979 * @adev: amdgpu device structure
980 * @vm: amdgpu vm structure
982 * Free the page directory or page table level and all sub levels.
984 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
985 struct amdgpu_vm *vm)
987 struct amdgpu_vm_pt_cursor cursor;
988 struct amdgpu_vm_pt *entry;
990 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) {
992 if (entry->base.bo) {
993 entry->base.bo->vm_bo = NULL;
994 list_del(&entry->base.vm_status);
995 amdgpu_bo_unref(&entry->base.bo->shadow);
996 amdgpu_bo_unref(&entry->base.bo);
998 kvfree(entry->entries);
1001 BUG_ON(vm->root.base.bo);
1005 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1007 * @adev: amdgpu_device pointer
1009 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1011 const struct amdgpu_ip_block *ip_block;
1012 bool has_compute_vm_bug;
1013 struct amdgpu_ring *ring;
1016 has_compute_vm_bug = false;
1018 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1020 /* Compute has a VM bug for GFX version < 7.
1021 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1022 if (ip_block->version->major <= 7)
1023 has_compute_vm_bug = true;
1024 else if (ip_block->version->major == 8)
1025 if (adev->gfx.mec_fw_version < 673)
1026 has_compute_vm_bug = true;
1029 for (i = 0; i < adev->num_rings; i++) {
1030 ring = adev->rings[i];
1031 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1032 /* only compute rings */
1033 ring->has_compute_vm_bug = has_compute_vm_bug;
1035 ring->has_compute_vm_bug = false;
1040 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1042 * @ring: ring on which the job will be submitted
1043 * @job: job to submit
1046 * True if sync is needed.
1048 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1049 struct amdgpu_job *job)
1051 struct amdgpu_device *adev = ring->adev;
1052 unsigned vmhub = ring->funcs->vmhub;
1053 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1054 struct amdgpu_vmid *id;
1055 bool gds_switch_needed;
1056 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1060 id = &id_mgr->ids[job->vmid];
1061 gds_switch_needed = ring->funcs->emit_gds_switch && (
1062 id->gds_base != job->gds_base ||
1063 id->gds_size != job->gds_size ||
1064 id->gws_base != job->gws_base ||
1065 id->gws_size != job->gws_size ||
1066 id->oa_base != job->oa_base ||
1067 id->oa_size != job->oa_size);
1069 if (amdgpu_vmid_had_gpu_reset(adev, id))
1072 return vm_flush_needed || gds_switch_needed;
1076 * amdgpu_vm_flush - hardware flush the vm
1078 * @ring: ring to use for flush
1080 * @need_pipe_sync: is pipe sync needed
1082 * Emit a VM flush when it is necessary.
1085 * 0 on success, errno otherwise.
1087 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1089 struct amdgpu_device *adev = ring->adev;
1090 unsigned vmhub = ring->funcs->vmhub;
1091 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1092 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1093 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1094 id->gds_base != job->gds_base ||
1095 id->gds_size != job->gds_size ||
1096 id->gws_base != job->gws_base ||
1097 id->gws_size != job->gws_size ||
1098 id->oa_base != job->oa_base ||
1099 id->oa_size != job->oa_size);
1100 bool vm_flush_needed = job->vm_needs_flush;
1101 bool pasid_mapping_needed = id->pasid != job->pasid ||
1102 !id->pasid_mapping ||
1103 !dma_fence_is_signaled(id->pasid_mapping);
1104 struct dma_fence *fence = NULL;
1105 unsigned patch_offset = 0;
1108 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1109 gds_switch_needed = true;
1110 vm_flush_needed = true;
1111 pasid_mapping_needed = true;
1114 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1115 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1116 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1117 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1118 ring->funcs->emit_wreg;
1120 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1123 if (ring->funcs->init_cond_exec)
1124 patch_offset = amdgpu_ring_init_cond_exec(ring);
1127 amdgpu_ring_emit_pipeline_sync(ring);
1129 if (vm_flush_needed) {
1130 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1131 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1134 if (pasid_mapping_needed)
1135 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1137 if (vm_flush_needed || pasid_mapping_needed) {
1138 r = amdgpu_fence_emit(ring, &fence, 0);
1143 if (vm_flush_needed) {
1144 mutex_lock(&id_mgr->lock);
1145 dma_fence_put(id->last_flush);
1146 id->last_flush = dma_fence_get(fence);
1147 id->current_gpu_reset_count =
1148 atomic_read(&adev->gpu_reset_counter);
1149 mutex_unlock(&id_mgr->lock);
1152 if (pasid_mapping_needed) {
1153 id->pasid = job->pasid;
1154 dma_fence_put(id->pasid_mapping);
1155 id->pasid_mapping = dma_fence_get(fence);
1157 dma_fence_put(fence);
1159 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1160 id->gds_base = job->gds_base;
1161 id->gds_size = job->gds_size;
1162 id->gws_base = job->gws_base;
1163 id->gws_size = job->gws_size;
1164 id->oa_base = job->oa_base;
1165 id->oa_size = job->oa_size;
1166 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1167 job->gds_size, job->gws_base,
1168 job->gws_size, job->oa_base,
1172 if (ring->funcs->patch_cond_exec)
1173 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1175 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1176 if (ring->funcs->emit_switch_buffer) {
1177 amdgpu_ring_emit_switch_buffer(ring);
1178 amdgpu_ring_emit_switch_buffer(ring);
1184 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1187 * @bo: requested buffer object
1189 * Find @bo inside the requested vm.
1190 * Search inside the @bos vm list for the requested vm
1191 * Returns the found bo_va or NULL if none is found
1193 * Object has to be reserved!
1196 * Found bo_va or NULL.
1198 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1199 struct amdgpu_bo *bo)
1201 struct amdgpu_vm_bo_base *base;
1203 for (base = bo->vm_bo; base; base = base->next) {
1207 return container_of(base, struct amdgpu_bo_va, base);
1213 * amdgpu_vm_do_set_ptes - helper to call the right asic function
1215 * @params: see amdgpu_pte_update_params definition
1216 * @bo: PD/PT to update
1217 * @pe: addr of the page entry
1218 * @addr: dst addr to write into pe
1219 * @count: number of page entries to update
1220 * @incr: increase next addr by incr bytes
1221 * @flags: hw access flags
1223 * Traces the parameters and calls the right asic functions
1224 * to setup the page table using the DMA.
1226 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
1227 struct amdgpu_bo *bo,
1228 uint64_t pe, uint64_t addr,
1229 unsigned count, uint32_t incr,
1232 pe += amdgpu_bo_gpu_offset(bo);
1233 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1236 amdgpu_vm_write_pte(params->adev, params->ib, pe,
1237 addr | flags, count, incr);
1240 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
1241 count, incr, flags);
1246 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
1248 * @params: see amdgpu_pte_update_params definition
1249 * @bo: PD/PT to update
1250 * @pe: addr of the page entry
1251 * @addr: dst addr to write into pe
1252 * @count: number of page entries to update
1253 * @incr: increase next addr by incr bytes
1254 * @flags: hw access flags
1256 * Traces the parameters and calls the DMA function to copy the PTEs.
1258 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
1259 struct amdgpu_bo *bo,
1260 uint64_t pe, uint64_t addr,
1261 unsigned count, uint32_t incr,
1264 uint64_t src = (params->src + (addr >> 12) * 8);
1266 pe += amdgpu_bo_gpu_offset(bo);
1267 trace_amdgpu_vm_copy_ptes(pe, src, count);
1269 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
1273 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1275 * @pages_addr: optional DMA address to use for lookup
1276 * @addr: the unmapped addr
1278 * Look up the physical address of the page that the pte resolves
1282 * The pointer for the page table entry.
1284 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1288 /* page table offset */
1289 result = pages_addr[addr >> PAGE_SHIFT];
1291 /* in case cpu page size != gpu page size*/
1292 result |= addr & (~PAGE_MASK);
1294 result &= 0xFFFFFFFFFFFFF000ULL;
1300 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1302 * @params: see amdgpu_pte_update_params definition
1303 * @bo: PD/PT to update
1304 * @pe: kmap addr of the page entry
1305 * @addr: dst addr to write into pe
1306 * @count: number of page entries to update
1307 * @incr: increase next addr by incr bytes
1308 * @flags: hw access flags
1310 * Write count number of PT/PD entries directly.
1312 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
1313 struct amdgpu_bo *bo,
1314 uint64_t pe, uint64_t addr,
1315 unsigned count, uint32_t incr,
1321 pe += (unsigned long)amdgpu_bo_kptr(bo);
1323 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1325 for (i = 0; i < count; i++) {
1326 value = params->pages_addr ?
1327 amdgpu_vm_map_gart(params->pages_addr, addr) :
1329 amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
1337 * amdgpu_vm_wait_pd - Wait for PT BOs to be free.
1339 * @adev: amdgpu_device pointer
1341 * @owner: fence owner
1344 * 0 on success, errno otherwise.
1346 static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1349 struct amdgpu_sync sync;
1352 amdgpu_sync_create(&sync);
1353 amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
1354 r = amdgpu_sync_wait(&sync, true);
1355 amdgpu_sync_free(&sync);
1361 * amdgpu_vm_update_func - helper to call update function
1363 * Calls the update function for both the given BO as well as its shadow.
1365 static void amdgpu_vm_update_func(struct amdgpu_pte_update_params *params,
1366 struct amdgpu_bo *bo,
1367 uint64_t pe, uint64_t addr,
1368 unsigned count, uint32_t incr,
1372 params->func(params, bo->shadow, pe, addr, count, incr, flags);
1373 params->func(params, bo, pe, addr, count, incr, flags);
1377 * amdgpu_vm_update_pde - update a single level in the hierarchy
1379 * @param: parameters for the update
1381 * @parent: parent directory
1382 * @entry: entry to update
1384 * Makes sure the requested entry in parent is up to date.
1386 static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
1387 struct amdgpu_vm *vm,
1388 struct amdgpu_vm_pt *parent,
1389 struct amdgpu_vm_pt *entry)
1391 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1392 uint64_t pde, pt, flags;
1395 /* Don't update huge pages here */
1399 for (level = 0, pbo = bo->parent; pbo; ++level)
1402 level += params->adev->vm_manager.root_level;
1403 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1404 pde = (entry - parent->entries) * 8;
1405 amdgpu_vm_update_func(params, bo, pde, pt, 1, 0, flags);
1409 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1411 * @adev: amdgpu_device pointer
1414 * Mark all PD level as invalid after an error.
1416 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1417 struct amdgpu_vm *vm)
1419 struct amdgpu_vm_pt_cursor cursor;
1420 struct amdgpu_vm_pt *entry;
1422 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry)
1423 if (entry->base.bo && !entry->base.moved)
1424 amdgpu_vm_bo_relocated(&entry->base);
1428 * amdgpu_vm_update_directories - make sure that all directories are valid
1430 * @adev: amdgpu_device pointer
1433 * Makes sure all directories are up to date.
1436 * 0 for success, error for failure.
1438 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1439 struct amdgpu_vm *vm)
1441 struct amdgpu_pte_update_params params;
1442 struct amdgpu_job *job;
1446 if (list_empty(&vm->relocated))
1450 memset(¶ms, 0, sizeof(params));
1453 if (vm->use_cpu_for_update) {
1454 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
1458 params.func = amdgpu_vm_cpu_set_ptes;
1461 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1465 params.ib = &job->ibs[0];
1466 params.func = amdgpu_vm_do_set_ptes;
1469 while (!list_empty(&vm->relocated)) {
1470 struct amdgpu_vm_pt *pt, *entry;
1472 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1474 amdgpu_vm_bo_idle(&entry->base);
1476 pt = amdgpu_vm_pt_parent(entry);
1480 amdgpu_vm_update_pde(¶ms, vm, pt, entry);
1482 if (!vm->use_cpu_for_update &&
1483 (ndw - params.ib->length_dw) < 32)
1487 if (vm->use_cpu_for_update) {
1490 amdgpu_asic_flush_hdp(adev, NULL);
1491 } else if (params.ib->length_dw == 0) {
1492 amdgpu_job_free(job);
1494 struct amdgpu_bo *root = vm->root.base.bo;
1495 struct amdgpu_ring *ring;
1496 struct dma_fence *fence;
1498 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring,
1501 amdgpu_ring_pad_ib(ring, params.ib);
1502 amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
1503 AMDGPU_FENCE_OWNER_VM, false);
1504 WARN_ON(params.ib->length_dw > ndw);
1505 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM,
1510 amdgpu_bo_fence(root, fence, true);
1511 dma_fence_put(vm->last_update);
1512 vm->last_update = fence;
1515 if (!list_empty(&vm->relocated))
1521 amdgpu_vm_invalidate_pds(adev, vm);
1522 amdgpu_job_free(job);
1527 * amdgpu_vm_update_flags - figure out flags for PTE updates
1529 * Make sure to set the right flags for the PTEs at the desired level.
1531 static void amdgpu_vm_update_flags(struct amdgpu_pte_update_params *params,
1532 struct amdgpu_bo *bo, unsigned level,
1533 uint64_t pe, uint64_t addr,
1534 unsigned count, uint32_t incr,
1538 if (level != AMDGPU_VM_PTB) {
1539 flags |= AMDGPU_PDE_PTE;
1540 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1542 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1543 !(flags & AMDGPU_PTE_VALID) &&
1544 !(flags & AMDGPU_PTE_PRT)) {
1546 /* Workaround for fault priority problem on GMC9 */
1547 flags |= AMDGPU_PTE_EXECUTABLE;
1550 amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags);
1554 * amdgpu_vm_fragment - get fragment for PTEs
1556 * @params: see amdgpu_pte_update_params definition
1557 * @start: first PTE to handle
1558 * @end: last PTE to handle
1559 * @flags: hw mapping flags
1560 * @frag: resulting fragment size
1561 * @frag_end: end of this fragment
1563 * Returns the first possible fragment for the start and end address.
1565 static void amdgpu_vm_fragment(struct amdgpu_pte_update_params *params,
1566 uint64_t start, uint64_t end, uint64_t flags,
1567 unsigned int *frag, uint64_t *frag_end)
1570 * The MC L1 TLB supports variable sized pages, based on a fragment
1571 * field in the PTE. When this field is set to a non-zero value, page
1572 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1573 * flags are considered valid for all PTEs within the fragment range
1574 * and corresponding mappings are assumed to be physically contiguous.
1576 * The L1 TLB can store a single PTE for the whole fragment,
1577 * significantly increasing the space available for translation
1578 * caching. This leads to large improvements in throughput when the
1579 * TLB is under pressure.
1581 * The L2 TLB distributes small and large fragments into two
1582 * asymmetric partitions. The large fragment cache is significantly
1583 * larger. Thus, we try to use large fragments wherever possible.
1584 * Userspace can support this by aligning virtual base address and
1585 * allocation size to the fragment size.
1587 * Starting with Vega10 the fragment size only controls the L1. The L2
1588 * is now directly feed with small/huge/giant pages from the walker.
1592 if (params->adev->asic_type < CHIP_VEGA10)
1593 max_frag = params->adev->vm_manager.fragment_size;
1597 /* system pages are non continuously */
1604 /* This intentionally wraps around if no bit is set */
1605 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1606 if (*frag >= max_frag) {
1608 *frag_end = end & ~((1ULL << max_frag) - 1);
1610 *frag_end = start + (1 << *frag);
1615 * amdgpu_vm_update_ptes - make sure that page tables are valid
1617 * @params: see amdgpu_pte_update_params definition
1618 * @start: start of GPU address range
1619 * @end: end of GPU address range
1620 * @dst: destination address to map to, the next dst inside the function
1621 * @flags: mapping flags
1623 * Update the page tables in the range @start - @end.
1626 * 0 for success, -EINVAL for failure.
1628 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1629 uint64_t start, uint64_t end,
1630 uint64_t dst, uint64_t flags)
1632 struct amdgpu_device *adev = params->adev;
1633 struct amdgpu_vm_pt_cursor cursor;
1634 uint64_t frag_start = start, frag_end;
1637 /* figure out the initial fragment */
1638 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1640 /* walk over the address space and update the PTs */
1641 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1642 while (cursor.pfn < end) {
1643 struct amdgpu_bo *pt = cursor.entry->base.bo;
1644 unsigned shift, parent_shift, mask;
1645 uint64_t incr, entry_end, pe_start;
1650 /* The root level can't be a huge page */
1651 if (cursor.level == adev->vm_manager.root_level) {
1652 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1657 /* If it isn't already handled it can't be a huge page */
1658 if (cursor.entry->huge) {
1659 /* Add the entry to the relocated list to update it. */
1660 cursor.entry->huge = false;
1661 amdgpu_vm_bo_relocated(&cursor.entry->base);
1664 shift = amdgpu_vm_level_shift(adev, cursor.level);
1665 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1666 if (adev->asic_type < CHIP_VEGA10) {
1667 /* No huge page support before GMC v9 */
1668 if (cursor.level != AMDGPU_VM_PTB) {
1669 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1673 } else if (frag < shift) {
1674 /* We can't use this level when the fragment size is
1675 * smaller than the address shift. Go to the next
1676 * child entry and try again.
1678 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1681 } else if (frag >= parent_shift &&
1682 cursor.level - 1 != adev->vm_manager.root_level) {
1683 /* If the fragment size is even larger than the parent
1684 * shift we should go up one level and check it again
1685 * unless one level up is the root level.
1687 if (!amdgpu_vm_pt_ancestor(&cursor))
1692 /* Looks good so far, calculate parameters for the update */
1693 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1694 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1695 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1696 entry_end = (uint64_t)(mask + 1) << shift;
1697 entry_end += cursor.pfn & ~(entry_end - 1);
1698 entry_end = min(entry_end, end);
1701 uint64_t upd_end = min(entry_end, frag_end);
1702 unsigned nptes = (upd_end - frag_start) >> shift;
1704 amdgpu_vm_update_flags(params, pt, cursor.level,
1705 pe_start, dst, nptes, incr,
1706 flags | AMDGPU_PTE_FRAG(frag));
1708 pe_start += nptes * 8;
1709 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1711 frag_start = upd_end;
1712 if (frag_start >= frag_end) {
1713 /* figure out the next fragment */
1714 amdgpu_vm_fragment(params, frag_start, end,
1715 flags, &frag, &frag_end);
1719 } while (frag_start < entry_end);
1721 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1722 /* Mark all child entries as huge */
1723 while (cursor.pfn < frag_start) {
1724 cursor.entry->huge = true;
1725 amdgpu_vm_pt_next(adev, &cursor);
1728 } else if (frag >= shift) {
1729 /* or just move on to the next on the same level. */
1730 amdgpu_vm_pt_next(adev, &cursor);
1738 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1740 * @adev: amdgpu_device pointer
1741 * @exclusive: fence we need to sync to
1742 * @pages_addr: DMA addresses to use for mapping
1744 * @start: start of mapped range
1745 * @last: last mapped entry
1746 * @flags: flags for the entries
1747 * @addr: addr to set the area to
1748 * @fence: optional resulting fence
1750 * Fill in the page table entries between @start and @last.
1753 * 0 for success, -EINVAL for failure.
1755 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1756 struct dma_fence *exclusive,
1757 dma_addr_t *pages_addr,
1758 struct amdgpu_vm *vm,
1759 uint64_t start, uint64_t last,
1760 uint64_t flags, uint64_t addr,
1761 struct dma_fence **fence)
1763 struct amdgpu_ring *ring;
1764 void *owner = AMDGPU_FENCE_OWNER_VM;
1765 unsigned nptes, ncmds, ndw;
1766 struct amdgpu_job *job;
1767 struct amdgpu_pte_update_params params;
1768 struct dma_fence *f = NULL;
1771 memset(¶ms, 0, sizeof(params));
1775 /* sync to everything on unmapping */
1776 if (!(flags & AMDGPU_PTE_VALID))
1777 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1779 if (vm->use_cpu_for_update) {
1780 /* params.src is used as flag to indicate system Memory */
1784 /* Wait for PT BOs to be idle. PTs share the same resv. object
1787 r = amdgpu_vm_wait_pd(adev, vm, owner);
1791 /* Wait for any BO move to be completed */
1793 r = dma_fence_wait(exclusive, true);
1798 params.func = amdgpu_vm_cpu_set_ptes;
1799 params.pages_addr = pages_addr;
1800 return amdgpu_vm_update_ptes(¶ms, start, last + 1,
1804 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
1806 nptes = last - start + 1;
1809 * reserve space for two commands every (1 << BLOCK_SIZE)
1810 * entries or 2k dwords (whatever is smaller)
1812 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1814 /* The second command is for the shadow pagetables. */
1815 if (vm->root.base.bo->shadow)
1822 /* copy commands needed */
1823 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1828 params.func = amdgpu_vm_do_copy_ptes;
1831 /* set page commands needed */
1834 /* extra commands for begin/end fragments */
1835 ncmds = 2 * adev->vm_manager.fragment_size;
1836 if (vm->root.base.bo->shadow)
1841 params.func = amdgpu_vm_do_set_ptes;
1844 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1848 params.ib = &job->ibs[0];
1854 /* Put the PTEs at the end of the IB. */
1855 i = ndw - nptes * 2;
1856 pte= (uint64_t *)&(job->ibs->ptr[i]);
1857 params.src = job->ibs->gpu_addr + i * 4;
1859 for (i = 0; i < nptes; ++i) {
1860 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1861 AMDGPU_GPU_PAGE_SIZE);
1867 r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1871 r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1876 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1880 amdgpu_ring_pad_ib(ring, params.ib);
1881 WARN_ON(params.ib->length_dw > ndw);
1882 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
1886 amdgpu_bo_fence(vm->root.base.bo, f, true);
1887 dma_fence_put(*fence);
1892 amdgpu_job_free(job);
1897 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1899 * @adev: amdgpu_device pointer
1900 * @exclusive: fence we need to sync to
1901 * @pages_addr: DMA addresses to use for mapping
1903 * @mapping: mapped range and flags to use for the update
1904 * @flags: HW flags for the mapping
1905 * @nodes: array of drm_mm_nodes with the MC addresses
1906 * @fence: optional resulting fence
1908 * Split the mapping into smaller chunks so that each update fits
1912 * 0 for success, -EINVAL for failure.
1914 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1915 struct dma_fence *exclusive,
1916 dma_addr_t *pages_addr,
1917 struct amdgpu_vm *vm,
1918 struct amdgpu_bo_va_mapping *mapping,
1920 struct drm_mm_node *nodes,
1921 struct dma_fence **fence)
1923 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1924 uint64_t pfn, start = mapping->start;
1927 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1928 * but in case of something, we filter the flags in first place
1930 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1931 flags &= ~AMDGPU_PTE_READABLE;
1932 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1933 flags &= ~AMDGPU_PTE_WRITEABLE;
1935 flags &= ~AMDGPU_PTE_EXECUTABLE;
1936 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1938 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1939 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1941 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1942 (adev->asic_type >= CHIP_VEGA10)) {
1943 flags |= AMDGPU_PTE_PRT;
1944 flags &= ~AMDGPU_PTE_VALID;
1947 trace_amdgpu_vm_bo_update(mapping);
1949 pfn = mapping->offset >> PAGE_SHIFT;
1951 while (pfn >= nodes->size) {
1958 dma_addr_t *dma_addr = NULL;
1959 uint64_t max_entries;
1960 uint64_t addr, last;
1963 addr = nodes->start << PAGE_SHIFT;
1964 max_entries = (nodes->size - pfn) *
1965 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1968 max_entries = S64_MAX;
1974 max_entries = min(max_entries, 16ull * 1024ull);
1976 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1978 uint64_t idx = pfn + count;
1980 if (pages_addr[idx] !=
1981 (pages_addr[idx - 1] + PAGE_SIZE))
1985 if (count < min_linear_pages) {
1986 addr = pfn << PAGE_SHIFT;
1987 dma_addr = pages_addr;
1989 addr = pages_addr[pfn];
1990 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1993 } else if (flags & AMDGPU_PTE_VALID) {
1994 addr += adev->vm_manager.vram_base_offset;
1995 addr += pfn << PAGE_SHIFT;
1998 last = min((uint64_t)mapping->last, start + max_entries - 1);
1999 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
2000 start, last, flags, addr,
2005 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
2006 if (nodes && nodes->size == pfn) {
2012 } while (unlikely(start != mapping->last + 1));
2018 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
2020 * @adev: amdgpu_device pointer
2021 * @bo_va: requested BO and VM object
2022 * @clear: if true clear the entries
2024 * Fill in the page table entries for @bo_va.
2027 * 0 for success, -EINVAL for failure.
2029 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2030 struct amdgpu_bo_va *bo_va,
2033 struct amdgpu_bo *bo = bo_va->base.bo;
2034 struct amdgpu_vm *vm = bo_va->base.vm;
2035 struct amdgpu_bo_va_mapping *mapping;
2036 dma_addr_t *pages_addr = NULL;
2037 struct ttm_mem_reg *mem;
2038 struct drm_mm_node *nodes;
2039 struct dma_fence *exclusive, **last_update;
2048 struct ttm_dma_tt *ttm;
2051 nodes = mem->mm_node;
2052 if (mem->mem_type == TTM_PL_TT) {
2053 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
2054 pages_addr = ttm->dma_address;
2056 exclusive = reservation_object_get_excl(bo->tbo.resv);
2060 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
2064 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
2065 last_update = &vm->last_update;
2067 last_update = &bo_va->last_pt_update;
2069 if (!clear && bo_va->base.moved) {
2070 bo_va->base.moved = false;
2071 list_splice_init(&bo_va->valids, &bo_va->invalids);
2073 } else if (bo_va->cleared != clear) {
2074 list_splice_init(&bo_va->valids, &bo_va->invalids);
2077 list_for_each_entry(mapping, &bo_va->invalids, list) {
2078 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
2079 mapping, flags, nodes,
2085 if (vm->use_cpu_for_update) {
2088 amdgpu_asic_flush_hdp(adev, NULL);
2091 /* If the BO is not in its preferred location add it back to
2092 * the evicted list so that it gets validated again on the
2093 * next command submission.
2095 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2096 uint32_t mem_type = bo->tbo.mem.mem_type;
2098 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
2099 amdgpu_vm_bo_evicted(&bo_va->base);
2101 amdgpu_vm_bo_idle(&bo_va->base);
2103 amdgpu_vm_bo_done(&bo_va->base);
2106 list_splice_init(&bo_va->invalids, &bo_va->valids);
2107 bo_va->cleared = clear;
2109 if (trace_amdgpu_vm_bo_mapping_enabled()) {
2110 list_for_each_entry(mapping, &bo_va->valids, list)
2111 trace_amdgpu_vm_bo_mapping(mapping);
2118 * amdgpu_vm_update_prt_state - update the global PRT state
2120 * @adev: amdgpu_device pointer
2122 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
2124 unsigned long flags;
2127 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
2128 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
2129 adev->gmc.gmc_funcs->set_prt(adev, enable);
2130 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
2134 * amdgpu_vm_prt_get - add a PRT user
2136 * @adev: amdgpu_device pointer
2138 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
2140 if (!adev->gmc.gmc_funcs->set_prt)
2143 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
2144 amdgpu_vm_update_prt_state(adev);
2148 * amdgpu_vm_prt_put - drop a PRT user
2150 * @adev: amdgpu_device pointer
2152 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
2154 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
2155 amdgpu_vm_update_prt_state(adev);
2159 * amdgpu_vm_prt_cb - callback for updating the PRT status
2161 * @fence: fence for the callback
2162 * @_cb: the callback function
2164 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
2166 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
2168 amdgpu_vm_prt_put(cb->adev);
2173 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
2175 * @adev: amdgpu_device pointer
2176 * @fence: fence for the callback
2178 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
2179 struct dma_fence *fence)
2181 struct amdgpu_prt_cb *cb;
2183 if (!adev->gmc.gmc_funcs->set_prt)
2186 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2188 /* Last resort when we are OOM */
2190 dma_fence_wait(fence, false);
2192 amdgpu_vm_prt_put(adev);
2195 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2197 amdgpu_vm_prt_cb(fence, &cb->cb);
2202 * amdgpu_vm_free_mapping - free a mapping
2204 * @adev: amdgpu_device pointer
2206 * @mapping: mapping to be freed
2207 * @fence: fence of the unmap operation
2209 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2211 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2212 struct amdgpu_vm *vm,
2213 struct amdgpu_bo_va_mapping *mapping,
2214 struct dma_fence *fence)
2216 if (mapping->flags & AMDGPU_PTE_PRT)
2217 amdgpu_vm_add_prt_cb(adev, fence);
2222 * amdgpu_vm_prt_fini - finish all prt mappings
2224 * @adev: amdgpu_device pointer
2227 * Register a cleanup callback to disable PRT support after VM dies.
2229 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2231 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
2232 struct dma_fence *excl, **shared;
2233 unsigned i, shared_count;
2236 r = reservation_object_get_fences_rcu(resv, &excl,
2237 &shared_count, &shared);
2239 /* Not enough memory to grab the fence list, as last resort
2240 * block for all the fences to complete.
2242 reservation_object_wait_timeout_rcu(resv, true, false,
2243 MAX_SCHEDULE_TIMEOUT);
2247 /* Add a callback for each fence in the reservation object */
2248 amdgpu_vm_prt_get(adev);
2249 amdgpu_vm_add_prt_cb(adev, excl);
2251 for (i = 0; i < shared_count; ++i) {
2252 amdgpu_vm_prt_get(adev);
2253 amdgpu_vm_add_prt_cb(adev, shared[i]);
2260 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2262 * @adev: amdgpu_device pointer
2264 * @fence: optional resulting fence (unchanged if no work needed to be done
2265 * or if an error occurred)
2267 * Make sure all freed BOs are cleared in the PT.
2268 * PTs have to be reserved and mutex must be locked!
2274 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2275 struct amdgpu_vm *vm,
2276 struct dma_fence **fence)
2278 struct amdgpu_bo_va_mapping *mapping;
2279 uint64_t init_pte_value = 0;
2280 struct dma_fence *f = NULL;
2283 while (!list_empty(&vm->freed)) {
2284 mapping = list_first_entry(&vm->freed,
2285 struct amdgpu_bo_va_mapping, list);
2286 list_del(&mapping->list);
2288 if (vm->pte_support_ats &&
2289 mapping->start < AMDGPU_GMC_HOLE_START)
2290 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2292 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
2293 mapping->start, mapping->last,
2294 init_pte_value, 0, &f);
2295 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2303 dma_fence_put(*fence);
2314 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2316 * @adev: amdgpu_device pointer
2319 * Make sure all BOs which are moved are updated in the PTs.
2324 * PTs have to be reserved!
2326 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2327 struct amdgpu_vm *vm)
2329 struct amdgpu_bo_va *bo_va, *tmp;
2330 struct reservation_object *resv;
2334 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2335 /* Per VM BOs never need to bo cleared in the page tables */
2336 r = amdgpu_vm_bo_update(adev, bo_va, false);
2341 spin_lock(&vm->invalidated_lock);
2342 while (!list_empty(&vm->invalidated)) {
2343 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2345 resv = bo_va->base.bo->tbo.resv;
2346 spin_unlock(&vm->invalidated_lock);
2348 /* Try to reserve the BO to avoid clearing its ptes */
2349 if (!amdgpu_vm_debug && reservation_object_trylock(resv))
2351 /* Somebody else is using the BO right now */
2355 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2360 reservation_object_unlock(resv);
2361 spin_lock(&vm->invalidated_lock);
2363 spin_unlock(&vm->invalidated_lock);
2369 * amdgpu_vm_bo_add - add a bo to a specific vm
2371 * @adev: amdgpu_device pointer
2373 * @bo: amdgpu buffer object
2375 * Add @bo into the requested vm.
2376 * Add @bo to the list of bos associated with the vm
2379 * Newly added bo_va or NULL for failure
2381 * Object has to be reserved!
2383 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2384 struct amdgpu_vm *vm,
2385 struct amdgpu_bo *bo)
2387 struct amdgpu_bo_va *bo_va;
2389 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2390 if (bo_va == NULL) {
2393 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2395 bo_va->ref_count = 1;
2396 INIT_LIST_HEAD(&bo_va->valids);
2397 INIT_LIST_HEAD(&bo_va->invalids);
2404 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2406 * @adev: amdgpu_device pointer
2407 * @bo_va: bo_va to store the address
2408 * @mapping: the mapping to insert
2410 * Insert a new mapping into all structures.
2412 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2413 struct amdgpu_bo_va *bo_va,
2414 struct amdgpu_bo_va_mapping *mapping)
2416 struct amdgpu_vm *vm = bo_va->base.vm;
2417 struct amdgpu_bo *bo = bo_va->base.bo;
2419 mapping->bo_va = bo_va;
2420 list_add(&mapping->list, &bo_va->invalids);
2421 amdgpu_vm_it_insert(mapping, &vm->va);
2423 if (mapping->flags & AMDGPU_PTE_PRT)
2424 amdgpu_vm_prt_get(adev);
2426 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
2427 !bo_va->base.moved) {
2428 list_move(&bo_va->base.vm_status, &vm->moved);
2430 trace_amdgpu_vm_bo_map(bo_va, mapping);
2434 * amdgpu_vm_bo_map - map bo inside a vm
2436 * @adev: amdgpu_device pointer
2437 * @bo_va: bo_va to store the address
2438 * @saddr: where to map the BO
2439 * @offset: requested offset in the BO
2440 * @size: BO size in bytes
2441 * @flags: attributes of pages (read/write/valid/etc.)
2443 * Add a mapping of the BO at the specefied addr into the VM.
2446 * 0 for success, error for failure.
2448 * Object has to be reserved and unreserved outside!
2450 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2451 struct amdgpu_bo_va *bo_va,
2452 uint64_t saddr, uint64_t offset,
2453 uint64_t size, uint64_t flags)
2455 struct amdgpu_bo_va_mapping *mapping, *tmp;
2456 struct amdgpu_bo *bo = bo_va->base.bo;
2457 struct amdgpu_vm *vm = bo_va->base.vm;
2460 /* validate the parameters */
2461 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2462 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2465 /* make sure object fit at this offset */
2466 eaddr = saddr + size - 1;
2467 if (saddr >= eaddr ||
2468 (bo && offset + size > amdgpu_bo_size(bo)))
2471 saddr /= AMDGPU_GPU_PAGE_SIZE;
2472 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2474 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2476 /* bo and tmp overlap, invalid addr */
2477 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2478 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2479 tmp->start, tmp->last + 1);
2483 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2487 mapping->start = saddr;
2488 mapping->last = eaddr;
2489 mapping->offset = offset;
2490 mapping->flags = flags;
2492 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2498 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2500 * @adev: amdgpu_device pointer
2501 * @bo_va: bo_va to store the address
2502 * @saddr: where to map the BO
2503 * @offset: requested offset in the BO
2504 * @size: BO size in bytes
2505 * @flags: attributes of pages (read/write/valid/etc.)
2507 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2508 * mappings as we do so.
2511 * 0 for success, error for failure.
2513 * Object has to be reserved and unreserved outside!
2515 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2516 struct amdgpu_bo_va *bo_va,
2517 uint64_t saddr, uint64_t offset,
2518 uint64_t size, uint64_t flags)
2520 struct amdgpu_bo_va_mapping *mapping;
2521 struct amdgpu_bo *bo = bo_va->base.bo;
2525 /* validate the parameters */
2526 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2527 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2530 /* make sure object fit at this offset */
2531 eaddr = saddr + size - 1;
2532 if (saddr >= eaddr ||
2533 (bo && offset + size > amdgpu_bo_size(bo)))
2536 /* Allocate all the needed memory */
2537 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2541 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2547 saddr /= AMDGPU_GPU_PAGE_SIZE;
2548 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2550 mapping->start = saddr;
2551 mapping->last = eaddr;
2552 mapping->offset = offset;
2553 mapping->flags = flags;
2555 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2561 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2563 * @adev: amdgpu_device pointer
2564 * @bo_va: bo_va to remove the address from
2565 * @saddr: where to the BO is mapped
2567 * Remove a mapping of the BO at the specefied addr from the VM.
2570 * 0 for success, error for failure.
2572 * Object has to be reserved and unreserved outside!
2574 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2575 struct amdgpu_bo_va *bo_va,
2578 struct amdgpu_bo_va_mapping *mapping;
2579 struct amdgpu_vm *vm = bo_va->base.vm;
2582 saddr /= AMDGPU_GPU_PAGE_SIZE;
2584 list_for_each_entry(mapping, &bo_va->valids, list) {
2585 if (mapping->start == saddr)
2589 if (&mapping->list == &bo_va->valids) {
2592 list_for_each_entry(mapping, &bo_va->invalids, list) {
2593 if (mapping->start == saddr)
2597 if (&mapping->list == &bo_va->invalids)
2601 list_del(&mapping->list);
2602 amdgpu_vm_it_remove(mapping, &vm->va);
2603 mapping->bo_va = NULL;
2604 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2607 list_add(&mapping->list, &vm->freed);
2609 amdgpu_vm_free_mapping(adev, vm, mapping,
2610 bo_va->last_pt_update);
2616 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2618 * @adev: amdgpu_device pointer
2619 * @vm: VM structure to use
2620 * @saddr: start of the range
2621 * @size: size of the range
2623 * Remove all mappings in a range, split them as appropriate.
2626 * 0 for success, error for failure.
2628 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2629 struct amdgpu_vm *vm,
2630 uint64_t saddr, uint64_t size)
2632 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2636 eaddr = saddr + size - 1;
2637 saddr /= AMDGPU_GPU_PAGE_SIZE;
2638 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2640 /* Allocate all the needed memory */
2641 before = kzalloc(sizeof(*before), GFP_KERNEL);
2644 INIT_LIST_HEAD(&before->list);
2646 after = kzalloc(sizeof(*after), GFP_KERNEL);
2651 INIT_LIST_HEAD(&after->list);
2653 /* Now gather all removed mappings */
2654 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2656 /* Remember mapping split at the start */
2657 if (tmp->start < saddr) {
2658 before->start = tmp->start;
2659 before->last = saddr - 1;
2660 before->offset = tmp->offset;
2661 before->flags = tmp->flags;
2662 before->bo_va = tmp->bo_va;
2663 list_add(&before->list, &tmp->bo_va->invalids);
2666 /* Remember mapping split at the end */
2667 if (tmp->last > eaddr) {
2668 after->start = eaddr + 1;
2669 after->last = tmp->last;
2670 after->offset = tmp->offset;
2671 after->offset += after->start - tmp->start;
2672 after->flags = tmp->flags;
2673 after->bo_va = tmp->bo_va;
2674 list_add(&after->list, &tmp->bo_va->invalids);
2677 list_del(&tmp->list);
2678 list_add(&tmp->list, &removed);
2680 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2683 /* And free them up */
2684 list_for_each_entry_safe(tmp, next, &removed, list) {
2685 amdgpu_vm_it_remove(tmp, &vm->va);
2686 list_del(&tmp->list);
2688 if (tmp->start < saddr)
2690 if (tmp->last > eaddr)
2694 list_add(&tmp->list, &vm->freed);
2695 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2698 /* Insert partial mapping before the range */
2699 if (!list_empty(&before->list)) {
2700 amdgpu_vm_it_insert(before, &vm->va);
2701 if (before->flags & AMDGPU_PTE_PRT)
2702 amdgpu_vm_prt_get(adev);
2707 /* Insert partial mapping after the range */
2708 if (!list_empty(&after->list)) {
2709 amdgpu_vm_it_insert(after, &vm->va);
2710 if (after->flags & AMDGPU_PTE_PRT)
2711 amdgpu_vm_prt_get(adev);
2720 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2722 * @vm: the requested VM
2723 * @addr: the address
2725 * Find a mapping by it's address.
2728 * The amdgpu_bo_va_mapping matching for addr or NULL
2731 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2734 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2738 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2740 * @vm: the requested vm
2741 * @ticket: CS ticket
2743 * Trace all mappings of BOs reserved during a command submission.
2745 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2747 struct amdgpu_bo_va_mapping *mapping;
2749 if (!trace_amdgpu_vm_bo_cs_enabled())
2752 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2753 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2754 if (mapping->bo_va && mapping->bo_va->base.bo) {
2755 struct amdgpu_bo *bo;
2757 bo = mapping->bo_va->base.bo;
2758 if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
2762 trace_amdgpu_vm_bo_cs(mapping);
2767 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2769 * @adev: amdgpu_device pointer
2770 * @bo_va: requested bo_va
2772 * Remove @bo_va->bo from the requested vm.
2774 * Object have to be reserved!
2776 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2777 struct amdgpu_bo_va *bo_va)
2779 struct amdgpu_bo_va_mapping *mapping, *next;
2780 struct amdgpu_bo *bo = bo_va->base.bo;
2781 struct amdgpu_vm *vm = bo_va->base.vm;
2782 struct amdgpu_vm_bo_base **base;
2785 if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2786 vm->bulk_moveable = false;
2788 for (base = &bo_va->base.bo->vm_bo; *base;
2789 base = &(*base)->next) {
2790 if (*base != &bo_va->base)
2793 *base = bo_va->base.next;
2798 spin_lock(&vm->invalidated_lock);
2799 list_del(&bo_va->base.vm_status);
2800 spin_unlock(&vm->invalidated_lock);
2802 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2803 list_del(&mapping->list);
2804 amdgpu_vm_it_remove(mapping, &vm->va);
2805 mapping->bo_va = NULL;
2806 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2807 list_add(&mapping->list, &vm->freed);
2809 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2810 list_del(&mapping->list);
2811 amdgpu_vm_it_remove(mapping, &vm->va);
2812 amdgpu_vm_free_mapping(adev, vm, mapping,
2813 bo_va->last_pt_update);
2816 dma_fence_put(bo_va->last_pt_update);
2821 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2823 * @adev: amdgpu_device pointer
2824 * @bo: amdgpu buffer object
2825 * @evicted: is the BO evicted
2827 * Mark @bo as invalid.
2829 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2830 struct amdgpu_bo *bo, bool evicted)
2832 struct amdgpu_vm_bo_base *bo_base;
2834 /* shadow bo doesn't have bo base, its validation needs its parent */
2835 if (bo->parent && bo->parent->shadow == bo)
2838 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2839 struct amdgpu_vm *vm = bo_base->vm;
2841 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2842 amdgpu_vm_bo_evicted(bo_base);
2848 bo_base->moved = true;
2850 if (bo->tbo.type == ttm_bo_type_kernel)
2851 amdgpu_vm_bo_relocated(bo_base);
2852 else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2853 amdgpu_vm_bo_moved(bo_base);
2855 amdgpu_vm_bo_invalidated(bo_base);
2860 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2865 * VM page table as power of two
2867 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2869 /* Total bits covered by PD + PTs */
2870 unsigned bits = ilog2(vm_size) + 18;
2872 /* Make sure the PD is 4K in size up to 8GB address space.
2873 Above that split equal between PD and PTs */
2877 return ((bits + 3) / 2);
2881 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2883 * @adev: amdgpu_device pointer
2884 * @min_vm_size: the minimum vm size in GB if it's set auto
2885 * @fragment_size_default: Default PTE fragment size
2886 * @max_level: max VMPT level
2887 * @max_bits: max address space size in bits
2890 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2891 uint32_t fragment_size_default, unsigned max_level,
2894 unsigned int max_size = 1 << (max_bits - 30);
2895 unsigned int vm_size;
2898 /* adjust vm size first */
2899 if (amdgpu_vm_size != -1) {
2900 vm_size = amdgpu_vm_size;
2901 if (vm_size > max_size) {
2902 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2903 amdgpu_vm_size, max_size);
2908 unsigned int phys_ram_gb;
2910 /* Optimal VM size depends on the amount of physical
2911 * RAM available. Underlying requirements and
2914 * - Need to map system memory and VRAM from all GPUs
2915 * - VRAM from other GPUs not known here
2916 * - Assume VRAM <= system memory
2917 * - On GFX8 and older, VM space can be segmented for
2919 * - Need to allow room for fragmentation, guard pages etc.
2921 * This adds up to a rough guess of system memory x3.
2922 * Round up to power of two to maximize the available
2923 * VM size with the given page table size.
2926 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2927 (1 << 30) - 1) >> 30;
2928 vm_size = roundup_pow_of_two(
2929 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2932 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2934 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2935 if (amdgpu_vm_block_size != -1)
2936 tmp >>= amdgpu_vm_block_size - 9;
2937 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2938 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2939 switch (adev->vm_manager.num_level) {
2941 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2944 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2947 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2950 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2952 /* block size depends on vm size and hw setup*/
2953 if (amdgpu_vm_block_size != -1)
2954 adev->vm_manager.block_size =
2955 min((unsigned)amdgpu_vm_block_size, max_bits
2956 - AMDGPU_GPU_PAGE_SHIFT
2957 - 9 * adev->vm_manager.num_level);
2958 else if (adev->vm_manager.num_level > 1)
2959 adev->vm_manager.block_size = 9;
2961 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2963 if (amdgpu_vm_fragment_size == -1)
2964 adev->vm_manager.fragment_size = fragment_size_default;
2966 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2968 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2969 vm_size, adev->vm_manager.num_level + 1,
2970 adev->vm_manager.block_size,
2971 adev->vm_manager.fragment_size);
2974 static struct amdgpu_retryfault_hashtable *init_fault_hash(void)
2976 struct amdgpu_retryfault_hashtable *fault_hash;
2978 fault_hash = kmalloc(sizeof(*fault_hash), GFP_KERNEL);
2982 INIT_CHASH_TABLE(fault_hash->hash,
2983 AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
2984 spin_lock_init(&fault_hash->lock);
2985 fault_hash->count = 0;
2991 * amdgpu_vm_init - initialize a vm instance
2993 * @adev: amdgpu_device pointer
2995 * @vm_context: Indicates if it GFX or Compute context
2996 * @pasid: Process address space identifier
3001 * 0 for success, error for failure.
3003 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3004 int vm_context, unsigned int pasid)
3006 struct amdgpu_bo_param bp;
3007 struct amdgpu_bo *root;
3010 vm->va = RB_ROOT_CACHED;
3011 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3012 vm->reserved_vmid[i] = NULL;
3013 INIT_LIST_HEAD(&vm->evicted);
3014 INIT_LIST_HEAD(&vm->relocated);
3015 INIT_LIST_HEAD(&vm->moved);
3016 INIT_LIST_HEAD(&vm->idle);
3017 INIT_LIST_HEAD(&vm->invalidated);
3018 spin_lock_init(&vm->invalidated_lock);
3019 INIT_LIST_HEAD(&vm->freed);
3021 /* create scheduler entity for page table updates */
3022 r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
3023 adev->vm_manager.vm_pte_num_rqs, NULL);
3027 vm->pte_support_ats = false;
3029 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
3030 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3031 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3033 if (adev->asic_type == CHIP_RAVEN)
3034 vm->pte_support_ats = true;
3036 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3037 AMDGPU_VM_USE_CPU_FOR_GFX);
3039 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3040 vm->use_cpu_for_update ? "CPU" : "SDMA");
3041 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3042 "CPU update of VM recommended only for large BAR system\n");
3043 vm->last_update = NULL;
3045 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
3046 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
3047 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
3048 r = amdgpu_bo_create(adev, &bp, &root);
3050 goto error_free_sched_entity;
3052 r = amdgpu_bo_reserve(root, true);
3054 goto error_free_root;
3056 r = reservation_object_reserve_shared(root->tbo.resv, 1);
3058 goto error_unreserve;
3060 r = amdgpu_vm_clear_bo(adev, vm, root,
3061 adev->vm_manager.root_level,
3062 vm->pte_support_ats);
3064 goto error_unreserve;
3066 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
3067 amdgpu_bo_unreserve(vm->root.base.bo);
3070 unsigned long flags;
3072 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3073 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3075 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3077 goto error_free_root;
3082 vm->fault_hash = init_fault_hash();
3083 if (!vm->fault_hash) {
3085 goto error_free_root;
3088 INIT_KFIFO(vm->faults);
3093 amdgpu_bo_unreserve(vm->root.base.bo);
3096 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3097 amdgpu_bo_unref(&vm->root.base.bo);
3098 vm->root.base.bo = NULL;
3100 error_free_sched_entity:
3101 drm_sched_entity_destroy(&vm->entity);
3107 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3109 * @adev: amdgpu_device pointer
3112 * This only works on GFX VMs that don't have any BOs added and no
3113 * page tables allocated yet.
3115 * Changes the following VM parameters:
3116 * - use_cpu_for_update
3117 * - pte_supports_ats
3118 * - pasid (old PASID is released, because compute manages its own PASIDs)
3120 * Reinitializes the page directory to reflect the changed ATS
3124 * 0 for success, -errno for errors.
3126 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
3128 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3131 r = amdgpu_bo_reserve(vm->root.base.bo, true);
3136 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
3142 unsigned long flags;
3144 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3145 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3147 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3154 /* Check if PD needs to be reinitialized and do it before
3155 * changing any other state, in case it fails.
3157 if (pte_support_ats != vm->pte_support_ats) {
3158 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
3159 adev->vm_manager.root_level,
3165 /* Update VM state */
3166 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3167 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3168 vm->pte_support_ats = pte_support_ats;
3169 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3170 vm->use_cpu_for_update ? "CPU" : "SDMA");
3171 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3172 "CPU update of VM recommended only for large BAR system\n");
3175 unsigned long flags;
3177 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3178 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3179 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3181 /* Free the original amdgpu allocated pasid
3182 * Will be replaced with kfd allocated pasid
3184 amdgpu_pasid_free(vm->pasid);
3188 /* Free the shadow bo for compute VM */
3189 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3198 unsigned long flags;
3200 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3201 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3202 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3205 amdgpu_bo_unreserve(vm->root.base.bo);
3210 * amdgpu_vm_release_compute - release a compute vm
3211 * @adev: amdgpu_device pointer
3212 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3214 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3215 * pasid from vm. Compute should stop use of vm after this call.
3217 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3220 unsigned long flags;
3222 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3223 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3224 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3230 * amdgpu_vm_fini - tear down a vm instance
3232 * @adev: amdgpu_device pointer
3236 * Unbind the VM and remove all bos from the vm bo list
3238 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3240 struct amdgpu_bo_va_mapping *mapping, *tmp;
3241 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3242 struct amdgpu_bo *root;
3246 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3248 /* Clear pending page faults from IH when the VM is destroyed */
3249 while (kfifo_get(&vm->faults, &fault))
3250 amdgpu_vm_clear_fault(vm->fault_hash, fault);
3253 unsigned long flags;
3255 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3256 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3257 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3260 kfree(vm->fault_hash);
3261 vm->fault_hash = NULL;
3263 drm_sched_entity_destroy(&vm->entity);
3265 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3266 dev_err(adev->dev, "still active bo inside vm\n");
3268 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3269 &vm->va.rb_root, rb) {
3270 /* Don't remove the mapping here, we don't want to trigger a
3271 * rebalance and the tree is about to be destroyed anyway.
3273 list_del(&mapping->list);
3276 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3277 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3278 amdgpu_vm_prt_fini(adev, vm);
3279 prt_fini_needed = false;
3282 list_del(&mapping->list);
3283 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3286 root = amdgpu_bo_ref(vm->root.base.bo);
3287 r = amdgpu_bo_reserve(root, true);
3289 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
3291 amdgpu_vm_free_pts(adev, vm);
3292 amdgpu_bo_unreserve(root);
3294 amdgpu_bo_unref(&root);
3295 dma_fence_put(vm->last_update);
3296 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3297 amdgpu_vmid_free_reserved(adev, vm, i);
3301 * amdgpu_vm_manager_init - init the VM manager
3303 * @adev: amdgpu_device pointer
3305 * Initialize the VM manager structures
3307 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3311 amdgpu_vmid_mgr_init(adev);
3313 adev->vm_manager.fence_context =
3314 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3315 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3316 adev->vm_manager.seqno[i] = 0;
3318 spin_lock_init(&adev->vm_manager.prt_lock);
3319 atomic_set(&adev->vm_manager.num_prt_users, 0);
3321 /* If not overridden by the user, by default, only in large BAR systems
3322 * Compute VM tables will be updated by CPU
3324 #ifdef CONFIG_X86_64
3325 if (amdgpu_vm_update_mode == -1) {
3326 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3327 adev->vm_manager.vm_update_mode =
3328 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3330 adev->vm_manager.vm_update_mode = 0;
3332 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3334 adev->vm_manager.vm_update_mode = 0;
3337 idr_init(&adev->vm_manager.pasid_idr);
3338 spin_lock_init(&adev->vm_manager.pasid_lock);
3342 * amdgpu_vm_manager_fini - cleanup VM manager
3344 * @adev: amdgpu_device pointer
3346 * Cleanup the VM manager and free resources.
3348 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3350 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3351 idr_destroy(&adev->vm_manager.pasid_idr);
3353 amdgpu_vmid_mgr_fini(adev);
3357 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3359 * @dev: drm device pointer
3360 * @data: drm_amdgpu_vm
3361 * @filp: drm file pointer
3364 * 0 for success, -errno for errors.
3366 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3368 union drm_amdgpu_vm *args = data;
3369 struct amdgpu_device *adev = dev->dev_private;
3370 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3373 switch (args->in.op) {
3374 case AMDGPU_VM_OP_RESERVE_VMID:
3375 /* current, we only have requirement to reserve vmid from gfxhub */
3376 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3380 case AMDGPU_VM_OP_UNRESERVE_VMID:
3381 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3391 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3393 * @adev: drm device pointer
3394 * @pasid: PASID identifier for VM
3395 * @task_info: task_info to fill.
3397 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3398 struct amdgpu_task_info *task_info)
3400 struct amdgpu_vm *vm;
3401 unsigned long flags;
3403 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3405 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3407 *task_info = vm->task_info;
3409 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3413 * amdgpu_vm_set_task_info - Sets VMs task info.
3415 * @vm: vm for which to set the info
3417 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3419 if (!vm->task_info.pid) {
3420 vm->task_info.pid = current->pid;
3421 get_task_comm(vm->task_info.task_name, current);
3423 if (current->group_leader->mm == current->mm) {
3424 vm->task_info.tgid = current->group_leader->pid;
3425 get_task_comm(vm->task_info.process_name, current->group_leader);
3431 * amdgpu_vm_add_fault - Add a page fault record to fault hash table
3433 * @fault_hash: fault hash table
3434 * @key: 64-bit encoding of PASID and address
3436 * This should be called when a retry page fault interrupt is
3437 * received. If this is a new page fault, it will be added to a hash
3438 * table. The return value indicates whether this is a new fault, or
3439 * a fault that was already known and is already being handled.
3441 * If there are too many pending page faults, this will fail. Retry
3442 * interrupts should be ignored in this case until there is enough
3445 * Returns 0 if the fault was added, 1 if the fault was already known,
3446 * -ENOSPC if there are too many pending faults.
3448 int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
3450 unsigned long flags;
3453 if (WARN_ON_ONCE(!fault_hash))
3454 /* Should be allocated in amdgpu_vm_init
3458 spin_lock_irqsave(&fault_hash->lock, flags);
3460 /* Only let the hash table fill up to 50% for best performance */
3461 if (fault_hash->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1)))
3464 r = chash_table_copy_in(&fault_hash->hash, key, NULL);
3466 fault_hash->count++;
3468 /* chash_table_copy_in should never fail unless we're losing count */
3469 WARN_ON_ONCE(r < 0);
3472 spin_unlock_irqrestore(&fault_hash->lock, flags);
3477 * amdgpu_vm_clear_fault - Remove a page fault record
3479 * @fault_hash: fault hash table
3480 * @key: 64-bit encoding of PASID and address
3482 * This should be called when a page fault has been handled. Any
3483 * future interrupt with this key will be processed as a new
3486 void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
3488 unsigned long flags;
3494 spin_lock_irqsave(&fault_hash->lock, flags);
3496 r = chash_table_remove(&fault_hash->hash, key, NULL);
3497 if (!WARN_ON_ONCE(r < 0)) {
3498 fault_hash->count--;
3499 WARN_ON_ONCE(fault_hash->count < 0);
3502 spin_unlock_irqrestore(&fault_hash->lock, flags);