2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
36 #include "amdgpu_trace.h"
37 #include "amdgpu_amdkfd.h"
38 #include "amdgpu_gmc.h"
39 #include "amdgpu_xgmi.h"
40 #include "amdgpu_dma_buf.h"
41 #include "amdgpu_res_cursor.h"
47 * GPUVM is similar to the legacy gart on older asics, however
48 * rather than there being a single global gart table
49 * for the entire GPU, there are multiple VM page tables active
50 * at any given time. The VM page tables can contain a mix
51 * vram pages and system memory pages and system memory pages
52 * can be mapped as snooped (cached system pages) or unsnooped
53 * (uncached system pages).
54 * Each VM has an ID associated with it and there is a page table
55 * associated with each VMID. When execting a command buffer,
56 * the kernel tells the the ring what VMID to use for that command
57 * buffer. VMIDs are allocated dynamically as commands are submitted.
58 * The userspace drivers maintain their own address space and the kernel
59 * sets up their pages tables accordingly when they submit their
60 * command buffers and a VMID is assigned.
61 * Cayman/Trinity support up to 8 active VMs at any given time;
65 #define START(node) ((node)->start)
66 #define LAST(node) ((node)->last)
68 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
69 START, LAST, static, amdgpu_vm_it)
75 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
77 struct amdgpu_prt_cb {
80 * @adev: amdgpu device
82 struct amdgpu_device *adev;
87 struct dma_fence_cb cb;
91 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
92 * happens while holding this lock anywhere to prevent deadlocks when
93 * an MMU notifier runs in reclaim-FS context.
95 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
97 mutex_lock(&vm->eviction_lock);
98 vm->saved_flags = memalloc_noreclaim_save();
101 static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
103 if (mutex_trylock(&vm->eviction_lock)) {
104 vm->saved_flags = memalloc_noreclaim_save();
110 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
112 memalloc_noreclaim_restore(vm->saved_flags);
113 mutex_unlock(&vm->eviction_lock);
117 * amdgpu_vm_level_shift - return the addr shift for each level
119 * @adev: amdgpu_device pointer
123 * The number of bits the pfn needs to be right shifted for a level.
125 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
132 return 9 * (AMDGPU_VM_PDB0 - level) +
133 adev->vm_manager.block_size;
142 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
144 * @adev: amdgpu_device pointer
148 * The number of entries in a page directory or page table.
150 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
153 unsigned shift = amdgpu_vm_level_shift(adev,
154 adev->vm_manager.root_level);
156 if (level == adev->vm_manager.root_level)
157 /* For the root directory */
158 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
160 else if (level != AMDGPU_VM_PTB)
161 /* Everything in between */
164 /* For the page tables on the leaves */
165 return AMDGPU_VM_PTE_COUNT(adev);
169 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
171 * @adev: amdgpu_device pointer
174 * The number of entries in the root page directory which needs the ATS setting.
176 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
180 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
181 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
185 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
187 * @adev: amdgpu_device pointer
191 * The mask to extract the entry number of a PD/PT from an address.
193 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
196 if (level <= adev->vm_manager.root_level)
198 else if (level != AMDGPU_VM_PTB)
201 return AMDGPU_VM_PTE_COUNT(adev) - 1;
205 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
207 * @adev: amdgpu_device pointer
211 * The size of the BO for a page directory or page table in bytes.
213 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
215 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
219 * amdgpu_vm_bo_evicted - vm_bo is evicted
221 * @vm_bo: vm_bo which is evicted
223 * State for PDs/PTs and per VM BOs which are not at the location they should
226 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
228 struct amdgpu_vm *vm = vm_bo->vm;
229 struct amdgpu_bo *bo = vm_bo->bo;
232 if (bo->tbo.type == ttm_bo_type_kernel)
233 list_move(&vm_bo->vm_status, &vm->evicted);
235 list_move_tail(&vm_bo->vm_status, &vm->evicted);
238 * amdgpu_vm_bo_moved - vm_bo is moved
240 * @vm_bo: vm_bo which is moved
242 * State for per VM BOs which are moved, but that change is not yet reflected
243 * in the page tables.
245 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
247 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
251 * amdgpu_vm_bo_idle - vm_bo is idle
253 * @vm_bo: vm_bo which is now idle
255 * State for PDs/PTs and per VM BOs which have gone through the state machine
258 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
260 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
261 vm_bo->moved = false;
265 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
267 * @vm_bo: vm_bo which is now invalidated
269 * State for normal BOs which are invalidated and that change not yet reflected
272 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
274 spin_lock(&vm_bo->vm->invalidated_lock);
275 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
276 spin_unlock(&vm_bo->vm->invalidated_lock);
280 * amdgpu_vm_bo_relocated - vm_bo is reloacted
282 * @vm_bo: vm_bo which is relocated
284 * State for PDs/PTs which needs to update their parent PD.
285 * For the root PD, just move to idle state.
287 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
289 if (vm_bo->bo->parent)
290 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
292 amdgpu_vm_bo_idle(vm_bo);
296 * amdgpu_vm_bo_done - vm_bo is done
298 * @vm_bo: vm_bo which is now done
300 * State for normal BOs which are invalidated and that change has been updated
303 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
305 spin_lock(&vm_bo->vm->invalidated_lock);
306 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
307 spin_unlock(&vm_bo->vm->invalidated_lock);
311 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
313 * @base: base structure for tracking BO usage in a VM
314 * @vm: vm to which bo is to be added
315 * @bo: amdgpu buffer object
317 * Initialize a bo_va_base structure and add it to the appropriate lists
320 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
321 struct amdgpu_vm *vm,
322 struct amdgpu_bo *bo)
327 INIT_LIST_HEAD(&base->vm_status);
331 base->next = bo->vm_bo;
334 if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
337 vm->bulk_moveable = false;
338 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
339 amdgpu_vm_bo_relocated(base);
341 amdgpu_vm_bo_idle(base);
343 if (bo->preferred_domains &
344 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
348 * we checked all the prerequisites, but it looks like this per vm bo
349 * is currently evicted. add the bo to the evicted list to make sure it
350 * is validated on next vm use to avoid fault.
352 amdgpu_vm_bo_evicted(base);
356 * amdgpu_vm_pt_parent - get the parent page directory
358 * @pt: child page table
360 * Helper to get the parent entry for the child page table. NULL if we are at
361 * the root page directory.
363 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
365 struct amdgpu_bo *parent = pt->base.bo->parent;
370 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
374 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
376 struct amdgpu_vm_pt_cursor {
378 struct amdgpu_vm_pt *parent;
379 struct amdgpu_vm_pt *entry;
384 * amdgpu_vm_pt_start - start PD/PT walk
386 * @adev: amdgpu_device pointer
387 * @vm: amdgpu_vm structure
388 * @start: start address of the walk
389 * @cursor: state to initialize
391 * Initialize a amdgpu_vm_pt_cursor to start a walk.
393 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
394 struct amdgpu_vm *vm, uint64_t start,
395 struct amdgpu_vm_pt_cursor *cursor)
398 cursor->parent = NULL;
399 cursor->entry = &vm->root;
400 cursor->level = adev->vm_manager.root_level;
404 * amdgpu_vm_pt_descendant - go to child node
406 * @adev: amdgpu_device pointer
407 * @cursor: current state
409 * Walk to the child node of the current node.
411 * True if the walk was possible, false otherwise.
413 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
414 struct amdgpu_vm_pt_cursor *cursor)
416 unsigned mask, shift, idx;
418 if (!cursor->entry->entries)
421 BUG_ON(!cursor->entry->base.bo);
422 mask = amdgpu_vm_entries_mask(adev, cursor->level);
423 shift = amdgpu_vm_level_shift(adev, cursor->level);
426 idx = (cursor->pfn >> shift) & mask;
427 cursor->parent = cursor->entry;
428 cursor->entry = &cursor->entry->entries[idx];
433 * amdgpu_vm_pt_sibling - go to sibling node
435 * @adev: amdgpu_device pointer
436 * @cursor: current state
438 * Walk to the sibling node of the current node.
440 * True if the walk was possible, false otherwise.
442 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
443 struct amdgpu_vm_pt_cursor *cursor)
445 unsigned shift, num_entries;
447 /* Root doesn't have a sibling */
451 /* Go to our parents and see if we got a sibling */
452 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
453 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
455 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
458 cursor->pfn += 1ULL << shift;
459 cursor->pfn &= ~((1ULL << shift) - 1);
465 * amdgpu_vm_pt_ancestor - go to parent node
467 * @cursor: current state
469 * Walk to the parent node of the current node.
471 * True if the walk was possible, false otherwise.
473 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
479 cursor->entry = cursor->parent;
480 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
485 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
487 * @adev: amdgpu_device pointer
488 * @cursor: current state
490 * Walk the PD/PT tree to the next node.
492 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
493 struct amdgpu_vm_pt_cursor *cursor)
495 /* First try a newborn child */
496 if (amdgpu_vm_pt_descendant(adev, cursor))
499 /* If that didn't worked try to find a sibling */
500 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
501 /* No sibling, go to our parents and grandparents */
502 if (!amdgpu_vm_pt_ancestor(cursor)) {
510 * amdgpu_vm_pt_first_dfs - start a deep first search
512 * @adev: amdgpu_device structure
513 * @vm: amdgpu_vm structure
514 * @start: optional cursor to start with
515 * @cursor: state to initialize
517 * Starts a deep first traversal of the PD/PT tree.
519 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
520 struct amdgpu_vm *vm,
521 struct amdgpu_vm_pt_cursor *start,
522 struct amdgpu_vm_pt_cursor *cursor)
527 amdgpu_vm_pt_start(adev, vm, 0, cursor);
528 while (amdgpu_vm_pt_descendant(adev, cursor));
532 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
534 * @start: starting point for the search
535 * @entry: current entry
538 * True when the search should continue, false otherwise.
540 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
541 struct amdgpu_vm_pt *entry)
543 return entry && (!start || entry != start->entry);
547 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
549 * @adev: amdgpu_device structure
550 * @cursor: current state
552 * Move the cursor to the next node in a deep first search.
554 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
555 struct amdgpu_vm_pt_cursor *cursor)
561 cursor->entry = NULL;
562 else if (amdgpu_vm_pt_sibling(adev, cursor))
563 while (amdgpu_vm_pt_descendant(adev, cursor));
565 amdgpu_vm_pt_ancestor(cursor);
569 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
571 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
572 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
573 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
574 amdgpu_vm_pt_continue_dfs((start), (entry)); \
575 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
578 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
580 * @vm: vm providing the BOs
581 * @validated: head of validation list
582 * @entry: entry to add
584 * Add the page directory to the list of BOs to
585 * validate for command submission.
587 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
588 struct list_head *validated,
589 struct amdgpu_bo_list_entry *entry)
592 entry->tv.bo = &vm->root.base.bo->tbo;
593 /* Two for VM updates, one for TTM and one for the CS job */
594 entry->tv.num_shared = 4;
595 entry->user_pages = NULL;
596 list_add(&entry->tv.head, validated);
600 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
602 * @bo: BO which was removed from the LRU
604 * Make sure the bulk_moveable flag is updated when a BO is removed from the
607 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
609 struct amdgpu_bo *abo;
610 struct amdgpu_vm_bo_base *bo_base;
612 if (!amdgpu_bo_is_amdgpu_bo(bo))
618 abo = ttm_to_amdgpu_bo(bo);
621 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
622 struct amdgpu_vm *vm = bo_base->vm;
624 if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
625 vm->bulk_moveable = false;
630 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
632 * @adev: amdgpu device pointer
633 * @vm: vm providing the BOs
635 * Move all BOs to the end of LRU and remember their positions to put them
638 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
639 struct amdgpu_vm *vm)
641 struct amdgpu_vm_bo_base *bo_base;
643 if (vm->bulk_moveable) {
644 spin_lock(&adev->mman.bdev.lru_lock);
645 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
646 spin_unlock(&adev->mman.bdev.lru_lock);
650 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
652 spin_lock(&adev->mman.bdev.lru_lock);
653 list_for_each_entry(bo_base, &vm->idle, vm_status) {
654 struct amdgpu_bo *bo = bo_base->bo;
659 ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
662 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
663 &bo->shadow->tbo.mem,
666 spin_unlock(&adev->mman.bdev.lru_lock);
668 vm->bulk_moveable = true;
672 * amdgpu_vm_validate_pt_bos - validate the page table BOs
674 * @adev: amdgpu device pointer
675 * @vm: vm providing the BOs
676 * @validate: callback to do the validation
677 * @param: parameter for the validation callback
679 * Validate the page table BOs on command submission if neccessary.
684 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
685 int (*validate)(void *p, struct amdgpu_bo *bo),
688 struct amdgpu_vm_bo_base *bo_base, *tmp;
691 vm->bulk_moveable &= list_empty(&vm->evicted);
693 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
694 struct amdgpu_bo *bo = bo_base->bo;
696 r = validate(param, bo);
700 if (bo->tbo.type != ttm_bo_type_kernel) {
701 amdgpu_vm_bo_moved(bo_base);
703 vm->update_funcs->map_table(bo);
704 amdgpu_vm_bo_relocated(bo_base);
708 amdgpu_vm_eviction_lock(vm);
709 vm->evicting = false;
710 amdgpu_vm_eviction_unlock(vm);
716 * amdgpu_vm_ready - check VM is ready for updates
720 * Check if all VM PDs/PTs are ready for updates
723 * True if eviction list is empty.
725 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
727 return list_empty(&vm->evicted);
731 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
733 * @adev: amdgpu_device pointer
734 * @vm: VM to clear BO from
736 * @immediate: use an immediate update
738 * Root PD needs to be reserved when calling this.
741 * 0 on success, errno otherwise.
743 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
744 struct amdgpu_vm *vm,
745 struct amdgpu_bo *bo,
748 struct ttm_operation_ctx ctx = { true, false };
749 unsigned level = adev->vm_manager.root_level;
750 struct amdgpu_vm_update_params params;
751 struct amdgpu_bo *ancestor = bo;
752 unsigned entries, ats_entries;
756 /* Figure out our place in the hierarchy */
757 if (ancestor->parent) {
759 while (ancestor->parent->parent) {
761 ancestor = ancestor->parent;
765 entries = amdgpu_bo_size(bo) / 8;
766 if (!vm->pte_support_ats) {
769 } else if (!bo->parent) {
770 ats_entries = amdgpu_vm_num_ats_entries(adev);
771 ats_entries = min(ats_entries, entries);
772 entries -= ats_entries;
775 struct amdgpu_vm_pt *pt;
777 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
778 ats_entries = amdgpu_vm_num_ats_entries(adev);
779 if ((pt - vm->root.entries) >= ats_entries) {
782 ats_entries = entries;
787 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
792 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
798 r = vm->update_funcs->map_table(bo);
802 memset(¶ms, 0, sizeof(params));
805 params.immediate = immediate;
807 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
813 uint64_t value = 0, flags;
815 flags = AMDGPU_PTE_DEFAULT_ATC;
816 if (level != AMDGPU_VM_PTB) {
817 /* Handle leaf PDEs as PTEs */
818 flags |= AMDGPU_PDE_PTE;
819 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
822 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
827 addr += ats_entries * 8;
831 uint64_t value = 0, flags = 0;
833 if (adev->asic_type >= CHIP_VEGA10) {
834 if (level != AMDGPU_VM_PTB) {
835 /* Handle leaf PDEs as PTEs */
836 flags |= AMDGPU_PDE_PTE;
837 amdgpu_gmc_get_vm_pde(adev, level,
840 /* Workaround for fault priority problem on GMC9 */
841 flags = AMDGPU_PTE_EXECUTABLE;
845 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
851 return vm->update_funcs->commit(¶ms, NULL);
855 * amdgpu_vm_pt_create - create bo for PD/PT
857 * @adev: amdgpu_device pointer
859 * @level: the page table level
860 * @immediate: use a immediate update
861 * @bo: pointer to the buffer object pointer
863 static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
864 struct amdgpu_vm *vm,
865 int level, bool immediate,
866 struct amdgpu_bo **bo)
868 struct amdgpu_bo_param bp;
871 memset(&bp, 0, sizeof(bp));
873 bp.size = amdgpu_vm_bo_size(adev, level);
874 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
875 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
876 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
877 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
878 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
879 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
880 if (vm->use_cpu_for_update)
881 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
883 bp.type = ttm_bo_type_kernel;
884 bp.no_wait_gpu = immediate;
885 if (vm->root.base.bo)
886 bp.resv = vm->root.base.bo->tbo.base.resv;
888 r = amdgpu_bo_create(adev, &bp, bo);
892 if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
896 WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
898 r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
901 dma_resv_unlock((*bo)->tbo.base.resv);
912 * amdgpu_vm_alloc_pts - Allocate a specific page table
914 * @adev: amdgpu_device pointer
915 * @vm: VM to allocate page tables for
916 * @cursor: Which page table to allocate
917 * @immediate: use an immediate update
919 * Make sure a specific page table or directory is allocated.
922 * 1 if page table needed to be allocated, 0 if page table was already
923 * allocated, negative errno if an error occurred.
925 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
926 struct amdgpu_vm *vm,
927 struct amdgpu_vm_pt_cursor *cursor,
930 struct amdgpu_vm_pt *entry = cursor->entry;
931 struct amdgpu_bo *pt;
934 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
935 unsigned num_entries;
937 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
938 entry->entries = kvmalloc_array(num_entries,
939 sizeof(*entry->entries),
940 GFP_KERNEL | __GFP_ZERO);
948 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
952 /* Keep a reference to the root directory to avoid
953 * freeing them up in the wrong order.
955 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
956 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
958 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
965 amdgpu_bo_unref(&pt->shadow);
966 amdgpu_bo_unref(&pt);
971 * amdgpu_vm_free_table - fre one PD/PT
973 * @entry: PDE to free
975 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
977 if (entry->base.bo) {
978 entry->base.bo->vm_bo = NULL;
979 list_del(&entry->base.vm_status);
980 amdgpu_bo_unref(&entry->base.bo->shadow);
981 amdgpu_bo_unref(&entry->base.bo);
983 kvfree(entry->entries);
984 entry->entries = NULL;
988 * amdgpu_vm_free_pts - free PD/PT levels
990 * @adev: amdgpu device structure
991 * @vm: amdgpu vm structure
992 * @start: optional cursor where to start freeing PDs/PTs
994 * Free the page directory or page table level and all sub levels.
996 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
997 struct amdgpu_vm *vm,
998 struct amdgpu_vm_pt_cursor *start)
1000 struct amdgpu_vm_pt_cursor cursor;
1001 struct amdgpu_vm_pt *entry;
1003 vm->bulk_moveable = false;
1005 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1006 amdgpu_vm_free_table(entry);
1009 amdgpu_vm_free_table(start->entry);
1013 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1015 * @adev: amdgpu_device pointer
1017 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1019 const struct amdgpu_ip_block *ip_block;
1020 bool has_compute_vm_bug;
1021 struct amdgpu_ring *ring;
1024 has_compute_vm_bug = false;
1026 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1028 /* Compute has a VM bug for GFX version < 7.
1029 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1030 if (ip_block->version->major <= 7)
1031 has_compute_vm_bug = true;
1032 else if (ip_block->version->major == 8)
1033 if (adev->gfx.mec_fw_version < 673)
1034 has_compute_vm_bug = true;
1037 for (i = 0; i < adev->num_rings; i++) {
1038 ring = adev->rings[i];
1039 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1040 /* only compute rings */
1041 ring->has_compute_vm_bug = has_compute_vm_bug;
1043 ring->has_compute_vm_bug = false;
1048 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1050 * @ring: ring on which the job will be submitted
1051 * @job: job to submit
1054 * True if sync is needed.
1056 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1057 struct amdgpu_job *job)
1059 struct amdgpu_device *adev = ring->adev;
1060 unsigned vmhub = ring->funcs->vmhub;
1061 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1062 struct amdgpu_vmid *id;
1063 bool gds_switch_needed;
1064 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1068 id = &id_mgr->ids[job->vmid];
1069 gds_switch_needed = ring->funcs->emit_gds_switch && (
1070 id->gds_base != job->gds_base ||
1071 id->gds_size != job->gds_size ||
1072 id->gws_base != job->gws_base ||
1073 id->gws_size != job->gws_size ||
1074 id->oa_base != job->oa_base ||
1075 id->oa_size != job->oa_size);
1077 if (amdgpu_vmid_had_gpu_reset(adev, id))
1080 return vm_flush_needed || gds_switch_needed;
1084 * amdgpu_vm_flush - hardware flush the vm
1086 * @ring: ring to use for flush
1088 * @need_pipe_sync: is pipe sync needed
1090 * Emit a VM flush when it is necessary.
1093 * 0 on success, errno otherwise.
1095 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1096 bool need_pipe_sync)
1098 struct amdgpu_device *adev = ring->adev;
1099 unsigned vmhub = ring->funcs->vmhub;
1100 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1101 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1102 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1103 id->gds_base != job->gds_base ||
1104 id->gds_size != job->gds_size ||
1105 id->gws_base != job->gws_base ||
1106 id->gws_size != job->gws_size ||
1107 id->oa_base != job->oa_base ||
1108 id->oa_size != job->oa_size);
1109 bool vm_flush_needed = job->vm_needs_flush;
1110 struct dma_fence *fence = NULL;
1111 bool pasid_mapping_needed = false;
1112 unsigned patch_offset = 0;
1113 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1116 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1117 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1119 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1120 gds_switch_needed = true;
1121 vm_flush_needed = true;
1122 pasid_mapping_needed = true;
1125 mutex_lock(&id_mgr->lock);
1126 if (id->pasid != job->pasid || !id->pasid_mapping ||
1127 !dma_fence_is_signaled(id->pasid_mapping))
1128 pasid_mapping_needed = true;
1129 mutex_unlock(&id_mgr->lock);
1131 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1132 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1133 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1134 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1135 ring->funcs->emit_wreg;
1137 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1140 if (ring->funcs->init_cond_exec)
1141 patch_offset = amdgpu_ring_init_cond_exec(ring);
1144 amdgpu_ring_emit_pipeline_sync(ring);
1146 if (vm_flush_needed) {
1147 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1148 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1151 if (pasid_mapping_needed)
1152 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1154 if (vm_flush_needed || pasid_mapping_needed) {
1155 r = amdgpu_fence_emit(ring, &fence, 0);
1160 if (vm_flush_needed) {
1161 mutex_lock(&id_mgr->lock);
1162 dma_fence_put(id->last_flush);
1163 id->last_flush = dma_fence_get(fence);
1164 id->current_gpu_reset_count =
1165 atomic_read(&adev->gpu_reset_counter);
1166 mutex_unlock(&id_mgr->lock);
1169 if (pasid_mapping_needed) {
1170 mutex_lock(&id_mgr->lock);
1171 id->pasid = job->pasid;
1172 dma_fence_put(id->pasid_mapping);
1173 id->pasid_mapping = dma_fence_get(fence);
1174 mutex_unlock(&id_mgr->lock);
1176 dma_fence_put(fence);
1178 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1179 id->gds_base = job->gds_base;
1180 id->gds_size = job->gds_size;
1181 id->gws_base = job->gws_base;
1182 id->gws_size = job->gws_size;
1183 id->oa_base = job->oa_base;
1184 id->oa_size = job->oa_size;
1185 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1186 job->gds_size, job->gws_base,
1187 job->gws_size, job->oa_base,
1191 if (ring->funcs->patch_cond_exec)
1192 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1194 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1195 if (ring->funcs->emit_switch_buffer) {
1196 amdgpu_ring_emit_switch_buffer(ring);
1197 amdgpu_ring_emit_switch_buffer(ring);
1203 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1206 * @bo: requested buffer object
1208 * Find @bo inside the requested vm.
1209 * Search inside the @bos vm list for the requested vm
1210 * Returns the found bo_va or NULL if none is found
1212 * Object has to be reserved!
1215 * Found bo_va or NULL.
1217 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1218 struct amdgpu_bo *bo)
1220 struct amdgpu_vm_bo_base *base;
1222 for (base = bo->vm_bo; base; base = base->next) {
1226 return container_of(base, struct amdgpu_bo_va, base);
1232 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1234 * @pages_addr: optional DMA address to use for lookup
1235 * @addr: the unmapped addr
1237 * Look up the physical address of the page that the pte resolves
1241 * The pointer for the page table entry.
1243 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1247 /* page table offset */
1248 result = pages_addr[addr >> PAGE_SHIFT];
1250 /* in case cpu page size != gpu page size*/
1251 result |= addr & (~PAGE_MASK);
1253 result &= 0xFFFFFFFFFFFFF000ULL;
1259 * amdgpu_vm_update_pde - update a single level in the hierarchy
1261 * @params: parameters for the update
1263 * @entry: entry to update
1265 * Makes sure the requested entry in parent is up to date.
1267 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1268 struct amdgpu_vm *vm,
1269 struct amdgpu_vm_pt *entry)
1271 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1272 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1273 uint64_t pde, pt, flags;
1276 for (level = 0, pbo = bo->parent; pbo; ++level)
1279 level += params->adev->vm_manager.root_level;
1280 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1281 pde = (entry - parent->entries) * 8;
1282 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1286 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1288 * @adev: amdgpu_device pointer
1291 * Mark all PD level as invalid after an error.
1293 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1294 struct amdgpu_vm *vm)
1296 struct amdgpu_vm_pt_cursor cursor;
1297 struct amdgpu_vm_pt *entry;
1299 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1300 if (entry->base.bo && !entry->base.moved)
1301 amdgpu_vm_bo_relocated(&entry->base);
1305 * amdgpu_vm_update_pdes - make sure that all directories are valid
1307 * @adev: amdgpu_device pointer
1309 * @immediate: submit immediately to the paging queue
1311 * Makes sure all directories are up to date.
1314 * 0 for success, error for failure.
1316 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1317 struct amdgpu_vm *vm, bool immediate)
1319 struct amdgpu_vm_update_params params;
1322 if (list_empty(&vm->relocated))
1325 memset(¶ms, 0, sizeof(params));
1328 params.immediate = immediate;
1330 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1334 while (!list_empty(&vm->relocated)) {
1335 struct amdgpu_vm_pt *entry;
1337 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1339 amdgpu_vm_bo_idle(&entry->base);
1341 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1346 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1352 amdgpu_vm_invalidate_pds(adev, vm);
1357 * amdgpu_vm_update_flags - figure out flags for PTE updates
1359 * Make sure to set the right flags for the PTEs at the desired level.
1361 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1362 struct amdgpu_bo *bo, unsigned level,
1363 uint64_t pe, uint64_t addr,
1364 unsigned count, uint32_t incr,
1368 if (level != AMDGPU_VM_PTB) {
1369 flags |= AMDGPU_PDE_PTE;
1370 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1372 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1373 !(flags & AMDGPU_PTE_VALID) &&
1374 !(flags & AMDGPU_PTE_PRT)) {
1376 /* Workaround for fault priority problem on GMC9 */
1377 flags |= AMDGPU_PTE_EXECUTABLE;
1380 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1385 * amdgpu_vm_fragment - get fragment for PTEs
1387 * @params: see amdgpu_vm_update_params definition
1388 * @start: first PTE to handle
1389 * @end: last PTE to handle
1390 * @flags: hw mapping flags
1391 * @frag: resulting fragment size
1392 * @frag_end: end of this fragment
1394 * Returns the first possible fragment for the start and end address.
1396 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1397 uint64_t start, uint64_t end, uint64_t flags,
1398 unsigned int *frag, uint64_t *frag_end)
1401 * The MC L1 TLB supports variable sized pages, based on a fragment
1402 * field in the PTE. When this field is set to a non-zero value, page
1403 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1404 * flags are considered valid for all PTEs within the fragment range
1405 * and corresponding mappings are assumed to be physically contiguous.
1407 * The L1 TLB can store a single PTE for the whole fragment,
1408 * significantly increasing the space available for translation
1409 * caching. This leads to large improvements in throughput when the
1410 * TLB is under pressure.
1412 * The L2 TLB distributes small and large fragments into two
1413 * asymmetric partitions. The large fragment cache is significantly
1414 * larger. Thus, we try to use large fragments wherever possible.
1415 * Userspace can support this by aligning virtual base address and
1416 * allocation size to the fragment size.
1418 * Starting with Vega10 the fragment size only controls the L1. The L2
1419 * is now directly feed with small/huge/giant pages from the walker.
1423 if (params->adev->asic_type < CHIP_VEGA10)
1424 max_frag = params->adev->vm_manager.fragment_size;
1428 /* system pages are non continuously */
1429 if (params->pages_addr) {
1435 /* This intentionally wraps around if no bit is set */
1436 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1437 if (*frag >= max_frag) {
1439 *frag_end = end & ~((1ULL << max_frag) - 1);
1441 *frag_end = start + (1 << *frag);
1446 * amdgpu_vm_update_ptes - make sure that page tables are valid
1448 * @params: see amdgpu_vm_update_params definition
1449 * @start: start of GPU address range
1450 * @end: end of GPU address range
1451 * @dst: destination address to map to, the next dst inside the function
1452 * @flags: mapping flags
1454 * Update the page tables in the range @start - @end.
1457 * 0 for success, -EINVAL for failure.
1459 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1460 uint64_t start, uint64_t end,
1461 uint64_t dst, uint64_t flags)
1463 struct amdgpu_device *adev = params->adev;
1464 struct amdgpu_vm_pt_cursor cursor;
1465 uint64_t frag_start = start, frag_end;
1469 /* figure out the initial fragment */
1470 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1472 /* walk over the address space and update the PTs */
1473 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1474 while (cursor.pfn < end) {
1475 unsigned shift, parent_shift, mask;
1476 uint64_t incr, entry_end, pe_start;
1477 struct amdgpu_bo *pt;
1479 if (!params->unlocked) {
1480 /* make sure that the page tables covering the
1481 * address range are actually allocated
1483 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1484 &cursor, params->immediate);
1489 shift = amdgpu_vm_level_shift(adev, cursor.level);
1490 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1491 if (params->unlocked) {
1492 /* Unlocked updates are only allowed on the leaves */
1493 if (amdgpu_vm_pt_descendant(adev, &cursor))
1495 } else if (adev->asic_type < CHIP_VEGA10 &&
1496 (flags & AMDGPU_PTE_VALID)) {
1497 /* No huge page support before GMC v9 */
1498 if (cursor.level != AMDGPU_VM_PTB) {
1499 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1503 } else if (frag < shift) {
1504 /* We can't use this level when the fragment size is
1505 * smaller than the address shift. Go to the next
1506 * child entry and try again.
1508 if (amdgpu_vm_pt_descendant(adev, &cursor))
1510 } else if (frag >= parent_shift) {
1511 /* If the fragment size is even larger than the parent
1512 * shift we should go up one level and check it again.
1514 if (!amdgpu_vm_pt_ancestor(&cursor))
1519 pt = cursor.entry->base.bo;
1521 /* We need all PDs and PTs for mapping something, */
1522 if (flags & AMDGPU_PTE_VALID)
1525 /* but unmapping something can happen at a higher
1528 if (!amdgpu_vm_pt_ancestor(&cursor))
1531 pt = cursor.entry->base.bo;
1532 shift = parent_shift;
1533 frag_end = max(frag_end, ALIGN(frag_start + 1,
1537 /* Looks good so far, calculate parameters for the update */
1538 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1539 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1540 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1541 entry_end = ((uint64_t)mask + 1) << shift;
1542 entry_end += cursor.pfn & ~(entry_end - 1);
1543 entry_end = min(entry_end, end);
1546 struct amdgpu_vm *vm = params->vm;
1547 uint64_t upd_end = min(entry_end, frag_end);
1548 unsigned nptes = (upd_end - frag_start) >> shift;
1549 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1551 /* This can happen when we set higher level PDs to
1552 * silent to stop fault floods.
1554 nptes = max(nptes, 1u);
1556 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1557 nptes, dst, incr, upd_flags,
1559 vm->immediate.fence_context);
1560 amdgpu_vm_update_flags(params, pt, cursor.level,
1561 pe_start, dst, nptes, incr,
1564 pe_start += nptes * 8;
1565 dst += nptes * incr;
1567 frag_start = upd_end;
1568 if (frag_start >= frag_end) {
1569 /* figure out the next fragment */
1570 amdgpu_vm_fragment(params, frag_start, end,
1571 flags, &frag, &frag_end);
1575 } while (frag_start < entry_end);
1577 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1578 /* Free all child entries.
1579 * Update the tables with the flags and addresses and free up subsequent
1580 * tables in the case of huge pages or freed up areas.
1581 * This is the maximum you can free, because all other page tables are not
1582 * completely covered by the range and so potentially still in use.
1584 while (cursor.pfn < frag_start) {
1585 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1586 amdgpu_vm_pt_next(adev, &cursor);
1587 params->table_freed = true;
1590 } else if (frag >= shift) {
1591 /* or just move on to the next on the same level. */
1592 amdgpu_vm_pt_next(adev, &cursor);
1600 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1602 * @adev: amdgpu_device pointer of the VM
1603 * @bo_adev: amdgpu_device pointer of the mapped BO
1605 * @immediate: immediate submission in a page fault
1606 * @unlocked: unlocked invalidation during MM callback
1607 * @resv: fences we need to sync to
1608 * @start: start of mapped range
1609 * @last: last mapped entry
1610 * @flags: flags for the entries
1611 * @offset: offset into nodes and pages_addr
1612 * @res: ttm_resource to map
1613 * @pages_addr: DMA addresses to use for mapping
1614 * @fence: optional resulting fence
1615 * @table_freed: return true if page table is freed
1617 * Fill in the page table entries between @start and @last.
1620 * 0 for success, -EINVAL for failure.
1622 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1623 struct amdgpu_device *bo_adev,
1624 struct amdgpu_vm *vm, bool immediate,
1625 bool unlocked, struct dma_resv *resv,
1626 uint64_t start, uint64_t last,
1627 uint64_t flags, uint64_t offset,
1628 struct ttm_resource *res,
1629 dma_addr_t *pages_addr,
1630 struct dma_fence **fence,
1633 struct amdgpu_vm_update_params params;
1634 struct amdgpu_res_cursor cursor;
1635 enum amdgpu_sync_mode sync_mode;
1638 memset(¶ms, 0, sizeof(params));
1641 params.immediate = immediate;
1642 params.pages_addr = pages_addr;
1643 params.unlocked = unlocked;
1645 /* Implicitly sync to command submissions in the same VM before
1646 * unmapping. Sync to moving fences before mapping.
1648 if (!(flags & AMDGPU_PTE_VALID))
1649 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1651 sync_mode = AMDGPU_SYNC_EXPLICIT;
1653 amdgpu_vm_eviction_lock(vm);
1659 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1660 struct dma_fence *tmp = dma_fence_get_stub();
1662 amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
1663 swap(vm->last_unlocked, tmp);
1667 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1671 amdgpu_res_first(res, offset, (last - start + 1) * AMDGPU_GPU_PAGE_SIZE,
1673 while (cursor.remaining) {
1674 uint64_t tmp, num_entries, addr;
1676 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1678 bool contiguous = true;
1680 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1681 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1684 contiguous = pages_addr[pfn + 1] ==
1685 pages_addr[pfn] + PAGE_SIZE;
1688 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1689 for (count = 2; count < tmp; ++count) {
1690 uint64_t idx = pfn + count;
1692 if (contiguous != (pages_addr[idx] ==
1693 pages_addr[idx - 1] + PAGE_SIZE))
1696 num_entries = count *
1697 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1701 addr = cursor.start;
1702 params.pages_addr = pages_addr;
1704 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1705 params.pages_addr = NULL;
1708 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1709 addr = bo_adev->vm_manager.vram_base_offset +
1715 tmp = start + num_entries;
1716 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1720 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1724 r = vm->update_funcs->commit(¶ms, fence);
1727 *table_freed = params.table_freed;
1730 amdgpu_vm_eviction_unlock(vm);
1734 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1735 uint64_t *gtt_mem, uint64_t *cpu_mem)
1737 struct amdgpu_bo_va *bo_va, *tmp;
1739 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1740 if (!bo_va->base.bo)
1742 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1745 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1746 if (!bo_va->base.bo)
1748 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1751 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1752 if (!bo_va->base.bo)
1754 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1757 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1758 if (!bo_va->base.bo)
1760 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1763 spin_lock(&vm->invalidated_lock);
1764 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1765 if (!bo_va->base.bo)
1767 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1770 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1771 if (!bo_va->base.bo)
1773 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1776 spin_unlock(&vm->invalidated_lock);
1779 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1781 * @adev: amdgpu_device pointer
1782 * @bo_va: requested BO and VM object
1783 * @clear: if true clear the entries
1785 * Fill in the page table entries for @bo_va.
1788 * 0 for success, -EINVAL for failure.
1790 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1793 struct amdgpu_bo *bo = bo_va->base.bo;
1794 struct amdgpu_vm *vm = bo_va->base.vm;
1795 struct amdgpu_bo_va_mapping *mapping;
1796 dma_addr_t *pages_addr = NULL;
1797 struct ttm_resource *mem;
1798 struct dma_fence **last_update;
1799 struct dma_resv *resv;
1801 struct amdgpu_device *bo_adev = adev;
1806 resv = vm->root.base.bo->tbo.base.resv;
1808 struct drm_gem_object *obj = &bo->tbo.base;
1810 resv = bo->tbo.base.resv;
1811 if (obj->import_attach && bo_va->is_xgmi) {
1812 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1813 struct drm_gem_object *gobj = dma_buf->priv;
1814 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1816 if (abo->tbo.mem.mem_type == TTM_PL_VRAM)
1817 bo = gem_to_amdgpu_bo(gobj);
1820 if (mem->mem_type == TTM_PL_TT)
1821 pages_addr = bo->tbo.ttm->dma_address;
1825 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1827 if (amdgpu_bo_encrypted(bo))
1828 flags |= AMDGPU_PTE_TMZ;
1830 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1835 if (clear || (bo && bo->tbo.base.resv ==
1836 vm->root.base.bo->tbo.base.resv))
1837 last_update = &vm->last_update;
1839 last_update = &bo_va->last_pt_update;
1841 if (!clear && bo_va->base.moved) {
1842 bo_va->base.moved = false;
1843 list_splice_init(&bo_va->valids, &bo_va->invalids);
1845 } else if (bo_va->cleared != clear) {
1846 list_splice_init(&bo_va->valids, &bo_va->invalids);
1849 list_for_each_entry(mapping, &bo_va->invalids, list) {
1850 uint64_t update_flags = flags;
1852 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1853 * but in case of something, we filter the flags in first place
1855 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1856 update_flags &= ~AMDGPU_PTE_READABLE;
1857 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1858 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1860 /* Apply ASIC specific mapping flags */
1861 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1863 trace_amdgpu_vm_bo_update(mapping);
1865 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1866 resv, mapping->start,
1867 mapping->last, update_flags,
1868 mapping->offset, mem,
1869 pages_addr, last_update, NULL);
1874 /* If the BO is not in its preferred location add it back to
1875 * the evicted list so that it gets validated again on the
1876 * next command submission.
1878 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1879 uint32_t mem_type = bo->tbo.mem.mem_type;
1881 if (!(bo->preferred_domains &
1882 amdgpu_mem_type_to_domain(mem_type)))
1883 amdgpu_vm_bo_evicted(&bo_va->base);
1885 amdgpu_vm_bo_idle(&bo_va->base);
1887 amdgpu_vm_bo_done(&bo_va->base);
1890 list_splice_init(&bo_va->invalids, &bo_va->valids);
1891 bo_va->cleared = clear;
1893 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1894 list_for_each_entry(mapping, &bo_va->valids, list)
1895 trace_amdgpu_vm_bo_mapping(mapping);
1902 * amdgpu_vm_update_prt_state - update the global PRT state
1904 * @adev: amdgpu_device pointer
1906 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1908 unsigned long flags;
1911 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1912 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1913 adev->gmc.gmc_funcs->set_prt(adev, enable);
1914 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1918 * amdgpu_vm_prt_get - add a PRT user
1920 * @adev: amdgpu_device pointer
1922 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1924 if (!adev->gmc.gmc_funcs->set_prt)
1927 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1928 amdgpu_vm_update_prt_state(adev);
1932 * amdgpu_vm_prt_put - drop a PRT user
1934 * @adev: amdgpu_device pointer
1936 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1938 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1939 amdgpu_vm_update_prt_state(adev);
1943 * amdgpu_vm_prt_cb - callback for updating the PRT status
1945 * @fence: fence for the callback
1946 * @_cb: the callback function
1948 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1950 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1952 amdgpu_vm_prt_put(cb->adev);
1957 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1959 * @adev: amdgpu_device pointer
1960 * @fence: fence for the callback
1962 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1963 struct dma_fence *fence)
1965 struct amdgpu_prt_cb *cb;
1967 if (!adev->gmc.gmc_funcs->set_prt)
1970 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1972 /* Last resort when we are OOM */
1974 dma_fence_wait(fence, false);
1976 amdgpu_vm_prt_put(adev);
1979 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1981 amdgpu_vm_prt_cb(fence, &cb->cb);
1986 * amdgpu_vm_free_mapping - free a mapping
1988 * @adev: amdgpu_device pointer
1990 * @mapping: mapping to be freed
1991 * @fence: fence of the unmap operation
1993 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1995 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1996 struct amdgpu_vm *vm,
1997 struct amdgpu_bo_va_mapping *mapping,
1998 struct dma_fence *fence)
2000 if (mapping->flags & AMDGPU_PTE_PRT)
2001 amdgpu_vm_add_prt_cb(adev, fence);
2006 * amdgpu_vm_prt_fini - finish all prt mappings
2008 * @adev: amdgpu_device pointer
2011 * Register a cleanup callback to disable PRT support after VM dies.
2013 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2015 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2016 struct dma_fence *excl, **shared;
2017 unsigned i, shared_count;
2020 r = dma_resv_get_fences_rcu(resv, &excl,
2021 &shared_count, &shared);
2023 /* Not enough memory to grab the fence list, as last resort
2024 * block for all the fences to complete.
2026 dma_resv_wait_timeout_rcu(resv, true, false,
2027 MAX_SCHEDULE_TIMEOUT);
2031 /* Add a callback for each fence in the reservation object */
2032 amdgpu_vm_prt_get(adev);
2033 amdgpu_vm_add_prt_cb(adev, excl);
2035 for (i = 0; i < shared_count; ++i) {
2036 amdgpu_vm_prt_get(adev);
2037 amdgpu_vm_add_prt_cb(adev, shared[i]);
2044 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2046 * @adev: amdgpu_device pointer
2048 * @fence: optional resulting fence (unchanged if no work needed to be done
2049 * or if an error occurred)
2051 * Make sure all freed BOs are cleared in the PT.
2052 * PTs have to be reserved and mutex must be locked!
2058 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2059 struct amdgpu_vm *vm,
2060 struct dma_fence **fence)
2062 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2063 struct amdgpu_bo_va_mapping *mapping;
2064 uint64_t init_pte_value = 0;
2065 struct dma_fence *f = NULL;
2068 while (!list_empty(&vm->freed)) {
2069 mapping = list_first_entry(&vm->freed,
2070 struct amdgpu_bo_va_mapping, list);
2071 list_del(&mapping->list);
2073 if (vm->pte_support_ats &&
2074 mapping->start < AMDGPU_GMC_HOLE_START)
2075 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2077 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2078 resv, mapping->start,
2079 mapping->last, init_pte_value,
2080 0, NULL, NULL, &f, NULL);
2081 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2089 dma_fence_put(*fence);
2100 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2102 * @adev: amdgpu_device pointer
2105 * Make sure all BOs which are moved are updated in the PTs.
2110 * PTs have to be reserved!
2112 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2113 struct amdgpu_vm *vm)
2115 struct amdgpu_bo_va *bo_va, *tmp;
2116 struct dma_resv *resv;
2120 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2121 /* Per VM BOs never need to bo cleared in the page tables */
2122 r = amdgpu_vm_bo_update(adev, bo_va, false);
2127 spin_lock(&vm->invalidated_lock);
2128 while (!list_empty(&vm->invalidated)) {
2129 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2131 resv = bo_va->base.bo->tbo.base.resv;
2132 spin_unlock(&vm->invalidated_lock);
2134 /* Try to reserve the BO to avoid clearing its ptes */
2135 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2137 /* Somebody else is using the BO right now */
2141 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2146 dma_resv_unlock(resv);
2147 spin_lock(&vm->invalidated_lock);
2149 spin_unlock(&vm->invalidated_lock);
2155 * amdgpu_vm_bo_add - add a bo to a specific vm
2157 * @adev: amdgpu_device pointer
2159 * @bo: amdgpu buffer object
2161 * Add @bo into the requested vm.
2162 * Add @bo to the list of bos associated with the vm
2165 * Newly added bo_va or NULL for failure
2167 * Object has to be reserved!
2169 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2170 struct amdgpu_vm *vm,
2171 struct amdgpu_bo *bo)
2173 struct amdgpu_bo_va *bo_va;
2175 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2176 if (bo_va == NULL) {
2179 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2181 bo_va->ref_count = 1;
2182 INIT_LIST_HEAD(&bo_va->valids);
2183 INIT_LIST_HEAD(&bo_va->invalids);
2188 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2189 bo_va->is_xgmi = true;
2190 /* Power up XGMI if it can be potentially used */
2191 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2199 * amdgpu_vm_bo_insert_map - insert a new mapping
2201 * @adev: amdgpu_device pointer
2202 * @bo_va: bo_va to store the address
2203 * @mapping: the mapping to insert
2205 * Insert a new mapping into all structures.
2207 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2208 struct amdgpu_bo_va *bo_va,
2209 struct amdgpu_bo_va_mapping *mapping)
2211 struct amdgpu_vm *vm = bo_va->base.vm;
2212 struct amdgpu_bo *bo = bo_va->base.bo;
2214 mapping->bo_va = bo_va;
2215 list_add(&mapping->list, &bo_va->invalids);
2216 amdgpu_vm_it_insert(mapping, &vm->va);
2218 if (mapping->flags & AMDGPU_PTE_PRT)
2219 amdgpu_vm_prt_get(adev);
2221 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2222 !bo_va->base.moved) {
2223 list_move(&bo_va->base.vm_status, &vm->moved);
2225 trace_amdgpu_vm_bo_map(bo_va, mapping);
2229 * amdgpu_vm_bo_map - map bo inside a vm
2231 * @adev: amdgpu_device pointer
2232 * @bo_va: bo_va to store the address
2233 * @saddr: where to map the BO
2234 * @offset: requested offset in the BO
2235 * @size: BO size in bytes
2236 * @flags: attributes of pages (read/write/valid/etc.)
2238 * Add a mapping of the BO at the specefied addr into the VM.
2241 * 0 for success, error for failure.
2243 * Object has to be reserved and unreserved outside!
2245 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2246 struct amdgpu_bo_va *bo_va,
2247 uint64_t saddr, uint64_t offset,
2248 uint64_t size, uint64_t flags)
2250 struct amdgpu_bo_va_mapping *mapping, *tmp;
2251 struct amdgpu_bo *bo = bo_va->base.bo;
2252 struct amdgpu_vm *vm = bo_va->base.vm;
2255 /* validate the parameters */
2256 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2257 size == 0 || size & ~PAGE_MASK)
2260 /* make sure object fit at this offset */
2261 eaddr = saddr + size - 1;
2262 if (saddr >= eaddr ||
2263 (bo && offset + size > amdgpu_bo_size(bo)) ||
2264 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2267 saddr /= AMDGPU_GPU_PAGE_SIZE;
2268 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2270 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2272 /* bo and tmp overlap, invalid addr */
2273 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2274 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2275 tmp->start, tmp->last + 1);
2279 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2283 mapping->start = saddr;
2284 mapping->last = eaddr;
2285 mapping->offset = offset;
2286 mapping->flags = flags;
2288 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2294 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2296 * @adev: amdgpu_device pointer
2297 * @bo_va: bo_va to store the address
2298 * @saddr: where to map the BO
2299 * @offset: requested offset in the BO
2300 * @size: BO size in bytes
2301 * @flags: attributes of pages (read/write/valid/etc.)
2303 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2304 * mappings as we do so.
2307 * 0 for success, error for failure.
2309 * Object has to be reserved and unreserved outside!
2311 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2312 struct amdgpu_bo_va *bo_va,
2313 uint64_t saddr, uint64_t offset,
2314 uint64_t size, uint64_t flags)
2316 struct amdgpu_bo_va_mapping *mapping;
2317 struct amdgpu_bo *bo = bo_va->base.bo;
2321 /* validate the parameters */
2322 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2323 size == 0 || size & ~PAGE_MASK)
2326 /* make sure object fit at this offset */
2327 eaddr = saddr + size - 1;
2328 if (saddr >= eaddr ||
2329 (bo && offset + size > amdgpu_bo_size(bo)) ||
2330 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2333 /* Allocate all the needed memory */
2334 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2338 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2344 saddr /= AMDGPU_GPU_PAGE_SIZE;
2345 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2347 mapping->start = saddr;
2348 mapping->last = eaddr;
2349 mapping->offset = offset;
2350 mapping->flags = flags;
2352 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2358 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2360 * @adev: amdgpu_device pointer
2361 * @bo_va: bo_va to remove the address from
2362 * @saddr: where to the BO is mapped
2364 * Remove a mapping of the BO at the specefied addr from the VM.
2367 * 0 for success, error for failure.
2369 * Object has to be reserved and unreserved outside!
2371 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2372 struct amdgpu_bo_va *bo_va,
2375 struct amdgpu_bo_va_mapping *mapping;
2376 struct amdgpu_vm *vm = bo_va->base.vm;
2379 saddr /= AMDGPU_GPU_PAGE_SIZE;
2381 list_for_each_entry(mapping, &bo_va->valids, list) {
2382 if (mapping->start == saddr)
2386 if (&mapping->list == &bo_va->valids) {
2389 list_for_each_entry(mapping, &bo_va->invalids, list) {
2390 if (mapping->start == saddr)
2394 if (&mapping->list == &bo_va->invalids)
2398 list_del(&mapping->list);
2399 amdgpu_vm_it_remove(mapping, &vm->va);
2400 mapping->bo_va = NULL;
2401 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2404 list_add(&mapping->list, &vm->freed);
2406 amdgpu_vm_free_mapping(adev, vm, mapping,
2407 bo_va->last_pt_update);
2413 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2415 * @adev: amdgpu_device pointer
2416 * @vm: VM structure to use
2417 * @saddr: start of the range
2418 * @size: size of the range
2420 * Remove all mappings in a range, split them as appropriate.
2423 * 0 for success, error for failure.
2425 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2426 struct amdgpu_vm *vm,
2427 uint64_t saddr, uint64_t size)
2429 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2433 eaddr = saddr + size - 1;
2434 saddr /= AMDGPU_GPU_PAGE_SIZE;
2435 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2437 /* Allocate all the needed memory */
2438 before = kzalloc(sizeof(*before), GFP_KERNEL);
2441 INIT_LIST_HEAD(&before->list);
2443 after = kzalloc(sizeof(*after), GFP_KERNEL);
2448 INIT_LIST_HEAD(&after->list);
2450 /* Now gather all removed mappings */
2451 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2453 /* Remember mapping split at the start */
2454 if (tmp->start < saddr) {
2455 before->start = tmp->start;
2456 before->last = saddr - 1;
2457 before->offset = tmp->offset;
2458 before->flags = tmp->flags;
2459 before->bo_va = tmp->bo_va;
2460 list_add(&before->list, &tmp->bo_va->invalids);
2463 /* Remember mapping split at the end */
2464 if (tmp->last > eaddr) {
2465 after->start = eaddr + 1;
2466 after->last = tmp->last;
2467 after->offset = tmp->offset;
2468 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2469 after->flags = tmp->flags;
2470 after->bo_va = tmp->bo_va;
2471 list_add(&after->list, &tmp->bo_va->invalids);
2474 list_del(&tmp->list);
2475 list_add(&tmp->list, &removed);
2477 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2480 /* And free them up */
2481 list_for_each_entry_safe(tmp, next, &removed, list) {
2482 amdgpu_vm_it_remove(tmp, &vm->va);
2483 list_del(&tmp->list);
2485 if (tmp->start < saddr)
2487 if (tmp->last > eaddr)
2491 list_add(&tmp->list, &vm->freed);
2492 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2495 /* Insert partial mapping before the range */
2496 if (!list_empty(&before->list)) {
2497 amdgpu_vm_it_insert(before, &vm->va);
2498 if (before->flags & AMDGPU_PTE_PRT)
2499 amdgpu_vm_prt_get(adev);
2504 /* Insert partial mapping after the range */
2505 if (!list_empty(&after->list)) {
2506 amdgpu_vm_it_insert(after, &vm->va);
2507 if (after->flags & AMDGPU_PTE_PRT)
2508 amdgpu_vm_prt_get(adev);
2517 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2519 * @vm: the requested VM
2520 * @addr: the address
2522 * Find a mapping by it's address.
2525 * The amdgpu_bo_va_mapping matching for addr or NULL
2528 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2531 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2535 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2537 * @vm: the requested vm
2538 * @ticket: CS ticket
2540 * Trace all mappings of BOs reserved during a command submission.
2542 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2544 struct amdgpu_bo_va_mapping *mapping;
2546 if (!trace_amdgpu_vm_bo_cs_enabled())
2549 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2550 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2551 if (mapping->bo_va && mapping->bo_va->base.bo) {
2552 struct amdgpu_bo *bo;
2554 bo = mapping->bo_va->base.bo;
2555 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2560 trace_amdgpu_vm_bo_cs(mapping);
2565 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2567 * @adev: amdgpu_device pointer
2568 * @bo_va: requested bo_va
2570 * Remove @bo_va->bo from the requested vm.
2572 * Object have to be reserved!
2574 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2575 struct amdgpu_bo_va *bo_va)
2577 struct amdgpu_bo_va_mapping *mapping, *next;
2578 struct amdgpu_bo *bo = bo_va->base.bo;
2579 struct amdgpu_vm *vm = bo_va->base.vm;
2580 struct amdgpu_vm_bo_base **base;
2583 if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2584 vm->bulk_moveable = false;
2586 for (base = &bo_va->base.bo->vm_bo; *base;
2587 base = &(*base)->next) {
2588 if (*base != &bo_va->base)
2591 *base = bo_va->base.next;
2596 spin_lock(&vm->invalidated_lock);
2597 list_del(&bo_va->base.vm_status);
2598 spin_unlock(&vm->invalidated_lock);
2600 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2601 list_del(&mapping->list);
2602 amdgpu_vm_it_remove(mapping, &vm->va);
2603 mapping->bo_va = NULL;
2604 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2605 list_add(&mapping->list, &vm->freed);
2607 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2608 list_del(&mapping->list);
2609 amdgpu_vm_it_remove(mapping, &vm->va);
2610 amdgpu_vm_free_mapping(adev, vm, mapping,
2611 bo_va->last_pt_update);
2614 dma_fence_put(bo_va->last_pt_update);
2616 if (bo && bo_va->is_xgmi)
2617 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2623 * amdgpu_vm_evictable - check if we can evict a VM
2625 * @bo: A page table of the VM.
2627 * Check if it is possible to evict a VM.
2629 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2631 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2633 /* Page tables of a destroyed VM can go away immediately */
2634 if (!bo_base || !bo_base->vm)
2637 /* Don't evict VM page tables while they are busy */
2638 if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
2641 /* Try to block ongoing updates */
2642 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2645 /* Don't evict VM page tables while they are updated */
2646 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2647 amdgpu_vm_eviction_unlock(bo_base->vm);
2651 bo_base->vm->evicting = true;
2652 amdgpu_vm_eviction_unlock(bo_base->vm);
2657 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2659 * @adev: amdgpu_device pointer
2660 * @bo: amdgpu buffer object
2661 * @evicted: is the BO evicted
2663 * Mark @bo as invalid.
2665 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2666 struct amdgpu_bo *bo, bool evicted)
2668 struct amdgpu_vm_bo_base *bo_base;
2670 /* shadow bo doesn't have bo base, its validation needs its parent */
2671 if (bo->parent && bo->parent->shadow == bo)
2674 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2675 struct amdgpu_vm *vm = bo_base->vm;
2677 if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2678 amdgpu_vm_bo_evicted(bo_base);
2684 bo_base->moved = true;
2686 if (bo->tbo.type == ttm_bo_type_kernel)
2687 amdgpu_vm_bo_relocated(bo_base);
2688 else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2689 amdgpu_vm_bo_moved(bo_base);
2691 amdgpu_vm_bo_invalidated(bo_base);
2696 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2701 * VM page table as power of two
2703 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2705 /* Total bits covered by PD + PTs */
2706 unsigned bits = ilog2(vm_size) + 18;
2708 /* Make sure the PD is 4K in size up to 8GB address space.
2709 Above that split equal between PD and PTs */
2713 return ((bits + 3) / 2);
2717 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2719 * @adev: amdgpu_device pointer
2720 * @min_vm_size: the minimum vm size in GB if it's set auto
2721 * @fragment_size_default: Default PTE fragment size
2722 * @max_level: max VMPT level
2723 * @max_bits: max address space size in bits
2726 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2727 uint32_t fragment_size_default, unsigned max_level,
2730 unsigned int max_size = 1 << (max_bits - 30);
2731 unsigned int vm_size;
2734 /* adjust vm size first */
2735 if (amdgpu_vm_size != -1) {
2736 vm_size = amdgpu_vm_size;
2737 if (vm_size > max_size) {
2738 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2739 amdgpu_vm_size, max_size);
2744 unsigned int phys_ram_gb;
2746 /* Optimal VM size depends on the amount of physical
2747 * RAM available. Underlying requirements and
2750 * - Need to map system memory and VRAM from all GPUs
2751 * - VRAM from other GPUs not known here
2752 * - Assume VRAM <= system memory
2753 * - On GFX8 and older, VM space can be segmented for
2755 * - Need to allow room for fragmentation, guard pages etc.
2757 * This adds up to a rough guess of system memory x3.
2758 * Round up to power of two to maximize the available
2759 * VM size with the given page table size.
2762 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2763 (1 << 30) - 1) >> 30;
2764 vm_size = roundup_pow_of_two(
2765 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2768 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2770 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2771 if (amdgpu_vm_block_size != -1)
2772 tmp >>= amdgpu_vm_block_size - 9;
2773 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2774 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2775 switch (adev->vm_manager.num_level) {
2777 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2780 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2783 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2786 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2788 /* block size depends on vm size and hw setup*/
2789 if (amdgpu_vm_block_size != -1)
2790 adev->vm_manager.block_size =
2791 min((unsigned)amdgpu_vm_block_size, max_bits
2792 - AMDGPU_GPU_PAGE_SHIFT
2793 - 9 * adev->vm_manager.num_level);
2794 else if (adev->vm_manager.num_level > 1)
2795 adev->vm_manager.block_size = 9;
2797 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2799 if (amdgpu_vm_fragment_size == -1)
2800 adev->vm_manager.fragment_size = fragment_size_default;
2802 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2804 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2805 vm_size, adev->vm_manager.num_level + 1,
2806 adev->vm_manager.block_size,
2807 adev->vm_manager.fragment_size);
2811 * amdgpu_vm_wait_idle - wait for the VM to become idle
2813 * @vm: VM object to wait for
2814 * @timeout: timeout to wait for VM to become idle
2816 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2818 timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2819 true, true, timeout);
2823 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2827 * amdgpu_vm_init - initialize a vm instance
2829 * @adev: amdgpu_device pointer
2831 * @pasid: Process address space identifier
2836 * 0 for success, error for failure.
2838 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2840 struct amdgpu_bo *root;
2843 vm->va = RB_ROOT_CACHED;
2844 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2845 vm->reserved_vmid[i] = NULL;
2846 INIT_LIST_HEAD(&vm->evicted);
2847 INIT_LIST_HEAD(&vm->relocated);
2848 INIT_LIST_HEAD(&vm->moved);
2849 INIT_LIST_HEAD(&vm->idle);
2850 INIT_LIST_HEAD(&vm->invalidated);
2851 spin_lock_init(&vm->invalidated_lock);
2852 INIT_LIST_HEAD(&vm->freed);
2853 INIT_LIST_HEAD(&vm->done);
2855 /* create scheduler entities for page table updates */
2856 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2857 adev->vm_manager.vm_pte_scheds,
2858 adev->vm_manager.vm_pte_num_scheds, NULL);
2862 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2863 adev->vm_manager.vm_pte_scheds,
2864 adev->vm_manager.vm_pte_num_scheds, NULL);
2866 goto error_free_immediate;
2868 vm->pte_support_ats = false;
2869 vm->is_compute_context = false;
2871 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2872 AMDGPU_VM_USE_CPU_FOR_GFX);
2874 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2875 vm->use_cpu_for_update ? "CPU" : "SDMA");
2876 WARN_ONCE((vm->use_cpu_for_update &&
2877 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2878 "CPU update of VM recommended only for large BAR system\n");
2880 if (vm->use_cpu_for_update)
2881 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2883 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2884 vm->last_update = NULL;
2885 vm->last_unlocked = dma_fence_get_stub();
2887 mutex_init(&vm->eviction_lock);
2888 vm->evicting = false;
2890 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2893 goto error_free_delayed;
2895 r = amdgpu_bo_reserve(root, true);
2897 goto error_free_root;
2899 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2901 goto error_unreserve;
2903 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2905 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2907 goto error_unreserve;
2909 amdgpu_bo_unreserve(vm->root.base.bo);
2912 unsigned long flags;
2914 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2915 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2917 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2919 goto error_free_root;
2924 INIT_KFIFO(vm->faults);
2929 amdgpu_bo_unreserve(vm->root.base.bo);
2932 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2933 amdgpu_bo_unref(&vm->root.base.bo);
2934 vm->root.base.bo = NULL;
2937 dma_fence_put(vm->last_unlocked);
2938 drm_sched_entity_destroy(&vm->delayed);
2940 error_free_immediate:
2941 drm_sched_entity_destroy(&vm->immediate);
2947 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2949 * @adev: amdgpu_device pointer
2950 * @vm: the VM to check
2952 * check all entries of the root PD, if any subsequent PDs are allocated,
2953 * it means there are page table creating and filling, and is no a clean
2957 * 0 if this VM is clean
2959 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2960 struct amdgpu_vm *vm)
2962 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2963 unsigned int entries = amdgpu_vm_num_entries(adev, root);
2966 if (!(vm->root.entries))
2969 for (i = 0; i < entries; i++) {
2970 if (vm->root.entries[i].base.bo)
2978 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2980 * @adev: amdgpu_device pointer
2982 * @pasid: pasid to use
2984 * This only works on GFX VMs that don't have any BOs added and no
2985 * page tables allocated yet.
2987 * Changes the following VM parameters:
2988 * - use_cpu_for_update
2989 * - pte_supports_ats
2990 * - pasid (old PASID is released, because compute manages its own PASIDs)
2992 * Reinitializes the page directory to reflect the changed ATS
2996 * 0 for success, -errno for errors.
2998 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3001 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3004 r = amdgpu_bo_reserve(vm->root.base.bo, true);
3009 r = amdgpu_vm_check_clean_reserved(adev, vm);
3014 unsigned long flags;
3016 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3017 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3019 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3026 /* Check if PD needs to be reinitialized and do it before
3027 * changing any other state, in case it fails.
3029 if (pte_support_ats != vm->pte_support_ats) {
3030 vm->pte_support_ats = pte_support_ats;
3031 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
3036 /* Update VM state */
3037 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3038 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3039 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3040 vm->use_cpu_for_update ? "CPU" : "SDMA");
3041 WARN_ONCE((vm->use_cpu_for_update &&
3042 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3043 "CPU update of VM recommended only for large BAR system\n");
3045 if (vm->use_cpu_for_update) {
3046 /* Sync with last SDMA update/clear before switching to CPU */
3047 r = amdgpu_bo_sync_wait(vm->root.base.bo,
3048 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3052 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3054 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3056 dma_fence_put(vm->last_update);
3057 vm->last_update = NULL;
3058 vm->is_compute_context = true;
3061 unsigned long flags;
3063 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3064 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3065 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3067 /* Free the original amdgpu allocated pasid
3068 * Will be replaced with kfd allocated pasid
3070 amdgpu_pasid_free(vm->pasid);
3074 /* Free the shadow bo for compute VM */
3075 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3084 unsigned long flags;
3086 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3087 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3088 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3091 amdgpu_bo_unreserve(vm->root.base.bo);
3096 * amdgpu_vm_release_compute - release a compute vm
3097 * @adev: amdgpu_device pointer
3098 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3100 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3101 * pasid from vm. Compute should stop use of vm after this call.
3103 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3106 unsigned long flags;
3108 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3109 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3110 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3113 vm->is_compute_context = false;
3117 * amdgpu_vm_fini - tear down a vm instance
3119 * @adev: amdgpu_device pointer
3123 * Unbind the VM and remove all bos from the vm bo list
3125 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3127 struct amdgpu_bo_va_mapping *mapping, *tmp;
3128 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3129 struct amdgpu_bo *root;
3132 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3134 root = amdgpu_bo_ref(vm->root.base.bo);
3135 amdgpu_bo_reserve(root, true);
3137 unsigned long flags;
3139 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3140 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3141 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3145 dma_fence_wait(vm->last_unlocked, false);
3146 dma_fence_put(vm->last_unlocked);
3148 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3149 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3150 amdgpu_vm_prt_fini(adev, vm);
3151 prt_fini_needed = false;
3154 list_del(&mapping->list);
3155 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3158 amdgpu_vm_free_pts(adev, vm, NULL);
3159 amdgpu_bo_unreserve(root);
3160 amdgpu_bo_unref(&root);
3161 WARN_ON(vm->root.base.bo);
3163 drm_sched_entity_destroy(&vm->immediate);
3164 drm_sched_entity_destroy(&vm->delayed);
3166 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3167 dev_err(adev->dev, "still active bo inside vm\n");
3169 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3170 &vm->va.rb_root, rb) {
3171 /* Don't remove the mapping here, we don't want to trigger a
3172 * rebalance and the tree is about to be destroyed anyway.
3174 list_del(&mapping->list);
3178 dma_fence_put(vm->last_update);
3179 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3180 amdgpu_vmid_free_reserved(adev, vm, i);
3184 * amdgpu_vm_manager_init - init the VM manager
3186 * @adev: amdgpu_device pointer
3188 * Initialize the VM manager structures
3190 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3194 /* Concurrent flushes are only possible starting with Vega10 and
3195 * are broken on Navi10 and Navi14.
3197 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3198 adev->asic_type == CHIP_NAVI10 ||
3199 adev->asic_type == CHIP_NAVI14);
3200 amdgpu_vmid_mgr_init(adev);
3202 adev->vm_manager.fence_context =
3203 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3204 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3205 adev->vm_manager.seqno[i] = 0;
3207 spin_lock_init(&adev->vm_manager.prt_lock);
3208 atomic_set(&adev->vm_manager.num_prt_users, 0);
3210 /* If not overridden by the user, by default, only in large BAR systems
3211 * Compute VM tables will be updated by CPU
3213 #ifdef CONFIG_X86_64
3214 if (amdgpu_vm_update_mode == -1) {
3215 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3216 adev->vm_manager.vm_update_mode =
3217 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3219 adev->vm_manager.vm_update_mode = 0;
3221 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3223 adev->vm_manager.vm_update_mode = 0;
3226 idr_init(&adev->vm_manager.pasid_idr);
3227 spin_lock_init(&adev->vm_manager.pasid_lock);
3231 * amdgpu_vm_manager_fini - cleanup VM manager
3233 * @adev: amdgpu_device pointer
3235 * Cleanup the VM manager and free resources.
3237 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3239 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3240 idr_destroy(&adev->vm_manager.pasid_idr);
3242 amdgpu_vmid_mgr_fini(adev);
3246 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3248 * @dev: drm device pointer
3249 * @data: drm_amdgpu_vm
3250 * @filp: drm file pointer
3253 * 0 for success, -errno for errors.
3255 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3257 union drm_amdgpu_vm *args = data;
3258 struct amdgpu_device *adev = drm_to_adev(dev);
3259 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3260 long timeout = msecs_to_jiffies(2000);
3263 switch (args->in.op) {
3264 case AMDGPU_VM_OP_RESERVE_VMID:
3265 /* We only have requirement to reserve vmid from gfxhub */
3266 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3271 case AMDGPU_VM_OP_UNRESERVE_VMID:
3272 if (amdgpu_sriov_runtime(adev))
3273 timeout = 8 * timeout;
3275 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3276 * not referenced anymore.
3278 r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
3282 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3286 amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
3287 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3297 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3299 * @adev: drm device pointer
3300 * @pasid: PASID identifier for VM
3301 * @task_info: task_info to fill.
3303 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3304 struct amdgpu_task_info *task_info)
3306 struct amdgpu_vm *vm;
3307 unsigned long flags;
3309 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3311 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3313 *task_info = vm->task_info;
3315 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3319 * amdgpu_vm_set_task_info - Sets VMs task info.
3321 * @vm: vm for which to set the info
3323 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3325 if (vm->task_info.pid)
3328 vm->task_info.pid = current->pid;
3329 get_task_comm(vm->task_info.task_name, current);
3331 if (current->group_leader->mm != current->mm)
3334 vm->task_info.tgid = current->group_leader->pid;
3335 get_task_comm(vm->task_info.process_name, current->group_leader);
3339 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3340 * @adev: amdgpu device pointer
3341 * @pasid: PASID of the VM
3342 * @addr: Address of the fault
3344 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3345 * shouldn't be reported any more.
3347 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3350 bool is_compute_context = false;
3351 struct amdgpu_bo *root;
3352 uint64_t value, flags;
3353 struct amdgpu_vm *vm;
3356 spin_lock(&adev->vm_manager.pasid_lock);
3357 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3359 root = amdgpu_bo_ref(vm->root.base.bo);
3360 is_compute_context = vm->is_compute_context;
3364 spin_unlock(&adev->vm_manager.pasid_lock);
3369 addr /= AMDGPU_GPU_PAGE_SIZE;
3371 if (is_compute_context &&
3372 !svm_range_restore_pages(adev, pasid, addr)) {
3373 amdgpu_bo_unref(&root);
3377 r = amdgpu_bo_reserve(root, true);
3381 /* Double check that the VM still exists */
3382 spin_lock(&adev->vm_manager.pasid_lock);
3383 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3384 if (vm && vm->root.base.bo != root)
3386 spin_unlock(&adev->vm_manager.pasid_lock);
3390 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3393 if (is_compute_context) {
3394 /* Intentionally setting invalid PTE flag
3395 * combination to force a no-retry-fault
3397 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3400 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3401 /* Redirect the access to the dummy page */
3402 value = adev->dummy_page_addr;
3403 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3404 AMDGPU_PTE_WRITEABLE;
3407 /* Let the hw retry silently on the PTE */
3411 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3413 pr_debug("failed %d to reserve fence slot\n", r);
3417 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3418 addr, flags, value, NULL, NULL, NULL,
3423 r = amdgpu_vm_update_pdes(adev, vm, true);
3426 amdgpu_bo_unreserve(root);
3428 DRM_ERROR("Can't handle page fault (%d)\n", r);
3431 amdgpu_bo_unref(&root);
3436 #if defined(CONFIG_DEBUG_FS)
3438 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3440 * @vm: Requested VM for printing BO info
3443 * Print BO information in debugfs file for the VM
3445 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3447 struct amdgpu_bo_va *bo_va, *tmp;
3449 u64 total_evicted = 0;
3450 u64 total_relocated = 0;
3451 u64 total_moved = 0;
3452 u64 total_invalidated = 0;
3454 unsigned int total_idle_objs = 0;
3455 unsigned int total_evicted_objs = 0;
3456 unsigned int total_relocated_objs = 0;
3457 unsigned int total_moved_objs = 0;
3458 unsigned int total_invalidated_objs = 0;
3459 unsigned int total_done_objs = 0;
3460 unsigned int id = 0;
3462 seq_puts(m, "\tIdle BOs:\n");
3463 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3464 if (!bo_va->base.bo)
3466 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3468 total_idle_objs = id;
3471 seq_puts(m, "\tEvicted BOs:\n");
3472 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3473 if (!bo_va->base.bo)
3475 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3477 total_evicted_objs = id;
3480 seq_puts(m, "\tRelocated BOs:\n");
3481 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3482 if (!bo_va->base.bo)
3484 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3486 total_relocated_objs = id;
3489 seq_puts(m, "\tMoved BOs:\n");
3490 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3491 if (!bo_va->base.bo)
3493 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3495 total_moved_objs = id;
3498 seq_puts(m, "\tInvalidated BOs:\n");
3499 spin_lock(&vm->invalidated_lock);
3500 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3501 if (!bo_va->base.bo)
3503 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3505 total_invalidated_objs = id;
3508 seq_puts(m, "\tDone BOs:\n");
3509 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3510 if (!bo_va->base.bo)
3512 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3514 spin_unlock(&vm->invalidated_lock);
3515 total_done_objs = id;
3517 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3519 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3520 total_evicted_objs);
3521 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3522 total_relocated_objs);
3523 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3525 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3526 total_invalidated_objs);
3527 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,