2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
36 #include "amdgpu_trace.h"
37 #include "amdgpu_amdkfd.h"
38 #include "amdgpu_gmc.h"
39 #include "amdgpu_xgmi.h"
40 #include "amdgpu_dma_buf.h"
45 * GPUVM is similar to the legacy gart on older asics, however
46 * rather than there being a single global gart table
47 * for the entire GPU, there are multiple VM page tables active
48 * at any given time. The VM page tables can contain a mix
49 * vram pages and system memory pages and system memory pages
50 * can be mapped as snooped (cached system pages) or unsnooped
51 * (uncached system pages).
52 * Each VM has an ID associated with it and there is a page table
53 * associated with each VMID. When execting a command buffer,
54 * the kernel tells the the ring what VMID to use for that command
55 * buffer. VMIDs are allocated dynamically as commands are submitted.
56 * The userspace drivers maintain their own address space and the kernel
57 * sets up their pages tables accordingly when they submit their
58 * command buffers and a VMID is assigned.
59 * Cayman/Trinity support up to 8 active VMs at any given time;
63 #define START(node) ((node)->start)
64 #define LAST(node) ((node)->last)
66 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
67 START, LAST, static, amdgpu_vm_it)
73 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
75 struct amdgpu_prt_cb {
78 * @adev: amdgpu device
80 struct amdgpu_device *adev;
85 struct dma_fence_cb cb;
89 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
90 * happens while holding this lock anywhere to prevent deadlocks when
91 * an MMU notifier runs in reclaim-FS context.
93 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
95 mutex_lock(&vm->eviction_lock);
96 vm->saved_flags = memalloc_noreclaim_save();
99 static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
101 if (mutex_trylock(&vm->eviction_lock)) {
102 vm->saved_flags = memalloc_noreclaim_save();
108 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
110 memalloc_noreclaim_restore(vm->saved_flags);
111 mutex_unlock(&vm->eviction_lock);
115 * amdgpu_vm_level_shift - return the addr shift for each level
117 * @adev: amdgpu_device pointer
121 * The number of bits the pfn needs to be right shifted for a level.
123 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
130 return 9 * (AMDGPU_VM_PDB0 - level) +
131 adev->vm_manager.block_size;
140 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
142 * @adev: amdgpu_device pointer
146 * The number of entries in a page directory or page table.
148 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
151 unsigned shift = amdgpu_vm_level_shift(adev,
152 adev->vm_manager.root_level);
154 if (level == adev->vm_manager.root_level)
155 /* For the root directory */
156 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
158 else if (level != AMDGPU_VM_PTB)
159 /* Everything in between */
162 /* For the page tables on the leaves */
163 return AMDGPU_VM_PTE_COUNT(adev);
167 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
169 * @adev: amdgpu_device pointer
172 * The number of entries in the root page directory which needs the ATS setting.
174 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
178 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
179 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
183 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
185 * @adev: amdgpu_device pointer
189 * The mask to extract the entry number of a PD/PT from an address.
191 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
194 if (level <= adev->vm_manager.root_level)
196 else if (level != AMDGPU_VM_PTB)
199 return AMDGPU_VM_PTE_COUNT(adev) - 1;
203 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
205 * @adev: amdgpu_device pointer
209 * The size of the BO for a page directory or page table in bytes.
211 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
213 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
217 * amdgpu_vm_bo_evicted - vm_bo is evicted
219 * @vm_bo: vm_bo which is evicted
221 * State for PDs/PTs and per VM BOs which are not at the location they should
224 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
226 struct amdgpu_vm *vm = vm_bo->vm;
227 struct amdgpu_bo *bo = vm_bo->bo;
230 if (bo->tbo.type == ttm_bo_type_kernel)
231 list_move(&vm_bo->vm_status, &vm->evicted);
233 list_move_tail(&vm_bo->vm_status, &vm->evicted);
236 * amdgpu_vm_bo_moved - vm_bo is moved
238 * @vm_bo: vm_bo which is moved
240 * State for per VM BOs which are moved, but that change is not yet reflected
241 * in the page tables.
243 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
245 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
249 * amdgpu_vm_bo_idle - vm_bo is idle
251 * @vm_bo: vm_bo which is now idle
253 * State for PDs/PTs and per VM BOs which have gone through the state machine
256 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
258 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
259 vm_bo->moved = false;
263 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
265 * @vm_bo: vm_bo which is now invalidated
267 * State for normal BOs which are invalidated and that change not yet reflected
270 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
272 spin_lock(&vm_bo->vm->invalidated_lock);
273 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
274 spin_unlock(&vm_bo->vm->invalidated_lock);
278 * amdgpu_vm_bo_relocated - vm_bo is reloacted
280 * @vm_bo: vm_bo which is relocated
282 * State for PDs/PTs which needs to update their parent PD.
283 * For the root PD, just move to idle state.
285 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
287 if (vm_bo->bo->parent)
288 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
290 amdgpu_vm_bo_idle(vm_bo);
294 * amdgpu_vm_bo_done - vm_bo is done
296 * @vm_bo: vm_bo which is now done
298 * State for normal BOs which are invalidated and that change has been updated
301 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
303 spin_lock(&vm_bo->vm->invalidated_lock);
304 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
305 spin_unlock(&vm_bo->vm->invalidated_lock);
309 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
311 * @base: base structure for tracking BO usage in a VM
312 * @vm: vm to which bo is to be added
313 * @bo: amdgpu buffer object
315 * Initialize a bo_va_base structure and add it to the appropriate lists
318 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
319 struct amdgpu_vm *vm,
320 struct amdgpu_bo *bo)
325 INIT_LIST_HEAD(&base->vm_status);
329 base->next = bo->vm_bo;
332 if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
335 vm->bulk_moveable = false;
336 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
337 amdgpu_vm_bo_relocated(base);
339 amdgpu_vm_bo_idle(base);
341 if (bo->preferred_domains &
342 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
346 * we checked all the prerequisites, but it looks like this per vm bo
347 * is currently evicted. add the bo to the evicted list to make sure it
348 * is validated on next vm use to avoid fault.
350 amdgpu_vm_bo_evicted(base);
354 * amdgpu_vm_pt_parent - get the parent page directory
356 * @pt: child page table
358 * Helper to get the parent entry for the child page table. NULL if we are at
359 * the root page directory.
361 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
363 struct amdgpu_bo *parent = pt->base.bo->parent;
368 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
372 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
374 struct amdgpu_vm_pt_cursor {
376 struct amdgpu_vm_pt *parent;
377 struct amdgpu_vm_pt *entry;
382 * amdgpu_vm_pt_start - start PD/PT walk
384 * @adev: amdgpu_device pointer
385 * @vm: amdgpu_vm structure
386 * @start: start address of the walk
387 * @cursor: state to initialize
389 * Initialize a amdgpu_vm_pt_cursor to start a walk.
391 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
392 struct amdgpu_vm *vm, uint64_t start,
393 struct amdgpu_vm_pt_cursor *cursor)
396 cursor->parent = NULL;
397 cursor->entry = &vm->root;
398 cursor->level = adev->vm_manager.root_level;
402 * amdgpu_vm_pt_descendant - go to child node
404 * @adev: amdgpu_device pointer
405 * @cursor: current state
407 * Walk to the child node of the current node.
409 * True if the walk was possible, false otherwise.
411 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
412 struct amdgpu_vm_pt_cursor *cursor)
414 unsigned mask, shift, idx;
416 if (!cursor->entry->entries)
419 BUG_ON(!cursor->entry->base.bo);
420 mask = amdgpu_vm_entries_mask(adev, cursor->level);
421 shift = amdgpu_vm_level_shift(adev, cursor->level);
424 idx = (cursor->pfn >> shift) & mask;
425 cursor->parent = cursor->entry;
426 cursor->entry = &cursor->entry->entries[idx];
431 * amdgpu_vm_pt_sibling - go to sibling node
433 * @adev: amdgpu_device pointer
434 * @cursor: current state
436 * Walk to the sibling node of the current node.
438 * True if the walk was possible, false otherwise.
440 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
441 struct amdgpu_vm_pt_cursor *cursor)
443 unsigned shift, num_entries;
445 /* Root doesn't have a sibling */
449 /* Go to our parents and see if we got a sibling */
450 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
451 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
453 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
456 cursor->pfn += 1ULL << shift;
457 cursor->pfn &= ~((1ULL << shift) - 1);
463 * amdgpu_vm_pt_ancestor - go to parent node
465 * @cursor: current state
467 * Walk to the parent node of the current node.
469 * True if the walk was possible, false otherwise.
471 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
477 cursor->entry = cursor->parent;
478 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
483 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
485 * @adev: amdgpu_device pointer
486 * @cursor: current state
488 * Walk the PD/PT tree to the next node.
490 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
491 struct amdgpu_vm_pt_cursor *cursor)
493 /* First try a newborn child */
494 if (amdgpu_vm_pt_descendant(adev, cursor))
497 /* If that didn't worked try to find a sibling */
498 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
499 /* No sibling, go to our parents and grandparents */
500 if (!amdgpu_vm_pt_ancestor(cursor)) {
508 * amdgpu_vm_pt_first_dfs - start a deep first search
510 * @adev: amdgpu_device structure
511 * @vm: amdgpu_vm structure
512 * @start: optional cursor to start with
513 * @cursor: state to initialize
515 * Starts a deep first traversal of the PD/PT tree.
517 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
518 struct amdgpu_vm *vm,
519 struct amdgpu_vm_pt_cursor *start,
520 struct amdgpu_vm_pt_cursor *cursor)
525 amdgpu_vm_pt_start(adev, vm, 0, cursor);
526 while (amdgpu_vm_pt_descendant(adev, cursor));
530 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
532 * @start: starting point for the search
533 * @entry: current entry
536 * True when the search should continue, false otherwise.
538 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
539 struct amdgpu_vm_pt *entry)
541 return entry && (!start || entry != start->entry);
545 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
547 * @adev: amdgpu_device structure
548 * @cursor: current state
550 * Move the cursor to the next node in a deep first search.
552 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
553 struct amdgpu_vm_pt_cursor *cursor)
559 cursor->entry = NULL;
560 else if (amdgpu_vm_pt_sibling(adev, cursor))
561 while (amdgpu_vm_pt_descendant(adev, cursor));
563 amdgpu_vm_pt_ancestor(cursor);
567 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
569 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
570 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
571 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
572 amdgpu_vm_pt_continue_dfs((start), (entry)); \
573 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
576 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
578 * @vm: vm providing the BOs
579 * @validated: head of validation list
580 * @entry: entry to add
582 * Add the page directory to the list of BOs to
583 * validate for command submission.
585 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
586 struct list_head *validated,
587 struct amdgpu_bo_list_entry *entry)
590 entry->tv.bo = &vm->root.base.bo->tbo;
591 /* Two for VM updates, one for TTM and one for the CS job */
592 entry->tv.num_shared = 4;
593 entry->user_pages = NULL;
594 list_add(&entry->tv.head, validated);
598 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
600 * @bo: BO which was removed from the LRU
602 * Make sure the bulk_moveable flag is updated when a BO is removed from the
605 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
607 struct amdgpu_bo *abo;
608 struct amdgpu_vm_bo_base *bo_base;
610 if (!amdgpu_bo_is_amdgpu_bo(bo))
616 abo = ttm_to_amdgpu_bo(bo);
619 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
620 struct amdgpu_vm *vm = bo_base->vm;
622 if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
623 vm->bulk_moveable = false;
628 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
630 * @adev: amdgpu device pointer
631 * @vm: vm providing the BOs
633 * Move all BOs to the end of LRU and remember their positions to put them
636 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
637 struct amdgpu_vm *vm)
639 struct amdgpu_vm_bo_base *bo_base;
641 if (vm->bulk_moveable) {
642 spin_lock(&adev->mman.bdev.lru_lock);
643 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
644 spin_unlock(&adev->mman.bdev.lru_lock);
648 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
650 spin_lock(&adev->mman.bdev.lru_lock);
651 list_for_each_entry(bo_base, &vm->idle, vm_status) {
652 struct amdgpu_bo *bo = bo_base->bo;
657 ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
660 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
661 &bo->shadow->tbo.mem,
664 spin_unlock(&adev->mman.bdev.lru_lock);
666 vm->bulk_moveable = true;
670 * amdgpu_vm_validate_pt_bos - validate the page table BOs
672 * @adev: amdgpu device pointer
673 * @vm: vm providing the BOs
674 * @validate: callback to do the validation
675 * @param: parameter for the validation callback
677 * Validate the page table BOs on command submission if neccessary.
682 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
683 int (*validate)(void *p, struct amdgpu_bo *bo),
686 struct amdgpu_vm_bo_base *bo_base, *tmp;
689 vm->bulk_moveable &= list_empty(&vm->evicted);
691 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
692 struct amdgpu_bo *bo = bo_base->bo;
694 r = validate(param, bo);
698 if (bo->tbo.type != ttm_bo_type_kernel) {
699 amdgpu_vm_bo_moved(bo_base);
701 vm->update_funcs->map_table(bo);
702 amdgpu_vm_bo_relocated(bo_base);
706 amdgpu_vm_eviction_lock(vm);
707 vm->evicting = false;
708 amdgpu_vm_eviction_unlock(vm);
714 * amdgpu_vm_ready - check VM is ready for updates
718 * Check if all VM PDs/PTs are ready for updates
721 * True if eviction list is empty.
723 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
725 return list_empty(&vm->evicted);
729 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
731 * @adev: amdgpu_device pointer
732 * @vm: VM to clear BO from
734 * @immediate: use an immediate update
736 * Root PD needs to be reserved when calling this.
739 * 0 on success, errno otherwise.
741 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
742 struct amdgpu_vm *vm,
743 struct amdgpu_bo *bo,
746 struct ttm_operation_ctx ctx = { true, false };
747 unsigned level = adev->vm_manager.root_level;
748 struct amdgpu_vm_update_params params;
749 struct amdgpu_bo *ancestor = bo;
750 unsigned entries, ats_entries;
754 /* Figure out our place in the hierarchy */
755 if (ancestor->parent) {
757 while (ancestor->parent->parent) {
759 ancestor = ancestor->parent;
763 entries = amdgpu_bo_size(bo) / 8;
764 if (!vm->pte_support_ats) {
767 } else if (!bo->parent) {
768 ats_entries = amdgpu_vm_num_ats_entries(adev);
769 ats_entries = min(ats_entries, entries);
770 entries -= ats_entries;
773 struct amdgpu_vm_pt *pt;
775 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
776 ats_entries = amdgpu_vm_num_ats_entries(adev);
777 if ((pt - vm->root.entries) >= ats_entries) {
780 ats_entries = entries;
785 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
790 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
796 r = vm->update_funcs->map_table(bo);
800 memset(¶ms, 0, sizeof(params));
803 params.immediate = immediate;
805 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
811 uint64_t value = 0, flags;
813 flags = AMDGPU_PTE_DEFAULT_ATC;
814 if (level != AMDGPU_VM_PTB) {
815 /* Handle leaf PDEs as PTEs */
816 flags |= AMDGPU_PDE_PTE;
817 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
820 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
825 addr += ats_entries * 8;
829 uint64_t value = 0, flags = 0;
831 if (adev->asic_type >= CHIP_VEGA10) {
832 if (level != AMDGPU_VM_PTB) {
833 /* Handle leaf PDEs as PTEs */
834 flags |= AMDGPU_PDE_PTE;
835 amdgpu_gmc_get_vm_pde(adev, level,
838 /* Workaround for fault priority problem on GMC9 */
839 flags = AMDGPU_PTE_EXECUTABLE;
843 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
849 return vm->update_funcs->commit(¶ms, NULL);
853 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
855 * @adev: amdgpu_device pointer
857 * @level: the page table level
858 * @immediate: use a immediate update
859 * @bp: resulting BO allocation parameters
861 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
862 int level, bool immediate,
863 struct amdgpu_bo_param *bp)
865 memset(bp, 0, sizeof(*bp));
867 bp->size = amdgpu_vm_bo_size(adev, level);
868 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
869 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
870 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
871 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
872 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
873 bp->bo_ptr_size = sizeof(struct amdgpu_bo);
874 if (vm->use_cpu_for_update)
875 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
876 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
877 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
878 bp->type = ttm_bo_type_kernel;
879 bp->no_wait_gpu = immediate;
880 if (vm->root.base.bo)
881 bp->resv = vm->root.base.bo->tbo.base.resv;
885 * amdgpu_vm_alloc_pts - Allocate a specific page table
887 * @adev: amdgpu_device pointer
888 * @vm: VM to allocate page tables for
889 * @cursor: Which page table to allocate
890 * @immediate: use an immediate update
892 * Make sure a specific page table or directory is allocated.
895 * 1 if page table needed to be allocated, 0 if page table was already
896 * allocated, negative errno if an error occurred.
898 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
899 struct amdgpu_vm *vm,
900 struct amdgpu_vm_pt_cursor *cursor,
903 struct amdgpu_vm_pt *entry = cursor->entry;
904 struct amdgpu_bo_param bp;
905 struct amdgpu_bo *pt;
908 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
909 unsigned num_entries;
911 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
912 entry->entries = kvmalloc_array(num_entries,
913 sizeof(*entry->entries),
914 GFP_KERNEL | __GFP_ZERO);
922 amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, &bp);
924 r = amdgpu_bo_create(adev, &bp, &pt);
928 /* Keep a reference to the root directory to avoid
929 * freeing them up in the wrong order.
931 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
932 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
934 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
941 amdgpu_bo_unref(&pt->shadow);
942 amdgpu_bo_unref(&pt);
947 * amdgpu_vm_free_table - fre one PD/PT
949 * @entry: PDE to free
951 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
953 if (entry->base.bo) {
954 entry->base.bo->vm_bo = NULL;
955 list_del(&entry->base.vm_status);
956 amdgpu_bo_unref(&entry->base.bo->shadow);
957 amdgpu_bo_unref(&entry->base.bo);
959 kvfree(entry->entries);
960 entry->entries = NULL;
964 * amdgpu_vm_free_pts - free PD/PT levels
966 * @adev: amdgpu device structure
967 * @vm: amdgpu vm structure
968 * @start: optional cursor where to start freeing PDs/PTs
970 * Free the page directory or page table level and all sub levels.
972 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
973 struct amdgpu_vm *vm,
974 struct amdgpu_vm_pt_cursor *start)
976 struct amdgpu_vm_pt_cursor cursor;
977 struct amdgpu_vm_pt *entry;
979 vm->bulk_moveable = false;
981 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
982 amdgpu_vm_free_table(entry);
985 amdgpu_vm_free_table(start->entry);
989 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
991 * @adev: amdgpu_device pointer
993 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
995 const struct amdgpu_ip_block *ip_block;
996 bool has_compute_vm_bug;
997 struct amdgpu_ring *ring;
1000 has_compute_vm_bug = false;
1002 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1004 /* Compute has a VM bug for GFX version < 7.
1005 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1006 if (ip_block->version->major <= 7)
1007 has_compute_vm_bug = true;
1008 else if (ip_block->version->major == 8)
1009 if (adev->gfx.mec_fw_version < 673)
1010 has_compute_vm_bug = true;
1013 for (i = 0; i < adev->num_rings; i++) {
1014 ring = adev->rings[i];
1015 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1016 /* only compute rings */
1017 ring->has_compute_vm_bug = has_compute_vm_bug;
1019 ring->has_compute_vm_bug = false;
1024 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1026 * @ring: ring on which the job will be submitted
1027 * @job: job to submit
1030 * True if sync is needed.
1032 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1033 struct amdgpu_job *job)
1035 struct amdgpu_device *adev = ring->adev;
1036 unsigned vmhub = ring->funcs->vmhub;
1037 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1038 struct amdgpu_vmid *id;
1039 bool gds_switch_needed;
1040 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1044 id = &id_mgr->ids[job->vmid];
1045 gds_switch_needed = ring->funcs->emit_gds_switch && (
1046 id->gds_base != job->gds_base ||
1047 id->gds_size != job->gds_size ||
1048 id->gws_base != job->gws_base ||
1049 id->gws_size != job->gws_size ||
1050 id->oa_base != job->oa_base ||
1051 id->oa_size != job->oa_size);
1053 if (amdgpu_vmid_had_gpu_reset(adev, id))
1056 return vm_flush_needed || gds_switch_needed;
1060 * amdgpu_vm_flush - hardware flush the vm
1062 * @ring: ring to use for flush
1064 * @need_pipe_sync: is pipe sync needed
1066 * Emit a VM flush when it is necessary.
1069 * 0 on success, errno otherwise.
1071 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1072 bool need_pipe_sync)
1074 struct amdgpu_device *adev = ring->adev;
1075 unsigned vmhub = ring->funcs->vmhub;
1076 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1077 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1078 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1079 id->gds_base != job->gds_base ||
1080 id->gds_size != job->gds_size ||
1081 id->gws_base != job->gws_base ||
1082 id->gws_size != job->gws_size ||
1083 id->oa_base != job->oa_base ||
1084 id->oa_size != job->oa_size);
1085 bool vm_flush_needed = job->vm_needs_flush;
1086 struct dma_fence *fence = NULL;
1087 bool pasid_mapping_needed = false;
1088 unsigned patch_offset = 0;
1089 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1092 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1093 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1095 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1096 gds_switch_needed = true;
1097 vm_flush_needed = true;
1098 pasid_mapping_needed = true;
1101 mutex_lock(&id_mgr->lock);
1102 if (id->pasid != job->pasid || !id->pasid_mapping ||
1103 !dma_fence_is_signaled(id->pasid_mapping))
1104 pasid_mapping_needed = true;
1105 mutex_unlock(&id_mgr->lock);
1107 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1108 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1109 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1110 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1111 ring->funcs->emit_wreg;
1113 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1116 if (ring->funcs->init_cond_exec)
1117 patch_offset = amdgpu_ring_init_cond_exec(ring);
1120 amdgpu_ring_emit_pipeline_sync(ring);
1122 if (vm_flush_needed) {
1123 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1124 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1127 if (pasid_mapping_needed)
1128 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1130 if (vm_flush_needed || pasid_mapping_needed) {
1131 r = amdgpu_fence_emit(ring, &fence, 0);
1136 if (vm_flush_needed) {
1137 mutex_lock(&id_mgr->lock);
1138 dma_fence_put(id->last_flush);
1139 id->last_flush = dma_fence_get(fence);
1140 id->current_gpu_reset_count =
1141 atomic_read(&adev->gpu_reset_counter);
1142 mutex_unlock(&id_mgr->lock);
1145 if (pasid_mapping_needed) {
1146 mutex_lock(&id_mgr->lock);
1147 id->pasid = job->pasid;
1148 dma_fence_put(id->pasid_mapping);
1149 id->pasid_mapping = dma_fence_get(fence);
1150 mutex_unlock(&id_mgr->lock);
1152 dma_fence_put(fence);
1154 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1155 id->gds_base = job->gds_base;
1156 id->gds_size = job->gds_size;
1157 id->gws_base = job->gws_base;
1158 id->gws_size = job->gws_size;
1159 id->oa_base = job->oa_base;
1160 id->oa_size = job->oa_size;
1161 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1162 job->gds_size, job->gws_base,
1163 job->gws_size, job->oa_base,
1167 if (ring->funcs->patch_cond_exec)
1168 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1170 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1171 if (ring->funcs->emit_switch_buffer) {
1172 amdgpu_ring_emit_switch_buffer(ring);
1173 amdgpu_ring_emit_switch_buffer(ring);
1179 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1182 * @bo: requested buffer object
1184 * Find @bo inside the requested vm.
1185 * Search inside the @bos vm list for the requested vm
1186 * Returns the found bo_va or NULL if none is found
1188 * Object has to be reserved!
1191 * Found bo_va or NULL.
1193 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1194 struct amdgpu_bo *bo)
1196 struct amdgpu_vm_bo_base *base;
1198 for (base = bo->vm_bo; base; base = base->next) {
1202 return container_of(base, struct amdgpu_bo_va, base);
1208 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1210 * @pages_addr: optional DMA address to use for lookup
1211 * @addr: the unmapped addr
1213 * Look up the physical address of the page that the pte resolves
1217 * The pointer for the page table entry.
1219 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1223 /* page table offset */
1224 result = pages_addr[addr >> PAGE_SHIFT];
1226 /* in case cpu page size != gpu page size*/
1227 result |= addr & (~PAGE_MASK);
1229 result &= 0xFFFFFFFFFFFFF000ULL;
1235 * amdgpu_vm_update_pde - update a single level in the hierarchy
1237 * @params: parameters for the update
1239 * @entry: entry to update
1241 * Makes sure the requested entry in parent is up to date.
1243 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1244 struct amdgpu_vm *vm,
1245 struct amdgpu_vm_pt *entry)
1247 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1248 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1249 uint64_t pde, pt, flags;
1252 for (level = 0, pbo = bo->parent; pbo; ++level)
1255 level += params->adev->vm_manager.root_level;
1256 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1257 pde = (entry - parent->entries) * 8;
1258 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1262 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1264 * @adev: amdgpu_device pointer
1267 * Mark all PD level as invalid after an error.
1269 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1270 struct amdgpu_vm *vm)
1272 struct amdgpu_vm_pt_cursor cursor;
1273 struct amdgpu_vm_pt *entry;
1275 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1276 if (entry->base.bo && !entry->base.moved)
1277 amdgpu_vm_bo_relocated(&entry->base);
1281 * amdgpu_vm_update_pdes - make sure that all directories are valid
1283 * @adev: amdgpu_device pointer
1285 * @immediate: submit immediately to the paging queue
1287 * Makes sure all directories are up to date.
1290 * 0 for success, error for failure.
1292 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1293 struct amdgpu_vm *vm, bool immediate)
1295 struct amdgpu_vm_update_params params;
1298 if (list_empty(&vm->relocated))
1301 memset(¶ms, 0, sizeof(params));
1304 params.immediate = immediate;
1306 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1310 while (!list_empty(&vm->relocated)) {
1311 struct amdgpu_vm_pt *entry;
1313 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1315 amdgpu_vm_bo_idle(&entry->base);
1317 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1322 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1328 amdgpu_vm_invalidate_pds(adev, vm);
1333 * amdgpu_vm_update_flags - figure out flags for PTE updates
1335 * Make sure to set the right flags for the PTEs at the desired level.
1337 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1338 struct amdgpu_bo *bo, unsigned level,
1339 uint64_t pe, uint64_t addr,
1340 unsigned count, uint32_t incr,
1344 if (level != AMDGPU_VM_PTB) {
1345 flags |= AMDGPU_PDE_PTE;
1346 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1348 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1349 !(flags & AMDGPU_PTE_VALID) &&
1350 !(flags & AMDGPU_PTE_PRT)) {
1352 /* Workaround for fault priority problem on GMC9 */
1353 flags |= AMDGPU_PTE_EXECUTABLE;
1356 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1361 * amdgpu_vm_fragment - get fragment for PTEs
1363 * @params: see amdgpu_vm_update_params definition
1364 * @start: first PTE to handle
1365 * @end: last PTE to handle
1366 * @flags: hw mapping flags
1367 * @frag: resulting fragment size
1368 * @frag_end: end of this fragment
1370 * Returns the first possible fragment for the start and end address.
1372 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1373 uint64_t start, uint64_t end, uint64_t flags,
1374 unsigned int *frag, uint64_t *frag_end)
1377 * The MC L1 TLB supports variable sized pages, based on a fragment
1378 * field in the PTE. When this field is set to a non-zero value, page
1379 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1380 * flags are considered valid for all PTEs within the fragment range
1381 * and corresponding mappings are assumed to be physically contiguous.
1383 * The L1 TLB can store a single PTE for the whole fragment,
1384 * significantly increasing the space available for translation
1385 * caching. This leads to large improvements in throughput when the
1386 * TLB is under pressure.
1388 * The L2 TLB distributes small and large fragments into two
1389 * asymmetric partitions. The large fragment cache is significantly
1390 * larger. Thus, we try to use large fragments wherever possible.
1391 * Userspace can support this by aligning virtual base address and
1392 * allocation size to the fragment size.
1394 * Starting with Vega10 the fragment size only controls the L1. The L2
1395 * is now directly feed with small/huge/giant pages from the walker.
1399 if (params->adev->asic_type < CHIP_VEGA10)
1400 max_frag = params->adev->vm_manager.fragment_size;
1404 /* system pages are non continuously */
1405 if (params->pages_addr) {
1411 /* This intentionally wraps around if no bit is set */
1412 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1413 if (*frag >= max_frag) {
1415 *frag_end = end & ~((1ULL << max_frag) - 1);
1417 *frag_end = start + (1 << *frag);
1422 * amdgpu_vm_update_ptes - make sure that page tables are valid
1424 * @params: see amdgpu_vm_update_params definition
1425 * @start: start of GPU address range
1426 * @end: end of GPU address range
1427 * @dst: destination address to map to, the next dst inside the function
1428 * @flags: mapping flags
1430 * Update the page tables in the range @start - @end.
1433 * 0 for success, -EINVAL for failure.
1435 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1436 uint64_t start, uint64_t end,
1437 uint64_t dst, uint64_t flags)
1439 struct amdgpu_device *adev = params->adev;
1440 struct amdgpu_vm_pt_cursor cursor;
1441 uint64_t frag_start = start, frag_end;
1445 /* figure out the initial fragment */
1446 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1448 /* walk over the address space and update the PTs */
1449 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1450 while (cursor.pfn < end) {
1451 unsigned shift, parent_shift, mask;
1452 uint64_t incr, entry_end, pe_start;
1453 struct amdgpu_bo *pt;
1455 if (!params->unlocked) {
1456 /* make sure that the page tables covering the
1457 * address range are actually allocated
1459 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1460 &cursor, params->immediate);
1465 shift = amdgpu_vm_level_shift(adev, cursor.level);
1466 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1467 if (params->unlocked) {
1468 /* Unlocked updates are only allowed on the leaves */
1469 if (amdgpu_vm_pt_descendant(adev, &cursor))
1471 } else if (adev->asic_type < CHIP_VEGA10 &&
1472 (flags & AMDGPU_PTE_VALID)) {
1473 /* No huge page support before GMC v9 */
1474 if (cursor.level != AMDGPU_VM_PTB) {
1475 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1479 } else if (frag < shift) {
1480 /* We can't use this level when the fragment size is
1481 * smaller than the address shift. Go to the next
1482 * child entry and try again.
1484 if (amdgpu_vm_pt_descendant(adev, &cursor))
1486 } else if (frag >= parent_shift) {
1487 /* If the fragment size is even larger than the parent
1488 * shift we should go up one level and check it again.
1490 if (!amdgpu_vm_pt_ancestor(&cursor))
1495 pt = cursor.entry->base.bo;
1497 /* We need all PDs and PTs for mapping something, */
1498 if (flags & AMDGPU_PTE_VALID)
1501 /* but unmapping something can happen at a higher
1504 if (!amdgpu_vm_pt_ancestor(&cursor))
1507 pt = cursor.entry->base.bo;
1508 shift = parent_shift;
1509 frag_end = max(frag_end, ALIGN(frag_start + 1,
1513 /* Looks good so far, calculate parameters for the update */
1514 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1515 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1516 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1517 entry_end = ((uint64_t)mask + 1) << shift;
1518 entry_end += cursor.pfn & ~(entry_end - 1);
1519 entry_end = min(entry_end, end);
1522 struct amdgpu_vm *vm = params->vm;
1523 uint64_t upd_end = min(entry_end, frag_end);
1524 unsigned nptes = (upd_end - frag_start) >> shift;
1525 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1527 /* This can happen when we set higher level PDs to
1528 * silent to stop fault floods.
1530 nptes = max(nptes, 1u);
1532 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1533 nptes, dst, incr, upd_flags,
1535 vm->immediate.fence_context);
1536 amdgpu_vm_update_flags(params, pt, cursor.level,
1537 pe_start, dst, nptes, incr,
1540 pe_start += nptes * 8;
1541 dst += nptes * incr;
1543 frag_start = upd_end;
1544 if (frag_start >= frag_end) {
1545 /* figure out the next fragment */
1546 amdgpu_vm_fragment(params, frag_start, end,
1547 flags, &frag, &frag_end);
1551 } while (frag_start < entry_end);
1553 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1554 /* Free all child entries.
1555 * Update the tables with the flags and addresses and free up subsequent
1556 * tables in the case of huge pages or freed up areas.
1557 * This is the maximum you can free, because all other page tables are not
1558 * completely covered by the range and so potentially still in use.
1560 while (cursor.pfn < frag_start) {
1561 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1562 amdgpu_vm_pt_next(adev, &cursor);
1565 } else if (frag >= shift) {
1566 /* or just move on to the next on the same level. */
1567 amdgpu_vm_pt_next(adev, &cursor);
1575 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1577 * @adev: amdgpu_device pointer of the VM
1578 * @bo_adev: amdgpu_device pointer of the mapped BO
1580 * @immediate: immediate submission in a page fault
1581 * @unlocked: unlocked invalidation during MM callback
1582 * @resv: fences we need to sync to
1583 * @start: start of mapped range
1584 * @last: last mapped entry
1585 * @flags: flags for the entries
1586 * @offset: offset into nodes and pages_addr
1587 * @nodes: array of drm_mm_nodes with the MC addresses
1588 * @pages_addr: DMA addresses to use for mapping
1589 * @fence: optional resulting fence
1591 * Fill in the page table entries between @start and @last.
1594 * 0 for success, -EINVAL for failure.
1596 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1597 struct amdgpu_device *bo_adev,
1598 struct amdgpu_vm *vm, bool immediate,
1599 bool unlocked, struct dma_resv *resv,
1600 uint64_t start, uint64_t last,
1601 uint64_t flags, uint64_t offset,
1602 struct drm_mm_node *nodes,
1603 dma_addr_t *pages_addr,
1604 struct dma_fence **fence)
1606 struct amdgpu_vm_update_params params;
1607 enum amdgpu_sync_mode sync_mode;
1611 memset(¶ms, 0, sizeof(params));
1614 params.immediate = immediate;
1615 params.pages_addr = pages_addr;
1616 params.unlocked = unlocked;
1618 /* Implicitly sync to command submissions in the same VM before
1619 * unmapping. Sync to moving fences before mapping.
1621 if (!(flags & AMDGPU_PTE_VALID))
1622 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1624 sync_mode = AMDGPU_SYNC_EXPLICIT;
1626 pfn = offset >> PAGE_SHIFT;
1628 while (pfn >= nodes->size) {
1634 amdgpu_vm_eviction_lock(vm);
1640 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1641 struct dma_fence *tmp = dma_fence_get_stub();
1643 amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
1644 swap(vm->last_unlocked, tmp);
1648 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1653 uint64_t tmp, num_entries, addr;
1656 num_entries = last - start + 1;
1658 addr = nodes->start << PAGE_SHIFT;
1659 num_entries = min((nodes->size - pfn) *
1660 AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries);
1666 bool contiguous = true;
1668 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1671 contiguous = pages_addr[pfn + 1] ==
1672 pages_addr[pfn] + PAGE_SIZE;
1675 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1676 for (count = 2; count < tmp; ++count) {
1677 uint64_t idx = pfn + count;
1679 if (contiguous != (pages_addr[idx] ==
1680 pages_addr[idx - 1] + PAGE_SIZE))
1683 num_entries = count *
1684 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1688 addr = pfn << PAGE_SHIFT;
1689 params.pages_addr = pages_addr;
1691 addr = pages_addr[pfn];
1692 params.pages_addr = NULL;
1695 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1696 addr += bo_adev->vm_manager.vram_base_offset;
1697 addr += pfn << PAGE_SHIFT;
1700 tmp = start + num_entries;
1701 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1705 pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1706 if (nodes && nodes->size == pfn) {
1712 } while (unlikely(start != last + 1));
1714 r = vm->update_funcs->commit(¶ms, fence);
1717 amdgpu_vm_eviction_unlock(vm);
1721 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1722 uint64_t *gtt_mem, uint64_t *cpu_mem)
1724 struct amdgpu_bo_va *bo_va, *tmp;
1726 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1727 if (!bo_va->base.bo)
1729 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1732 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1733 if (!bo_va->base.bo)
1735 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1738 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1739 if (!bo_va->base.bo)
1741 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1744 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1745 if (!bo_va->base.bo)
1747 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1750 spin_lock(&vm->invalidated_lock);
1751 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1752 if (!bo_va->base.bo)
1754 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1757 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1758 if (!bo_va->base.bo)
1760 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1763 spin_unlock(&vm->invalidated_lock);
1766 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1768 * @adev: amdgpu_device pointer
1769 * @bo_va: requested BO and VM object
1770 * @clear: if true clear the entries
1772 * Fill in the page table entries for @bo_va.
1775 * 0 for success, -EINVAL for failure.
1777 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1780 struct amdgpu_bo *bo = bo_va->base.bo;
1781 struct amdgpu_vm *vm = bo_va->base.vm;
1782 struct amdgpu_bo_va_mapping *mapping;
1783 dma_addr_t *pages_addr = NULL;
1784 struct ttm_resource *mem;
1785 struct drm_mm_node *nodes;
1786 struct dma_fence **last_update;
1787 struct dma_resv *resv;
1789 struct amdgpu_device *bo_adev = adev;
1795 resv = vm->root.base.bo->tbo.base.resv;
1797 struct drm_gem_object *obj = &bo->tbo.base;
1799 resv = bo->tbo.base.resv;
1800 if (obj->import_attach && bo_va->is_xgmi) {
1801 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1802 struct drm_gem_object *gobj = dma_buf->priv;
1803 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1805 if (abo->tbo.mem.mem_type == TTM_PL_VRAM)
1806 bo = gem_to_amdgpu_bo(gobj);
1809 nodes = mem->mm_node;
1810 if (mem->mem_type == TTM_PL_TT)
1811 pages_addr = bo->tbo.ttm->dma_address;
1815 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1817 if (amdgpu_bo_encrypted(bo))
1818 flags |= AMDGPU_PTE_TMZ;
1820 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1825 if (clear || (bo && bo->tbo.base.resv ==
1826 vm->root.base.bo->tbo.base.resv))
1827 last_update = &vm->last_update;
1829 last_update = &bo_va->last_pt_update;
1831 if (!clear && bo_va->base.moved) {
1832 bo_va->base.moved = false;
1833 list_splice_init(&bo_va->valids, &bo_va->invalids);
1835 } else if (bo_va->cleared != clear) {
1836 list_splice_init(&bo_va->valids, &bo_va->invalids);
1839 list_for_each_entry(mapping, &bo_va->invalids, list) {
1840 uint64_t update_flags = flags;
1842 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1843 * but in case of something, we filter the flags in first place
1845 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1846 update_flags &= ~AMDGPU_PTE_READABLE;
1847 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1848 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1850 /* Apply ASIC specific mapping flags */
1851 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1853 trace_amdgpu_vm_bo_update(mapping);
1855 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1856 resv, mapping->start,
1857 mapping->last, update_flags,
1858 mapping->offset, nodes,
1859 pages_addr, last_update);
1864 /* If the BO is not in its preferred location add it back to
1865 * the evicted list so that it gets validated again on the
1866 * next command submission.
1868 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1869 uint32_t mem_type = bo->tbo.mem.mem_type;
1871 if (!(bo->preferred_domains &
1872 amdgpu_mem_type_to_domain(mem_type)))
1873 amdgpu_vm_bo_evicted(&bo_va->base);
1875 amdgpu_vm_bo_idle(&bo_va->base);
1877 amdgpu_vm_bo_done(&bo_va->base);
1880 list_splice_init(&bo_va->invalids, &bo_va->valids);
1881 bo_va->cleared = clear;
1883 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1884 list_for_each_entry(mapping, &bo_va->valids, list)
1885 trace_amdgpu_vm_bo_mapping(mapping);
1892 * amdgpu_vm_update_prt_state - update the global PRT state
1894 * @adev: amdgpu_device pointer
1896 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1898 unsigned long flags;
1901 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1902 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1903 adev->gmc.gmc_funcs->set_prt(adev, enable);
1904 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1908 * amdgpu_vm_prt_get - add a PRT user
1910 * @adev: amdgpu_device pointer
1912 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1914 if (!adev->gmc.gmc_funcs->set_prt)
1917 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1918 amdgpu_vm_update_prt_state(adev);
1922 * amdgpu_vm_prt_put - drop a PRT user
1924 * @adev: amdgpu_device pointer
1926 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1928 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1929 amdgpu_vm_update_prt_state(adev);
1933 * amdgpu_vm_prt_cb - callback for updating the PRT status
1935 * @fence: fence for the callback
1936 * @_cb: the callback function
1938 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1940 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1942 amdgpu_vm_prt_put(cb->adev);
1947 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1949 * @adev: amdgpu_device pointer
1950 * @fence: fence for the callback
1952 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1953 struct dma_fence *fence)
1955 struct amdgpu_prt_cb *cb;
1957 if (!adev->gmc.gmc_funcs->set_prt)
1960 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1962 /* Last resort when we are OOM */
1964 dma_fence_wait(fence, false);
1966 amdgpu_vm_prt_put(adev);
1969 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1971 amdgpu_vm_prt_cb(fence, &cb->cb);
1976 * amdgpu_vm_free_mapping - free a mapping
1978 * @adev: amdgpu_device pointer
1980 * @mapping: mapping to be freed
1981 * @fence: fence of the unmap operation
1983 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1985 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1986 struct amdgpu_vm *vm,
1987 struct amdgpu_bo_va_mapping *mapping,
1988 struct dma_fence *fence)
1990 if (mapping->flags & AMDGPU_PTE_PRT)
1991 amdgpu_vm_add_prt_cb(adev, fence);
1996 * amdgpu_vm_prt_fini - finish all prt mappings
1998 * @adev: amdgpu_device pointer
2001 * Register a cleanup callback to disable PRT support after VM dies.
2003 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2005 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2006 struct dma_fence *excl, **shared;
2007 unsigned i, shared_count;
2010 r = dma_resv_get_fences_rcu(resv, &excl,
2011 &shared_count, &shared);
2013 /* Not enough memory to grab the fence list, as last resort
2014 * block for all the fences to complete.
2016 dma_resv_wait_timeout_rcu(resv, true, false,
2017 MAX_SCHEDULE_TIMEOUT);
2021 /* Add a callback for each fence in the reservation object */
2022 amdgpu_vm_prt_get(adev);
2023 amdgpu_vm_add_prt_cb(adev, excl);
2025 for (i = 0; i < shared_count; ++i) {
2026 amdgpu_vm_prt_get(adev);
2027 amdgpu_vm_add_prt_cb(adev, shared[i]);
2034 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2036 * @adev: amdgpu_device pointer
2038 * @fence: optional resulting fence (unchanged if no work needed to be done
2039 * or if an error occurred)
2041 * Make sure all freed BOs are cleared in the PT.
2042 * PTs have to be reserved and mutex must be locked!
2048 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2049 struct amdgpu_vm *vm,
2050 struct dma_fence **fence)
2052 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2053 struct amdgpu_bo_va_mapping *mapping;
2054 uint64_t init_pte_value = 0;
2055 struct dma_fence *f = NULL;
2058 while (!list_empty(&vm->freed)) {
2059 mapping = list_first_entry(&vm->freed,
2060 struct amdgpu_bo_va_mapping, list);
2061 list_del(&mapping->list);
2063 if (vm->pte_support_ats &&
2064 mapping->start < AMDGPU_GMC_HOLE_START)
2065 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2067 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2068 resv, mapping->start,
2069 mapping->last, init_pte_value,
2071 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2079 dma_fence_put(*fence);
2090 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2092 * @adev: amdgpu_device pointer
2095 * Make sure all BOs which are moved are updated in the PTs.
2100 * PTs have to be reserved!
2102 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2103 struct amdgpu_vm *vm)
2105 struct amdgpu_bo_va *bo_va, *tmp;
2106 struct dma_resv *resv;
2110 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2111 /* Per VM BOs never need to bo cleared in the page tables */
2112 r = amdgpu_vm_bo_update(adev, bo_va, false);
2117 spin_lock(&vm->invalidated_lock);
2118 while (!list_empty(&vm->invalidated)) {
2119 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2121 resv = bo_va->base.bo->tbo.base.resv;
2122 spin_unlock(&vm->invalidated_lock);
2124 /* Try to reserve the BO to avoid clearing its ptes */
2125 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2127 /* Somebody else is using the BO right now */
2131 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2136 dma_resv_unlock(resv);
2137 spin_lock(&vm->invalidated_lock);
2139 spin_unlock(&vm->invalidated_lock);
2145 * amdgpu_vm_bo_add - add a bo to a specific vm
2147 * @adev: amdgpu_device pointer
2149 * @bo: amdgpu buffer object
2151 * Add @bo into the requested vm.
2152 * Add @bo to the list of bos associated with the vm
2155 * Newly added bo_va or NULL for failure
2157 * Object has to be reserved!
2159 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2160 struct amdgpu_vm *vm,
2161 struct amdgpu_bo *bo)
2163 struct amdgpu_bo_va *bo_va;
2165 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2166 if (bo_va == NULL) {
2169 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2171 bo_va->ref_count = 1;
2172 INIT_LIST_HEAD(&bo_va->valids);
2173 INIT_LIST_HEAD(&bo_va->invalids);
2178 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2179 bo_va->is_xgmi = true;
2180 /* Power up XGMI if it can be potentially used */
2181 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2189 * amdgpu_vm_bo_insert_map - insert a new mapping
2191 * @adev: amdgpu_device pointer
2192 * @bo_va: bo_va to store the address
2193 * @mapping: the mapping to insert
2195 * Insert a new mapping into all structures.
2197 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2198 struct amdgpu_bo_va *bo_va,
2199 struct amdgpu_bo_va_mapping *mapping)
2201 struct amdgpu_vm *vm = bo_va->base.vm;
2202 struct amdgpu_bo *bo = bo_va->base.bo;
2204 mapping->bo_va = bo_va;
2205 list_add(&mapping->list, &bo_va->invalids);
2206 amdgpu_vm_it_insert(mapping, &vm->va);
2208 if (mapping->flags & AMDGPU_PTE_PRT)
2209 amdgpu_vm_prt_get(adev);
2211 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2212 !bo_va->base.moved) {
2213 list_move(&bo_va->base.vm_status, &vm->moved);
2215 trace_amdgpu_vm_bo_map(bo_va, mapping);
2219 * amdgpu_vm_bo_map - map bo inside a vm
2221 * @adev: amdgpu_device pointer
2222 * @bo_va: bo_va to store the address
2223 * @saddr: where to map the BO
2224 * @offset: requested offset in the BO
2225 * @size: BO size in bytes
2226 * @flags: attributes of pages (read/write/valid/etc.)
2228 * Add a mapping of the BO at the specefied addr into the VM.
2231 * 0 for success, error for failure.
2233 * Object has to be reserved and unreserved outside!
2235 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2236 struct amdgpu_bo_va *bo_va,
2237 uint64_t saddr, uint64_t offset,
2238 uint64_t size, uint64_t flags)
2240 struct amdgpu_bo_va_mapping *mapping, *tmp;
2241 struct amdgpu_bo *bo = bo_va->base.bo;
2242 struct amdgpu_vm *vm = bo_va->base.vm;
2245 /* validate the parameters */
2246 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2247 size == 0 || size & ~PAGE_MASK)
2250 /* make sure object fit at this offset */
2251 eaddr = saddr + size - 1;
2252 if (saddr >= eaddr ||
2253 (bo && offset + size > amdgpu_bo_size(bo)) ||
2254 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2257 saddr /= AMDGPU_GPU_PAGE_SIZE;
2258 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2260 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2262 /* bo and tmp overlap, invalid addr */
2263 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2264 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2265 tmp->start, tmp->last + 1);
2269 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2273 mapping->start = saddr;
2274 mapping->last = eaddr;
2275 mapping->offset = offset;
2276 mapping->flags = flags;
2278 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2284 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2286 * @adev: amdgpu_device pointer
2287 * @bo_va: bo_va to store the address
2288 * @saddr: where to map the BO
2289 * @offset: requested offset in the BO
2290 * @size: BO size in bytes
2291 * @flags: attributes of pages (read/write/valid/etc.)
2293 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2294 * mappings as we do so.
2297 * 0 for success, error for failure.
2299 * Object has to be reserved and unreserved outside!
2301 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2302 struct amdgpu_bo_va *bo_va,
2303 uint64_t saddr, uint64_t offset,
2304 uint64_t size, uint64_t flags)
2306 struct amdgpu_bo_va_mapping *mapping;
2307 struct amdgpu_bo *bo = bo_va->base.bo;
2311 /* validate the parameters */
2312 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2313 size == 0 || size & ~PAGE_MASK)
2316 /* make sure object fit at this offset */
2317 eaddr = saddr + size - 1;
2318 if (saddr >= eaddr ||
2319 (bo && offset + size > amdgpu_bo_size(bo)) ||
2320 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2323 /* Allocate all the needed memory */
2324 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2328 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2334 saddr /= AMDGPU_GPU_PAGE_SIZE;
2335 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2337 mapping->start = saddr;
2338 mapping->last = eaddr;
2339 mapping->offset = offset;
2340 mapping->flags = flags;
2342 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2348 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2350 * @adev: amdgpu_device pointer
2351 * @bo_va: bo_va to remove the address from
2352 * @saddr: where to the BO is mapped
2354 * Remove a mapping of the BO at the specefied addr from the VM.
2357 * 0 for success, error for failure.
2359 * Object has to be reserved and unreserved outside!
2361 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2362 struct amdgpu_bo_va *bo_va,
2365 struct amdgpu_bo_va_mapping *mapping;
2366 struct amdgpu_vm *vm = bo_va->base.vm;
2369 saddr /= AMDGPU_GPU_PAGE_SIZE;
2371 list_for_each_entry(mapping, &bo_va->valids, list) {
2372 if (mapping->start == saddr)
2376 if (&mapping->list == &bo_va->valids) {
2379 list_for_each_entry(mapping, &bo_va->invalids, list) {
2380 if (mapping->start == saddr)
2384 if (&mapping->list == &bo_va->invalids)
2388 list_del(&mapping->list);
2389 amdgpu_vm_it_remove(mapping, &vm->va);
2390 mapping->bo_va = NULL;
2391 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2394 list_add(&mapping->list, &vm->freed);
2396 amdgpu_vm_free_mapping(adev, vm, mapping,
2397 bo_va->last_pt_update);
2403 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2405 * @adev: amdgpu_device pointer
2406 * @vm: VM structure to use
2407 * @saddr: start of the range
2408 * @size: size of the range
2410 * Remove all mappings in a range, split them as appropriate.
2413 * 0 for success, error for failure.
2415 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2416 struct amdgpu_vm *vm,
2417 uint64_t saddr, uint64_t size)
2419 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2423 eaddr = saddr + size - 1;
2424 saddr /= AMDGPU_GPU_PAGE_SIZE;
2425 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2427 /* Allocate all the needed memory */
2428 before = kzalloc(sizeof(*before), GFP_KERNEL);
2431 INIT_LIST_HEAD(&before->list);
2433 after = kzalloc(sizeof(*after), GFP_KERNEL);
2438 INIT_LIST_HEAD(&after->list);
2440 /* Now gather all removed mappings */
2441 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2443 /* Remember mapping split at the start */
2444 if (tmp->start < saddr) {
2445 before->start = tmp->start;
2446 before->last = saddr - 1;
2447 before->offset = tmp->offset;
2448 before->flags = tmp->flags;
2449 before->bo_va = tmp->bo_va;
2450 list_add(&before->list, &tmp->bo_va->invalids);
2453 /* Remember mapping split at the end */
2454 if (tmp->last > eaddr) {
2455 after->start = eaddr + 1;
2456 after->last = tmp->last;
2457 after->offset = tmp->offset;
2458 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2459 after->flags = tmp->flags;
2460 after->bo_va = tmp->bo_va;
2461 list_add(&after->list, &tmp->bo_va->invalids);
2464 list_del(&tmp->list);
2465 list_add(&tmp->list, &removed);
2467 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2470 /* And free them up */
2471 list_for_each_entry_safe(tmp, next, &removed, list) {
2472 amdgpu_vm_it_remove(tmp, &vm->va);
2473 list_del(&tmp->list);
2475 if (tmp->start < saddr)
2477 if (tmp->last > eaddr)
2481 list_add(&tmp->list, &vm->freed);
2482 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2485 /* Insert partial mapping before the range */
2486 if (!list_empty(&before->list)) {
2487 amdgpu_vm_it_insert(before, &vm->va);
2488 if (before->flags & AMDGPU_PTE_PRT)
2489 amdgpu_vm_prt_get(adev);
2494 /* Insert partial mapping after the range */
2495 if (!list_empty(&after->list)) {
2496 amdgpu_vm_it_insert(after, &vm->va);
2497 if (after->flags & AMDGPU_PTE_PRT)
2498 amdgpu_vm_prt_get(adev);
2507 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2509 * @vm: the requested VM
2510 * @addr: the address
2512 * Find a mapping by it's address.
2515 * The amdgpu_bo_va_mapping matching for addr or NULL
2518 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2521 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2525 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2527 * @vm: the requested vm
2528 * @ticket: CS ticket
2530 * Trace all mappings of BOs reserved during a command submission.
2532 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2534 struct amdgpu_bo_va_mapping *mapping;
2536 if (!trace_amdgpu_vm_bo_cs_enabled())
2539 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2540 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2541 if (mapping->bo_va && mapping->bo_va->base.bo) {
2542 struct amdgpu_bo *bo;
2544 bo = mapping->bo_va->base.bo;
2545 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2550 trace_amdgpu_vm_bo_cs(mapping);
2555 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2557 * @adev: amdgpu_device pointer
2558 * @bo_va: requested bo_va
2560 * Remove @bo_va->bo from the requested vm.
2562 * Object have to be reserved!
2564 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2565 struct amdgpu_bo_va *bo_va)
2567 struct amdgpu_bo_va_mapping *mapping, *next;
2568 struct amdgpu_bo *bo = bo_va->base.bo;
2569 struct amdgpu_vm *vm = bo_va->base.vm;
2570 struct amdgpu_vm_bo_base **base;
2573 if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2574 vm->bulk_moveable = false;
2576 for (base = &bo_va->base.bo->vm_bo; *base;
2577 base = &(*base)->next) {
2578 if (*base != &bo_va->base)
2581 *base = bo_va->base.next;
2586 spin_lock(&vm->invalidated_lock);
2587 list_del(&bo_va->base.vm_status);
2588 spin_unlock(&vm->invalidated_lock);
2590 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2591 list_del(&mapping->list);
2592 amdgpu_vm_it_remove(mapping, &vm->va);
2593 mapping->bo_va = NULL;
2594 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2595 list_add(&mapping->list, &vm->freed);
2597 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2598 list_del(&mapping->list);
2599 amdgpu_vm_it_remove(mapping, &vm->va);
2600 amdgpu_vm_free_mapping(adev, vm, mapping,
2601 bo_va->last_pt_update);
2604 dma_fence_put(bo_va->last_pt_update);
2606 if (bo && bo_va->is_xgmi)
2607 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2613 * amdgpu_vm_evictable - check if we can evict a VM
2615 * @bo: A page table of the VM.
2617 * Check if it is possible to evict a VM.
2619 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2621 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2623 /* Page tables of a destroyed VM can go away immediately */
2624 if (!bo_base || !bo_base->vm)
2627 /* Don't evict VM page tables while they are busy */
2628 if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
2631 /* Try to block ongoing updates */
2632 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2635 /* Don't evict VM page tables while they are updated */
2636 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2637 amdgpu_vm_eviction_unlock(bo_base->vm);
2641 bo_base->vm->evicting = true;
2642 amdgpu_vm_eviction_unlock(bo_base->vm);
2647 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2649 * @adev: amdgpu_device pointer
2650 * @bo: amdgpu buffer object
2651 * @evicted: is the BO evicted
2653 * Mark @bo as invalid.
2655 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2656 struct amdgpu_bo *bo, bool evicted)
2658 struct amdgpu_vm_bo_base *bo_base;
2660 /* shadow bo doesn't have bo base, its validation needs its parent */
2661 if (bo->parent && bo->parent->shadow == bo)
2664 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2665 struct amdgpu_vm *vm = bo_base->vm;
2667 if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2668 amdgpu_vm_bo_evicted(bo_base);
2674 bo_base->moved = true;
2676 if (bo->tbo.type == ttm_bo_type_kernel)
2677 amdgpu_vm_bo_relocated(bo_base);
2678 else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2679 amdgpu_vm_bo_moved(bo_base);
2681 amdgpu_vm_bo_invalidated(bo_base);
2686 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2691 * VM page table as power of two
2693 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2695 /* Total bits covered by PD + PTs */
2696 unsigned bits = ilog2(vm_size) + 18;
2698 /* Make sure the PD is 4K in size up to 8GB address space.
2699 Above that split equal between PD and PTs */
2703 return ((bits + 3) / 2);
2707 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2709 * @adev: amdgpu_device pointer
2710 * @min_vm_size: the minimum vm size in GB if it's set auto
2711 * @fragment_size_default: Default PTE fragment size
2712 * @max_level: max VMPT level
2713 * @max_bits: max address space size in bits
2716 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2717 uint32_t fragment_size_default, unsigned max_level,
2720 unsigned int max_size = 1 << (max_bits - 30);
2721 unsigned int vm_size;
2724 /* adjust vm size first */
2725 if (amdgpu_vm_size != -1) {
2726 vm_size = amdgpu_vm_size;
2727 if (vm_size > max_size) {
2728 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2729 amdgpu_vm_size, max_size);
2734 unsigned int phys_ram_gb;
2736 /* Optimal VM size depends on the amount of physical
2737 * RAM available. Underlying requirements and
2740 * - Need to map system memory and VRAM from all GPUs
2741 * - VRAM from other GPUs not known here
2742 * - Assume VRAM <= system memory
2743 * - On GFX8 and older, VM space can be segmented for
2745 * - Need to allow room for fragmentation, guard pages etc.
2747 * This adds up to a rough guess of system memory x3.
2748 * Round up to power of two to maximize the available
2749 * VM size with the given page table size.
2752 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2753 (1 << 30) - 1) >> 30;
2754 vm_size = roundup_pow_of_two(
2755 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2758 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2760 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2761 if (amdgpu_vm_block_size != -1)
2762 tmp >>= amdgpu_vm_block_size - 9;
2763 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2764 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2765 switch (adev->vm_manager.num_level) {
2767 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2770 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2773 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2776 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2778 /* block size depends on vm size and hw setup*/
2779 if (amdgpu_vm_block_size != -1)
2780 adev->vm_manager.block_size =
2781 min((unsigned)amdgpu_vm_block_size, max_bits
2782 - AMDGPU_GPU_PAGE_SHIFT
2783 - 9 * adev->vm_manager.num_level);
2784 else if (adev->vm_manager.num_level > 1)
2785 adev->vm_manager.block_size = 9;
2787 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2789 if (amdgpu_vm_fragment_size == -1)
2790 adev->vm_manager.fragment_size = fragment_size_default;
2792 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2794 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2795 vm_size, adev->vm_manager.num_level + 1,
2796 adev->vm_manager.block_size,
2797 adev->vm_manager.fragment_size);
2801 * amdgpu_vm_wait_idle - wait for the VM to become idle
2803 * @vm: VM object to wait for
2804 * @timeout: timeout to wait for VM to become idle
2806 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2808 timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2809 true, true, timeout);
2813 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2817 * amdgpu_vm_init - initialize a vm instance
2819 * @adev: amdgpu_device pointer
2821 * @vm_context: Indicates if it GFX or Compute context
2822 * @pasid: Process address space identifier
2827 * 0 for success, error for failure.
2829 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2830 int vm_context, u32 pasid)
2832 struct amdgpu_bo_param bp;
2833 struct amdgpu_bo *root;
2836 vm->va = RB_ROOT_CACHED;
2837 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2838 vm->reserved_vmid[i] = NULL;
2839 INIT_LIST_HEAD(&vm->evicted);
2840 INIT_LIST_HEAD(&vm->relocated);
2841 INIT_LIST_HEAD(&vm->moved);
2842 INIT_LIST_HEAD(&vm->idle);
2843 INIT_LIST_HEAD(&vm->invalidated);
2844 spin_lock_init(&vm->invalidated_lock);
2845 INIT_LIST_HEAD(&vm->freed);
2846 INIT_LIST_HEAD(&vm->done);
2848 /* create scheduler entities for page table updates */
2849 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2850 adev->vm_manager.vm_pte_scheds,
2851 adev->vm_manager.vm_pte_num_scheds, NULL);
2855 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2856 adev->vm_manager.vm_pte_scheds,
2857 adev->vm_manager.vm_pte_num_scheds, NULL);
2859 goto error_free_immediate;
2861 vm->pte_support_ats = false;
2862 vm->is_compute_context = false;
2864 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2865 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2866 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2868 if (adev->asic_type == CHIP_RAVEN)
2869 vm->pte_support_ats = true;
2871 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2872 AMDGPU_VM_USE_CPU_FOR_GFX);
2874 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2875 vm->use_cpu_for_update ? "CPU" : "SDMA");
2876 WARN_ONCE((vm->use_cpu_for_update &&
2877 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2878 "CPU update of VM recommended only for large BAR system\n");
2880 if (vm->use_cpu_for_update)
2881 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2883 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2884 vm->last_update = NULL;
2885 vm->last_unlocked = dma_fence_get_stub();
2887 mutex_init(&vm->eviction_lock);
2888 vm->evicting = false;
2890 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp);
2891 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2892 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2893 r = amdgpu_bo_create(adev, &bp, &root);
2895 goto error_free_delayed;
2897 r = amdgpu_bo_reserve(root, true);
2899 goto error_free_root;
2901 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2903 goto error_unreserve;
2905 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2907 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2909 goto error_unreserve;
2911 amdgpu_bo_unreserve(vm->root.base.bo);
2914 unsigned long flags;
2916 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2917 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2919 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2921 goto error_free_root;
2926 INIT_KFIFO(vm->faults);
2931 amdgpu_bo_unreserve(vm->root.base.bo);
2934 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2935 amdgpu_bo_unref(&vm->root.base.bo);
2936 vm->root.base.bo = NULL;
2939 dma_fence_put(vm->last_unlocked);
2940 drm_sched_entity_destroy(&vm->delayed);
2942 error_free_immediate:
2943 drm_sched_entity_destroy(&vm->immediate);
2949 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2951 * @adev: amdgpu_device pointer
2952 * @vm: the VM to check
2954 * check all entries of the root PD, if any subsequent PDs are allocated,
2955 * it means there are page table creating and filling, and is no a clean
2959 * 0 if this VM is clean
2961 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2962 struct amdgpu_vm *vm)
2964 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2965 unsigned int entries = amdgpu_vm_num_entries(adev, root);
2968 if (!(vm->root.entries))
2971 for (i = 0; i < entries; i++) {
2972 if (vm->root.entries[i].base.bo)
2980 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2982 * @adev: amdgpu_device pointer
2984 * @pasid: pasid to use
2986 * This only works on GFX VMs that don't have any BOs added and no
2987 * page tables allocated yet.
2989 * Changes the following VM parameters:
2990 * - use_cpu_for_update
2991 * - pte_supports_ats
2992 * - pasid (old PASID is released, because compute manages its own PASIDs)
2994 * Reinitializes the page directory to reflect the changed ATS
2998 * 0 for success, -errno for errors.
3000 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3003 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3006 r = amdgpu_bo_reserve(vm->root.base.bo, true);
3011 r = amdgpu_vm_check_clean_reserved(adev, vm);
3016 unsigned long flags;
3018 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3019 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3021 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3028 /* Check if PD needs to be reinitialized and do it before
3029 * changing any other state, in case it fails.
3031 if (pte_support_ats != vm->pte_support_ats) {
3032 vm->pte_support_ats = pte_support_ats;
3033 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
3038 /* Update VM state */
3039 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3040 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3041 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3042 vm->use_cpu_for_update ? "CPU" : "SDMA");
3043 WARN_ONCE((vm->use_cpu_for_update &&
3044 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3045 "CPU update of VM recommended only for large BAR system\n");
3047 if (vm->use_cpu_for_update) {
3048 /* Sync with last SDMA update/clear before switching to CPU */
3049 r = amdgpu_bo_sync_wait(vm->root.base.bo,
3050 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3054 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3056 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3058 dma_fence_put(vm->last_update);
3059 vm->last_update = NULL;
3060 vm->is_compute_context = true;
3063 unsigned long flags;
3065 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3066 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3067 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3069 /* Free the original amdgpu allocated pasid
3070 * Will be replaced with kfd allocated pasid
3072 amdgpu_pasid_free(vm->pasid);
3076 /* Free the shadow bo for compute VM */
3077 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3086 unsigned long flags;
3088 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3089 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3090 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3093 amdgpu_bo_unreserve(vm->root.base.bo);
3098 * amdgpu_vm_release_compute - release a compute vm
3099 * @adev: amdgpu_device pointer
3100 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3102 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3103 * pasid from vm. Compute should stop use of vm after this call.
3105 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3108 unsigned long flags;
3110 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3111 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3112 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3115 vm->is_compute_context = false;
3119 * amdgpu_vm_fini - tear down a vm instance
3121 * @adev: amdgpu_device pointer
3125 * Unbind the VM and remove all bos from the vm bo list
3127 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3129 struct amdgpu_bo_va_mapping *mapping, *tmp;
3130 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3131 struct amdgpu_bo *root;
3134 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3136 root = amdgpu_bo_ref(vm->root.base.bo);
3137 amdgpu_bo_reserve(root, true);
3139 unsigned long flags;
3141 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3142 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3143 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3147 dma_fence_wait(vm->last_unlocked, false);
3148 dma_fence_put(vm->last_unlocked);
3150 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3151 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3152 amdgpu_vm_prt_fini(adev, vm);
3153 prt_fini_needed = false;
3156 list_del(&mapping->list);
3157 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3160 amdgpu_vm_free_pts(adev, vm, NULL);
3161 amdgpu_bo_unreserve(root);
3162 amdgpu_bo_unref(&root);
3163 WARN_ON(vm->root.base.bo);
3165 drm_sched_entity_destroy(&vm->immediate);
3166 drm_sched_entity_destroy(&vm->delayed);
3168 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3169 dev_err(adev->dev, "still active bo inside vm\n");
3171 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3172 &vm->va.rb_root, rb) {
3173 /* Don't remove the mapping here, we don't want to trigger a
3174 * rebalance and the tree is about to be destroyed anyway.
3176 list_del(&mapping->list);
3180 dma_fence_put(vm->last_update);
3181 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3182 amdgpu_vmid_free_reserved(adev, vm, i);
3186 * amdgpu_vm_manager_init - init the VM manager
3188 * @adev: amdgpu_device pointer
3190 * Initialize the VM manager structures
3192 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3196 /* Concurrent flushes are only possible starting with Vega10 and
3197 * are broken on Navi10 and Navi14.
3199 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3200 adev->asic_type == CHIP_NAVI10 ||
3201 adev->asic_type == CHIP_NAVI14);
3202 amdgpu_vmid_mgr_init(adev);
3204 adev->vm_manager.fence_context =
3205 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3206 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3207 adev->vm_manager.seqno[i] = 0;
3209 spin_lock_init(&adev->vm_manager.prt_lock);
3210 atomic_set(&adev->vm_manager.num_prt_users, 0);
3212 /* If not overridden by the user, by default, only in large BAR systems
3213 * Compute VM tables will be updated by CPU
3215 #ifdef CONFIG_X86_64
3216 if (amdgpu_vm_update_mode == -1) {
3217 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3218 adev->vm_manager.vm_update_mode =
3219 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3221 adev->vm_manager.vm_update_mode = 0;
3223 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3225 adev->vm_manager.vm_update_mode = 0;
3228 idr_init(&adev->vm_manager.pasid_idr);
3229 spin_lock_init(&adev->vm_manager.pasid_lock);
3233 * amdgpu_vm_manager_fini - cleanup VM manager
3235 * @adev: amdgpu_device pointer
3237 * Cleanup the VM manager and free resources.
3239 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3241 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3242 idr_destroy(&adev->vm_manager.pasid_idr);
3244 amdgpu_vmid_mgr_fini(adev);
3248 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3250 * @dev: drm device pointer
3251 * @data: drm_amdgpu_vm
3252 * @filp: drm file pointer
3255 * 0 for success, -errno for errors.
3257 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3259 union drm_amdgpu_vm *args = data;
3260 struct amdgpu_device *adev = drm_to_adev(dev);
3261 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3262 long timeout = msecs_to_jiffies(2000);
3265 switch (args->in.op) {
3266 case AMDGPU_VM_OP_RESERVE_VMID:
3267 /* We only have requirement to reserve vmid from gfxhub */
3268 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3273 case AMDGPU_VM_OP_UNRESERVE_VMID:
3274 if (amdgpu_sriov_runtime(adev))
3275 timeout = 8 * timeout;
3277 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3278 * not referenced anymore.
3280 r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
3284 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3288 amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
3289 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3299 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3301 * @adev: drm device pointer
3302 * @pasid: PASID identifier for VM
3303 * @task_info: task_info to fill.
3305 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3306 struct amdgpu_task_info *task_info)
3308 struct amdgpu_vm *vm;
3309 unsigned long flags;
3311 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3313 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3315 *task_info = vm->task_info;
3317 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3321 * amdgpu_vm_set_task_info - Sets VMs task info.
3323 * @vm: vm for which to set the info
3325 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3327 if (vm->task_info.pid)
3330 vm->task_info.pid = current->pid;
3331 get_task_comm(vm->task_info.task_name, current);
3333 if (current->group_leader->mm != current->mm)
3336 vm->task_info.tgid = current->group_leader->pid;
3337 get_task_comm(vm->task_info.process_name, current->group_leader);
3341 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3342 * @adev: amdgpu device pointer
3343 * @pasid: PASID of the VM
3344 * @addr: Address of the fault
3346 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3347 * shouldn't be reported any more.
3349 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3352 struct amdgpu_bo *root;
3353 uint64_t value, flags;
3354 struct amdgpu_vm *vm;
3357 spin_lock(&adev->vm_manager.pasid_lock);
3358 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3360 root = amdgpu_bo_ref(vm->root.base.bo);
3363 spin_unlock(&adev->vm_manager.pasid_lock);
3368 r = amdgpu_bo_reserve(root, true);
3372 /* Double check that the VM still exists */
3373 spin_lock(&adev->vm_manager.pasid_lock);
3374 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3375 if (vm && vm->root.base.bo != root)
3377 spin_unlock(&adev->vm_manager.pasid_lock);
3381 addr /= AMDGPU_GPU_PAGE_SIZE;
3382 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3385 if (vm->is_compute_context) {
3386 /* Intentionally setting invalid PTE flag
3387 * combination to force a no-retry-fault
3389 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3393 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3394 /* Redirect the access to the dummy page */
3395 value = adev->dummy_page_addr;
3396 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3397 AMDGPU_PTE_WRITEABLE;
3400 /* Let the hw retry silently on the PTE */
3404 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3406 pr_debug("failed %d to reserve fence slot\n", r);
3410 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3411 addr, flags, value, NULL, NULL,
3416 r = amdgpu_vm_update_pdes(adev, vm, true);
3419 amdgpu_bo_unreserve(root);
3421 DRM_ERROR("Can't handle page fault (%d)\n", r);
3424 amdgpu_bo_unref(&root);
3429 #if defined(CONFIG_DEBUG_FS)
3431 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3433 * @vm: Requested VM for printing BO info
3436 * Print BO information in debugfs file for the VM
3438 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3440 struct amdgpu_bo_va *bo_va, *tmp;
3442 u64 total_evicted = 0;
3443 u64 total_relocated = 0;
3444 u64 total_moved = 0;
3445 u64 total_invalidated = 0;
3447 unsigned int total_idle_objs = 0;
3448 unsigned int total_evicted_objs = 0;
3449 unsigned int total_relocated_objs = 0;
3450 unsigned int total_moved_objs = 0;
3451 unsigned int total_invalidated_objs = 0;
3452 unsigned int total_done_objs = 0;
3453 unsigned int id = 0;
3455 seq_puts(m, "\tIdle BOs:\n");
3456 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3457 if (!bo_va->base.bo)
3459 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3461 total_idle_objs = id;
3464 seq_puts(m, "\tEvicted BOs:\n");
3465 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3466 if (!bo_va->base.bo)
3468 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3470 total_evicted_objs = id;
3473 seq_puts(m, "\tRelocated BOs:\n");
3474 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3475 if (!bo_va->base.bo)
3477 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3479 total_relocated_objs = id;
3482 seq_puts(m, "\tMoved BOs:\n");
3483 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3484 if (!bo_va->base.bo)
3486 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3488 total_moved_objs = id;
3491 seq_puts(m, "\tInvalidated BOs:\n");
3492 spin_lock(&vm->invalidated_lock);
3493 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3494 if (!bo_va->base.bo)
3496 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3498 total_invalidated_objs = id;
3501 seq_puts(m, "\tDone BOs:\n");
3502 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3503 if (!bo_va->base.bo)
3505 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3507 spin_unlock(&vm->invalidated_lock);
3508 total_done_objs = id;
3510 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3512 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3513 total_evicted_objs);
3514 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3515 total_relocated_objs);
3516 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3518 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3519 total_invalidated_objs);
3520 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,