drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25
  26 #ifdef CONFIG_X86
  27 #include <asm/hypervisor.h>
  28 #endif
  29
  30 #include <drm/drm_drv.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "vi.h"
  35 #include "soc15.h"
  36 #include "nv.h"
  37
  38 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
  39         do { \
  40                 vf2pf_info->ucode_info[ucode].id = ucode; \
  41                 vf2pf_info->ucode_info[ucode].version = ver; \
  42         } while (0)
  43
  44 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
  45 {
  46         /* By now all MMIO pages except mailbox are blocked */
  47         /* if blocking is enabled in hypervisor. Choose the */
  48         /* SCRATCH_REG0 to test. */
  49         return RREG32_NO_KIQ(0xc040) == 0xffffffff;
  50 }
  51
  52 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
  53 {
  54         struct drm_device *ddev = adev_to_drm(adev);
  55
  56         /* enable virtual display */
  57         if (adev->asic_type != CHIP_ALDEBARAN &&
  58             adev->asic_type != CHIP_ARCTURUS) {
  59                 if (adev->mode_info.num_crtc == 0)
  60                         adev->mode_info.num_crtc = 1;
  61                 adev->enable_virtual_display = true;
  62         }
  63         ddev->driver_features &= ~DRIVER_ATOMIC;
  64         adev->cg_flags = 0;
  65         adev->pg_flags = 0;
  66 }
  67
  68 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
  69                                         uint32_t reg0, uint32_t reg1,
  70                                         uint32_t ref, uint32_t mask)
  71 {
  72         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
  73         struct amdgpu_ring *ring = &kiq->ring;
  74         signed long r, cnt = 0;
  75         unsigned long flags;
  76         uint32_t seq;
  77
  78         spin_lock_irqsave(&kiq->ring_lock, flags);
  79         amdgpu_ring_alloc(ring, 32);
  80         amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
  81                                             ref, mask);
  82         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
  83         if (r)
  84                 goto failed_undo;
  85
  86         amdgpu_ring_commit(ring);
  87         spin_unlock_irqrestore(&kiq->ring_lock, flags);
  88
  89         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
  90
  91         /* don't wait anymore for IRQ context */
  92         if (r < 1 && in_interrupt())
  93                 goto failed_kiq;
  94
  95         might_sleep();
  96         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
  97
  98                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
  99                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 100         }
 101
 102         if (cnt > MAX_KIQ_REG_TRY)
 103                 goto failed_kiq;
 104
 105         return;
 106
 107 failed_undo:
 108         amdgpu_ring_undo(ring);
 109         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 110 failed_kiq:
 111         dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
 112 }
 113
 114 /**
 115  * amdgpu_virt_request_full_gpu() - request full gpu access
 116  * @adev:       amdgpu device.
 117  * @init:       is driver init time.
 118  * When start to init/fini driver, first need to request full gpu access.
 119  * Return: Zero if request success, otherwise will return error.
 120  */
 121 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 122 {
 123         struct amdgpu_virt *virt = &adev->virt;
 124         int r;
 125
 126         if (virt->ops && virt->ops->req_full_gpu) {
 127                 r = virt->ops->req_full_gpu(adev, init);
 128                 if (r)
 129                         return r;
 130
 131                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 132         }
 133
 134         return 0;
 135 }
 136
 137 /**
 138  * amdgpu_virt_release_full_gpu() - release full gpu access
 139  * @adev:       amdgpu device.
 140  * @init:       is driver init time.
 141  * When finishing driver init/fini, need to release full gpu access.
 142  * Return: Zero if release success, otherwise will returen error.
 143  */
 144 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 145 {
 146         struct amdgpu_virt *virt = &adev->virt;
 147         int r;
 148
 149         if (virt->ops && virt->ops->rel_full_gpu) {
 150                 r = virt->ops->rel_full_gpu(adev, init);
 151                 if (r)
 152                         return r;
 153
 154                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 155         }
 156         return 0;
 157 }
 158
 159 /**
 160  * amdgpu_virt_reset_gpu() - reset gpu
 161  * @adev:       amdgpu device.
 162  * Send reset command to GPU hypervisor to reset GPU that VM is using
 163  * Return: Zero if reset success, otherwise will return error.
 164  */
 165 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 166 {
 167         struct amdgpu_virt *virt = &adev->virt;
 168         int r;
 169
 170         if (virt->ops && virt->ops->reset_gpu) {
 171                 r = virt->ops->reset_gpu(adev);
 172                 if (r)
 173                         return r;
 174
 175                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 176         }
 177
 178         return 0;
 179 }
 180
 181 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
 182 {
 183         struct amdgpu_virt *virt = &adev->virt;
 184
 185         if (virt->ops && virt->ops->req_init_data)
 186                 virt->ops->req_init_data(adev);
 187
 188         if (adev->virt.req_init_data_ver > 0)
 189                 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
 190         else
 191                 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
 192 }
 193
 194 /**
 195  * amdgpu_virt_wait_reset() - wait for reset gpu completed
 196  * @adev:       amdgpu device.
 197  * Wait for GPU reset completed.
 198  * Return: Zero if reset success, otherwise will return error.
 199  */
 200 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
 201 {
 202         struct amdgpu_virt *virt = &adev->virt;
 203
 204         if (!virt->ops || !virt->ops->wait_reset)
 205                 return -EINVAL;
 206
 207         return virt->ops->wait_reset(adev);
 208 }
 209
 210 /**
 211  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 212  * @adev:       amdgpu device.
 213  * MM table is used by UVD and VCE for its initialization
 214  * Return: Zero if allocate success.
 215  */
 216 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 217 {
 218         int r;
 219
 220         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 221                 return 0;
 222
 223         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 224                                     AMDGPU_GEM_DOMAIN_VRAM,
 225                                     &adev->virt.mm_table.bo,
 226                                     &adev->virt.mm_table.gpu_addr,
 227                                     (void *)&adev->virt.mm_table.cpu_addr);
 228         if (r) {
 229                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 230                 return r;
 231         }
 232
 233         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 234         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 235                  adev->virt.mm_table.gpu_addr,
 236                  adev->virt.mm_table.cpu_addr);
 237         return 0;
 238 }
 239
 240 /**
 241  * amdgpu_virt_free_mm_table() - free mm table memory
 242  * @adev:       amdgpu device.
 243  * Free MM table memory
 244  */
 245 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 246 {
 247         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 248                 return;
 249
 250         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 251                               &adev->virt.mm_table.gpu_addr,
 252                               (void *)&adev->virt.mm_table.cpu_addr);
 253         adev->virt.mm_table.gpu_addr = 0;
 254 }
 255
 256
 257 unsigned int amd_sriov_msg_checksum(void *obj,
 258                                 unsigned long obj_size,
 259                                 unsigned int key,
 260                                 unsigned int checksum)
 261 {
 262         unsigned int ret = key;
 263         unsigned long i = 0;
 264         unsigned char *pos;
 265
 266         pos = (char *)obj;
 267         /* calculate checksum */
 268         for (i = 0; i < obj_size; ++i)
 269                 ret += *(pos + i);
 270         /* minus the checksum itself */
 271         pos = (char *)&checksum;
 272         for (i = 0; i < sizeof(checksum); ++i)
 273                 ret -= *(pos + i);
 274         return ret;
 275 }
 276
 277 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
 278 {
 279         struct amdgpu_virt *virt = &adev->virt;
 280         struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
 281         /* GPU will be marked bad on host if bp count more then 10,
 282          * so alloc 512 is enough.
 283          */
 284         unsigned int align_space = 512;
 285         void *bps = NULL;
 286         struct amdgpu_bo **bps_bo = NULL;
 287
 288         *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
 289         if (!*data)
 290                 goto data_failure;
 291
 292         bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL);
 293         if (!bps)
 294                 goto bps_failure;
 295
 296         bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL);
 297         if (!bps_bo)
 298                 goto bps_bo_failure;
 299
 300         (*data)->bps = bps;
 301         (*data)->bps_bo = bps_bo;
 302         (*data)->count = 0;
 303         (*data)->last_reserved = 0;
 304
 305         virt->ras_init_done = true;
 306
 307         return 0;
 308
 309 bps_bo_failure:
 310         kfree(bps);
 311 bps_failure:
 312         kfree(*data);
 313 data_failure:
 314         return -ENOMEM;
 315 }
 316
 317 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
 318 {
 319         struct amdgpu_virt *virt = &adev->virt;
 320         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 321         struct amdgpu_bo *bo;
 322         int i;
 323
 324         if (!data)
 325                 return;
 326
 327         for (i = data->last_reserved - 1; i >= 0; i--) {
 328                 bo = data->bps_bo[i];
 329                 amdgpu_bo_free_kernel(&bo, NULL, NULL);
 330                 data->bps_bo[i] = bo;
 331                 data->last_reserved = i;
 332         }
 333 }
 334
 335 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
 336 {
 337         struct amdgpu_virt *virt = &adev->virt;
 338         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 339
 340         virt->ras_init_done = false;
 341
 342         if (!data)
 343                 return;
 344
 345         amdgpu_virt_ras_release_bp(adev);
 346
 347         kfree(data->bps);
 348         kfree(data->bps_bo);
 349         kfree(data);
 350         virt->virt_eh_data = NULL;
 351 }
 352
 353 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
 354                 struct eeprom_table_record *bps, int pages)
 355 {
 356         struct amdgpu_virt *virt = &adev->virt;
 357         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 358
 359         if (!data)
 360                 return;
 361
 362         memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
 363         data->count += pages;
 364 }
 365
 366 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
 367 {
 368         struct amdgpu_virt *virt = &adev->virt;
 369         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 370         struct amdgpu_bo *bo = NULL;
 371         uint64_t bp;
 372         int i;
 373
 374         if (!data)
 375                 return;
 376
 377         for (i = data->last_reserved; i < data->count; i++) {
 378                 bp = data->bps[i].retired_page;
 379
 380                 /* There are two cases of reserve error should be ignored:
 381                  * 1) a ras bad page has been allocated (used by someone);
 382                  * 2) a ras bad page has been reserved (duplicate error injection
 383                  *    for one page);
 384                  */
 385                 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
 386                                                AMDGPU_GPU_PAGE_SIZE,
 387                                                AMDGPU_GEM_DOMAIN_VRAM,
 388                                                &bo, NULL))
 389                         DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
 390
 391                 data->bps_bo[i] = bo;
 392                 data->last_reserved = i + 1;
 393                 bo = NULL;
 394         }
 395 }
 396
 397 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
 398                 uint64_t retired_page)
 399 {
 400         struct amdgpu_virt *virt = &adev->virt;
 401         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 402         int i;
 403
 404         if (!data)
 405                 return true;
 406
 407         for (i = 0; i < data->count; i++)
 408                 if (retired_page == data->bps[i].retired_page)
 409                         return true;
 410
 411         return false;
 412 }
 413
 414 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
 415                 uint64_t bp_block_offset, uint32_t bp_block_size)
 416 {
 417         struct eeprom_table_record bp;
 418         uint64_t retired_page;
 419         uint32_t bp_idx, bp_cnt;
 420
 421         if (bp_block_size) {
 422                 bp_cnt = bp_block_size / sizeof(uint64_t);
 423                 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
 424                         retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +
 425                                         bp_block_offset + bp_idx * sizeof(uint64_t));
 426                         bp.retired_page = retired_page;
 427
 428                         if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
 429                                 continue;
 430
 431                         amdgpu_virt_ras_add_bps(adev, &bp, 1);
 432
 433                         amdgpu_virt_ras_reserve_bps(adev);
 434                 }
 435         }
 436 }
 437
 438 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
 439 {
 440         struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
 441         uint32_t checksum;
 442         uint32_t checkval;
 443
 444         uint32_t i;
 445         uint32_t tmp;
 446
 447         if (adev->virt.fw_reserve.p_pf2vf == NULL)
 448                 return -EINVAL;
 449
 450         if (pf2vf_info->size > 1024) {
 451                 DRM_ERROR("invalid pf2vf message size\n");
 452                 return -EINVAL;
 453         }
 454
 455         switch (pf2vf_info->version) {
 456         case 1:
 457                 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
 458                 checkval = amd_sriov_msg_checksum(
 459                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 460                         adev->virt.fw_reserve.checksum_key, checksum);
 461                 if (checksum != checkval) {
 462                         DRM_ERROR("invalid pf2vf message\n");
 463                         return -EINVAL;
 464                 }
 465
 466                 adev->virt.gim_feature =
 467                         ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
 468                 break;
 469         case 2:
 470                 /* TODO: missing key, need to add it later */
 471                 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
 472                 checkval = amd_sriov_msg_checksum(
 473                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 474                         0, checksum);
 475                 if (checksum != checkval) {
 476                         DRM_ERROR("invalid pf2vf message\n");
 477                         return -EINVAL;
 478                 }
 479
 480                 adev->virt.vf2pf_update_interval_ms =
 481                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
 482                 adev->virt.gim_feature =
 483                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
 484                 adev->virt.reg_access =
 485                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
 486
 487                 adev->virt.decode_max_dimension_pixels = 0;
 488                 adev->virt.decode_max_frame_pixels = 0;
 489                 adev->virt.encode_max_dimension_pixels = 0;
 490                 adev->virt.encode_max_frame_pixels = 0;
 491                 adev->virt.is_mm_bw_enabled = false;
 492                 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
 493                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
 494                         adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
 495
 496                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
 497                         adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
 498
 499                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
 500                         adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
 501
 502                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
 503                         adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
 504                 }
 505                 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
 506                         adev->virt.is_mm_bw_enabled = true;
 507
 508                 adev->unique_id =
 509                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
 510                 break;
 511         default:
 512                 DRM_ERROR("invalid pf2vf version\n");
 513                 return -EINVAL;
 514         }
 515
 516         /* correct too large or too little interval value */
 517         if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
 518                 adev->virt.vf2pf_update_interval_ms = 2000;
 519
 520         return 0;
 521 }
 522
 523 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
 524 {
 525         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 526         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 527
 528         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 529                 return;
 530
 531         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);
 532         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);
 533         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);
 534         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);
 535         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);
 536         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);
 537         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);
 538         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
 539         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
 540         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
 541         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);
 542         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);
 543         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos.fw_version);
 544         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
 545                             adev->psp.asd_context.bin_desc.fw_version);
 546         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,
 547                             adev->psp.ras_context.context.bin_desc.fw_version);
 548         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,
 549                             adev->psp.xgmi_context.context.bin_desc.fw_version);
 550         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);
 551         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);
 552         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);
 553         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);
 554         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);
 555 }
 556
 557 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
 558 {
 559         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 560
 561         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 562
 563         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 564                 return -EINVAL;
 565
 566         memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
 567
 568         vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
 569         vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
 570
 571 #ifdef MODULE
 572         if (THIS_MODULE->version != NULL)
 573                 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
 574         else
 575 #endif
 576                 strcpy(vf2pf_info->driver_version, "N/A");
 577
 578         vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
 579         vf2pf_info->driver_cert = 0;
 580         vf2pf_info->os_info.all = 0;
 581
 582         vf2pf_info->fb_usage =
 583                 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;
 584         vf2pf_info->fb_vis_usage =
 585                 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
 586         vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
 587         vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
 588
 589         amdgpu_virt_populate_vf2pf_ucode_info(adev);
 590
 591         /* TODO: read dynamic info */
 592         vf2pf_info->gfx_usage = 0;
 593         vf2pf_info->compute_usage = 0;
 594         vf2pf_info->encode_usage = 0;
 595         vf2pf_info->decode_usage = 0;
 596
 597         vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
 598         vf2pf_info->checksum =
 599                 amd_sriov_msg_checksum(
 600                 vf2pf_info, vf2pf_info->header.size, 0, 0);
 601
 602         return 0;
 603 }
 604
 605 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
 606 {
 607         struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
 608         int ret;
 609
 610         ret = amdgpu_virt_read_pf2vf_data(adev);
 611         if (ret)
 612                 goto out;
 613         amdgpu_virt_write_vf2pf_data(adev);
 614
 615 out:
 616         schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
 617 }
 618
 619 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
 620 {
 621         if (adev->virt.vf2pf_update_interval_ms != 0) {
 622                 DRM_INFO("clean up the vf2pf work item\n");
 623                 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
 624                 adev->virt.vf2pf_update_interval_ms = 0;
 625         }
 626 }
 627
 628 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 629 {
 630         adev->virt.fw_reserve.p_pf2vf = NULL;
 631         adev->virt.fw_reserve.p_vf2pf = NULL;
 632         adev->virt.vf2pf_update_interval_ms = 0;
 633
 634         if (adev->mman.fw_vram_usage_va != NULL) {
 635                 /* go through this logic in ip_init and reset to init workqueue*/
 636                 amdgpu_virt_exchange_data(adev);
 637
 638                 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
 639                 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
 640         } else if (adev->bios != NULL) {
 641                 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/
 642                 adev->virt.fw_reserve.p_pf2vf =
 643                         (struct amd_sriov_msg_pf2vf_info_header *)
 644                         (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 645
 646                 amdgpu_virt_read_pf2vf_data(adev);
 647         }
 648 }
 649
 650
 651 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
 652 {
 653         uint64_t bp_block_offset = 0;
 654         uint32_t bp_block_size = 0;
 655         struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
 656
 657         if (adev->mman.fw_vram_usage_va != NULL) {
 658
 659                 adev->virt.fw_reserve.p_pf2vf =
 660                         (struct amd_sriov_msg_pf2vf_info_header *)
 661                         (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 662                 adev->virt.fw_reserve.p_vf2pf =
 663                         (struct amd_sriov_msg_vf2pf_info_header *)
 664                         (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
 665
 666                 amdgpu_virt_read_pf2vf_data(adev);
 667                 amdgpu_virt_write_vf2pf_data(adev);
 668
 669                 /* bad page handling for version 2 */
 670                 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
 671                                 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
 672
 673                                 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
 674                                                 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
 675                                 bp_block_size = pf2vf_v2->bp_block_size;
 676
 677                                 if (bp_block_size && !adev->virt.ras_init_done)
 678                                         amdgpu_virt_init_ras_err_handler_data(adev);
 679
 680                                 if (adev->virt.ras_init_done)
 681                                         amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
 682                         }
 683         }
 684 }
 685
 686
 687 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 688 {
 689         uint32_t reg;
 690
 691         switch (adev->asic_type) {
 692         case CHIP_TONGA:
 693         case CHIP_FIJI:
 694                 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 695                 break;
 696         case CHIP_VEGA10:
 697         case CHIP_VEGA20:
 698         case CHIP_NAVI10:
 699         case CHIP_NAVI12:
 700         case CHIP_SIENNA_CICHLID:
 701         case CHIP_ARCTURUS:
 702         case CHIP_ALDEBARAN:
 703                 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
 704                 break;
 705         default: /* other chip doesn't support SRIOV */
 706                 reg = 0;
 707                 break;
 708         }
 709
 710         if (reg & 1)
 711                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 712
 713         if (reg & 0x80000000)
 714                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 715
 716         if (!reg) {
 717                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 718                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 719         }
 720
 721         /* we have the ability to check now */
 722         if (amdgpu_sriov_vf(adev)) {
 723                 switch (adev->asic_type) {
 724                 case CHIP_TONGA:
 725                 case CHIP_FIJI:
 726                         vi_set_virt_ops(adev);
 727                         break;
 728                 case CHIP_VEGA10:
 729                         soc15_set_virt_ops(adev);
 730 #ifdef CONFIG_X86
 731                         /* not send GPU_INIT_DATA with MS_HYPERV*/
 732                         if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
 733 #endif
 734                                 /* send a dummy GPU_INIT_DATA request to host on vega10 */
 735                                 amdgpu_virt_request_init_data(adev);
 736                         break;
 737                 case CHIP_VEGA20:
 738                 case CHIP_ARCTURUS:
 739                 case CHIP_ALDEBARAN:
 740                         soc15_set_virt_ops(adev);
 741                         break;
 742                 case CHIP_NAVI10:
 743                 case CHIP_NAVI12:
 744                 case CHIP_SIENNA_CICHLID:
 745                         nv_set_virt_ops(adev);
 746                         /* try send GPU_INIT_DATA request to host */
 747                         amdgpu_virt_request_init_data(adev);
 748                         break;
 749                 default: /* other chip doesn't support SRIOV */
 750                         DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
 751                         break;
 752                 }
 753         }
 754 }
 755
 756 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 757 {
 758         return amdgpu_sriov_is_debug(adev) ? true : false;
 759 }
 760
 761 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 762 {
 763         return amdgpu_sriov_is_normal(adev) ? true : false;
 764 }
 765
 766 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
 767 {
 768         if (!amdgpu_sriov_vf(adev) ||
 769             amdgpu_virt_access_debugfs_is_kiq(adev))
 770                 return 0;
 771
 772         if (amdgpu_virt_access_debugfs_is_mmio(adev))
 773                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 774         else
 775                 return -EPERM;
 776
 777         return 0;
 778 }
 779
 780 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
 781 {
 782         if (amdgpu_sriov_vf(adev))
 783                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 784 }
 785
 786 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
 787 {
 788         enum amdgpu_sriov_vf_mode mode;
 789
 790         if (amdgpu_sriov_vf(adev)) {
 791                 if (amdgpu_sriov_is_pp_one_vf(adev))
 792                         mode = SRIOV_VF_MODE_ONE_VF;
 793                 else
 794                         mode = SRIOV_VF_MODE_MULTI_VF;
 795         } else {
 796                 mode = SRIOV_VF_MODE_BARE_METAL;
 797         }
 798
 799         return mode;
 800 }
 801
 802 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
 803                         struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
 804                         struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
 805 {
 806         uint32_t i;
 807
 808         if (!adev->virt.is_mm_bw_enabled)
 809                 return;
 810
 811         if (encode) {
 812                 for (i = 0; i < encode_array_size; i++) {
 813                         encode[i].max_width = adev->virt.encode_max_dimension_pixels;
 814                         encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
 815                         if (encode[i].max_width > 0)
 816                                 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width;
 817                         else
 818                                 encode[i].max_height = 0;
 819                 }
 820         }
 821
 822         if (decode) {
 823                 for (i = 0; i < decode_array_size; i++) {
 824                         decode[i].max_width = adev->virt.decode_max_dimension_pixels;
 825                         decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;
 826                         if (decode[i].max_width > 0)
 827                                 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width;
 828                         else
 829                                 decode[i].max_height = 0;
 830                 }
 831         }
 832 }
 833
 834 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
 835                                                  u32 acc_flags, u32 hwip,
 836                                                  bool write, u32 *rlcg_flag)
 837 {
 838         bool ret = false;
 839
 840         switch (hwip) {
 841         case GC_HWIP:
 842                 if (amdgpu_sriov_reg_indirect_gc(adev)) {
 843                         *rlcg_flag =
 844                                 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
 845                         ret = true;
 846                 /* only in new version, AMDGPU_REGS_NO_KIQ and
 847                  * AMDGPU_REGS_RLC are enabled simultaneously */
 848                 } else if ((acc_flags & AMDGPU_REGS_RLC) &&
 849                                 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
 850                         *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
 851                         ret = true;
 852                 }
 853                 break;
 854         case MMHUB_HWIP:
 855                 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
 856                     (acc_flags & AMDGPU_REGS_RLC) && write) {
 857                         *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
 858                         ret = true;
 859                 }
 860                 break;
 861         default:
 862                 break;
 863         }
 864         return ret;
 865 }
 866
 867 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
 868 {
 869         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 870         uint32_t timeout = 50000;
 871         uint32_t i, tmp;
 872         uint32_t ret = 0;
 873         void *scratch_reg0;
 874         void *scratch_reg1;
 875         void *scratch_reg2;
 876         void *scratch_reg3;
 877         void *spare_int;
 878
 879         if (!adev->gfx.rlc.rlcg_reg_access_supported) {
 880                 dev_err(adev->dev,
 881                         "indirect registers access through rlcg is not available\n");
 882                 return 0;
 883         }
 884
 885         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
 886         scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
 887         scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
 888         scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
 889         scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
 890         if (reg_access_ctrl->spare_int)
 891                 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
 892
 893         if (offset == reg_access_ctrl->grbm_cntl) {
 894                 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
 895                 writel(v, scratch_reg2);
 896                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
 897         } else if (offset == reg_access_ctrl->grbm_idx) {
 898                 /* if the target reg offset is grbm_idx, write to scratch_reg3 */
 899                 writel(v, scratch_reg3);
 900                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
 901         } else {
 902                 /*
 903                  * SCRATCH_REG0         = read/write value
 904                  * SCRATCH_REG1[30:28]  = command
 905                  * SCRATCH_REG1[19:0]   = address in dword
 906                  * SCRATCH_REG1[26:24]  = Error reporting
 907                  */
 908                 writel(v, scratch_reg0);
 909                 writel((offset | flag), scratch_reg1);
 910                 if (reg_access_ctrl->spare_int)
 911                         writel(1, spare_int);
 912
 913                 for (i = 0; i < timeout; i++) {
 914                         tmp = readl(scratch_reg1);
 915                         if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
 916                                 break;
 917                         udelay(10);
 918                 }
 919
 920                 if (i >= timeout) {
 921                         if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
 922                                 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
 923                                         dev_err(adev->dev,
 924                                                 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
 925                                 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
 926                                         dev_err(adev->dev,
 927                                                 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
 928                                 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
 929                                         dev_err(adev->dev,
 930                                                 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset);
 931                                 } else {
 932                                         dev_err(adev->dev,
 933                                                 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
 934                                 }
 935                         } else {
 936                                 dev_err(adev->dev,
 937                                         "timeout: rlcg faled to program reg: 0x%05x\n", offset);
 938                         }
 939                 }
 940         }
 941
 942         ret = readl(scratch_reg0);
 943         return ret;
 944 }
 945
 946 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
 947                        u32 offset, u32 value,
 948                        u32 acc_flags, u32 hwip)
 949 {
 950         u32 rlcg_flag;
 951
 952         if (!amdgpu_sriov_runtime(adev) &&
 953                 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
 954                 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
 955                 return;
 956         }
 957
 958         if (acc_flags & AMDGPU_REGS_NO_KIQ)
 959                 WREG32_NO_KIQ(offset, value);
 960         else
 961                 WREG32(offset, value);
 962 }
 963
 964 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
 965                       u32 offset, u32 acc_flags, u32 hwip)
 966 {
 967         u32 rlcg_flag;
 968
 969         if (!amdgpu_sriov_runtime(adev) &&
 970                 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
 971                 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
 972
 973         if (acc_flags & AMDGPU_REGS_NO_KIQ)
 974                 return RREG32_NO_KIQ(offset);
 975         else
 976                 return RREG32(offset);
 977 }