2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT_MS 1000
46 #ifdef CONFIG_DRM_AMDGPU_CIK
47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
56 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
59 * amdgpu_uvd_cs_ctx - Command submission parser context
61 * Used for emulating virtual memory support on UVD 4.2.
63 struct amdgpu_uvd_cs_ctx {
64 struct amdgpu_cs_parser *parser;
66 unsigned data0, data1;
70 /* does the IB has a msg command */
73 /* minimum buffer sizes */
77 #ifdef CONFIG_DRM_AMDGPU_CIK
78 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
79 MODULE_FIRMWARE(FIRMWARE_KABINI);
80 MODULE_FIRMWARE(FIRMWARE_KAVERI);
81 MODULE_FIRMWARE(FIRMWARE_HAWAII);
82 MODULE_FIRMWARE(FIRMWARE_MULLINS);
84 MODULE_FIRMWARE(FIRMWARE_TONGA);
85 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
86 MODULE_FIRMWARE(FIRMWARE_FIJI);
87 MODULE_FIRMWARE(FIRMWARE_STONEY);
89 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
90 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
92 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
94 unsigned long bo_size;
96 const struct common_firmware_header *hdr;
97 unsigned version_major, version_minor, family_id;
100 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
102 switch (adev->asic_type) {
103 #ifdef CONFIG_DRM_AMDGPU_CIK
105 fw_name = FIRMWARE_BONAIRE;
108 fw_name = FIRMWARE_KABINI;
111 fw_name = FIRMWARE_KAVERI;
114 fw_name = FIRMWARE_HAWAII;
117 fw_name = FIRMWARE_MULLINS;
121 fw_name = FIRMWARE_TONGA;
124 fw_name = FIRMWARE_FIJI;
127 fw_name = FIRMWARE_CARRIZO;
130 fw_name = FIRMWARE_STONEY;
136 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
138 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
143 r = amdgpu_ucode_validate(adev->uvd.fw);
145 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
147 release_firmware(adev->uvd.fw);
152 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
153 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
154 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
155 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
156 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
157 version_major, version_minor, family_id);
159 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
160 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
161 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
162 AMDGPU_GEM_DOMAIN_VRAM,
163 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
164 NULL, NULL, &adev->uvd.vcpu_bo);
166 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
170 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
172 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
173 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
177 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
178 &adev->uvd.gpu_addr);
180 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
181 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
182 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
186 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
188 dev_err(adev->dev, "(%d) UVD map failed\n", r);
192 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
194 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
195 atomic_set(&adev->uvd.handles[i], 0);
196 adev->uvd.filp[i] = NULL;
199 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
200 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
201 adev->uvd.address_64_bit = true;
206 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
210 if (adev->uvd.vcpu_bo == NULL)
213 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
215 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
216 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
217 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
220 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
222 amdgpu_ring_fini(&adev->uvd.ring);
224 release_firmware(adev->uvd.fw);
229 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
231 struct amdgpu_ring *ring = &adev->uvd.ring;
234 if (adev->uvd.vcpu_bo == NULL)
237 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
238 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
242 amdgpu_uvd_note_usage(adev);
244 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
246 DRM_ERROR("Error destroying UVD (%d)!\n", r);
250 fence_wait(fence, false);
253 adev->uvd.filp[i] = NULL;
254 atomic_set(&adev->uvd.handles[i], 0);
261 int amdgpu_uvd_resume(struct amdgpu_device *adev)
265 const struct common_firmware_header *hdr;
268 if (adev->uvd.vcpu_bo == NULL)
271 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
272 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
273 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
274 (adev->uvd.fw->size) - offset);
276 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
277 size -= le32_to_cpu(hdr->ucode_size_bytes);
278 ptr = adev->uvd.cpu_addr;
279 ptr += le32_to_cpu(hdr->ucode_size_bytes);
281 memset(ptr, 0, size);
286 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
288 struct amdgpu_ring *ring = &adev->uvd.ring;
291 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
292 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
293 if (handle != 0 && adev->uvd.filp[i] == filp) {
296 amdgpu_uvd_note_usage(adev);
298 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
300 DRM_ERROR("Error destroying UVD (%d)!\n", r);
304 fence_wait(fence, false);
307 adev->uvd.filp[i] = NULL;
308 atomic_set(&adev->uvd.handles[i], 0);
313 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
316 for (i = 0; i < rbo->placement.num_placement; ++i) {
317 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
318 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
323 * amdgpu_uvd_cs_pass1 - first parsing round
325 * @ctx: UVD parser context
327 * Make sure UVD message and feedback buffers are in VRAM and
328 * nobody is violating an 256MB boundary.
330 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
332 struct amdgpu_bo_va_mapping *mapping;
333 struct amdgpu_bo *bo;
334 uint32_t cmd, lo, hi;
338 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
339 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
340 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
342 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
343 if (mapping == NULL) {
344 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
348 if (!ctx->parser->adev->uvd.address_64_bit) {
349 /* check if it's a message or feedback command */
350 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
351 if (cmd == 0x0 || cmd == 0x3) {
352 /* yes, force it into VRAM */
353 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
354 amdgpu_ttm_placement_from_domain(bo, domain);
356 amdgpu_uvd_force_into_uvd_segment(bo);
358 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
365 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
367 * @msg: pointer to message structure
368 * @buf_sizes: returned buffer sizes
370 * Peek into the decode message and calculate the necessary buffer sizes.
372 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
374 unsigned stream_type = msg[4];
375 unsigned width = msg[6];
376 unsigned height = msg[7];
377 unsigned dpb_size = msg[9];
378 unsigned pitch = msg[28];
379 unsigned level = msg[57];
381 unsigned width_in_mb = width / 16;
382 unsigned height_in_mb = ALIGN(height / 16, 2);
383 unsigned fs_in_mb = width_in_mb * height_in_mb;
385 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
386 unsigned min_ctx_size = 0;
388 image_size = width * height;
389 image_size += image_size / 2;
390 image_size = ALIGN(image_size, 1024);
392 switch (stream_type) {
394 case 7: /* H264 Perf */
397 num_dpb_buffer = 8100 / fs_in_mb;
400 num_dpb_buffer = 18000 / fs_in_mb;
403 num_dpb_buffer = 20480 / fs_in_mb;
406 num_dpb_buffer = 32768 / fs_in_mb;
409 num_dpb_buffer = 34816 / fs_in_mb;
412 num_dpb_buffer = 110400 / fs_in_mb;
415 num_dpb_buffer = 184320 / fs_in_mb;
418 num_dpb_buffer = 184320 / fs_in_mb;
422 if (num_dpb_buffer > 17)
425 /* reference picture buffer */
426 min_dpb_size = image_size * num_dpb_buffer;
428 /* macroblock context buffer */
429 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
431 /* IT surface buffer */
432 min_dpb_size += width_in_mb * height_in_mb * 32;
437 /* reference picture buffer */
438 min_dpb_size = image_size * 3;
441 min_dpb_size += width_in_mb * height_in_mb * 128;
443 /* IT surface buffer */
444 min_dpb_size += width_in_mb * 64;
446 /* DB surface buffer */
447 min_dpb_size += width_in_mb * 128;
450 tmp = max(width_in_mb, height_in_mb);
451 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
456 /* reference picture buffer */
457 min_dpb_size = image_size * 3;
462 /* reference picture buffer */
463 min_dpb_size = image_size * 3;
466 min_dpb_size += width_in_mb * height_in_mb * 64;
468 /* IT surface buffer */
469 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
473 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
474 image_size = ALIGN(image_size, 256);
476 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
477 min_dpb_size = image_size * num_dpb_buffer;
478 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
479 * 16 * num_dpb_buffer + 52 * 1024;
483 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
488 DRM_ERROR("Invalid UVD decoding target pitch!\n");
492 if (dpb_size < min_dpb_size) {
493 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
494 dpb_size, min_dpb_size);
498 buf_sizes[0x1] = dpb_size;
499 buf_sizes[0x2] = image_size;
500 buf_sizes[0x4] = min_ctx_size;
505 * amdgpu_uvd_cs_msg - handle UVD message
507 * @ctx: UVD parser context
508 * @bo: buffer object containing the message
509 * @offset: offset into the buffer object
511 * Peek into the UVD message and extract the session id.
512 * Make sure that we don't open up to many sessions.
514 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
515 struct amdgpu_bo *bo, unsigned offset)
517 struct amdgpu_device *adev = ctx->parser->adev;
518 int32_t *msg, msg_type, handle;
524 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
528 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
529 MAX_SCHEDULE_TIMEOUT);
531 DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
535 r = amdgpu_bo_kmap(bo, &ptr);
537 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
547 DRM_ERROR("Invalid UVD handle!\n");
553 /* it's a create msg, calc image size (width * height) */
554 amdgpu_bo_kunmap(bo);
556 /* try to alloc a new handle */
557 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
558 if (atomic_read(&adev->uvd.handles[i]) == handle) {
559 DRM_ERROR("Handle 0x%x already in use!\n", handle);
563 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
564 adev->uvd.filp[i] = ctx->parser->filp;
569 DRM_ERROR("No more free UVD handles!\n");
573 /* it's a decode msg, calc buffer sizes */
574 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
575 amdgpu_bo_kunmap(bo);
579 /* validate the handle */
580 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
581 if (atomic_read(&adev->uvd.handles[i]) == handle) {
582 if (adev->uvd.filp[i] != ctx->parser->filp) {
583 DRM_ERROR("UVD handle collision detected!\n");
590 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
594 /* it's a destroy msg, free the handle */
595 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
596 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
597 amdgpu_bo_kunmap(bo);
601 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
609 * amdgpu_uvd_cs_pass2 - second parsing round
611 * @ctx: UVD parser context
613 * Patch buffer addresses, make sure buffer sizes are correct.
615 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
617 struct amdgpu_bo_va_mapping *mapping;
618 struct amdgpu_bo *bo;
619 uint32_t cmd, lo, hi;
624 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
625 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
626 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
628 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
632 start = amdgpu_bo_gpu_offset(bo);
634 end = (mapping->it.last + 1 - mapping->it.start);
635 end = end * AMDGPU_GPU_PAGE_SIZE + start;
637 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
640 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
641 lower_32_bits(start));
642 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
643 upper_32_bits(start));
645 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
647 if ((end - start) < ctx->buf_sizes[cmd]) {
648 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
649 (unsigned)(end - start),
650 ctx->buf_sizes[cmd]);
654 } else if (cmd == 0x206) {
655 if ((end - start) < ctx->buf_sizes[4]) {
656 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
657 (unsigned)(end - start),
661 } else if ((cmd != 0x100) && (cmd != 0x204)) {
662 DRM_ERROR("invalid UVD command %X!\n", cmd);
666 if (!ctx->parser->adev->uvd.address_64_bit) {
667 if ((start >> 28) != ((end - 1) >> 28)) {
668 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
673 if ((cmd == 0 || cmd == 0x3) &&
674 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
675 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
682 ctx->has_msg_cmd = true;
683 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
686 } else if (!ctx->has_msg_cmd) {
687 DRM_ERROR("Message needed before other commands are send!\n");
695 * amdgpu_uvd_cs_reg - parse register writes
697 * @ctx: UVD parser context
698 * @cb: callback function
700 * Parse the register writes, call cb on each complete command.
702 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
703 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
705 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
709 for (i = 0; i <= ctx->count; ++i) {
710 unsigned reg = ctx->reg + i;
712 if (ctx->idx >= ib->length_dw) {
713 DRM_ERROR("Register command after end of CS!\n");
718 case mmUVD_GPCOM_VCPU_DATA0:
719 ctx->data0 = ctx->idx;
721 case mmUVD_GPCOM_VCPU_DATA1:
722 ctx->data1 = ctx->idx;
724 case mmUVD_GPCOM_VCPU_CMD:
729 case mmUVD_ENGINE_CNTL:
732 DRM_ERROR("Invalid reg 0x%X!\n", reg);
741 * amdgpu_uvd_cs_packets - parse UVD packets
743 * @ctx: UVD parser context
744 * @cb: callback function
746 * Parse the command stream packets.
748 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
749 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
751 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
754 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
755 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
756 unsigned type = CP_PACKET_GET_TYPE(cmd);
759 ctx->reg = CP_PACKET0_GET_REG(cmd);
760 ctx->count = CP_PACKET_GET_COUNT(cmd);
761 r = amdgpu_uvd_cs_reg(ctx, cb);
769 DRM_ERROR("Unknown packet type %d !\n", type);
777 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
779 * @parser: Command submission parser context
781 * Parse the command stream, patch in addresses as necessary.
783 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
785 struct amdgpu_uvd_cs_ctx ctx = {};
786 unsigned buf_sizes[] = {
788 [0x00000001] = 0xFFFFFFFF,
789 [0x00000002] = 0xFFFFFFFF,
791 [0x00000004] = 0xFFFFFFFF,
793 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
796 if (ib->length_dw % 16) {
797 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
803 ctx.buf_sizes = buf_sizes;
806 /* first round, make sure the buffers are actually in the UVD segment */
807 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
811 /* second round, patch buffer addresses into the command stream */
812 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
816 if (!ctx.has_msg_cmd) {
817 DRM_ERROR("UVD-IBs need a msg command!\n");
821 amdgpu_uvd_note_usage(ctx.parser->adev);
826 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
827 struct amdgpu_bo *bo,
828 struct fence **fence)
830 struct ttm_validate_buffer tv;
831 struct ww_acquire_ctx ticket;
832 struct list_head head;
833 struct amdgpu_job *job;
834 struct amdgpu_ib *ib;
835 struct fence *f = NULL;
836 struct amdgpu_device *adev = ring->adev;
840 memset(&tv, 0, sizeof(tv));
843 INIT_LIST_HEAD(&head);
844 list_add(&tv.head, &head);
846 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
850 if (!bo->adev->uvd.address_64_bit) {
851 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
852 amdgpu_uvd_force_into_uvd_segment(bo);
855 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
859 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
864 addr = amdgpu_bo_gpu_offset(bo);
865 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
867 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
868 ib->ptr[3] = addr >> 32;
869 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
871 for (i = 6; i < 16; ++i)
872 ib->ptr[i] = PACKET2(0);
875 r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
879 ttm_eu_fence_buffer_objects(&ticket, &head, f);
882 *fence = fence_get(f);
883 amdgpu_bo_unref(&bo);
889 amdgpu_job_free(job);
892 ttm_eu_backoff_reservation(&ticket, &head);
896 /* multiple fence commands without any stream commands in between can
897 crash the vcpu so just try to emmit a dummy create/destroy msg to
899 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
900 struct fence **fence)
902 struct amdgpu_device *adev = ring->adev;
903 struct amdgpu_bo *bo;
907 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
908 AMDGPU_GEM_DOMAIN_VRAM,
909 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
914 r = amdgpu_bo_reserve(bo, false);
916 amdgpu_bo_unref(&bo);
920 r = amdgpu_bo_kmap(bo, (void **)&msg);
922 amdgpu_bo_unreserve(bo);
923 amdgpu_bo_unref(&bo);
927 /* stitch together an UVD create msg */
928 msg[0] = cpu_to_le32(0x00000de4);
929 msg[1] = cpu_to_le32(0x00000000);
930 msg[2] = cpu_to_le32(handle);
931 msg[3] = cpu_to_le32(0x00000000);
932 msg[4] = cpu_to_le32(0x00000000);
933 msg[5] = cpu_to_le32(0x00000000);
934 msg[6] = cpu_to_le32(0x00000000);
935 msg[7] = cpu_to_le32(0x00000780);
936 msg[8] = cpu_to_le32(0x00000440);
937 msg[9] = cpu_to_le32(0x00000000);
938 msg[10] = cpu_to_le32(0x01b37000);
939 for (i = 11; i < 1024; ++i)
940 msg[i] = cpu_to_le32(0x0);
942 amdgpu_bo_kunmap(bo);
943 amdgpu_bo_unreserve(bo);
945 return amdgpu_uvd_send_msg(ring, bo, fence);
948 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
949 struct fence **fence)
951 struct amdgpu_device *adev = ring->adev;
952 struct amdgpu_bo *bo;
956 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
957 AMDGPU_GEM_DOMAIN_VRAM,
958 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
963 r = amdgpu_bo_reserve(bo, false);
965 amdgpu_bo_unref(&bo);
969 r = amdgpu_bo_kmap(bo, (void **)&msg);
971 amdgpu_bo_unreserve(bo);
972 amdgpu_bo_unref(&bo);
976 /* stitch together an UVD destroy msg */
977 msg[0] = cpu_to_le32(0x00000de4);
978 msg[1] = cpu_to_le32(0x00000002);
979 msg[2] = cpu_to_le32(handle);
980 msg[3] = cpu_to_le32(0x00000000);
981 for (i = 4; i < 1024; ++i)
982 msg[i] = cpu_to_le32(0x0);
984 amdgpu_bo_kunmap(bo);
985 amdgpu_bo_unreserve(bo);
987 return amdgpu_uvd_send_msg(ring, bo, fence);
990 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
992 struct amdgpu_device *adev =
993 container_of(work, struct amdgpu_device, uvd.idle_work.work);
994 unsigned i, fences, handles = 0;
996 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
998 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
999 if (atomic_read(&adev->uvd.handles[i]))
1002 if (fences == 0 && handles == 0) {
1003 if (adev->pm.dpm_enabled) {
1004 amdgpu_dpm_enable_uvd(adev, false);
1006 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1009 schedule_delayed_work(&adev->uvd.idle_work,
1010 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1014 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1016 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1017 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1018 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1021 if (adev->pm.dpm_enabled) {
1022 amdgpu_dpm_enable_uvd(adev, true);
1024 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);