drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  44
  45 /* Firmware versions for VI */
  46 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
  47 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
  48 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
  49 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
  50
  51 /* Polaris10/11 firmware version */
  52 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
  53
  54 /* Firmware Names */
  55 #ifdef CONFIG_DRM_AMDGPU_CIK
  56 #define FIRMWARE_BONAIRE        "radeon/bonaire_uvd.bin"
  57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
  58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
  59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
  60 #define FIRMWARE_MULLINS        "radeon/mullins_uvd.bin"
  61 #endif
  62 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  63 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  64 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  65 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
  66 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
  67 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
  68
  69 /**
  70  * amdgpu_uvd_cs_ctx - Command submission parser context
  71  *
  72  * Used for emulating virtual memory support on UVD 4.2.
  73  */
  74 struct amdgpu_uvd_cs_ctx {
  75         struct amdgpu_cs_parser *parser;
  76         unsigned reg, count;
  77         unsigned data0, data1;
  78         unsigned idx;
  79         unsigned ib_idx;
  80
  81         /* does the IB has a msg command */
  82         bool has_msg_cmd;
  83
  84         /* minimum buffer sizes */
  85         unsigned *buf_sizes;
  86 };
  87
  88 #ifdef CONFIG_DRM_AMDGPU_CIK
  89 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  90 MODULE_FIRMWARE(FIRMWARE_KABINI);
  91 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  92 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  93 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  94 #endif
  95 MODULE_FIRMWARE(FIRMWARE_TONGA);
  96 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  97 MODULE_FIRMWARE(FIRMWARE_FIJI);
  98 MODULE_FIRMWARE(FIRMWARE_STONEY);
  99 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 100 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 101
 102 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 103
 104 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 105 {
 106         struct amdgpu_ring *ring;
 107         struct amd_sched_rq *rq;
 108         unsigned long bo_size;
 109         const char *fw_name;
 110         const struct common_firmware_header *hdr;
 111         unsigned version_major, version_minor, family_id;
 112         int i, r;
 113
 114         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 115
 116         switch (adev->asic_type) {
 117 #ifdef CONFIG_DRM_AMDGPU_CIK
 118         case CHIP_BONAIRE:
 119                 fw_name = FIRMWARE_BONAIRE;
 120                 break;
 121         case CHIP_KABINI:
 122                 fw_name = FIRMWARE_KABINI;
 123                 break;
 124         case CHIP_KAVERI:
 125                 fw_name = FIRMWARE_KAVERI;
 126                 break;
 127         case CHIP_HAWAII:
 128                 fw_name = FIRMWARE_HAWAII;
 129                 break;
 130         case CHIP_MULLINS:
 131                 fw_name = FIRMWARE_MULLINS;
 132                 break;
 133 #endif
 134         case CHIP_TONGA:
 135                 fw_name = FIRMWARE_TONGA;
 136                 break;
 137         case CHIP_FIJI:
 138                 fw_name = FIRMWARE_FIJI;
 139                 break;
 140         case CHIP_CARRIZO:
 141                 fw_name = FIRMWARE_CARRIZO;
 142                 break;
 143         case CHIP_STONEY:
 144                 fw_name = FIRMWARE_STONEY;
 145                 break;
 146         case CHIP_POLARIS10:
 147                 fw_name = FIRMWARE_POLARIS10;
 148                 break;
 149         case CHIP_POLARIS11:
 150                 fw_name = FIRMWARE_POLARIS11;
 151                 break;
 152         default:
 153                 return -EINVAL;
 154         }
 155
 156         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 157         if (r) {
 158                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 159                         fw_name);
 160                 return r;
 161         }
 162
 163         r = amdgpu_ucode_validate(adev->uvd.fw);
 164         if (r) {
 165                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 166                         fw_name);
 167                 release_firmware(adev->uvd.fw);
 168                 adev->uvd.fw = NULL;
 169                 return r;
 170         }
 171
 172         /* Set the default UVD handles that the firmware can handle */
 173         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 174
 175         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 176         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 177         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 178         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 179         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 180                 version_major, version_minor, family_id);
 181
 182         /*
 183          * Limit the number of UVD handles depending on microcode major
 184          * and minor versions. The firmware version which has 40 UVD
 185          * instances support is 1.80. So all subsequent versions should
 186          * also have the same support.
 187          */
 188         if ((version_major > 0x01) ||
 189             ((version_major == 0x01) && (version_minor >= 0x50)))
 190                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 191
 192         adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 193                                 (family_id << 8));
 194
 195         if ((adev->asic_type == CHIP_POLARIS10 ||
 196              adev->asic_type == CHIP_POLARIS11) &&
 197             (adev->uvd.fw_version < FW_1_66_16))
 198                 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
 199                           version_major, version_minor);
 200
 201         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 202                   +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 203                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 204         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 205                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
 206                                     &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
 207         if (r) {
 208                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 209                 return r;
 210         }
 211
 212         ring = &adev->uvd.ring;
 213         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 214         r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
 215                                   rq, amdgpu_sched_jobs);
 216         if (r != 0) {
 217                 DRM_ERROR("Failed setting up UVD run queue.\n");
 218                 return r;
 219         }
 220
 221         for (i = 0; i < adev->uvd.max_handles; ++i) {
 222                 atomic_set(&adev->uvd.handles[i], 0);
 223                 adev->uvd.filp[i] = NULL;
 224         }
 225
 226         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 227         if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 228                 adev->uvd.address_64_bit = true;
 229
 230         switch (adev->asic_type) {
 231         case CHIP_TONGA:
 232                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
 233                 break;
 234         case CHIP_CARRIZO:
 235                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
 236                 break;
 237         case CHIP_FIJI:
 238                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
 239                 break;
 240         case CHIP_STONEY:
 241                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
 242                 break;
 243         default:
 244                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
 245         }
 246
 247         return 0;
 248 }
 249
 250 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 251 {
 252         kfree(adev->uvd.saved_bo);
 253
 254         amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
 255
 256         amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
 257                               &adev->uvd.gpu_addr,
 258                               (void **)&adev->uvd.cpu_addr);
 259
 260         amdgpu_ring_fini(&adev->uvd.ring);
 261
 262         release_firmware(adev->uvd.fw);
 263
 264         return 0;
 265 }
 266
 267 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 268 {
 269         unsigned size;
 270         void *ptr;
 271         int i;
 272
 273         if (adev->uvd.vcpu_bo == NULL)
 274                 return 0;
 275
 276         for (i = 0; i < adev->uvd.max_handles; ++i)
 277                 if (atomic_read(&adev->uvd.handles[i]))
 278                         break;
 279
 280         if (i == AMDGPU_MAX_UVD_HANDLES)
 281                 return 0;
 282
 283         cancel_delayed_work_sync(&adev->uvd.idle_work);
 284
 285         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 286         ptr = adev->uvd.cpu_addr;
 287
 288         adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 289         if (!adev->uvd.saved_bo)
 290                 return -ENOMEM;
 291
 292         memcpy_fromio(adev->uvd.saved_bo, ptr, size);
 293
 294         return 0;
 295 }
 296
 297 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 298 {
 299         unsigned size;
 300         void *ptr;
 301
 302         if (adev->uvd.vcpu_bo == NULL)
 303                 return -EINVAL;
 304
 305         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 306         ptr = adev->uvd.cpu_addr;
 307
 308         if (adev->uvd.saved_bo != NULL) {
 309                 memcpy_toio(ptr, adev->uvd.saved_bo, size);
 310                 kfree(adev->uvd.saved_bo);
 311                 adev->uvd.saved_bo = NULL;
 312         } else {
 313                 const struct common_firmware_header *hdr;
 314                 unsigned offset;
 315
 316                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 317                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 318                 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
 319                             le32_to_cpu(hdr->ucode_size_bytes));
 320                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 321                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 322                 memset_io(ptr, 0, size);
 323         }
 324
 325         return 0;
 326 }
 327
 328 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 329 {
 330         struct amdgpu_ring *ring = &adev->uvd.ring;
 331         int i, r;
 332
 333         for (i = 0; i < adev->uvd.max_handles; ++i) {
 334                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 335                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 336                         struct dma_fence *fence;
 337
 338                         r = amdgpu_uvd_get_destroy_msg(ring, handle,
 339                                                        false, &fence);
 340                         if (r) {
 341                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 342                                 continue;
 343                         }
 344
 345                         dma_fence_wait(fence, false);
 346                         dma_fence_put(fence);
 347
 348                         adev->uvd.filp[i] = NULL;
 349                         atomic_set(&adev->uvd.handles[i], 0);
 350                 }
 351         }
 352 }
 353
 354 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
 355 {
 356         int i;
 357         for (i = 0; i < abo->placement.num_placement; ++i) {
 358                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 359                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 360         }
 361 }
 362
 363 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
 364 {
 365         uint32_t lo, hi;
 366         uint64_t addr;
 367
 368         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 369         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 370         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 371
 372         return addr;
 373 }
 374
 375 /**
 376  * amdgpu_uvd_cs_pass1 - first parsing round
 377  *
 378  * @ctx: UVD parser context
 379  *
 380  * Make sure UVD message and feedback buffers are in VRAM and
 381  * nobody is violating an 256MB boundary.
 382  */
 383 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 384 {
 385         struct amdgpu_bo_va_mapping *mapping;
 386         struct amdgpu_bo *bo;
 387         uint32_t cmd;
 388         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 389         int r = 0;
 390
 391         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 392         if (mapping == NULL) {
 393                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 394                 return -EINVAL;
 395         }
 396
 397         if (!ctx->parser->adev->uvd.address_64_bit) {
 398                 /* check if it's a message or feedback command */
 399                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 400                 if (cmd == 0x0 || cmd == 0x3) {
 401                         /* yes, force it into VRAM */
 402                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 403                         amdgpu_ttm_placement_from_domain(bo, domain);
 404                 }
 405                 amdgpu_uvd_force_into_uvd_segment(bo);
 406
 407                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 408         }
 409
 410         return r;
 411 }
 412
 413 /**
 414  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 415  *
 416  * @msg: pointer to message structure
 417  * @buf_sizes: returned buffer sizes
 418  *
 419  * Peek into the decode message and calculate the necessary buffer sizes.
 420  */
 421 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
 422         unsigned buf_sizes[])
 423 {
 424         unsigned stream_type = msg[4];
 425         unsigned width = msg[6];
 426         unsigned height = msg[7];
 427         unsigned dpb_size = msg[9];
 428         unsigned pitch = msg[28];
 429         unsigned level = msg[57];
 430
 431         unsigned width_in_mb = width / 16;
 432         unsigned height_in_mb = ALIGN(height / 16, 2);
 433         unsigned fs_in_mb = width_in_mb * height_in_mb;
 434
 435         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 436         unsigned min_ctx_size = ~0;
 437
 438         image_size = width * height;
 439         image_size += image_size / 2;
 440         image_size = ALIGN(image_size, 1024);
 441
 442         switch (stream_type) {
 443         case 0: /* H264 */
 444                 switch(level) {
 445                 case 30:
 446                         num_dpb_buffer = 8100 / fs_in_mb;
 447                         break;
 448                 case 31:
 449                         num_dpb_buffer = 18000 / fs_in_mb;
 450                         break;
 451                 case 32:
 452                         num_dpb_buffer = 20480 / fs_in_mb;
 453                         break;
 454                 case 41:
 455                         num_dpb_buffer = 32768 / fs_in_mb;
 456                         break;
 457                 case 42:
 458                         num_dpb_buffer = 34816 / fs_in_mb;
 459                         break;
 460                 case 50:
 461                         num_dpb_buffer = 110400 / fs_in_mb;
 462                         break;
 463                 case 51:
 464                         num_dpb_buffer = 184320 / fs_in_mb;
 465                         break;
 466                 default:
 467                         num_dpb_buffer = 184320 / fs_in_mb;
 468                         break;
 469                 }
 470                 num_dpb_buffer++;
 471                 if (num_dpb_buffer > 17)
 472                         num_dpb_buffer = 17;
 473
 474                 /* reference picture buffer */
 475                 min_dpb_size = image_size * num_dpb_buffer;
 476
 477                 /* macroblock context buffer */
 478                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 479
 480                 /* IT surface buffer */
 481                 min_dpb_size += width_in_mb * height_in_mb * 32;
 482                 break;
 483
 484         case 1: /* VC1 */
 485
 486                 /* reference picture buffer */
 487                 min_dpb_size = image_size * 3;
 488
 489                 /* CONTEXT_BUFFER */
 490                 min_dpb_size += width_in_mb * height_in_mb * 128;
 491
 492                 /* IT surface buffer */
 493                 min_dpb_size += width_in_mb * 64;
 494
 495                 /* DB surface buffer */
 496                 min_dpb_size += width_in_mb * 128;
 497
 498                 /* BP */
 499                 tmp = max(width_in_mb, height_in_mb);
 500                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 501                 break;
 502
 503         case 3: /* MPEG2 */
 504
 505                 /* reference picture buffer */
 506                 min_dpb_size = image_size * 3;
 507                 break;
 508
 509         case 4: /* MPEG4 */
 510
 511                 /* reference picture buffer */
 512                 min_dpb_size = image_size * 3;
 513
 514                 /* CM */
 515                 min_dpb_size += width_in_mb * height_in_mb * 64;
 516
 517                 /* IT surface buffer */
 518                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 519                 break;
 520
 521         case 7: /* H264 Perf */
 522                 switch(level) {
 523                 case 30:
 524                         num_dpb_buffer = 8100 / fs_in_mb;
 525                         break;
 526                 case 31:
 527                         num_dpb_buffer = 18000 / fs_in_mb;
 528                         break;
 529                 case 32:
 530                         num_dpb_buffer = 20480 / fs_in_mb;
 531                         break;
 532                 case 41:
 533                         num_dpb_buffer = 32768 / fs_in_mb;
 534                         break;
 535                 case 42:
 536                         num_dpb_buffer = 34816 / fs_in_mb;
 537                         break;
 538                 case 50:
 539                         num_dpb_buffer = 110400 / fs_in_mb;
 540                         break;
 541                 case 51:
 542                         num_dpb_buffer = 184320 / fs_in_mb;
 543                         break;
 544                 default:
 545                         num_dpb_buffer = 184320 / fs_in_mb;
 546                         break;
 547                 }
 548                 num_dpb_buffer++;
 549                 if (num_dpb_buffer > 17)
 550                         num_dpb_buffer = 17;
 551
 552                 /* reference picture buffer */
 553                 min_dpb_size = image_size * num_dpb_buffer;
 554
 555                 if (!adev->uvd.use_ctx_buf){
 556                         /* macroblock context buffer */
 557                         min_dpb_size +=
 558                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 559
 560                         /* IT surface buffer */
 561                         min_dpb_size += width_in_mb * height_in_mb * 32;
 562                 } else {
 563                         /* macroblock context buffer */
 564                         min_ctx_size =
 565                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 566                 }
 567                 break;
 568
 569         case 16: /* H265 */
 570                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 571                 image_size = ALIGN(image_size, 256);
 572
 573                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 574                 min_dpb_size = image_size * num_dpb_buffer;
 575                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 576                                            * 16 * num_dpb_buffer + 52 * 1024;
 577                 break;
 578
 579         default:
 580                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 581                 return -EINVAL;
 582         }
 583
 584         if (width > pitch) {
 585                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 586                 return -EINVAL;
 587         }
 588
 589         if (dpb_size < min_dpb_size) {
 590                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 591                           dpb_size, min_dpb_size);
 592                 return -EINVAL;
 593         }
 594
 595         buf_sizes[0x1] = dpb_size;
 596         buf_sizes[0x2] = image_size;
 597         buf_sizes[0x4] = min_ctx_size;
 598         return 0;
 599 }
 600
 601 /**
 602  * amdgpu_uvd_cs_msg - handle UVD message
 603  *
 604  * @ctx: UVD parser context
 605  * @bo: buffer object containing the message
 606  * @offset: offset into the buffer object
 607  *
 608  * Peek into the UVD message and extract the session id.
 609  * Make sure that we don't open up to many sessions.
 610  */
 611 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 612                              struct amdgpu_bo *bo, unsigned offset)
 613 {
 614         struct amdgpu_device *adev = ctx->parser->adev;
 615         int32_t *msg, msg_type, handle;
 616         void *ptr;
 617         long r;
 618         int i;
 619
 620         if (offset & 0x3F) {
 621                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 622                 return -EINVAL;
 623         }
 624
 625         r = amdgpu_bo_kmap(bo, &ptr);
 626         if (r) {
 627                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
 628                 return r;
 629         }
 630
 631         msg = ptr + offset;
 632
 633         msg_type = msg[1];
 634         handle = msg[2];
 635
 636         if (handle == 0) {
 637                 DRM_ERROR("Invalid UVD handle!\n");
 638                 return -EINVAL;
 639         }
 640
 641         switch (msg_type) {
 642         case 0:
 643                 /* it's a create msg, calc image size (width * height) */
 644                 amdgpu_bo_kunmap(bo);
 645
 646                 /* try to alloc a new handle */
 647                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 648                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 649                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
 650                                 return -EINVAL;
 651                         }
 652
 653                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 654                                 adev->uvd.filp[i] = ctx->parser->filp;
 655                                 return 0;
 656                         }
 657                 }
 658
 659                 DRM_ERROR("No more free UVD handles!\n");
 660                 return -ENOSPC;
 661
 662         case 1:
 663                 /* it's a decode msg, calc buffer sizes */
 664                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
 665                 amdgpu_bo_kunmap(bo);
 666                 if (r)
 667                         return r;
 668
 669                 /* validate the handle */
 670                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 671                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 672                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 673                                         DRM_ERROR("UVD handle collision detected!\n");
 674                                         return -EINVAL;
 675                                 }
 676                                 return 0;
 677                         }
 678                 }
 679
 680                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 681                 return -ENOENT;
 682
 683         case 2:
 684                 /* it's a destroy msg, free the handle */
 685                 for (i = 0; i < adev->uvd.max_handles; ++i)
 686                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 687                 amdgpu_bo_kunmap(bo);
 688                 return 0;
 689
 690         default:
 691                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 692                 return -EINVAL;
 693         }
 694         BUG();
 695         return -EINVAL;
 696 }
 697
 698 /**
 699  * amdgpu_uvd_cs_pass2 - second parsing round
 700  *
 701  * @ctx: UVD parser context
 702  *
 703  * Patch buffer addresses, make sure buffer sizes are correct.
 704  */
 705 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 706 {
 707         struct amdgpu_bo_va_mapping *mapping;
 708         struct amdgpu_bo *bo;
 709         uint32_t cmd;
 710         uint64_t start, end;
 711         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 712         int r;
 713
 714         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 715         if (mapping == NULL) {
 716                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 717                 return -EINVAL;
 718         }
 719
 720         start = amdgpu_bo_gpu_offset(bo);
 721
 722         end = (mapping->it.last + 1 - mapping->it.start);
 723         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 724
 725         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 726         start += addr;
 727
 728         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 729                             lower_32_bits(start));
 730         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 731                             upper_32_bits(start));
 732
 733         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 734         if (cmd < 0x4) {
 735                 if ((end - start) < ctx->buf_sizes[cmd]) {
 736                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 737                                   (unsigned)(end - start),
 738                                   ctx->buf_sizes[cmd]);
 739                         return -EINVAL;
 740                 }
 741
 742         } else if (cmd == 0x206) {
 743                 if ((end - start) < ctx->buf_sizes[4]) {
 744                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 745                                           (unsigned)(end - start),
 746                                           ctx->buf_sizes[4]);
 747                         return -EINVAL;
 748                 }
 749         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 750                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 751                 return -EINVAL;
 752         }
 753
 754         if (!ctx->parser->adev->uvd.address_64_bit) {
 755                 if ((start >> 28) != ((end - 1) >> 28)) {
 756                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 757                                   start, end);
 758                         return -EINVAL;
 759                 }
 760
 761                 if ((cmd == 0 || cmd == 0x3) &&
 762                     (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
 763                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 764                                   start, end);
 765                         return -EINVAL;
 766                 }
 767         }
 768
 769         if (cmd == 0) {
 770                 ctx->has_msg_cmd = true;
 771                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 772                 if (r)
 773                         return r;
 774         } else if (!ctx->has_msg_cmd) {
 775                 DRM_ERROR("Message needed before other commands are send!\n");
 776                 return -EINVAL;
 777         }
 778
 779         return 0;
 780 }
 781
 782 /**
 783  * amdgpu_uvd_cs_reg - parse register writes
 784  *
 785  * @ctx: UVD parser context
 786  * @cb: callback function
 787  *
 788  * Parse the register writes, call cb on each complete command.
 789  */
 790 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 791                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 792 {
 793         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 794         int i, r;
 795
 796         ctx->idx++;
 797         for (i = 0; i <= ctx->count; ++i) {
 798                 unsigned reg = ctx->reg + i;
 799
 800                 if (ctx->idx >= ib->length_dw) {
 801                         DRM_ERROR("Register command after end of CS!\n");
 802                         return -EINVAL;
 803                 }
 804
 805                 switch (reg) {
 806                 case mmUVD_GPCOM_VCPU_DATA0:
 807                         ctx->data0 = ctx->idx;
 808                         break;
 809                 case mmUVD_GPCOM_VCPU_DATA1:
 810                         ctx->data1 = ctx->idx;
 811                         break;
 812                 case mmUVD_GPCOM_VCPU_CMD:
 813                         r = cb(ctx);
 814                         if (r)
 815                                 return r;
 816                         break;
 817                 case mmUVD_ENGINE_CNTL:
 818                 case mmUVD_NO_OP:
 819                         break;
 820                 default:
 821                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 822                         return -EINVAL;
 823                 }
 824                 ctx->idx++;
 825         }
 826         return 0;
 827 }
 828
 829 /**
 830  * amdgpu_uvd_cs_packets - parse UVD packets
 831  *
 832  * @ctx: UVD parser context
 833  * @cb: callback function
 834  *
 835  * Parse the command stream packets.
 836  */
 837 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 838                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 839 {
 840         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 841         int r;
 842
 843         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 844                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 845                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 846                 switch (type) {
 847                 case PACKET_TYPE0:
 848                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 849                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 850                         r = amdgpu_uvd_cs_reg(ctx, cb);
 851                         if (r)
 852                                 return r;
 853                         break;
 854                 case PACKET_TYPE2:
 855                         ++ctx->idx;
 856                         break;
 857                 default:
 858                         DRM_ERROR("Unknown packet type %d !\n", type);
 859                         return -EINVAL;
 860                 }
 861         }
 862         return 0;
 863 }
 864
 865 /**
 866  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 867  *
 868  * @parser: Command submission parser context
 869  *
 870  * Parse the command stream, patch in addresses as necessary.
 871  */
 872 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 873 {
 874         struct amdgpu_uvd_cs_ctx ctx = {};
 875         unsigned buf_sizes[] = {
 876                 [0x00000000]    =       2048,
 877                 [0x00000001]    =       0xFFFFFFFF,
 878                 [0x00000002]    =       0xFFFFFFFF,
 879                 [0x00000003]    =       2048,
 880                 [0x00000004]    =       0xFFFFFFFF,
 881         };
 882         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 883         int r;
 884
 885         parser->job->vm = NULL;
 886         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 887
 888         if (ib->length_dw % 16) {
 889                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 890                           ib->length_dw);
 891                 return -EINVAL;
 892         }
 893
 894         r = amdgpu_cs_sysvm_access_required(parser);
 895         if (r)
 896                 return r;
 897
 898         ctx.parser = parser;
 899         ctx.buf_sizes = buf_sizes;
 900         ctx.ib_idx = ib_idx;
 901
 902         /* first round only required on chips without UVD 64 bit address support */
 903         if (!parser->adev->uvd.address_64_bit) {
 904                 /* first round, make sure the buffers are actually in the UVD segment */
 905                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 906                 if (r)
 907                         return r;
 908         }
 909
 910         /* second round, patch buffer addresses into the command stream */
 911         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 912         if (r)
 913                 return r;
 914
 915         if (!ctx.has_msg_cmd) {
 916                 DRM_ERROR("UVD-IBs need a msg command!\n");
 917                 return -EINVAL;
 918         }
 919
 920         return 0;
 921 }
 922
 923 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 924                                bool direct, struct dma_fence **fence)
 925 {
 926         struct ttm_validate_buffer tv;
 927         struct ww_acquire_ctx ticket;
 928         struct list_head head;
 929         struct amdgpu_job *job;
 930         struct amdgpu_ib *ib;
 931         struct dma_fence *f = NULL;
 932         struct amdgpu_device *adev = ring->adev;
 933         uint64_t addr;
 934         int i, r;
 935
 936         memset(&tv, 0, sizeof(tv));
 937         tv.bo = &bo->tbo;
 938
 939         INIT_LIST_HEAD(&head);
 940         list_add(&tv.head, &head);
 941
 942         r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
 943         if (r)
 944                 return r;
 945
 946         if (!ring->adev->uvd.address_64_bit) {
 947                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 948                 amdgpu_uvd_force_into_uvd_segment(bo);
 949         }
 950
 951         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 952         if (r)
 953                 goto err;
 954
 955         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 956         if (r)
 957                 goto err;
 958
 959         ib = &job->ibs[0];
 960         addr = amdgpu_bo_gpu_offset(bo);
 961         ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
 962         ib->ptr[1] = addr;
 963         ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
 964         ib->ptr[3] = addr >> 32;
 965         ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
 966         ib->ptr[5] = 0;
 967         for (i = 6; i < 16; i += 2) {
 968                 ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0);
 969                 ib->ptr[i+1] = 0;
 970         }
 971         ib->length_dw = 16;
 972
 973         if (direct) {
 974                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
 975                 job->fence = dma_fence_get(f);
 976                 if (r)
 977                         goto err_free;
 978
 979                 amdgpu_job_free(job);
 980         } else {
 981                 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
 982                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 983                 if (r)
 984                         goto err_free;
 985         }
 986
 987         ttm_eu_fence_buffer_objects(&ticket, &head, f);
 988
 989         if (fence)
 990                 *fence = dma_fence_get(f);
 991         amdgpu_bo_unref(&bo);
 992         dma_fence_put(f);
 993
 994         return 0;
 995
 996 err_free:
 997         amdgpu_job_free(job);
 998
 999 err:
1000         ttm_eu_backoff_reservation(&ticket, &head);
1001         return r;
1002 }
1003
1004 /* multiple fence commands without any stream commands in between can
1005    crash the vcpu so just try to emmit a dummy create/destroy msg to
1006    avoid this */
1007 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1008                               struct dma_fence **fence)
1009 {
1010         struct amdgpu_device *adev = ring->adev;
1011         struct amdgpu_bo *bo;
1012         uint32_t *msg;
1013         int r, i;
1014
1015         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1016                              AMDGPU_GEM_DOMAIN_VRAM,
1017                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1018                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1019                              NULL, NULL, &bo);
1020         if (r)
1021                 return r;
1022
1023         r = amdgpu_bo_reserve(bo, false);
1024         if (r) {
1025                 amdgpu_bo_unref(&bo);
1026                 return r;
1027         }
1028
1029         r = amdgpu_bo_kmap(bo, (void **)&msg);
1030         if (r) {
1031                 amdgpu_bo_unreserve(bo);
1032                 amdgpu_bo_unref(&bo);
1033                 return r;
1034         }
1035
1036         /* stitch together an UVD create msg */
1037         msg[0] = cpu_to_le32(0x00000de4);
1038         msg[1] = cpu_to_le32(0x00000000);
1039         msg[2] = cpu_to_le32(handle);
1040         msg[3] = cpu_to_le32(0x00000000);
1041         msg[4] = cpu_to_le32(0x00000000);
1042         msg[5] = cpu_to_le32(0x00000000);
1043         msg[6] = cpu_to_le32(0x00000000);
1044         msg[7] = cpu_to_le32(0x00000780);
1045         msg[8] = cpu_to_le32(0x00000440);
1046         msg[9] = cpu_to_le32(0x00000000);
1047         msg[10] = cpu_to_le32(0x01b37000);
1048         for (i = 11; i < 1024; ++i)
1049                 msg[i] = cpu_to_le32(0x0);
1050
1051         amdgpu_bo_kunmap(bo);
1052         amdgpu_bo_unreserve(bo);
1053
1054         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1055 }
1056
1057 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1058                                bool direct, struct dma_fence **fence)
1059 {
1060         struct amdgpu_device *adev = ring->adev;
1061         struct amdgpu_bo *bo;
1062         uint32_t *msg;
1063         int r, i;
1064
1065         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1066                              AMDGPU_GEM_DOMAIN_VRAM,
1067                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1068                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1069                              NULL, NULL, &bo);
1070         if (r)
1071                 return r;
1072
1073         r = amdgpu_bo_reserve(bo, false);
1074         if (r) {
1075                 amdgpu_bo_unref(&bo);
1076                 return r;
1077         }
1078
1079         r = amdgpu_bo_kmap(bo, (void **)&msg);
1080         if (r) {
1081                 amdgpu_bo_unreserve(bo);
1082                 amdgpu_bo_unref(&bo);
1083                 return r;
1084         }
1085
1086         /* stitch together an UVD destroy msg */
1087         msg[0] = cpu_to_le32(0x00000de4);
1088         msg[1] = cpu_to_le32(0x00000002);
1089         msg[2] = cpu_to_le32(handle);
1090         msg[3] = cpu_to_le32(0x00000000);
1091         for (i = 4; i < 1024; ++i)
1092                 msg[i] = cpu_to_le32(0x0);
1093
1094         amdgpu_bo_kunmap(bo);
1095         amdgpu_bo_unreserve(bo);
1096
1097         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1098 }
1099
1100 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1101 {
1102         struct amdgpu_device *adev =
1103                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1104         unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1105
1106         if (fences == 0) {
1107                 if (adev->pm.dpm_enabled) {
1108                         amdgpu_dpm_enable_uvd(adev, false);
1109                 } else {
1110                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1111                 }
1112         } else {
1113                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1114         }
1115 }
1116
1117 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1118 {
1119         struct amdgpu_device *adev = ring->adev;
1120         bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1121
1122         if (set_clocks) {
1123                 if (adev->pm.dpm_enabled) {
1124                         amdgpu_dpm_enable_uvd(adev, true);
1125                 } else {
1126                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1127                 }
1128         }
1129 }
1130
1131 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1132 {
1133         schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1134 }
1135
1136 /**
1137  * amdgpu_uvd_ring_test_ib - test ib execution
1138  *
1139  * @ring: amdgpu_ring pointer
1140  *
1141  * Test if we can successfully execute an IB
1142  */
1143 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1144 {
1145         struct dma_fence *fence;
1146         long r;
1147
1148         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1149         if (r) {
1150                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1151                 goto error;
1152         }
1153
1154         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1155         if (r) {
1156                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1157                 goto error;
1158         }
1159
1160         r = dma_fence_wait_timeout(fence, false, timeout);
1161         if (r == 0) {
1162                 DRM_ERROR("amdgpu: IB test timed out.\n");
1163                 r = -ETIMEDOUT;
1164         } else if (r < 0) {
1165                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1166         } else {
1167                 DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
1168                 r = 0;
1169         }
1170
1171         dma_fence_put(fence);
1172
1173 error:
1174         return r;
1175 }