2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
44 /* Polaris10/11 firmware version */
45 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
50 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
51 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
52 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
53 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
55 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
56 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
57 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
58 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
59 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
60 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
63 * amdgpu_uvd_cs_ctx - Command submission parser context
65 * Used for emulating virtual memory support on UVD 4.2.
67 struct amdgpu_uvd_cs_ctx {
68 struct amdgpu_cs_parser *parser;
70 unsigned data0, data1;
74 /* does the IB has a msg command */
77 /* minimum buffer sizes */
81 #ifdef CONFIG_DRM_AMDGPU_CIK
82 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
83 MODULE_FIRMWARE(FIRMWARE_KABINI);
84 MODULE_FIRMWARE(FIRMWARE_KAVERI);
85 MODULE_FIRMWARE(FIRMWARE_HAWAII);
86 MODULE_FIRMWARE(FIRMWARE_MULLINS);
88 MODULE_FIRMWARE(FIRMWARE_TONGA);
89 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
90 MODULE_FIRMWARE(FIRMWARE_FIJI);
91 MODULE_FIRMWARE(FIRMWARE_STONEY);
92 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
93 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
95 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
96 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
98 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
100 struct amdgpu_ring *ring;
101 struct amd_sched_rq *rq;
102 unsigned long bo_size;
104 const struct common_firmware_header *hdr;
105 unsigned version_major, version_minor, family_id;
108 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
110 switch (adev->asic_type) {
111 #ifdef CONFIG_DRM_AMDGPU_CIK
113 fw_name = FIRMWARE_BONAIRE;
116 fw_name = FIRMWARE_KABINI;
119 fw_name = FIRMWARE_KAVERI;
122 fw_name = FIRMWARE_HAWAII;
125 fw_name = FIRMWARE_MULLINS;
129 fw_name = FIRMWARE_TONGA;
132 fw_name = FIRMWARE_FIJI;
135 fw_name = FIRMWARE_CARRIZO;
138 fw_name = FIRMWARE_STONEY;
141 fw_name = FIRMWARE_POLARIS10;
144 fw_name = FIRMWARE_POLARIS11;
150 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
152 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
157 r = amdgpu_ucode_validate(adev->uvd.fw);
159 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
161 release_firmware(adev->uvd.fw);
166 /* Set the default UVD handles that the firmware can handle */
167 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
169 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
170 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
171 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
172 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
173 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
174 version_major, version_minor, family_id);
177 * Limit the number of UVD handles depending on microcode major
178 * and minor versions. The firmware version which has 40 UVD
179 * instances support is 1.80. So all subsequent versions should
180 * also have the same support.
182 if ((version_major > 0x01) ||
183 ((version_major == 0x01) && (version_minor >= 0x50)))
184 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
186 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
189 if ((adev->asic_type == CHIP_POLARIS10 ||
190 adev->asic_type == CHIP_POLARIS11) &&
191 (adev->uvd.fw_version < FW_1_66_16))
192 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
193 version_major, version_minor);
195 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
196 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
197 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
198 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
199 AMDGPU_GEM_DOMAIN_VRAM,
200 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
201 NULL, NULL, &adev->uvd.vcpu_bo);
203 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
207 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
209 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
210 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
214 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
215 &adev->uvd.gpu_addr);
217 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
218 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
219 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
223 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
225 dev_err(adev->dev, "(%d) UVD map failed\n", r);
229 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
231 ring = &adev->uvd.ring;
232 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
233 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
234 rq, amdgpu_sched_jobs);
236 DRM_ERROR("Failed setting up UVD run queue.\n");
240 for (i = 0; i < adev->uvd.max_handles; ++i) {
241 atomic_set(&adev->uvd.handles[i], 0);
242 adev->uvd.filp[i] = NULL;
245 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
246 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
247 adev->uvd.address_64_bit = true;
252 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
256 kfree(adev->uvd.saved_bo);
258 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
260 if (adev->uvd.vcpu_bo) {
261 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
263 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
264 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
265 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
268 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
271 amdgpu_ring_fini(&adev->uvd.ring);
273 release_firmware(adev->uvd.fw);
278 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
284 if (adev->uvd.vcpu_bo == NULL)
287 for (i = 0; i < adev->uvd.max_handles; ++i)
288 if (atomic_read(&adev->uvd.handles[i]))
291 if (i == AMDGPU_MAX_UVD_HANDLES)
294 cancel_delayed_work_sync(&adev->uvd.idle_work);
296 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
297 ptr = adev->uvd.cpu_addr;
299 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
300 if (!adev->uvd.saved_bo)
303 memcpy(adev->uvd.saved_bo, ptr, size);
308 int amdgpu_uvd_resume(struct amdgpu_device *adev)
313 if (adev->uvd.vcpu_bo == NULL)
316 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
317 ptr = adev->uvd.cpu_addr;
319 if (adev->uvd.saved_bo != NULL) {
320 memcpy(ptr, adev->uvd.saved_bo, size);
321 kfree(adev->uvd.saved_bo);
322 adev->uvd.saved_bo = NULL;
324 const struct common_firmware_header *hdr;
327 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
328 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
329 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
330 (adev->uvd.fw->size) - offset);
331 size -= le32_to_cpu(hdr->ucode_size_bytes);
332 ptr += le32_to_cpu(hdr->ucode_size_bytes);
333 memset(ptr, 0, size);
339 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
341 struct amdgpu_ring *ring = &adev->uvd.ring;
344 for (i = 0; i < adev->uvd.max_handles; ++i) {
345 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
346 if (handle != 0 && adev->uvd.filp[i] == filp) {
349 amdgpu_uvd_note_usage(adev);
351 r = amdgpu_uvd_get_destroy_msg(ring, handle,
354 DRM_ERROR("Error destroying UVD (%d)!\n", r);
358 fence_wait(fence, false);
361 adev->uvd.filp[i] = NULL;
362 atomic_set(&adev->uvd.handles[i], 0);
367 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
370 for (i = 0; i < rbo->placement.num_placement; ++i) {
371 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
372 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
377 * amdgpu_uvd_cs_pass1 - first parsing round
379 * @ctx: UVD parser context
381 * Make sure UVD message and feedback buffers are in VRAM and
382 * nobody is violating an 256MB boundary.
384 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
386 struct amdgpu_bo_va_mapping *mapping;
387 struct amdgpu_bo *bo;
388 uint32_t cmd, lo, hi;
392 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
393 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
394 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
396 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
397 if (mapping == NULL) {
398 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
402 if (!ctx->parser->adev->uvd.address_64_bit) {
403 /* check if it's a message or feedback command */
404 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
405 if (cmd == 0x0 || cmd == 0x3) {
406 /* yes, force it into VRAM */
407 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
408 amdgpu_ttm_placement_from_domain(bo, domain);
410 amdgpu_uvd_force_into_uvd_segment(bo);
412 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
419 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
421 * @msg: pointer to message structure
422 * @buf_sizes: returned buffer sizes
424 * Peek into the decode message and calculate the necessary buffer sizes.
426 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
427 unsigned buf_sizes[])
429 unsigned stream_type = msg[4];
430 unsigned width = msg[6];
431 unsigned height = msg[7];
432 unsigned dpb_size = msg[9];
433 unsigned pitch = msg[28];
434 unsigned level = msg[57];
436 unsigned width_in_mb = width / 16;
437 unsigned height_in_mb = ALIGN(height / 16, 2);
438 unsigned fs_in_mb = width_in_mb * height_in_mb;
440 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
441 unsigned min_ctx_size = 0;
443 image_size = width * height;
444 image_size += image_size / 2;
445 image_size = ALIGN(image_size, 1024);
447 switch (stream_type) {
451 num_dpb_buffer = 8100 / fs_in_mb;
454 num_dpb_buffer = 18000 / fs_in_mb;
457 num_dpb_buffer = 20480 / fs_in_mb;
460 num_dpb_buffer = 32768 / fs_in_mb;
463 num_dpb_buffer = 34816 / fs_in_mb;
466 num_dpb_buffer = 110400 / fs_in_mb;
469 num_dpb_buffer = 184320 / fs_in_mb;
472 num_dpb_buffer = 184320 / fs_in_mb;
476 if (num_dpb_buffer > 17)
479 /* reference picture buffer */
480 min_dpb_size = image_size * num_dpb_buffer;
482 /* macroblock context buffer */
483 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
485 /* IT surface buffer */
486 min_dpb_size += width_in_mb * height_in_mb * 32;
491 /* reference picture buffer */
492 min_dpb_size = image_size * 3;
495 min_dpb_size += width_in_mb * height_in_mb * 128;
497 /* IT surface buffer */
498 min_dpb_size += width_in_mb * 64;
500 /* DB surface buffer */
501 min_dpb_size += width_in_mb * 128;
504 tmp = max(width_in_mb, height_in_mb);
505 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
510 /* reference picture buffer */
511 min_dpb_size = image_size * 3;
516 /* reference picture buffer */
517 min_dpb_size = image_size * 3;
520 min_dpb_size += width_in_mb * height_in_mb * 64;
522 /* IT surface buffer */
523 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
526 case 7: /* H264 Perf */
529 num_dpb_buffer = 8100 / fs_in_mb;
532 num_dpb_buffer = 18000 / fs_in_mb;
535 num_dpb_buffer = 20480 / fs_in_mb;
538 num_dpb_buffer = 32768 / fs_in_mb;
541 num_dpb_buffer = 34816 / fs_in_mb;
544 num_dpb_buffer = 110400 / fs_in_mb;
547 num_dpb_buffer = 184320 / fs_in_mb;
550 num_dpb_buffer = 184320 / fs_in_mb;
554 if (num_dpb_buffer > 17)
557 /* reference picture buffer */
558 min_dpb_size = image_size * num_dpb_buffer;
560 if (adev->asic_type < CHIP_POLARIS10){
561 /* macroblock context buffer */
563 width_in_mb * height_in_mb * num_dpb_buffer * 192;
565 /* IT surface buffer */
566 min_dpb_size += width_in_mb * height_in_mb * 32;
568 /* macroblock context buffer */
570 width_in_mb * height_in_mb * num_dpb_buffer * 192;
575 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
576 image_size = ALIGN(image_size, 256);
578 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
579 min_dpb_size = image_size * num_dpb_buffer;
580 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
581 * 16 * num_dpb_buffer + 52 * 1024;
585 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
590 DRM_ERROR("Invalid UVD decoding target pitch!\n");
594 if (dpb_size < min_dpb_size) {
595 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
596 dpb_size, min_dpb_size);
600 buf_sizes[0x1] = dpb_size;
601 buf_sizes[0x2] = image_size;
602 buf_sizes[0x4] = min_ctx_size;
607 * amdgpu_uvd_cs_msg - handle UVD message
609 * @ctx: UVD parser context
610 * @bo: buffer object containing the message
611 * @offset: offset into the buffer object
613 * Peek into the UVD message and extract the session id.
614 * Make sure that we don't open up to many sessions.
616 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
617 struct amdgpu_bo *bo, unsigned offset)
619 struct amdgpu_device *adev = ctx->parser->adev;
620 int32_t *msg, msg_type, handle;
626 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
630 r = amdgpu_bo_kmap(bo, &ptr);
632 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
642 DRM_ERROR("Invalid UVD handle!\n");
648 /* it's a create msg, calc image size (width * height) */
649 amdgpu_bo_kunmap(bo);
651 /* try to alloc a new handle */
652 for (i = 0; i < adev->uvd.max_handles; ++i) {
653 if (atomic_read(&adev->uvd.handles[i]) == handle) {
654 DRM_ERROR("Handle 0x%x already in use!\n", handle);
658 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
659 adev->uvd.filp[i] = ctx->parser->filp;
664 DRM_ERROR("No more free UVD handles!\n");
668 /* it's a decode msg, calc buffer sizes */
669 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
670 amdgpu_bo_kunmap(bo);
674 /* validate the handle */
675 for (i = 0; i < adev->uvd.max_handles; ++i) {
676 if (atomic_read(&adev->uvd.handles[i]) == handle) {
677 if (adev->uvd.filp[i] != ctx->parser->filp) {
678 DRM_ERROR("UVD handle collision detected!\n");
685 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
689 /* it's a destroy msg, free the handle */
690 for (i = 0; i < adev->uvd.max_handles; ++i)
691 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
692 amdgpu_bo_kunmap(bo);
696 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
704 * amdgpu_uvd_cs_pass2 - second parsing round
706 * @ctx: UVD parser context
708 * Patch buffer addresses, make sure buffer sizes are correct.
710 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
712 struct amdgpu_bo_va_mapping *mapping;
713 struct amdgpu_bo *bo;
714 uint32_t cmd, lo, hi;
719 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
720 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
721 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
723 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
727 start = amdgpu_bo_gpu_offset(bo);
729 end = (mapping->it.last + 1 - mapping->it.start);
730 end = end * AMDGPU_GPU_PAGE_SIZE + start;
732 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
735 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
736 lower_32_bits(start));
737 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
738 upper_32_bits(start));
740 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
742 if ((end - start) < ctx->buf_sizes[cmd]) {
743 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
744 (unsigned)(end - start),
745 ctx->buf_sizes[cmd]);
749 } else if (cmd == 0x206) {
750 if ((end - start) < ctx->buf_sizes[4]) {
751 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
752 (unsigned)(end - start),
756 } else if ((cmd != 0x100) && (cmd != 0x204)) {
757 DRM_ERROR("invalid UVD command %X!\n", cmd);
761 if (!ctx->parser->adev->uvd.address_64_bit) {
762 if ((start >> 28) != ((end - 1) >> 28)) {
763 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
768 if ((cmd == 0 || cmd == 0x3) &&
769 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
770 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
777 ctx->has_msg_cmd = true;
778 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
781 } else if (!ctx->has_msg_cmd) {
782 DRM_ERROR("Message needed before other commands are send!\n");
790 * amdgpu_uvd_cs_reg - parse register writes
792 * @ctx: UVD parser context
793 * @cb: callback function
795 * Parse the register writes, call cb on each complete command.
797 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
798 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
800 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
804 for (i = 0; i <= ctx->count; ++i) {
805 unsigned reg = ctx->reg + i;
807 if (ctx->idx >= ib->length_dw) {
808 DRM_ERROR("Register command after end of CS!\n");
813 case mmUVD_GPCOM_VCPU_DATA0:
814 ctx->data0 = ctx->idx;
816 case mmUVD_GPCOM_VCPU_DATA1:
817 ctx->data1 = ctx->idx;
819 case mmUVD_GPCOM_VCPU_CMD:
824 case mmUVD_ENGINE_CNTL:
827 DRM_ERROR("Invalid reg 0x%X!\n", reg);
836 * amdgpu_uvd_cs_packets - parse UVD packets
838 * @ctx: UVD parser context
839 * @cb: callback function
841 * Parse the command stream packets.
843 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
844 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
846 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
849 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
850 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
851 unsigned type = CP_PACKET_GET_TYPE(cmd);
854 ctx->reg = CP_PACKET0_GET_REG(cmd);
855 ctx->count = CP_PACKET_GET_COUNT(cmd);
856 r = amdgpu_uvd_cs_reg(ctx, cb);
864 DRM_ERROR("Unknown packet type %d !\n", type);
872 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
874 * @parser: Command submission parser context
876 * Parse the command stream, patch in addresses as necessary.
878 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
880 struct amdgpu_uvd_cs_ctx ctx = {};
881 unsigned buf_sizes[] = {
883 [0x00000001] = 0xFFFFFFFF,
884 [0x00000002] = 0xFFFFFFFF,
886 [0x00000004] = 0xFFFFFFFF,
888 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
891 if (ib->length_dw % 16) {
892 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
898 ctx.buf_sizes = buf_sizes;
901 /* first round, make sure the buffers are actually in the UVD segment */
902 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
906 /* second round, patch buffer addresses into the command stream */
907 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
911 if (!ctx.has_msg_cmd) {
912 DRM_ERROR("UVD-IBs need a msg command!\n");
916 amdgpu_uvd_note_usage(ctx.parser->adev);
921 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
922 bool direct, struct fence **fence)
924 struct ttm_validate_buffer tv;
925 struct ww_acquire_ctx ticket;
926 struct list_head head;
927 struct amdgpu_job *job;
928 struct amdgpu_ib *ib;
929 struct fence *f = NULL;
930 struct amdgpu_device *adev = ring->adev;
934 memset(&tv, 0, sizeof(tv));
937 INIT_LIST_HEAD(&head);
938 list_add(&tv.head, &head);
940 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
944 if (!bo->adev->uvd.address_64_bit) {
945 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
946 amdgpu_uvd_force_into_uvd_segment(bo);
949 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
953 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
958 addr = amdgpu_bo_gpu_offset(bo);
959 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
961 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
962 ib->ptr[3] = addr >> 32;
963 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
965 for (i = 6; i < 16; ++i)
966 ib->ptr[i] = PACKET2(0);
970 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
971 job->fence = fence_get(f);
975 amdgpu_job_free(job);
977 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
978 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
983 ttm_eu_fence_buffer_objects(&ticket, &head, f);
986 *fence = fence_get(f);
987 amdgpu_bo_unref(&bo);
993 amdgpu_job_free(job);
996 ttm_eu_backoff_reservation(&ticket, &head);
1000 /* multiple fence commands without any stream commands in between can
1001 crash the vcpu so just try to emmit a dummy create/destroy msg to
1003 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1004 struct fence **fence)
1006 struct amdgpu_device *adev = ring->adev;
1007 struct amdgpu_bo *bo;
1011 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1012 AMDGPU_GEM_DOMAIN_VRAM,
1013 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1018 r = amdgpu_bo_reserve(bo, false);
1020 amdgpu_bo_unref(&bo);
1024 r = amdgpu_bo_kmap(bo, (void **)&msg);
1026 amdgpu_bo_unreserve(bo);
1027 amdgpu_bo_unref(&bo);
1031 /* stitch together an UVD create msg */
1032 msg[0] = cpu_to_le32(0x00000de4);
1033 msg[1] = cpu_to_le32(0x00000000);
1034 msg[2] = cpu_to_le32(handle);
1035 msg[3] = cpu_to_le32(0x00000000);
1036 msg[4] = cpu_to_le32(0x00000000);
1037 msg[5] = cpu_to_le32(0x00000000);
1038 msg[6] = cpu_to_le32(0x00000000);
1039 msg[7] = cpu_to_le32(0x00000780);
1040 msg[8] = cpu_to_le32(0x00000440);
1041 msg[9] = cpu_to_le32(0x00000000);
1042 msg[10] = cpu_to_le32(0x01b37000);
1043 for (i = 11; i < 1024; ++i)
1044 msg[i] = cpu_to_le32(0x0);
1046 amdgpu_bo_kunmap(bo);
1047 amdgpu_bo_unreserve(bo);
1049 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1052 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1053 bool direct, struct fence **fence)
1055 struct amdgpu_device *adev = ring->adev;
1056 struct amdgpu_bo *bo;
1060 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1061 AMDGPU_GEM_DOMAIN_VRAM,
1062 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1067 r = amdgpu_bo_reserve(bo, false);
1069 amdgpu_bo_unref(&bo);
1073 r = amdgpu_bo_kmap(bo, (void **)&msg);
1075 amdgpu_bo_unreserve(bo);
1076 amdgpu_bo_unref(&bo);
1080 /* stitch together an UVD destroy msg */
1081 msg[0] = cpu_to_le32(0x00000de4);
1082 msg[1] = cpu_to_le32(0x00000002);
1083 msg[2] = cpu_to_le32(handle);
1084 msg[3] = cpu_to_le32(0x00000000);
1085 for (i = 4; i < 1024; ++i)
1086 msg[i] = cpu_to_le32(0x0);
1088 amdgpu_bo_kunmap(bo);
1089 amdgpu_bo_unreserve(bo);
1091 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1094 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1096 struct amdgpu_device *adev =
1097 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1098 unsigned i, fences, handles = 0;
1100 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1102 for (i = 0; i < adev->uvd.max_handles; ++i)
1103 if (atomic_read(&adev->uvd.handles[i]))
1106 if (fences == 0 && handles == 0) {
1107 if (adev->pm.dpm_enabled) {
1108 amdgpu_dpm_enable_uvd(adev, false);
1109 /* just work around for uvd clock remain high even
1110 * when uvd dpm disabled on Polaris10 */
1111 if (adev->asic_type == CHIP_POLARIS10)
1112 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1114 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1117 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1121 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1123 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1124 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1128 if (adev->pm.dpm_enabled) {
1129 amdgpu_dpm_enable_uvd(adev, true);
1131 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);