2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/hmm.h>
36 #include <linux/pagemap.h>
37 #include <linux/sched/task.h>
38 #include <linux/sched/mm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/swiotlb.h>
43 #include <linux/dma-buf.h>
44 #include <linux/sizes.h>
46 #include <drm/ttm/ttm_bo_api.h>
47 #include <drm/ttm/ttm_bo_driver.h>
48 #include <drm/ttm/ttm_placement.h>
49 #include <drm/ttm/ttm_module.h>
50 #include <drm/ttm/ttm_page_alloc.h>
52 #include <drm/drm_debugfs.h>
53 #include <drm/amdgpu_drm.h>
56 #include "amdgpu_object.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_sdma.h"
60 #include "amdgpu_ras.h"
61 #include "bif/bif_4_1_d.h"
63 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
67 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
70 * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
71 * @type: The type of memory requested
72 * @man: The memory type manager for each domain
74 * This is called by ttm_bo_init_mm() when a buffer object is being
77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
78 struct ttm_mem_type_manager *man)
80 struct amdgpu_device *adev;
82 adev = amdgpu_ttm_adev(bdev);
87 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
88 man->available_caching = TTM_PL_MASK_CACHING;
89 man->default_caching = TTM_PL_FLAG_CACHED;
93 man->func = &amdgpu_gtt_mgr_func;
94 man->gpu_offset = adev->gmc.gart_start;
95 man->available_caching = TTM_PL_MASK_CACHING;
96 man->default_caching = TTM_PL_FLAG_CACHED;
97 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
100 /* "On-card" video ram */
101 man->func = &amdgpu_vram_mgr_func;
102 man->gpu_offset = adev->gmc.vram_start;
103 man->flags = TTM_MEMTYPE_FLAG_FIXED |
104 TTM_MEMTYPE_FLAG_MAPPABLE;
105 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
106 man->default_caching = TTM_PL_FLAG_WC;
111 /* On-chip GDS memory*/
112 man->func = &ttm_bo_manager_func;
114 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
115 man->available_caching = TTM_PL_FLAG_UNCACHED;
116 man->default_caching = TTM_PL_FLAG_UNCACHED;
119 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
126 * amdgpu_evict_flags - Compute placement flags
128 * @bo: The buffer object to evict
129 * @placement: Possible destination(s) for evicted BO
131 * Fill in placement data when ttm_bo_evict() is called
133 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
134 struct ttm_placement *placement)
136 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
137 struct amdgpu_bo *abo;
138 static const struct ttm_place placements = {
141 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
144 /* Don't handle scatter gather BOs */
145 if (bo->type == ttm_bo_type_sg) {
146 placement->num_placement = 0;
147 placement->num_busy_placement = 0;
151 /* Object isn't an AMDGPU object so ignore */
152 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
153 placement->placement = &placements;
154 placement->busy_placement = &placements;
155 placement->num_placement = 1;
156 placement->num_busy_placement = 1;
160 abo = ttm_to_amdgpu_bo(bo);
161 switch (bo->mem.mem_type) {
165 placement->num_placement = 0;
166 placement->num_busy_placement = 0;
170 if (!adev->mman.buffer_funcs_enabled) {
171 /* Move to system memory */
172 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
173 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
174 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
175 amdgpu_bo_in_cpu_visible_vram(abo)) {
177 /* Try evicting to the CPU inaccessible part of VRAM
178 * first, but only set GTT as busy placement, so this
179 * BO will be evicted to GTT rather than causing other
180 * BOs to be evicted from VRAM
182 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
183 AMDGPU_GEM_DOMAIN_GTT);
184 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
185 abo->placements[0].lpfn = 0;
186 abo->placement.busy_placement = &abo->placements[1];
187 abo->placement.num_busy_placement = 1;
189 /* Move to GTT memory */
190 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
195 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
198 *placement = abo->placement;
202 * amdgpu_verify_access - Verify access for a mmap call
204 * @bo: The buffer object to map
205 * @filp: The file pointer from the process performing the mmap
207 * This is called by ttm_bo_mmap() to verify whether a process
208 * has the right to mmap a BO to their process space.
210 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
212 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
215 * Don't verify access for KFD BOs. They don't have a GEM
216 * object associated with them.
221 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
223 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
228 * amdgpu_move_null - Register memory for a buffer object
230 * @bo: The bo to assign the memory to
231 * @new_mem: The memory to be assigned.
233 * Assign the memory from new_mem to the memory of the buffer object bo.
235 static void amdgpu_move_null(struct ttm_buffer_object *bo,
236 struct ttm_mem_reg *new_mem)
238 struct ttm_mem_reg *old_mem = &bo->mem;
240 BUG_ON(old_mem->mm_node != NULL);
242 new_mem->mm_node = NULL;
246 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
248 * @bo: The bo to assign the memory to.
249 * @mm_node: Memory manager node for drm allocator.
250 * @mem: The region where the bo resides.
253 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
254 struct drm_mm_node *mm_node,
255 struct ttm_mem_reg *mem)
259 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
260 addr = mm_node->start << PAGE_SHIFT;
261 addr += bo->bdev->man[mem->mem_type].gpu_offset;
267 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
268 * @offset. It also modifies the offset to be within the drm_mm_node returned
270 * @mem: The region where the bo resides.
271 * @offset: The offset that drm_mm_node is used for finding.
274 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
277 struct drm_mm_node *mm_node = mem->mm_node;
279 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
280 *offset -= (mm_node->size << PAGE_SHIFT);
287 * amdgpu_ttm_map_buffer - Map memory into the GART windows
288 * @bo: buffer object to map
289 * @mem: memory object to map
290 * @mm_node: drm_mm node object to map
291 * @num_pages: number of pages to map
292 * @offset: offset into @mm_node where to start
293 * @window: which GART window to use
294 * @ring: DMA ring to use for the copy
295 * @tmz: if we should setup a TMZ enabled mapping
296 * @addr: resulting address inside the MC address space
298 * Setup one of the GART windows to access a specific piece of memory or return
299 * the physical address for local memory.
301 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
302 struct ttm_mem_reg *mem,
303 struct drm_mm_node *mm_node,
304 unsigned num_pages, uint64_t offset,
305 unsigned window, struct amdgpu_ring *ring,
306 bool tmz, uint64_t *addr)
308 struct amdgpu_device *adev = ring->adev;
309 struct amdgpu_job *job;
310 unsigned num_dw, num_bytes;
311 struct dma_fence *fence;
312 uint64_t src_addr, dst_addr;
318 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
319 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
321 /* Map only what can't be accessed directly */
322 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
323 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
327 *addr = adev->gmc.gart_start;
328 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
329 AMDGPU_GPU_PAGE_SIZE;
330 *addr += offset & ~PAGE_MASK;
332 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
333 num_bytes = num_pages * 8;
335 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
336 AMDGPU_IB_POOL_DELAYED, &job);
340 src_addr = num_dw * 4;
341 src_addr += job->ibs[0].gpu_addr;
343 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
344 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
345 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
346 dst_addr, num_bytes, false);
348 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
349 WARN_ON(job->ibs[0].length_dw > num_dw);
351 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
353 flags |= AMDGPU_PTE_TMZ;
355 cpu_addr = &job->ibs[0].ptr[num_dw];
357 if (mem->mem_type == TTM_PL_TT) {
358 struct ttm_dma_tt *dma;
359 dma_addr_t *dma_address;
361 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
362 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
363 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
368 dma_addr_t dma_address;
370 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
371 dma_address += adev->vm_manager.vram_base_offset;
373 for (i = 0; i < num_pages; ++i) {
374 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
375 &dma_address, flags, cpu_addr);
379 dma_address += PAGE_SIZE;
383 r = amdgpu_job_submit(job, &adev->mman.entity,
384 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
388 dma_fence_put(fence);
393 amdgpu_job_free(job);
398 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
399 * @adev: amdgpu device
400 * @src: buffer/address where to read from
401 * @dst: buffer/address where to write to
402 * @size: number of bytes to copy
403 * @tmz: if a secure copy should be used
404 * @resv: resv object to sync to
405 * @f: Returns the last fence if multiple jobs are submitted.
407 * The function copies @size bytes from {src->mem + src->offset} to
408 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
409 * move and different for a BO to BO copy.
412 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
413 const struct amdgpu_copy_mem *src,
414 const struct amdgpu_copy_mem *dst,
415 uint64_t size, bool tmz,
416 struct dma_resv *resv,
417 struct dma_fence **f)
419 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
420 AMDGPU_GPU_PAGE_SIZE);
422 uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
423 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
424 struct drm_mm_node *src_mm, *dst_mm;
425 struct dma_fence *fence = NULL;
428 if (!adev->mman.buffer_funcs_enabled) {
429 DRM_ERROR("Trying to move memory with ring turned off.\n");
433 src_offset = src->offset;
434 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
435 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
437 dst_offset = dst->offset;
438 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
439 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
441 mutex_lock(&adev->mman.gtt_window_lock);
444 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
445 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
446 struct dma_fence *next;
450 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
451 * begins at an offset, then adjust the size accordingly
453 cur_size = max(src_page_offset, dst_page_offset);
454 cur_size = min(min3(src_node_size, dst_node_size, size),
455 (uint64_t)(GTT_MAX_BYTES - cur_size));
457 /* Map src to window 0 and dst to window 1. */
458 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
459 PFN_UP(cur_size + src_page_offset),
460 src_offset, 0, ring, tmz, &from);
464 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
465 PFN_UP(cur_size + dst_page_offset),
466 dst_offset, 1, ring, tmz, &to);
470 r = amdgpu_copy_buffer(ring, from, to, cur_size,
471 resv, &next, false, true, tmz);
475 dma_fence_put(fence);
482 src_node_size -= cur_size;
483 if (!src_node_size) {
485 src_node_size = src_mm->size << PAGE_SHIFT;
488 src_offset += cur_size;
491 dst_node_size -= cur_size;
492 if (!dst_node_size) {
494 dst_node_size = dst_mm->size << PAGE_SHIFT;
497 dst_offset += cur_size;
501 mutex_unlock(&adev->mman.gtt_window_lock);
503 *f = dma_fence_get(fence);
504 dma_fence_put(fence);
509 * amdgpu_move_blit - Copy an entire buffer to another buffer
511 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
512 * help move buffers to and from VRAM.
514 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
515 bool evict, bool no_wait_gpu,
516 struct ttm_mem_reg *new_mem,
517 struct ttm_mem_reg *old_mem)
519 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
520 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
521 struct amdgpu_copy_mem src, dst;
522 struct dma_fence *fence = NULL;
532 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
533 new_mem->num_pages << PAGE_SHIFT,
534 amdgpu_bo_encrypted(abo),
535 bo->base.resv, &fence);
539 /* clear the space being freed */
540 if (old_mem->mem_type == TTM_PL_VRAM &&
541 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
542 struct dma_fence *wipe_fence = NULL;
544 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
548 } else if (wipe_fence) {
549 dma_fence_put(fence);
554 /* Always block for VM page tables before committing the new location */
555 if (bo->type == ttm_bo_type_kernel)
556 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
558 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
559 dma_fence_put(fence);
564 dma_fence_wait(fence, false);
565 dma_fence_put(fence);
570 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
572 * Called by amdgpu_bo_move().
574 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
575 struct ttm_operation_ctx *ctx,
576 struct ttm_mem_reg *new_mem)
578 struct ttm_mem_reg *old_mem = &bo->mem;
579 struct ttm_mem_reg tmp_mem;
580 struct ttm_place placements;
581 struct ttm_placement placement;
584 /* create space/pages for new_mem in GTT space */
586 tmp_mem.mm_node = NULL;
587 placement.num_placement = 1;
588 placement.placement = &placements;
589 placement.num_busy_placement = 1;
590 placement.busy_placement = &placements;
593 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
594 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
596 pr_err("Failed to find GTT space for blit from VRAM\n");
600 /* set caching flags */
601 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
606 /* Bind the memory to the GTT space */
607 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
612 /* blit VRAM to GTT */
613 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
618 /* move BO (in tmp_mem) to new_mem */
619 r = ttm_bo_move_ttm(bo, ctx, new_mem);
621 ttm_bo_mem_put(bo, &tmp_mem);
626 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
628 * Called by amdgpu_bo_move().
630 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
631 struct ttm_operation_ctx *ctx,
632 struct ttm_mem_reg *new_mem)
634 struct ttm_mem_reg *old_mem = &bo->mem;
635 struct ttm_mem_reg tmp_mem;
636 struct ttm_placement placement;
637 struct ttm_place placements;
640 /* make space in GTT for old_mem buffer */
642 tmp_mem.mm_node = NULL;
643 placement.num_placement = 1;
644 placement.placement = &placements;
645 placement.num_busy_placement = 1;
646 placement.busy_placement = &placements;
649 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
650 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
652 pr_err("Failed to find GTT space for blit to VRAM\n");
656 /* move/bind old memory to GTT space */
657 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
663 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
668 ttm_bo_mem_put(bo, &tmp_mem);
673 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
675 * Called by amdgpu_bo_move()
677 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
678 struct ttm_mem_reg *mem)
680 struct drm_mm_node *nodes = mem->mm_node;
682 if (mem->mem_type == TTM_PL_SYSTEM ||
683 mem->mem_type == TTM_PL_TT)
685 if (mem->mem_type != TTM_PL_VRAM)
688 /* ttm_mem_reg_ioremap only supports contiguous memory */
689 if (nodes->size != mem->num_pages)
692 return ((nodes->start + nodes->size) << PAGE_SHIFT)
693 <= adev->gmc.visible_vram_size;
697 * amdgpu_bo_move - Move a buffer object to a new memory location
699 * Called by ttm_bo_handle_move_mem()
701 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
702 struct ttm_operation_ctx *ctx,
703 struct ttm_mem_reg *new_mem)
705 struct amdgpu_device *adev;
706 struct amdgpu_bo *abo;
707 struct ttm_mem_reg *old_mem = &bo->mem;
710 /* Can't move a pinned BO */
711 abo = ttm_to_amdgpu_bo(bo);
712 if (WARN_ON_ONCE(abo->pin_count > 0))
715 adev = amdgpu_ttm_adev(bo->bdev);
717 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
718 amdgpu_move_null(bo, new_mem);
721 if ((old_mem->mem_type == TTM_PL_TT &&
722 new_mem->mem_type == TTM_PL_SYSTEM) ||
723 (old_mem->mem_type == TTM_PL_SYSTEM &&
724 new_mem->mem_type == TTM_PL_TT)) {
726 amdgpu_move_null(bo, new_mem);
729 if (old_mem->mem_type == AMDGPU_PL_GDS ||
730 old_mem->mem_type == AMDGPU_PL_GWS ||
731 old_mem->mem_type == AMDGPU_PL_OA ||
732 new_mem->mem_type == AMDGPU_PL_GDS ||
733 new_mem->mem_type == AMDGPU_PL_GWS ||
734 new_mem->mem_type == AMDGPU_PL_OA) {
735 /* Nothing to save here */
736 amdgpu_move_null(bo, new_mem);
740 if (!adev->mman.buffer_funcs_enabled) {
745 if (old_mem->mem_type == TTM_PL_VRAM &&
746 new_mem->mem_type == TTM_PL_SYSTEM) {
747 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
748 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
749 new_mem->mem_type == TTM_PL_VRAM) {
750 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
752 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
758 /* Check that all memory is CPU accessible */
759 if (!amdgpu_mem_visible(adev, old_mem) ||
760 !amdgpu_mem_visible(adev, new_mem)) {
761 pr_err("Move buffer fallback to memcpy unavailable\n");
765 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
770 if (bo->type == ttm_bo_type_device &&
771 new_mem->mem_type == TTM_PL_VRAM &&
772 old_mem->mem_type != TTM_PL_VRAM) {
773 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
774 * accesses the BO after it's moved.
776 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
779 /* update statistics */
780 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
785 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
787 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
789 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
791 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
792 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
793 struct drm_mm_node *mm_node = mem->mm_node;
795 mem->bus.addr = NULL;
797 mem->bus.size = mem->num_pages << PAGE_SHIFT;
799 mem->bus.is_iomem = false;
800 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
802 switch (mem->mem_type) {
809 mem->bus.offset = mem->start << PAGE_SHIFT;
810 /* check if it's visible */
811 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
813 /* Only physically contiguous buffers apply. In a contiguous
814 * buffer, size of the first mm_node would match the number of
815 * pages in ttm_mem_reg.
817 if (adev->mman.aper_base_kaddr &&
818 (mm_node->size == mem->num_pages))
819 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
822 mem->bus.base = adev->gmc.aper_base;
823 mem->bus.is_iomem = true;
831 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
835 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
836 unsigned long page_offset)
838 uint64_t offset = (page_offset << PAGE_SHIFT);
839 struct drm_mm_node *mm;
841 mm = amdgpu_find_mm_node(&bo->mem, &offset);
842 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
843 (offset >> PAGE_SHIFT);
847 * TTM backend functions.
849 struct amdgpu_ttm_tt {
850 struct ttm_dma_tt ttm;
851 struct drm_gem_object *gobj;
854 struct task_struct *usertask;
856 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
857 struct hmm_range *range;
861 #ifdef CONFIG_DRM_AMDGPU_USERPTR
862 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
863 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
864 (1 << 0), /* HMM_PFN_VALID */
865 (1 << 1), /* HMM_PFN_WRITE */
868 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
869 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
870 0, /* HMM_PFN_NONE */
871 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
875 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
876 * memory and start HMM tracking CPU page table update
878 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
879 * once afterwards to stop HMM tracking
881 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
883 struct ttm_tt *ttm = bo->tbo.ttm;
884 struct amdgpu_ttm_tt *gtt = (void *)ttm;
885 unsigned long start = gtt->userptr;
886 struct vm_area_struct *vma;
887 struct hmm_range *range;
888 unsigned long timeout;
889 struct mm_struct *mm;
893 mm = bo->notifier.mm;
895 DRM_DEBUG_DRIVER("BO is not registered?\n");
899 /* Another get_user_pages is running at the same time?? */
900 if (WARN_ON(gtt->range))
903 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
906 range = kzalloc(sizeof(*range), GFP_KERNEL);
907 if (unlikely(!range)) {
911 range->notifier = &bo->notifier;
912 range->flags = hmm_range_flags;
913 range->values = hmm_range_values;
914 range->pfn_shift = PAGE_SHIFT;
915 range->start = bo->notifier.interval_tree.start;
916 range->end = bo->notifier.interval_tree.last + 1;
917 range->default_flags = hmm_range_flags[HMM_PFN_VALID];
918 if (!amdgpu_ttm_tt_is_readonly(ttm))
919 range->default_flags |= range->flags[HMM_PFN_WRITE];
921 range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
923 if (unlikely(!range->pfns)) {
925 goto out_free_ranges;
928 down_read(&mm->mmap_sem);
929 vma = find_vma(mm, start);
930 if (unlikely(!vma || start < vma->vm_start)) {
934 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
939 up_read(&mm->mmap_sem);
940 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
943 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
945 down_read(&mm->mmap_sem);
946 r = hmm_range_fault(range);
947 up_read(&mm->mmap_sem);
948 if (unlikely(r <= 0)) {
950 * FIXME: This timeout should encompass the retry from
951 * mmu_interval_read_retry() as well.
953 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
958 for (i = 0; i < ttm->num_pages; i++) {
959 /* FIXME: The pages cannot be touched outside the notifier_lock */
960 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
961 if (unlikely(!pages[i])) {
962 pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
976 up_read(&mm->mmap_sem);
987 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
988 * Check if the pages backing this ttm range have been invalidated
990 * Returns: true if pages are still valid
992 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
994 struct amdgpu_ttm_tt *gtt = (void *)ttm;
997 if (!gtt || !gtt->userptr)
1000 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1001 gtt->userptr, ttm->num_pages);
1003 WARN_ONCE(!gtt->range || !gtt->range->pfns,
1004 "No user pages to check\n");
1008 * FIXME: Must always hold notifier_lock for this, and must
1009 * not ignore the return code.
1011 r = mmu_interval_read_retry(gtt->range->notifier,
1012 gtt->range->notifier_seq);
1013 kvfree(gtt->range->pfns);
1023 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1025 * Called by amdgpu_cs_list_validate(). This creates the page list
1026 * that backs user memory and will ultimately be mapped into the device
1029 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1033 for (i = 0; i < ttm->num_pages; ++i)
1034 ttm->pages[i] = pages ? pages[i] : NULL;
1038 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
1040 * Called by amdgpu_ttm_backend_bind()
1042 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1044 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1045 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1049 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1050 enum dma_data_direction direction = write ?
1051 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1053 /* Allocate an SG array and squash pages into it */
1054 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1055 ttm->num_pages << PAGE_SHIFT,
1060 /* Map SG to device */
1062 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1066 /* convert SG to linear array of pages and dma addresses */
1067 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1068 gtt->ttm.dma_address, ttm->num_pages);
1078 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1080 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1082 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1083 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1085 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1086 enum dma_data_direction direction = write ?
1087 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1089 /* double check that we don't free the table twice */
1093 /* unmap the pages mapped to the device */
1094 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1096 sg_free_table(ttm->sg);
1098 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1102 for (i = 0; i < ttm->num_pages; i++) {
1103 if (ttm->pages[i] !=
1104 hmm_device_entry_to_page(gtt->range,
1105 gtt->range->pfns[i]))
1109 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1114 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1115 struct ttm_buffer_object *tbo,
1118 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1119 struct ttm_tt *ttm = tbo->ttm;
1120 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1123 if (amdgpu_bo_encrypted(abo))
1124 flags |= AMDGPU_PTE_TMZ;
1126 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1127 uint64_t page_idx = 1;
1129 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1130 ttm->pages, gtt->ttm.dma_address, flags);
1132 goto gart_bind_fail;
1134 /* The memory type of the first page defaults to UC. Now
1135 * modify the memory type to NC from the second page of
1138 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1139 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1141 r = amdgpu_gart_bind(adev,
1142 gtt->offset + (page_idx << PAGE_SHIFT),
1143 ttm->num_pages - page_idx,
1144 &ttm->pages[page_idx],
1145 &(gtt->ttm.dma_address[page_idx]), flags);
1147 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1148 ttm->pages, gtt->ttm.dma_address, flags);
1153 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1154 ttm->num_pages, gtt->offset);
1160 * amdgpu_ttm_backend_bind - Bind GTT memory
1162 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1163 * This handles binding GTT memory to the device address space.
1165 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1166 struct ttm_mem_reg *bo_mem)
1168 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1169 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1174 r = amdgpu_ttm_tt_pin_userptr(ttm);
1176 DRM_ERROR("failed to pin userptr\n");
1180 if (!ttm->num_pages) {
1181 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1182 ttm->num_pages, bo_mem, ttm);
1185 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1186 bo_mem->mem_type == AMDGPU_PL_GWS ||
1187 bo_mem->mem_type == AMDGPU_PL_OA)
1190 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1191 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1195 /* compute PTE flags relevant to this BO memory */
1196 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1198 /* bind pages into GART page tables */
1199 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1200 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1201 ttm->pages, gtt->ttm.dma_address, flags);
1204 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1205 ttm->num_pages, gtt->offset);
1210 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1212 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1214 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1215 struct ttm_operation_ctx ctx = { false, false };
1216 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1217 struct ttm_mem_reg tmp;
1218 struct ttm_placement placement;
1219 struct ttm_place placements;
1220 uint64_t addr, flags;
1223 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1226 addr = amdgpu_gmc_agp_addr(bo);
1227 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1228 bo->mem.start = addr >> PAGE_SHIFT;
1231 /* allocate GART space */
1234 placement.num_placement = 1;
1235 placement.placement = &placements;
1236 placement.num_busy_placement = 1;
1237 placement.busy_placement = &placements;
1238 placements.fpfn = 0;
1239 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1240 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1243 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1247 /* compute PTE flags for this buffer object */
1248 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1251 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1252 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1254 ttm_bo_mem_put(bo, &tmp);
1258 ttm_bo_mem_put(bo, &bo->mem);
1262 bo->offset = (bo->mem.start << PAGE_SHIFT) +
1263 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1269 * amdgpu_ttm_recover_gart - Rebind GTT pages
1271 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1272 * rebind GTT pages during a GPU reset.
1274 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1276 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1283 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1284 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1290 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1292 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1295 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1297 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1298 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1301 /* if the pages have userptr pinning then clear that first */
1303 amdgpu_ttm_tt_unpin_userptr(ttm);
1305 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1308 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1309 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1311 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1312 gtt->ttm.ttm.num_pages, gtt->offset);
1316 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1318 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1321 put_task_struct(gtt->usertask);
1323 ttm_dma_tt_fini(>t->ttm);
1327 static struct ttm_backend_func amdgpu_backend_func = {
1328 .bind = &amdgpu_ttm_backend_bind,
1329 .unbind = &amdgpu_ttm_backend_unbind,
1330 .destroy = &amdgpu_ttm_backend_destroy,
1334 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1336 * @bo: The buffer object to create a GTT ttm_tt object around
1338 * Called by ttm_tt_create().
1340 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1341 uint32_t page_flags)
1343 struct amdgpu_ttm_tt *gtt;
1345 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1349 gtt->ttm.ttm.func = &amdgpu_backend_func;
1350 gtt->gobj = &bo->base;
1352 /* allocate space for the uninitialized page entries */
1353 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) {
1357 return >t->ttm.ttm;
1361 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1363 * Map the pages of a ttm_tt object to an address space visible
1364 * to the underlying device.
1366 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1367 struct ttm_operation_ctx *ctx)
1369 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1370 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1372 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1373 if (gtt && gtt->userptr) {
1374 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1378 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1379 ttm->state = tt_unbound;
1383 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1385 struct dma_buf_attachment *attach;
1386 struct sg_table *sgt;
1388 attach = gtt->gobj->import_attach;
1389 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1391 return PTR_ERR(sgt);
1396 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1397 gtt->ttm.dma_address,
1399 ttm->state = tt_unbound;
1403 #ifdef CONFIG_SWIOTLB
1404 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1405 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1409 /* fall back to generic helper to populate the page array
1410 * and map them to the device */
1411 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1415 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1417 * Unmaps pages of a ttm_tt object from the device address space and
1418 * unpopulates the page array backing it.
1420 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1422 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1423 struct amdgpu_device *adev;
1425 if (gtt && gtt->userptr) {
1426 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1428 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1432 if (ttm->sg && gtt->gobj->import_attach) {
1433 struct dma_buf_attachment *attach;
1435 attach = gtt->gobj->import_attach;
1436 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1441 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1444 adev = amdgpu_ttm_adev(ttm->bdev);
1446 #ifdef CONFIG_SWIOTLB
1447 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1448 ttm_dma_unpopulate(>t->ttm, adev->dev);
1453 /* fall back to generic helper to unmap and unpopulate array */
1454 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1458 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1461 * @ttm: The ttm_tt object to bind this userptr object to
1462 * @addr: The address in the current tasks VM space to use
1463 * @flags: Requirements of userptr object.
1465 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1468 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1471 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1476 gtt->userptr = addr;
1477 gtt->userflags = flags;
1480 put_task_struct(gtt->usertask);
1481 gtt->usertask = current->group_leader;
1482 get_task_struct(gtt->usertask);
1488 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1490 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1492 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1497 if (gtt->usertask == NULL)
1500 return gtt->usertask->mm;
1504 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1505 * address range for the current task.
1508 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1511 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1514 if (gtt == NULL || !gtt->userptr)
1517 /* Return false if no part of the ttm_tt object lies within
1520 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1521 if (gtt->userptr > end || gtt->userptr + size <= start)
1528 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1530 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1532 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1534 if (gtt == NULL || !gtt->userptr)
1541 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1543 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1545 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1550 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1554 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1556 * @ttm: The ttm_tt object to compute the flags for
1557 * @mem: The memory registry backing this ttm_tt object
1559 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1561 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1565 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1566 flags |= AMDGPU_PTE_VALID;
1568 if (mem && mem->mem_type == TTM_PL_TT) {
1569 flags |= AMDGPU_PTE_SYSTEM;
1571 if (ttm->caching_state == tt_cached)
1572 flags |= AMDGPU_PTE_SNOOPED;
1579 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1581 * @ttm: The ttm_tt object to compute the flags for
1582 * @mem: The memory registry backing this ttm_tt object
1584 * Figure out the flags to use for a VM PTE (Page Table Entry).
1586 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1587 struct ttm_mem_reg *mem)
1589 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1591 flags |= adev->gart.gart_pte_flags;
1592 flags |= AMDGPU_PTE_READABLE;
1594 if (!amdgpu_ttm_tt_is_readonly(ttm))
1595 flags |= AMDGPU_PTE_WRITEABLE;
1601 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1604 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1605 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1606 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1607 * used to clean out a memory space.
1609 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1610 const struct ttm_place *place)
1612 unsigned long num_pages = bo->mem.num_pages;
1613 struct drm_mm_node *node = bo->mem.mm_node;
1614 struct dma_resv_list *flist;
1615 struct dma_fence *f;
1618 if (bo->type == ttm_bo_type_kernel &&
1619 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1622 /* If bo is a KFD BO, check if the bo belongs to the current process.
1623 * If true, then return false as any KFD process needs all its BOs to
1624 * be resident to run successfully
1626 flist = dma_resv_get_list(bo->base.resv);
1628 for (i = 0; i < flist->shared_count; ++i) {
1629 f = rcu_dereference_protected(flist->shared[i],
1630 dma_resv_held(bo->base.resv));
1631 if (amdkfd_fence_check_mm(f, current->mm))
1636 switch (bo->mem.mem_type) {
1638 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1639 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1644 /* Check each drm MM node individually */
1646 if (place->fpfn < (node->start + node->size) &&
1647 !(place->lpfn && place->lpfn <= node->start))
1650 num_pages -= node->size;
1659 return ttm_bo_eviction_valuable(bo, place);
1663 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1665 * @bo: The buffer object to read/write
1666 * @offset: Offset into buffer object
1667 * @buf: Secondary buffer to write/read from
1668 * @len: Length in bytes of access
1669 * @write: true if writing
1671 * This is used to access VRAM that backs a buffer object via MMIO
1672 * access for debugging purposes.
1674 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1675 unsigned long offset,
1676 void *buf, int len, int write)
1678 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1679 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1680 struct drm_mm_node *nodes;
1684 unsigned long flags;
1686 if (bo->mem.mem_type != TTM_PL_VRAM)
1690 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1691 pos += (nodes->start << PAGE_SHIFT);
1693 while (len && pos < adev->gmc.mc_vram_size) {
1694 uint64_t aligned_pos = pos & ~(uint64_t)3;
1695 uint64_t bytes = 4 - (pos & 3);
1696 uint32_t shift = (pos & 3) * 8;
1697 uint32_t mask = 0xffffffff << shift;
1700 mask &= 0xffffffff >> (bytes - len) * 8;
1704 if (mask != 0xffffffff) {
1705 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1706 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1707 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1708 if (!write || mask != 0xffffffff)
1709 value = RREG32_NO_KIQ(mmMM_DATA);
1712 value |= (*(uint32_t *)buf << shift) & mask;
1713 WREG32_NO_KIQ(mmMM_DATA, value);
1715 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1717 value = (value & mask) >> shift;
1718 memcpy(buf, &value, bytes);
1721 bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1722 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1724 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1729 buf = (uint8_t *)buf + bytes;
1732 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1734 pos = (nodes->start << PAGE_SHIFT);
1741 static struct ttm_bo_driver amdgpu_bo_driver = {
1742 .ttm_tt_create = &amdgpu_ttm_tt_create,
1743 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1744 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1745 .init_mem_type = &amdgpu_init_mem_type,
1746 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1747 .evict_flags = &amdgpu_evict_flags,
1748 .move = &amdgpu_bo_move,
1749 .verify_access = &amdgpu_verify_access,
1750 .move_notify = &amdgpu_bo_move_notify,
1751 .release_notify = &amdgpu_bo_release_notify,
1752 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1753 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1754 .io_mem_free = &amdgpu_ttm_io_mem_free,
1755 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1756 .access_memory = &amdgpu_ttm_access_memory,
1757 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1761 * Firmware Reservation functions
1764 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1766 * @adev: amdgpu_device pointer
1768 * free fw reserved vram if it has been reserved.
1770 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1772 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1773 NULL, &adev->fw_vram_usage.va);
1777 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1779 * @adev: amdgpu_device pointer
1781 * create bo vram reservation from fw.
1783 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1785 uint64_t vram_size = adev->gmc.visible_vram_size;
1787 adev->fw_vram_usage.va = NULL;
1788 adev->fw_vram_usage.reserved_bo = NULL;
1790 if (adev->fw_vram_usage.size == 0 ||
1791 adev->fw_vram_usage.size > vram_size)
1794 return amdgpu_bo_create_kernel_at(adev,
1795 adev->fw_vram_usage.start_offset,
1796 adev->fw_vram_usage.size,
1797 AMDGPU_GEM_DOMAIN_VRAM,
1798 &adev->fw_vram_usage.reserved_bo,
1799 &adev->fw_vram_usage.va);
1803 * Memoy training reservation functions
1807 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1809 * @adev: amdgpu_device pointer
1811 * free memory training reserved vram if it has been reserved.
1813 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1815 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1817 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1818 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1824 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1826 if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1829 return ALIGN(vram_size, SZ_1M);
1833 * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1835 * @adev: amdgpu_device pointer
1837 * create bo vram reservation from memory training.
1839 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1842 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1844 memset(ctx, 0, sizeof(*ctx));
1845 if (!adev->fw_vram_usage.mem_train_support) {
1846 DRM_DEBUG("memory training does not support!\n");
1850 ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1851 ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1852 ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1854 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1855 ctx->train_data_size,
1856 ctx->p2c_train_data_offset,
1857 ctx->c2p_train_data_offset);
1859 ret = amdgpu_bo_create_kernel_at(adev,
1860 ctx->c2p_train_data_offset,
1861 ctx->train_data_size,
1862 AMDGPU_GEM_DOMAIN_VRAM,
1866 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1867 amdgpu_ttm_training_reserve_vram_fini(adev);
1871 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1876 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1877 * gtt/vram related fields.
1879 * This initializes all of the memory space pools that the TTM layer
1880 * will need such as the GTT space (system memory mapped to the device),
1881 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1882 * can be mapped per VMID.
1884 int amdgpu_ttm_init(struct amdgpu_device *adev)
1889 void *stolen_vga_buf;
1891 mutex_init(&adev->mman.gtt_window_lock);
1893 /* No others user of address space so set it to 0 */
1894 r = ttm_bo_device_init(&adev->mman.bdev,
1896 adev->ddev->anon_inode->i_mapping,
1897 adev->ddev->vma_offset_manager,
1898 dma_addressing_limited(adev->dev));
1900 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1903 adev->mman.initialized = true;
1905 /* We opt to avoid OOM on system pages allocations */
1906 adev->mman.bdev.no_retry = true;
1908 /* Initialize VRAM pool with all of VRAM divided into pages */
1909 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1910 adev->gmc.real_vram_size >> PAGE_SHIFT);
1912 DRM_ERROR("Failed initializing VRAM heap.\n");
1916 /* Reduce size of CPU-visible VRAM if requested */
1917 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1918 if (amdgpu_vis_vram_limit > 0 &&
1919 vis_vram_limit <= adev->gmc.visible_vram_size)
1920 adev->gmc.visible_vram_size = vis_vram_limit;
1922 /* Change the size here instead of the init above so only lpfn is affected */
1923 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1925 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1926 adev->gmc.visible_vram_size);
1930 *The reserved vram for firmware must be pinned to the specified
1931 *place on the VRAM, so reserve it early.
1933 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1939 *The reserved vram for memory training must be pinned to the specified
1940 *place on the VRAM, so reserve it early.
1942 if (!amdgpu_sriov_vf(adev)) {
1943 r = amdgpu_ttm_training_reserve_vram_init(adev);
1948 /* allocate memory as required for VGA
1949 * This is used for VGA emulation and pre-OS scanout buffers to
1950 * avoid display artifacts while transitioning between pre-OS
1952 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1953 AMDGPU_GEM_DOMAIN_VRAM,
1954 &adev->stolen_vga_memory,
1955 NULL, &stolen_vga_buf);
1960 * reserve one TMR (64K) memory at the top of VRAM which holds
1961 * IP Discovery data and is protected by PSP.
1963 r = amdgpu_bo_create_kernel_at(adev,
1964 adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1966 AMDGPU_GEM_DOMAIN_VRAM,
1967 &adev->discovery_memory,
1972 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1973 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1975 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1976 * or whatever the user passed on module init */
1977 if (amdgpu_gtt_size == -1) {
1981 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1982 adev->gmc.mc_vram_size),
1983 ((uint64_t)si.totalram * si.mem_unit * 3/4));
1986 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1988 /* Initialize GTT memory pool */
1989 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1991 DRM_ERROR("Failed initializing GTT heap.\n");
1994 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1995 (unsigned)(gtt_size / (1024 * 1024)));
1997 /* Initialize various on-chip memory pools */
1998 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1999 adev->gds.gds_size);
2001 DRM_ERROR("Failed initializing GDS heap.\n");
2005 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2006 adev->gds.gws_size);
2008 DRM_ERROR("Failed initializing gws heap.\n");
2012 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2015 DRM_ERROR("Failed initializing oa heap.\n");
2023 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2025 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2027 void *stolen_vga_buf;
2028 /* return the VGA stolen memory (if any) back to VRAM */
2029 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2033 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2035 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2037 if (!adev->mman.initialized)
2040 amdgpu_ttm_training_reserve_vram_fini(adev);
2041 /* return the IP Discovery TMR memory back to VRAM */
2042 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2043 amdgpu_ttm_fw_reserve_vram_fini(adev);
2045 if (adev->mman.aper_base_kaddr)
2046 iounmap(adev->mman.aper_base_kaddr);
2047 adev->mman.aper_base_kaddr = NULL;
2049 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2050 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2051 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2052 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2053 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2054 ttm_bo_device_release(&adev->mman.bdev);
2055 adev->mman.initialized = false;
2056 DRM_INFO("amdgpu: ttm finalized\n");
2060 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2062 * @adev: amdgpu_device pointer
2063 * @enable: true when we can use buffer functions.
2065 * Enable/disable use of buffer functions during suspend/resume. This should
2066 * only be called at bootup or when userspace isn't running.
2068 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2070 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2074 if (!adev->mman.initialized || adev->in_gpu_reset ||
2075 adev->mman.buffer_funcs_enabled == enable)
2079 struct amdgpu_ring *ring;
2080 struct drm_gpu_scheduler *sched;
2082 ring = adev->mman.buffer_funcs_ring;
2083 sched = &ring->sched;
2084 r = drm_sched_entity_init(&adev->mman.entity,
2085 DRM_SCHED_PRIORITY_KERNEL, &sched,
2088 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2093 drm_sched_entity_destroy(&adev->mman.entity);
2094 dma_fence_put(man->move);
2098 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2100 size = adev->gmc.real_vram_size;
2102 size = adev->gmc.visible_vram_size;
2103 man->size = size >> PAGE_SHIFT;
2104 adev->mman.buffer_funcs_enabled = enable;
2107 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2109 struct drm_file *file_priv = filp->private_data;
2110 struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2115 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2118 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2119 uint64_t dst_offset, uint32_t byte_count,
2120 struct dma_resv *resv,
2121 struct dma_fence **fence, bool direct_submit,
2122 bool vm_needs_flush, bool tmz)
2124 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2125 AMDGPU_IB_POOL_DELAYED;
2126 struct amdgpu_device *adev = ring->adev;
2127 struct amdgpu_job *job;
2130 unsigned num_loops, num_dw;
2134 if (direct_submit && !ring->sched.ready) {
2135 DRM_ERROR("Trying to move memory with ring turned off.\n");
2139 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2140 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2141 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2143 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2147 if (vm_needs_flush) {
2148 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2149 job->vm_needs_flush = true;
2152 r = amdgpu_sync_resv(adev, &job->sync, resv,
2154 AMDGPU_FENCE_OWNER_UNDEFINED);
2156 DRM_ERROR("sync failed (%d).\n", r);
2161 for (i = 0; i < num_loops; i++) {
2162 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2164 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2165 dst_offset, cur_size_in_bytes, tmz);
2167 src_offset += cur_size_in_bytes;
2168 dst_offset += cur_size_in_bytes;
2169 byte_count -= cur_size_in_bytes;
2172 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2173 WARN_ON(job->ibs[0].length_dw > num_dw);
2175 r = amdgpu_job_submit_direct(job, ring, fence);
2177 r = amdgpu_job_submit(job, &adev->mman.entity,
2178 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2185 amdgpu_job_free(job);
2186 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2190 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2192 struct dma_resv *resv,
2193 struct dma_fence **fence)
2195 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2196 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2197 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2199 struct drm_mm_node *mm_node;
2200 unsigned long num_pages;
2201 unsigned int num_loops, num_dw;
2203 struct amdgpu_job *job;
2206 if (!adev->mman.buffer_funcs_enabled) {
2207 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2211 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2212 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2217 num_pages = bo->tbo.num_pages;
2218 mm_node = bo->tbo.mem.mm_node;
2221 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2223 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2224 num_pages -= mm_node->size;
2227 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2229 /* for IB padding */
2232 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2238 r = amdgpu_sync_resv(adev, &job->sync, resv,
2240 AMDGPU_FENCE_OWNER_UNDEFINED);
2242 DRM_ERROR("sync failed (%d).\n", r);
2247 num_pages = bo->tbo.num_pages;
2248 mm_node = bo->tbo.mem.mm_node;
2251 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2254 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2255 while (byte_count) {
2256 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2259 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2260 dst_addr, cur_size_in_bytes);
2262 dst_addr += cur_size_in_bytes;
2263 byte_count -= cur_size_in_bytes;
2266 num_pages -= mm_node->size;
2270 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2271 WARN_ON(job->ibs[0].length_dw > num_dw);
2272 r = amdgpu_job_submit(job, &adev->mman.entity,
2273 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2280 amdgpu_job_free(job);
2284 #if defined(CONFIG_DEBUG_FS)
2286 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2288 struct drm_info_node *node = (struct drm_info_node *)m->private;
2289 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2290 struct drm_device *dev = node->minor->dev;
2291 struct amdgpu_device *adev = dev->dev_private;
2292 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2293 struct drm_printer p = drm_seq_file_printer(m);
2295 man->func->debug(man, &p);
2299 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2300 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2301 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2302 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2303 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2304 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2305 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2306 #ifdef CONFIG_SWIOTLB
2307 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2312 * amdgpu_ttm_vram_read - Linear read access to VRAM
2314 * Accesses VRAM via MMIO for debugging purposes.
2316 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2317 size_t size, loff_t *pos)
2319 struct amdgpu_device *adev = file_inode(f)->i_private;
2322 if (size & 0x3 || *pos & 0x3)
2325 if (*pos >= adev->gmc.mc_vram_size)
2328 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2330 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2331 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2333 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2334 if (copy_to_user(buf, value, bytes))
2347 * amdgpu_ttm_vram_write - Linear write access to VRAM
2349 * Accesses VRAM via MMIO for debugging purposes.
2351 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2352 size_t size, loff_t *pos)
2354 struct amdgpu_device *adev = file_inode(f)->i_private;
2358 if (size & 0x3 || *pos & 0x3)
2361 if (*pos >= adev->gmc.mc_vram_size)
2365 unsigned long flags;
2368 if (*pos >= adev->gmc.mc_vram_size)
2371 r = get_user(value, (uint32_t *)buf);
2375 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2376 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2377 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2378 WREG32_NO_KIQ(mmMM_DATA, value);
2379 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2390 static const struct file_operations amdgpu_ttm_vram_fops = {
2391 .owner = THIS_MODULE,
2392 .read = amdgpu_ttm_vram_read,
2393 .write = amdgpu_ttm_vram_write,
2394 .llseek = default_llseek,
2397 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2400 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2402 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2403 size_t size, loff_t *pos)
2405 struct amdgpu_device *adev = file_inode(f)->i_private;
2410 loff_t p = *pos / PAGE_SIZE;
2411 unsigned off = *pos & ~PAGE_MASK;
2412 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2416 if (p >= adev->gart.num_cpu_pages)
2419 page = adev->gart.pages[p];
2424 r = copy_to_user(buf, ptr, cur_size);
2425 kunmap(adev->gart.pages[p]);
2427 r = clear_user(buf, cur_size);
2441 static const struct file_operations amdgpu_ttm_gtt_fops = {
2442 .owner = THIS_MODULE,
2443 .read = amdgpu_ttm_gtt_read,
2444 .llseek = default_llseek
2450 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2452 * This function is used to read memory that has been mapped to the
2453 * GPU and the known addresses are not physical addresses but instead
2454 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2456 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2457 size_t size, loff_t *pos)
2459 struct amdgpu_device *adev = file_inode(f)->i_private;
2460 struct iommu_domain *dom;
2464 /* retrieve the IOMMU domain if any for this device */
2465 dom = iommu_get_domain_for_dev(adev->dev);
2468 phys_addr_t addr = *pos & PAGE_MASK;
2469 loff_t off = *pos & ~PAGE_MASK;
2470 size_t bytes = PAGE_SIZE - off;
2475 bytes = bytes < size ? bytes : size;
2477 /* Translate the bus address to a physical address. If
2478 * the domain is NULL it means there is no IOMMU active
2479 * and the address translation is the identity
2481 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2483 pfn = addr >> PAGE_SHIFT;
2484 if (!pfn_valid(pfn))
2487 p = pfn_to_page(pfn);
2488 if (p->mapping != adev->mman.bdev.dev_mapping)
2492 r = copy_to_user(buf, ptr + off, bytes);
2506 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2508 * This function is used to write memory that has been mapped to the
2509 * GPU and the known addresses are not physical addresses but instead
2510 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2512 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2513 size_t size, loff_t *pos)
2515 struct amdgpu_device *adev = file_inode(f)->i_private;
2516 struct iommu_domain *dom;
2520 dom = iommu_get_domain_for_dev(adev->dev);
2523 phys_addr_t addr = *pos & PAGE_MASK;
2524 loff_t off = *pos & ~PAGE_MASK;
2525 size_t bytes = PAGE_SIZE - off;
2530 bytes = bytes < size ? bytes : size;
2532 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2534 pfn = addr >> PAGE_SHIFT;
2535 if (!pfn_valid(pfn))
2538 p = pfn_to_page(pfn);
2539 if (p->mapping != adev->mman.bdev.dev_mapping)
2543 r = copy_from_user(ptr + off, buf, bytes);
2556 static const struct file_operations amdgpu_ttm_iomem_fops = {
2557 .owner = THIS_MODULE,
2558 .read = amdgpu_iomem_read,
2559 .write = amdgpu_iomem_write,
2560 .llseek = default_llseek
2563 static const struct {
2565 const struct file_operations *fops;
2567 } ttm_debugfs_entries[] = {
2568 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2569 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2570 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2572 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2577 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2579 #if defined(CONFIG_DEBUG_FS)
2582 struct drm_minor *minor = adev->ddev->primary;
2583 struct dentry *ent, *root = minor->debugfs_root;
2585 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2586 ent = debugfs_create_file(
2587 ttm_debugfs_entries[count].name,
2588 S_IFREG | S_IRUGO, root,
2590 ttm_debugfs_entries[count].fops);
2592 return PTR_ERR(ent);
2593 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2594 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2595 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2596 i_size_write(ent->d_inode, adev->gmc.gart_size);
2597 adev->mman.debugfs_entries[count] = ent;
2600 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2602 #ifdef CONFIG_SWIOTLB
2603 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2607 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);