drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  54 {
  55         struct amdgpu_mman *mman;
  56         struct amdgpu_device *adev;
  57
  58         mman = container_of(bdev, struct amdgpu_mman, bdev);
  59         adev = container_of(mman, struct amdgpu_device, mman);
  60         return adev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         int r;
  81
  82         adev->mman.mem_global_referenced = false;
  83         global_ref = &adev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &amdgpu_ttm_mem_global_init;
  87         global_ref->release = &amdgpu_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r != 0) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 return r;
  93         }
  94
  95         adev->mman.bo_global_ref.mem_glob =
  96                 adev->mman.mem_global_ref.object;
  97         global_ref = &adev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r != 0) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 drm_global_item_unref(&adev->mman.mem_global_ref);
 106                 return r;
 107         }
 108
 109         adev->mman.mem_global_referenced = true;
 110         return 0;
 111 }
 112
 113 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 114 {
 115         if (adev->mman.mem_global_referenced) {
 116                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 117                 drm_global_item_unref(&adev->mman.mem_global_ref);
 118                 adev->mman.mem_global_referenced = false;
 119         }
 120 }
 121
 122 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123 {
 124         return 0;
 125 }
 126
 127 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                 struct ttm_mem_type_manager *man)
 129 {
 130         struct amdgpu_device *adev;
 131
 132         adev = amdgpu_get_adev(bdev);
 133
 134         switch (type) {
 135         case TTM_PL_SYSTEM:
 136                 /* System memory */
 137                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                 man->available_caching = TTM_PL_MASK_CACHING;
 139                 man->default_caching = TTM_PL_FLAG_CACHED;
 140                 break;
 141         case TTM_PL_TT:
 142                 man->func = &ttm_bo_manager_func;
 143                 man->gpu_offset = adev->mc.gtt_start;
 144                 man->available_caching = TTM_PL_MASK_CACHING;
 145                 man->default_caching = TTM_PL_FLAG_CACHED;
 146                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147                 break;
 148         case TTM_PL_VRAM:
 149                 /* "On-card" video ram */
 150                 man->func = &ttm_bo_manager_func;
 151                 man->gpu_offset = adev->mc.vram_start;
 152                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 153                              TTM_MEMTYPE_FLAG_MAPPABLE;
 154                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 155                 man->default_caching = TTM_PL_FLAG_WC;
 156                 break;
 157         case AMDGPU_PL_GDS:
 158         case AMDGPU_PL_GWS:
 159         case AMDGPU_PL_OA:
 160                 /* On-chip GDS memory*/
 161                 man->func = &ttm_bo_manager_func;
 162                 man->gpu_offset = 0;
 163                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 164                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 165                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 166                 break;
 167         default:
 168                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 169                 return -EINVAL;
 170         }
 171         return 0;
 172 }
 173
 174 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 175                                 struct ttm_placement *placement)
 176 {
 177         struct amdgpu_bo *rbo;
 178         static struct ttm_place placements = {
 179                 .fpfn = 0,
 180                 .lpfn = 0,
 181                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 182         };
 183
 184         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 185                 placement->placement = &placements;
 186                 placement->busy_placement = &placements;
 187                 placement->num_placement = 1;
 188                 placement->num_busy_placement = 1;
 189                 return;
 190         }
 191         rbo = container_of(bo, struct amdgpu_bo, tbo);
 192         switch (bo->mem.mem_type) {
 193         case TTM_PL_VRAM:
 194                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 195                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 196                 else
 197                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 198                 break;
 199         case TTM_PL_TT:
 200         default:
 201                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 202         }
 203         *placement = rbo->placement;
 204 }
 205
 206 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 207 {
 208         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 209
 210         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 211 }
 212
 213 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 214                              struct ttm_mem_reg *new_mem)
 215 {
 216         struct ttm_mem_reg *old_mem = &bo->mem;
 217
 218         BUG_ON(old_mem->mm_node != NULL);
 219         *old_mem = *new_mem;
 220         new_mem->mm_node = NULL;
 221 }
 222
 223 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 224                         bool evict, bool no_wait_gpu,
 225                         struct ttm_mem_reg *new_mem,
 226                         struct ttm_mem_reg *old_mem)
 227 {
 228         struct amdgpu_device *adev;
 229         struct amdgpu_ring *ring;
 230         uint64_t old_start, new_start;
 231         struct fence *fence;
 232         int r;
 233
 234         adev = amdgpu_get_adev(bo->bdev);
 235         ring = adev->mman.buffer_funcs_ring;
 236         old_start = old_mem->start << PAGE_SHIFT;
 237         new_start = new_mem->start << PAGE_SHIFT;
 238
 239         switch (old_mem->mem_type) {
 240         case TTM_PL_VRAM:
 241                 old_start += adev->mc.vram_start;
 242                 break;
 243         case TTM_PL_TT:
 244                 old_start += adev->mc.gtt_start;
 245                 break;
 246         default:
 247                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 248                 return -EINVAL;
 249         }
 250         switch (new_mem->mem_type) {
 251         case TTM_PL_VRAM:
 252                 new_start += adev->mc.vram_start;
 253                 break;
 254         case TTM_PL_TT:
 255                 new_start += adev->mc.gtt_start;
 256                 break;
 257         default:
 258                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 259                 return -EINVAL;
 260         }
 261         if (!ring->ready) {
 262                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 263                 return -EINVAL;
 264         }
 265
 266         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 267
 268         r = amdgpu_copy_buffer(ring, old_start, new_start,
 269                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 270                                bo->resv, &fence);
 271         /* FIXME: handle copy error */
 272         r = ttm_bo_move_accel_cleanup(bo, fence,
 273                                       evict, no_wait_gpu, new_mem);
 274         fence_put(fence);
 275         return r;
 276 }
 277
 278 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 279                                 bool evict, bool interruptible,
 280                                 bool no_wait_gpu,
 281                                 struct ttm_mem_reg *new_mem)
 282 {
 283         struct amdgpu_device *adev;
 284         struct ttm_mem_reg *old_mem = &bo->mem;
 285         struct ttm_mem_reg tmp_mem;
 286         struct ttm_place placements;
 287         struct ttm_placement placement;
 288         int r;
 289
 290         adev = amdgpu_get_adev(bo->bdev);
 291         tmp_mem = *new_mem;
 292         tmp_mem.mm_node = NULL;
 293         placement.num_placement = 1;
 294         placement.placement = &placements;
 295         placement.num_busy_placement = 1;
 296         placement.busy_placement = &placements;
 297         placements.fpfn = 0;
 298         placements.lpfn = 0;
 299         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 300         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 301                              interruptible, no_wait_gpu);
 302         if (unlikely(r)) {
 303                 return r;
 304         }
 305
 306         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 307         if (unlikely(r)) {
 308                 goto out_cleanup;
 309         }
 310
 311         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 312         if (unlikely(r)) {
 313                 goto out_cleanup;
 314         }
 315         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 316         if (unlikely(r)) {
 317                 goto out_cleanup;
 318         }
 319         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 320 out_cleanup:
 321         ttm_bo_mem_put(bo, &tmp_mem);
 322         return r;
 323 }
 324
 325 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 326                                 bool evict, bool interruptible,
 327                                 bool no_wait_gpu,
 328                                 struct ttm_mem_reg *new_mem)
 329 {
 330         struct amdgpu_device *adev;
 331         struct ttm_mem_reg *old_mem = &bo->mem;
 332         struct ttm_mem_reg tmp_mem;
 333         struct ttm_placement placement;
 334         struct ttm_place placements;
 335         int r;
 336
 337         adev = amdgpu_get_adev(bo->bdev);
 338         tmp_mem = *new_mem;
 339         tmp_mem.mm_node = NULL;
 340         placement.num_placement = 1;
 341         placement.placement = &placements;
 342         placement.num_busy_placement = 1;
 343         placement.busy_placement = &placements;
 344         placements.fpfn = 0;
 345         placements.lpfn = 0;
 346         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 347         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 348                              interruptible, no_wait_gpu);
 349         if (unlikely(r)) {
 350                 return r;
 351         }
 352         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 353         if (unlikely(r)) {
 354                 goto out_cleanup;
 355         }
 356         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 357         if (unlikely(r)) {
 358                 goto out_cleanup;
 359         }
 360 out_cleanup:
 361         ttm_bo_mem_put(bo, &tmp_mem);
 362         return r;
 363 }
 364
 365 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 366                         bool evict, bool interruptible,
 367                         bool no_wait_gpu,
 368                         struct ttm_mem_reg *new_mem)
 369 {
 370         struct amdgpu_device *adev;
 371         struct ttm_mem_reg *old_mem = &bo->mem;
 372         int r;
 373
 374         adev = amdgpu_get_adev(bo->bdev);
 375         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 376                 amdgpu_move_null(bo, new_mem);
 377                 return 0;
 378         }
 379         if ((old_mem->mem_type == TTM_PL_TT &&
 380              new_mem->mem_type == TTM_PL_SYSTEM) ||
 381             (old_mem->mem_type == TTM_PL_SYSTEM &&
 382              new_mem->mem_type == TTM_PL_TT)) {
 383                 /* bind is enough */
 384                 amdgpu_move_null(bo, new_mem);
 385                 return 0;
 386         }
 387         if (adev->mman.buffer_funcs == NULL ||
 388             adev->mman.buffer_funcs_ring == NULL ||
 389             !adev->mman.buffer_funcs_ring->ready) {
 390                 /* use memcpy */
 391                 goto memcpy;
 392         }
 393
 394         if (old_mem->mem_type == TTM_PL_VRAM &&
 395             new_mem->mem_type == TTM_PL_SYSTEM) {
 396                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 397                                         no_wait_gpu, new_mem);
 398         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 399                    new_mem->mem_type == TTM_PL_VRAM) {
 400                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 401                                             no_wait_gpu, new_mem);
 402         } else {
 403                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 404         }
 405
 406         if (r) {
 407 memcpy:
 408                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 409                 if (r) {
 410                         return r;
 411                 }
 412         }
 413
 414         /* update statistics */
 415         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 416         return 0;
 417 }
 418
 419 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 420 {
 421         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 422         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 423
 424         mem->bus.addr = NULL;
 425         mem->bus.offset = 0;
 426         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 427         mem->bus.base = 0;
 428         mem->bus.is_iomem = false;
 429         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 430                 return -EINVAL;
 431         switch (mem->mem_type) {
 432         case TTM_PL_SYSTEM:
 433                 /* system memory */
 434                 return 0;
 435         case TTM_PL_TT:
 436                 break;
 437         case TTM_PL_VRAM:
 438                 mem->bus.offset = mem->start << PAGE_SHIFT;
 439                 /* check if it's visible */
 440                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 441                         return -EINVAL;
 442                 mem->bus.base = adev->mc.aper_base;
 443                 mem->bus.is_iomem = true;
 444 #ifdef __alpha__
 445                 /*
 446                  * Alpha: use bus.addr to hold the ioremap() return,
 447                  * so we can modify bus.base below.
 448                  */
 449                 if (mem->placement & TTM_PL_FLAG_WC)
 450                         mem->bus.addr =
 451                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 452                                            mem->bus.size);
 453                 else
 454                         mem->bus.addr =
 455                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 456                                                 mem->bus.size);
 457
 458                 /*
 459                  * Alpha: Use just the bus offset plus
 460                  * the hose/domain memory base for bus.base.
 461                  * It then can be used to build PTEs for VRAM
 462                  * access, as done in ttm_bo_vm_fault().
 463                  */
 464                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 465                         adev->ddev->hose->dense_mem_base;
 466 #endif
 467                 break;
 468         default:
 469                 return -EINVAL;
 470         }
 471         return 0;
 472 }
 473
 474 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 475 {
 476 }
 477
 478 /*
 479  * TTM backend functions.
 480  */
 481 struct amdgpu_ttm_tt {
 482         struct ttm_dma_tt               ttm;
 483         struct amdgpu_device            *adev;
 484         u64                             offset;
 485         uint64_t                        userptr;
 486         struct mm_struct                *usermm;
 487         uint32_t                        userflags;
 488 };
 489
 490 /* prepare the sg table with the user pages */
 491 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 492 {
 493         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 494         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 495         unsigned pinned = 0, nents;
 496         int r;
 497
 498         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 499         enum dma_data_direction direction = write ?
 500                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 501
 502         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 503                 /* check that we only pin down anonymous memory
 504                    to prevent problems with writeback */
 505                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 506                 struct vm_area_struct *vma;
 507
 508                 vma = find_vma(gtt->usermm, gtt->userptr);
 509                 if (!vma || vma->vm_file || vma->vm_end < end)
 510                         return -EPERM;
 511         }
 512
 513         do {
 514                 unsigned num_pages = ttm->num_pages - pinned;
 515                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 516                 struct page **pages = ttm->pages + pinned;
 517
 518                 r = get_user_pages(current, current->mm, userptr, num_pages,
 519                                    write, 0, pages, NULL);
 520                 if (r < 0)
 521                         goto release_pages;
 522
 523                 pinned += r;
 524
 525         } while (pinned < ttm->num_pages);
 526
 527         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 528                                       ttm->num_pages << PAGE_SHIFT,
 529                                       GFP_KERNEL);
 530         if (r)
 531                 goto release_sg;
 532
 533         r = -ENOMEM;
 534         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 535         if (nents != ttm->sg->nents)
 536                 goto release_sg;
 537
 538         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 539                                          gtt->ttm.dma_address, ttm->num_pages);
 540
 541         return 0;
 542
 543 release_sg:
 544         kfree(ttm->sg);
 545
 546 release_pages:
 547         release_pages(ttm->pages, pinned, 0);
 548         return r;
 549 }
 550
 551 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 552 {
 553         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 554         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 555         struct sg_page_iter sg_iter;
 556
 557         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 558         enum dma_data_direction direction = write ?
 559                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 560
 561         /* double check that we don't free the table twice */
 562         if (!ttm->sg->sgl)
 563                 return;
 564
 565         /* free the sg table and pages again */
 566         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 567
 568         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 569                 struct page *page = sg_page_iter_page(&sg_iter);
 570                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 571                         set_page_dirty(page);
 572
 573                 mark_page_accessed(page);
 574                 page_cache_release(page);
 575         }
 576
 577         sg_free_table(ttm->sg);
 578 }
 579
 580 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 581                                    struct ttm_mem_reg *bo_mem)
 582 {
 583         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 584         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 585         int r;
 586
 587         if (gtt->userptr) {
 588                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 589                 if (r) {
 590                         DRM_ERROR("failed to pin userptr\n");
 591                         return r;
 592                 }
 593         }
 594         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 595         if (!ttm->num_pages) {
 596                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 597                      ttm->num_pages, bo_mem, ttm);
 598         }
 599
 600         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 601             bo_mem->mem_type == AMDGPU_PL_GWS ||
 602             bo_mem->mem_type == AMDGPU_PL_OA)
 603                 return -EINVAL;
 604
 605         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 606                 ttm->pages, gtt->ttm.dma_address, flags);
 607
 608         if (r) {
 609                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 610                           ttm->num_pages, (unsigned)gtt->offset);
 611                 return r;
 612         }
 613         return 0;
 614 }
 615
 616 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 617 {
 618         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 619
 620         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 621         if (gtt->adev->gart.ready)
 622                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 623
 624         if (gtt->userptr)
 625                 amdgpu_ttm_tt_unpin_userptr(ttm);
 626
 627         return 0;
 628 }
 629
 630 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 631 {
 632         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 633
 634         ttm_dma_tt_fini(&gtt->ttm);
 635         kfree(gtt);
 636 }
 637
 638 static struct ttm_backend_func amdgpu_backend_func = {
 639         .bind = &amdgpu_ttm_backend_bind,
 640         .unbind = &amdgpu_ttm_backend_unbind,
 641         .destroy = &amdgpu_ttm_backend_destroy,
 642 };
 643
 644 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 645                                     unsigned long size, uint32_t page_flags,
 646                                     struct page *dummy_read_page)
 647 {
 648         struct amdgpu_device *adev;
 649         struct amdgpu_ttm_tt *gtt;
 650
 651         adev = amdgpu_get_adev(bdev);
 652
 653         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 654         if (gtt == NULL) {
 655                 return NULL;
 656         }
 657         gtt->ttm.ttm.func = &amdgpu_backend_func;
 658         gtt->adev = adev;
 659         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 660                 kfree(gtt);
 661                 return NULL;
 662         }
 663         return &gtt->ttm.ttm;
 664 }
 665
 666 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 667 {
 668         struct amdgpu_device *adev;
 669         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 670         unsigned i;
 671         int r;
 672         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 673
 674         if (ttm->state != tt_unpopulated)
 675                 return 0;
 676
 677         if (gtt && gtt->userptr) {
 678                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 679                 if (!ttm->sg)
 680                         return -ENOMEM;
 681
 682                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 683                 ttm->state = tt_unbound;
 684                 return 0;
 685         }
 686
 687         if (slave && ttm->sg) {
 688                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 689                                                  gtt->ttm.dma_address, ttm->num_pages);
 690                 ttm->state = tt_unbound;
 691                 return 0;
 692         }
 693
 694         adev = amdgpu_get_adev(ttm->bdev);
 695
 696 #ifdef CONFIG_SWIOTLB
 697         if (swiotlb_nr_tbl()) {
 698                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 699         }
 700 #endif
 701
 702         r = ttm_pool_populate(ttm);
 703         if (r) {
 704                 return r;
 705         }
 706
 707         for (i = 0; i < ttm->num_pages; i++) {
 708                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 709                                                        0, PAGE_SIZE,
 710                                                        PCI_DMA_BIDIRECTIONAL);
 711                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 712                         while (--i) {
 713                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 714                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 715                                 gtt->ttm.dma_address[i] = 0;
 716                         }
 717                         ttm_pool_unpopulate(ttm);
 718                         return -EFAULT;
 719                 }
 720         }
 721         return 0;
 722 }
 723
 724 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 725 {
 726         struct amdgpu_device *adev;
 727         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 728         unsigned i;
 729         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 730
 731         if (gtt && gtt->userptr) {
 732                 kfree(ttm->sg);
 733                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 734                 return;
 735         }
 736
 737         if (slave)
 738                 return;
 739
 740         adev = amdgpu_get_adev(ttm->bdev);
 741
 742 #ifdef CONFIG_SWIOTLB
 743         if (swiotlb_nr_tbl()) {
 744                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 745                 return;
 746         }
 747 #endif
 748
 749         for (i = 0; i < ttm->num_pages; i++) {
 750                 if (gtt->ttm.dma_address[i]) {
 751                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 752                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 753                 }
 754         }
 755
 756         ttm_pool_unpopulate(ttm);
 757 }
 758
 759 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 760                               uint32_t flags)
 761 {
 762         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 763
 764         if (gtt == NULL)
 765                 return -EINVAL;
 766
 767         gtt->userptr = addr;
 768         gtt->usermm = current->mm;
 769         gtt->userflags = flags;
 770         return 0;
 771 }
 772
 773 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 774 {
 775         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 776
 777         if (gtt == NULL)
 778                 return NULL;
 779
 780         return gtt->usermm;
 781 }
 782
 783 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 784                                   unsigned long end)
 785 {
 786         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 787         unsigned long size;
 788
 789         if (gtt == NULL)
 790                 return false;
 791
 792         if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
 793                 return false;
 794
 795         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 796         if (gtt->userptr > end || gtt->userptr + size <= start)
 797                 return false;
 798
 799         return true;
 800 }
 801
 802 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 803 {
 804         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 805
 806         if (gtt == NULL)
 807                 return false;
 808
 809         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 810 }
 811
 812 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 813                                  struct ttm_mem_reg *mem)
 814 {
 815         uint32_t flags = 0;
 816
 817         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 818                 flags |= AMDGPU_PTE_VALID;
 819
 820         if (mem && mem->mem_type == TTM_PL_TT) {
 821                 flags |= AMDGPU_PTE_SYSTEM;
 822
 823                 if (ttm->caching_state == tt_cached)
 824                         flags |= AMDGPU_PTE_SNOOPED;
 825         }
 826
 827         if (adev->asic_type >= CHIP_TONGA)
 828                 flags |= AMDGPU_PTE_EXECUTABLE;
 829
 830         flags |= AMDGPU_PTE_READABLE;
 831
 832         if (!amdgpu_ttm_tt_is_readonly(ttm))
 833                 flags |= AMDGPU_PTE_WRITEABLE;
 834
 835         return flags;
 836 }
 837
 838 static struct ttm_bo_driver amdgpu_bo_driver = {
 839         .ttm_tt_create = &amdgpu_ttm_tt_create,
 840         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 841         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 842         .invalidate_caches = &amdgpu_invalidate_caches,
 843         .init_mem_type = &amdgpu_init_mem_type,
 844         .evict_flags = &amdgpu_evict_flags,
 845         .move = &amdgpu_bo_move,
 846         .verify_access = &amdgpu_verify_access,
 847         .move_notify = &amdgpu_bo_move_notify,
 848         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 849         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 850         .io_mem_free = &amdgpu_ttm_io_mem_free,
 851 };
 852
 853 int amdgpu_ttm_init(struct amdgpu_device *adev)
 854 {
 855         int r;
 856
 857         r = amdgpu_ttm_global_init(adev);
 858         if (r) {
 859                 return r;
 860         }
 861         /* No others user of address space so set it to 0 */
 862         r = ttm_bo_device_init(&adev->mman.bdev,
 863                                adev->mman.bo_global_ref.ref.object,
 864                                &amdgpu_bo_driver,
 865                                adev->ddev->anon_inode->i_mapping,
 866                                DRM_FILE_PAGE_OFFSET,
 867                                adev->need_dma32);
 868         if (r) {
 869                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 870                 return r;
 871         }
 872         adev->mman.initialized = true;
 873         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
 874                                 adev->mc.real_vram_size >> PAGE_SHIFT);
 875         if (r) {
 876                 DRM_ERROR("Failed initializing VRAM heap.\n");
 877                 return r;
 878         }
 879         /* Change the size here instead of the init above so only lpfn is affected */
 880         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 881
 882         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
 883                              AMDGPU_GEM_DOMAIN_VRAM,
 884                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 885                              NULL, NULL, &adev->stollen_vga_memory);
 886         if (r) {
 887                 return r;
 888         }
 889         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 890         if (r)
 891                 return r;
 892         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
 893         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 894         if (r) {
 895                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 896                 return r;
 897         }
 898         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 899                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
 900         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
 901                                 adev->mc.gtt_size >> PAGE_SHIFT);
 902         if (r) {
 903                 DRM_ERROR("Failed initializing GTT heap.\n");
 904                 return r;
 905         }
 906         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
 907                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
 908
 909         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
 910         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
 911         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
 912         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
 913         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
 914         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
 915         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
 916         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
 917         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
 918         /* GDS Memory */
 919         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
 920                                 adev->gds.mem.total_size >> PAGE_SHIFT);
 921         if (r) {
 922                 DRM_ERROR("Failed initializing GDS heap.\n");
 923                 return r;
 924         }
 925
 926         /* GWS */
 927         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
 928                                 adev->gds.gws.total_size >> PAGE_SHIFT);
 929         if (r) {
 930                 DRM_ERROR("Failed initializing gws heap.\n");
 931                 return r;
 932         }
 933
 934         /* OA */
 935         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
 936                                 adev->gds.oa.total_size >> PAGE_SHIFT);
 937         if (r) {
 938                 DRM_ERROR("Failed initializing oa heap.\n");
 939                 return r;
 940         }
 941
 942         r = amdgpu_ttm_debugfs_init(adev);
 943         if (r) {
 944                 DRM_ERROR("Failed to init debugfs\n");
 945                 return r;
 946         }
 947         return 0;
 948 }
 949
 950 void amdgpu_ttm_fini(struct amdgpu_device *adev)
 951 {
 952         int r;
 953
 954         if (!adev->mman.initialized)
 955                 return;
 956         amdgpu_ttm_debugfs_fini(adev);
 957         if (adev->stollen_vga_memory) {
 958                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 959                 if (r == 0) {
 960                         amdgpu_bo_unpin(adev->stollen_vga_memory);
 961                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 962                 }
 963                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 964         }
 965         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
 966         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
 967         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
 968         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
 969         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
 970         ttm_bo_device_release(&adev->mman.bdev);
 971         amdgpu_gart_fini(adev);
 972         amdgpu_ttm_global_fini(adev);
 973         adev->mman.initialized = false;
 974         DRM_INFO("amdgpu: ttm finalized\n");
 975 }
 976
 977 /* this should only be called at bootup or when userspace
 978  * isn't running */
 979 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
 980 {
 981         struct ttm_mem_type_manager *man;
 982
 983         if (!adev->mman.initialized)
 984                 return;
 985
 986         man = &adev->mman.bdev.man[TTM_PL_VRAM];
 987         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 988         man->size = size >> PAGE_SHIFT;
 989 }
 990
 991 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
 992 {
 993         struct drm_file *file_priv;
 994         struct amdgpu_device *adev;
 995
 996         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
 997                 return -EINVAL;
 998
 999         file_priv = filp->private_data;
1000         adev = file_priv->minor->dev->dev_private;
1001         if (adev == NULL)
1002                 return -EINVAL;
1003
1004         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1005 }
1006
1007 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1008                        uint64_t src_offset,
1009                        uint64_t dst_offset,
1010                        uint32_t byte_count,
1011                        struct reservation_object *resv,
1012                        struct fence **fence)
1013 {
1014         struct amdgpu_device *adev = ring->adev;
1015         uint32_t max_bytes;
1016         unsigned num_loops, num_dw;
1017         struct amdgpu_ib *ib;
1018         unsigned i;
1019         int r;
1020
1021         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1022         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1023         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1024
1025         /* for IB padding */
1026         while (num_dw & 0x7)
1027                 num_dw++;
1028
1029         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
1030         if (!ib)
1031                 return -ENOMEM;
1032
1033         r = amdgpu_ib_get(adev, NULL, num_dw * 4, ib);
1034         if (r) {
1035                 kfree(ib);
1036                 return r;
1037         }
1038
1039         ib->length_dw = 0;
1040
1041         if (resv) {
1042                 r = amdgpu_sync_resv(adev, &ib->sync, resv,
1043                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1044                 if (r) {
1045                         DRM_ERROR("sync failed (%d).\n", r);
1046                         goto error_free;
1047                 }
1048         }
1049
1050         for (i = 0; i < num_loops; i++) {
1051                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1052
1053                 amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset,
1054                                         cur_size_in_bytes);
1055
1056                 src_offset += cur_size_in_bytes;
1057                 dst_offset += cur_size_in_bytes;
1058                 byte_count -= cur_size_in_bytes;
1059         }
1060
1061         amdgpu_ring_pad_ib(ring, ib);
1062         WARN_ON(ib->length_dw > num_dw);
1063         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
1064                                                  &amdgpu_vm_free_job,
1065                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
1066                                                  fence);
1067         if (r)
1068                 goto error_free;
1069
1070         return 0;
1071 error_free:
1072         amdgpu_ib_free(adev, ib);
1073         kfree(ib);
1074         return r;
1075 }
1076
1077 #if defined(CONFIG_DEBUG_FS)
1078
1079 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1080 {
1081         struct drm_info_node *node = (struct drm_info_node *)m->private;
1082         unsigned ttm_pl = *(int *)node->info_ent->data;
1083         struct drm_device *dev = node->minor->dev;
1084         struct amdgpu_device *adev = dev->dev_private;
1085         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1086         int ret;
1087         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1088
1089         spin_lock(&glob->lru_lock);
1090         ret = drm_mm_dump_table(m, mm);
1091         spin_unlock(&glob->lru_lock);
1092         if (ttm_pl == TTM_PL_VRAM)
1093                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1094                            adev->mman.bdev.man[ttm_pl].size,
1095                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1096                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1097         return ret;
1098 }
1099
1100 static int ttm_pl_vram = TTM_PL_VRAM;
1101 static int ttm_pl_tt = TTM_PL_TT;
1102
1103 static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1104         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1105         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1106         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1107 #ifdef CONFIG_SWIOTLB
1108         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1109 #endif
1110 };
1111
1112 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1113                                     size_t size, loff_t *pos)
1114 {
1115         struct amdgpu_device *adev = f->f_inode->i_private;
1116         ssize_t result = 0;
1117         int r;
1118
1119         if (size & 0x3 || *pos & 0x3)
1120                 return -EINVAL;
1121
1122         while (size) {
1123                 unsigned long flags;
1124                 uint32_t value;
1125
1126                 if (*pos >= adev->mc.mc_vram_size)
1127                         return result;
1128
1129                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1130                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1131                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1132                 value = RREG32(mmMM_DATA);
1133                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1134
1135                 r = put_user(value, (uint32_t *)buf);
1136                 if (r)
1137                         return r;
1138
1139                 result += 4;
1140                 buf += 4;
1141                 *pos += 4;
1142                 size -= 4;
1143         }
1144
1145         return result;
1146 }
1147
1148 static const struct file_operations amdgpu_ttm_vram_fops = {
1149         .owner = THIS_MODULE,
1150         .read = amdgpu_ttm_vram_read,
1151         .llseek = default_llseek
1152 };
1153
1154 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1155                                    size_t size, loff_t *pos)
1156 {
1157         struct amdgpu_device *adev = f->f_inode->i_private;
1158         ssize_t result = 0;
1159         int r;
1160
1161         while (size) {
1162                 loff_t p = *pos / PAGE_SIZE;
1163                 unsigned off = *pos & ~PAGE_MASK;
1164                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1165                 struct page *page;
1166                 void *ptr;
1167
1168                 if (p >= adev->gart.num_cpu_pages)
1169                         return result;
1170
1171                 page = adev->gart.pages[p];
1172                 if (page) {
1173                         ptr = kmap(page);
1174                         ptr += off;
1175
1176                         r = copy_to_user(buf, ptr, cur_size);
1177                         kunmap(adev->gart.pages[p]);
1178                 } else
1179                         r = clear_user(buf, cur_size);
1180
1181                 if (r)
1182                         return -EFAULT;
1183
1184                 result += cur_size;
1185                 buf += cur_size;
1186                 *pos += cur_size;
1187                 size -= cur_size;
1188         }
1189
1190         return result;
1191 }
1192
1193 static const struct file_operations amdgpu_ttm_gtt_fops = {
1194         .owner = THIS_MODULE,
1195         .read = amdgpu_ttm_gtt_read,
1196         .llseek = default_llseek
1197 };
1198
1199 #endif
1200
1201 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1202 {
1203 #if defined(CONFIG_DEBUG_FS)
1204         unsigned count;
1205
1206         struct drm_minor *minor = adev->ddev->primary;
1207         struct dentry *ent, *root = minor->debugfs_root;
1208
1209         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1210                                   adev, &amdgpu_ttm_vram_fops);
1211         if (IS_ERR(ent))
1212                 return PTR_ERR(ent);
1213         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1214         adev->mman.vram = ent;
1215
1216         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1217                                   adev, &amdgpu_ttm_gtt_fops);
1218         if (IS_ERR(ent))
1219                 return PTR_ERR(ent);
1220         i_size_write(ent->d_inode, adev->mc.gtt_size);
1221         adev->mman.gtt = ent;
1222
1223         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1224
1225 #ifdef CONFIG_SWIOTLB
1226         if (!swiotlb_nr_tbl())
1227                 --count;
1228 #endif
1229
1230         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1231 #else
1232
1233         return 0;
1234 #endif
1235 }
1236
1237 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1238 {
1239 #if defined(CONFIG_DEBUG_FS)
1240
1241         debugfs_remove(adev->mman.vram);
1242         adev->mman.vram = NULL;
1243
1244         debugfs_remove(adev->mman.gtt);
1245         adev->mman.gtt = NULL;
1246 #endif
1247 }