drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  54 {
  55         struct amdgpu_mman *mman;
  56         struct amdgpu_device *adev;
  57
  58         mman = container_of(bdev, struct amdgpu_mman, bdev);
  59         adev = container_of(mman, struct amdgpu_device, mman);
  60         return adev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         struct amdgpu_ring *ring;
  81         struct amd_sched_rq *rq;
  82         int r;
  83
  84         adev->mman.mem_global_referenced = false;
  85         global_ref = &adev->mman.mem_global_ref;
  86         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  87         global_ref->size = sizeof(struct ttm_mem_global);
  88         global_ref->init = &amdgpu_ttm_mem_global_init;
  89         global_ref->release = &amdgpu_ttm_mem_global_release;
  90         r = drm_global_item_ref(global_ref);
  91         if (r != 0) {
  92                 DRM_ERROR("Failed setting up TTM memory accounting "
  93                           "subsystem.\n");
  94                 return r;
  95         }
  96
  97         adev->mman.bo_global_ref.mem_glob =
  98                 adev->mman.mem_global_ref.object;
  99         global_ref = &adev->mman.bo_global_ref.ref;
 100         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 101         global_ref->size = sizeof(struct ttm_bo_global);
 102         global_ref->init = &ttm_bo_global_init;
 103         global_ref->release = &ttm_bo_global_release;
 104         r = drm_global_item_ref(global_ref);
 105         if (r != 0) {
 106                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 107                 drm_global_item_unref(&adev->mman.mem_global_ref);
 108                 return r;
 109         }
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs);
 115         if (r != 0) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 drm_global_item_unref(&adev->mman.mem_global_ref);
 118                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 119                 return r;
 120         }
 121
 122         adev->mman.mem_global_referenced = true;
 123
 124         return 0;
 125 }
 126
 127 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 128 {
 129         if (adev->mman.mem_global_referenced) {
 130                 amd_sched_entity_fini(adev->mman.entity.sched,
 131                                       &adev->mman.entity);
 132                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 133                 drm_global_item_unref(&adev->mman.mem_global_ref);
 134                 adev->mman.mem_global_referenced = false;
 135         }
 136 }
 137
 138 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 139 {
 140         return 0;
 141 }
 142
 143 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 144                                 struct ttm_mem_type_manager *man)
 145 {
 146         struct amdgpu_device *adev;
 147
 148         adev = amdgpu_get_adev(bdev);
 149
 150         switch (type) {
 151         case TTM_PL_SYSTEM:
 152                 /* System memory */
 153                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 break;
 157         case TTM_PL_TT:
 158                 man->func = &ttm_bo_manager_func;
 159                 man->gpu_offset = adev->mc.gtt_start;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 163                 break;
 164         case TTM_PL_VRAM:
 165                 /* "On-card" video ram */
 166                 man->func = &ttm_bo_manager_func;
 167                 man->gpu_offset = adev->mc.vram_start;
 168                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 169                              TTM_MEMTYPE_FLAG_MAPPABLE;
 170                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 171                 man->default_caching = TTM_PL_FLAG_WC;
 172                 break;
 173         case AMDGPU_PL_GDS:
 174         case AMDGPU_PL_GWS:
 175         case AMDGPU_PL_OA:
 176                 /* On-chip GDS memory*/
 177                 man->func = &ttm_bo_manager_func;
 178                 man->gpu_offset = 0;
 179                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 180                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 181                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 182                 break;
 183         default:
 184                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 185                 return -EINVAL;
 186         }
 187         return 0;
 188 }
 189
 190 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 191                                 struct ttm_placement *placement)
 192 {
 193         struct amdgpu_bo *rbo;
 194         static struct ttm_place placements = {
 195                 .fpfn = 0,
 196                 .lpfn = 0,
 197                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 198         };
 199
 200         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 201                 placement->placement = &placements;
 202                 placement->busy_placement = &placements;
 203                 placement->num_placement = 1;
 204                 placement->num_busy_placement = 1;
 205                 return;
 206         }
 207         rbo = container_of(bo, struct amdgpu_bo, tbo);
 208         switch (bo->mem.mem_type) {
 209         case TTM_PL_VRAM:
 210                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 211                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 212                 else
 213                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 214                 break;
 215         case TTM_PL_TT:
 216         default:
 217                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 218         }
 219         *placement = rbo->placement;
 220 }
 221
 222 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 223 {
 224         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 225
 226         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 227 }
 228
 229 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 230                              struct ttm_mem_reg *new_mem)
 231 {
 232         struct ttm_mem_reg *old_mem = &bo->mem;
 233
 234         BUG_ON(old_mem->mm_node != NULL);
 235         *old_mem = *new_mem;
 236         new_mem->mm_node = NULL;
 237 }
 238
 239 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 240                         bool evict, bool no_wait_gpu,
 241                         struct ttm_mem_reg *new_mem,
 242                         struct ttm_mem_reg *old_mem)
 243 {
 244         struct amdgpu_device *adev;
 245         struct amdgpu_ring *ring;
 246         uint64_t old_start, new_start;
 247         struct fence *fence;
 248         int r;
 249
 250         adev = amdgpu_get_adev(bo->bdev);
 251         ring = adev->mman.buffer_funcs_ring;
 252         old_start = old_mem->start << PAGE_SHIFT;
 253         new_start = new_mem->start << PAGE_SHIFT;
 254
 255         switch (old_mem->mem_type) {
 256         case TTM_PL_VRAM:
 257                 old_start += adev->mc.vram_start;
 258                 break;
 259         case TTM_PL_TT:
 260                 old_start += adev->mc.gtt_start;
 261                 break;
 262         default:
 263                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 264                 return -EINVAL;
 265         }
 266         switch (new_mem->mem_type) {
 267         case TTM_PL_VRAM:
 268                 new_start += adev->mc.vram_start;
 269                 break;
 270         case TTM_PL_TT:
 271                 new_start += adev->mc.gtt_start;
 272                 break;
 273         default:
 274                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 275                 return -EINVAL;
 276         }
 277         if (!ring->ready) {
 278                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 279                 return -EINVAL;
 280         }
 281
 282         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 283
 284         r = amdgpu_copy_buffer(ring, old_start, new_start,
 285                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 286                                bo->resv, &fence);
 287         /* FIXME: handle copy error */
 288         r = ttm_bo_move_accel_cleanup(bo, fence,
 289                                       evict, no_wait_gpu, new_mem);
 290         fence_put(fence);
 291         return r;
 292 }
 293
 294 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 295                                 bool evict, bool interruptible,
 296                                 bool no_wait_gpu,
 297                                 struct ttm_mem_reg *new_mem)
 298 {
 299         struct amdgpu_device *adev;
 300         struct ttm_mem_reg *old_mem = &bo->mem;
 301         struct ttm_mem_reg tmp_mem;
 302         struct ttm_place placements;
 303         struct ttm_placement placement;
 304         int r;
 305
 306         adev = amdgpu_get_adev(bo->bdev);
 307         tmp_mem = *new_mem;
 308         tmp_mem.mm_node = NULL;
 309         placement.num_placement = 1;
 310         placement.placement = &placements;
 311         placement.num_busy_placement = 1;
 312         placement.busy_placement = &placements;
 313         placements.fpfn = 0;
 314         placements.lpfn = 0;
 315         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 316         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 317                              interruptible, no_wait_gpu);
 318         if (unlikely(r)) {
 319                 return r;
 320         }
 321
 322         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 323         if (unlikely(r)) {
 324                 goto out_cleanup;
 325         }
 326
 327         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 328         if (unlikely(r)) {
 329                 goto out_cleanup;
 330         }
 331         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 332         if (unlikely(r)) {
 333                 goto out_cleanup;
 334         }
 335         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 336 out_cleanup:
 337         ttm_bo_mem_put(bo, &tmp_mem);
 338         return r;
 339 }
 340
 341 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 342                                 bool evict, bool interruptible,
 343                                 bool no_wait_gpu,
 344                                 struct ttm_mem_reg *new_mem)
 345 {
 346         struct amdgpu_device *adev;
 347         struct ttm_mem_reg *old_mem = &bo->mem;
 348         struct ttm_mem_reg tmp_mem;
 349         struct ttm_placement placement;
 350         struct ttm_place placements;
 351         int r;
 352
 353         adev = amdgpu_get_adev(bo->bdev);
 354         tmp_mem = *new_mem;
 355         tmp_mem.mm_node = NULL;
 356         placement.num_placement = 1;
 357         placement.placement = &placements;
 358         placement.num_busy_placement = 1;
 359         placement.busy_placement = &placements;
 360         placements.fpfn = 0;
 361         placements.lpfn = 0;
 362         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 363         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 364                              interruptible, no_wait_gpu);
 365         if (unlikely(r)) {
 366                 return r;
 367         }
 368         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 369         if (unlikely(r)) {
 370                 goto out_cleanup;
 371         }
 372         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 373         if (unlikely(r)) {
 374                 goto out_cleanup;
 375         }
 376 out_cleanup:
 377         ttm_bo_mem_put(bo, &tmp_mem);
 378         return r;
 379 }
 380
 381 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 382                         bool evict, bool interruptible,
 383                         bool no_wait_gpu,
 384                         struct ttm_mem_reg *new_mem)
 385 {
 386         struct amdgpu_device *adev;
 387         struct ttm_mem_reg *old_mem = &bo->mem;
 388         int r;
 389
 390         adev = amdgpu_get_adev(bo->bdev);
 391         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 392                 amdgpu_move_null(bo, new_mem);
 393                 return 0;
 394         }
 395         if ((old_mem->mem_type == TTM_PL_TT &&
 396              new_mem->mem_type == TTM_PL_SYSTEM) ||
 397             (old_mem->mem_type == TTM_PL_SYSTEM &&
 398              new_mem->mem_type == TTM_PL_TT)) {
 399                 /* bind is enough */
 400                 amdgpu_move_null(bo, new_mem);
 401                 return 0;
 402         }
 403         if (adev->mman.buffer_funcs == NULL ||
 404             adev->mman.buffer_funcs_ring == NULL ||
 405             !adev->mman.buffer_funcs_ring->ready) {
 406                 /* use memcpy */
 407                 goto memcpy;
 408         }
 409
 410         if (old_mem->mem_type == TTM_PL_VRAM &&
 411             new_mem->mem_type == TTM_PL_SYSTEM) {
 412                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 413                                         no_wait_gpu, new_mem);
 414         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 415                    new_mem->mem_type == TTM_PL_VRAM) {
 416                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 417                                             no_wait_gpu, new_mem);
 418         } else {
 419                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 420         }
 421
 422         if (r) {
 423 memcpy:
 424                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 425                 if (r) {
 426                         return r;
 427                 }
 428         }
 429
 430         /* update statistics */
 431         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 432         return 0;
 433 }
 434
 435 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 436 {
 437         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 438         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 439
 440         mem->bus.addr = NULL;
 441         mem->bus.offset = 0;
 442         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 443         mem->bus.base = 0;
 444         mem->bus.is_iomem = false;
 445         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 446                 return -EINVAL;
 447         switch (mem->mem_type) {
 448         case TTM_PL_SYSTEM:
 449                 /* system memory */
 450                 return 0;
 451         case TTM_PL_TT:
 452                 break;
 453         case TTM_PL_VRAM:
 454                 mem->bus.offset = mem->start << PAGE_SHIFT;
 455                 /* check if it's visible */
 456                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 457                         return -EINVAL;
 458                 mem->bus.base = adev->mc.aper_base;
 459                 mem->bus.is_iomem = true;
 460 #ifdef __alpha__
 461                 /*
 462                  * Alpha: use bus.addr to hold the ioremap() return,
 463                  * so we can modify bus.base below.
 464                  */
 465                 if (mem->placement & TTM_PL_FLAG_WC)
 466                         mem->bus.addr =
 467                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 468                                            mem->bus.size);
 469                 else
 470                         mem->bus.addr =
 471                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 472                                                 mem->bus.size);
 473
 474                 /*
 475                  * Alpha: Use just the bus offset plus
 476                  * the hose/domain memory base for bus.base.
 477                  * It then can be used to build PTEs for VRAM
 478                  * access, as done in ttm_bo_vm_fault().
 479                  */
 480                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 481                         adev->ddev->hose->dense_mem_base;
 482 #endif
 483                 break;
 484         default:
 485                 return -EINVAL;
 486         }
 487         return 0;
 488 }
 489
 490 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 491 {
 492 }
 493
 494 /*
 495  * TTM backend functions.
 496  */
 497 struct amdgpu_ttm_gup_task_list {
 498         struct list_head        list;
 499         struct task_struct      *task;
 500 };
 501
 502 struct amdgpu_ttm_tt {
 503         struct ttm_dma_tt       ttm;
 504         struct amdgpu_device    *adev;
 505         u64                     offset;
 506         uint64_t                userptr;
 507         struct mm_struct        *usermm;
 508         uint32_t                userflags;
 509         spinlock_t              guptasklock;
 510         struct list_head        guptasks;
 511         atomic_t                mmu_invalidations;
 512 };
 513
 514 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 515 {
 516         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 517         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 518         unsigned pinned = 0;
 519         int r;
 520
 521         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 522                 /* check that we only use anonymous memory
 523                    to prevent problems with writeback */
 524                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 525                 struct vm_area_struct *vma;
 526
 527                 vma = find_vma(gtt->usermm, gtt->userptr);
 528                 if (!vma || vma->vm_file || vma->vm_end < end)
 529                         return -EPERM;
 530         }
 531
 532         do {
 533                 unsigned num_pages = ttm->num_pages - pinned;
 534                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 535                 struct page **p = pages + pinned;
 536                 struct amdgpu_ttm_gup_task_list guptask;
 537
 538                 guptask.task = current;
 539                 spin_lock(&gtt->guptasklock);
 540                 list_add(&guptask.list, &gtt->guptasks);
 541                 spin_unlock(&gtt->guptasklock);
 542
 543                 r = get_user_pages(current, current->mm, userptr, num_pages,
 544                                    write, 0, p, NULL);
 545
 546                 spin_lock(&gtt->guptasklock);
 547                 list_del(&guptask.list);
 548                 spin_unlock(&gtt->guptasklock);
 549
 550                 if (r < 0)
 551                         goto release_pages;
 552
 553                 pinned += r;
 554
 555         } while (pinned < ttm->num_pages);
 556
 557         return 0;
 558
 559 release_pages:
 560         release_pages(pages, pinned, 0);
 561         return r;
 562 }
 563
 564 /* prepare the sg table with the user pages */
 565 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 566 {
 567         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 568         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 569         unsigned nents;
 570         int r;
 571
 572         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 573         enum dma_data_direction direction = write ?
 574                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 575
 576         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 577                                       ttm->num_pages << PAGE_SHIFT,
 578                                       GFP_KERNEL);
 579         if (r)
 580                 goto release_sg;
 581
 582         r = -ENOMEM;
 583         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 584         if (nents != ttm->sg->nents)
 585                 goto release_sg;
 586
 587         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 588                                          gtt->ttm.dma_address, ttm->num_pages);
 589
 590         return 0;
 591
 592 release_sg:
 593         kfree(ttm->sg);
 594         return r;
 595 }
 596
 597 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 598 {
 599         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 600         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 601         struct sg_page_iter sg_iter;
 602
 603         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 604         enum dma_data_direction direction = write ?
 605                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 606
 607         /* double check that we don't free the table twice */
 608         if (!ttm->sg->sgl)
 609                 return;
 610
 611         /* free the sg table and pages again */
 612         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 613
 614         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 615                 struct page *page = sg_page_iter_page(&sg_iter);
 616                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 617                         set_page_dirty(page);
 618
 619                 mark_page_accessed(page);
 620                 page_cache_release(page);
 621         }
 622
 623         sg_free_table(ttm->sg);
 624 }
 625
 626 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 627                                    struct ttm_mem_reg *bo_mem)
 628 {
 629         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 630         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 631         int r;
 632
 633         if (gtt->userptr) {
 634                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 635                 if (r) {
 636                         DRM_ERROR("failed to pin userptr\n");
 637                         return r;
 638                 }
 639         }
 640         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 641         if (!ttm->num_pages) {
 642                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 643                      ttm->num_pages, bo_mem, ttm);
 644         }
 645
 646         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 647             bo_mem->mem_type == AMDGPU_PL_GWS ||
 648             bo_mem->mem_type == AMDGPU_PL_OA)
 649                 return -EINVAL;
 650
 651         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 652                 ttm->pages, gtt->ttm.dma_address, flags);
 653
 654         if (r) {
 655                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 656                           ttm->num_pages, (unsigned)gtt->offset);
 657                 return r;
 658         }
 659         return 0;
 660 }
 661
 662 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 663 {
 664         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 665
 666         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 667         if (gtt->adev->gart.ready)
 668                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 669
 670         if (gtt->userptr)
 671                 amdgpu_ttm_tt_unpin_userptr(ttm);
 672
 673         return 0;
 674 }
 675
 676 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 677 {
 678         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 679
 680         ttm_dma_tt_fini(&gtt->ttm);
 681         kfree(gtt);
 682 }
 683
 684 static struct ttm_backend_func amdgpu_backend_func = {
 685         .bind = &amdgpu_ttm_backend_bind,
 686         .unbind = &amdgpu_ttm_backend_unbind,
 687         .destroy = &amdgpu_ttm_backend_destroy,
 688 };
 689
 690 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 691                                     unsigned long size, uint32_t page_flags,
 692                                     struct page *dummy_read_page)
 693 {
 694         struct amdgpu_device *adev;
 695         struct amdgpu_ttm_tt *gtt;
 696
 697         adev = amdgpu_get_adev(bdev);
 698
 699         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 700         if (gtt == NULL) {
 701                 return NULL;
 702         }
 703         gtt->ttm.ttm.func = &amdgpu_backend_func;
 704         gtt->adev = adev;
 705         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 706                 kfree(gtt);
 707                 return NULL;
 708         }
 709         return &gtt->ttm.ttm;
 710 }
 711
 712 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 713 {
 714         struct amdgpu_device *adev;
 715         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 716         unsigned i;
 717         int r;
 718         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 719
 720         if (ttm->state != tt_unpopulated)
 721                 return 0;
 722
 723         if (gtt && gtt->userptr) {
 724                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 725                 if (!ttm->sg)
 726                         return -ENOMEM;
 727
 728                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 729                 ttm->state = tt_unbound;
 730                 return 0;
 731         }
 732
 733         if (slave && ttm->sg) {
 734                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 735                                                  gtt->ttm.dma_address, ttm->num_pages);
 736                 ttm->state = tt_unbound;
 737                 return 0;
 738         }
 739
 740         adev = amdgpu_get_adev(ttm->bdev);
 741
 742 #ifdef CONFIG_SWIOTLB
 743         if (swiotlb_nr_tbl()) {
 744                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 745         }
 746 #endif
 747
 748         r = ttm_pool_populate(ttm);
 749         if (r) {
 750                 return r;
 751         }
 752
 753         for (i = 0; i < ttm->num_pages; i++) {
 754                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 755                                                        0, PAGE_SIZE,
 756                                                        PCI_DMA_BIDIRECTIONAL);
 757                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 758                         while (i--) {
 759                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 760                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 761                                 gtt->ttm.dma_address[i] = 0;
 762                         }
 763                         ttm_pool_unpopulate(ttm);
 764                         return -EFAULT;
 765                 }
 766         }
 767         return 0;
 768 }
 769
 770 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 771 {
 772         struct amdgpu_device *adev;
 773         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 774         unsigned i;
 775         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 776
 777         if (gtt && gtt->userptr) {
 778                 kfree(ttm->sg);
 779                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 780                 return;
 781         }
 782
 783         if (slave)
 784                 return;
 785
 786         adev = amdgpu_get_adev(ttm->bdev);
 787
 788 #ifdef CONFIG_SWIOTLB
 789         if (swiotlb_nr_tbl()) {
 790                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 791                 return;
 792         }
 793 #endif
 794
 795         for (i = 0; i < ttm->num_pages; i++) {
 796                 if (gtt->ttm.dma_address[i]) {
 797                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 798                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 799                 }
 800         }
 801
 802         ttm_pool_unpopulate(ttm);
 803 }
 804
 805 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 806                               uint32_t flags)
 807 {
 808         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 809
 810         if (gtt == NULL)
 811                 return -EINVAL;
 812
 813         gtt->userptr = addr;
 814         gtt->usermm = current->mm;
 815         gtt->userflags = flags;
 816         spin_lock_init(&gtt->guptasklock);
 817         INIT_LIST_HEAD(&gtt->guptasks);
 818         atomic_set(&gtt->mmu_invalidations, 0);
 819
 820         return 0;
 821 }
 822
 823 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 824 {
 825         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 826
 827         if (gtt == NULL)
 828                 return NULL;
 829
 830         return gtt->usermm;
 831 }
 832
 833 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 834                                   unsigned long end)
 835 {
 836         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 837         struct amdgpu_ttm_gup_task_list *entry;
 838         unsigned long size;
 839
 840         if (gtt == NULL || !gtt->userptr)
 841                 return false;
 842
 843         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 844         if (gtt->userptr > end || gtt->userptr + size <= start)
 845                 return false;
 846
 847         spin_lock(&gtt->guptasklock);
 848         list_for_each_entry(entry, &gtt->guptasks, list) {
 849                 if (entry->task == current) {
 850                         spin_unlock(&gtt->guptasklock);
 851                         return false;
 852                 }
 853         }
 854         spin_unlock(&gtt->guptasklock);
 855
 856         atomic_inc(&gtt->mmu_invalidations);
 857
 858         return true;
 859 }
 860
 861 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 862                                        int *last_invalidated)
 863 {
 864         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 865         int prev_invalidated = *last_invalidated;
 866
 867         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 868         return prev_invalidated != *last_invalidated;
 869 }
 870
 871 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 872 {
 873         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 874
 875         if (gtt == NULL)
 876                 return false;
 877
 878         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 879 }
 880
 881 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 882                                  struct ttm_mem_reg *mem)
 883 {
 884         uint32_t flags = 0;
 885
 886         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 887                 flags |= AMDGPU_PTE_VALID;
 888
 889         if (mem && mem->mem_type == TTM_PL_TT) {
 890                 flags |= AMDGPU_PTE_SYSTEM;
 891
 892                 if (ttm->caching_state == tt_cached)
 893                         flags |= AMDGPU_PTE_SNOOPED;
 894         }
 895
 896         if (adev->asic_type >= CHIP_TONGA)
 897                 flags |= AMDGPU_PTE_EXECUTABLE;
 898
 899         flags |= AMDGPU_PTE_READABLE;
 900
 901         if (!amdgpu_ttm_tt_is_readonly(ttm))
 902                 flags |= AMDGPU_PTE_WRITEABLE;
 903
 904         return flags;
 905 }
 906
 907 static struct ttm_bo_driver amdgpu_bo_driver = {
 908         .ttm_tt_create = &amdgpu_ttm_tt_create,
 909         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 910         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 911         .invalidate_caches = &amdgpu_invalidate_caches,
 912         .init_mem_type = &amdgpu_init_mem_type,
 913         .evict_flags = &amdgpu_evict_flags,
 914         .move = &amdgpu_bo_move,
 915         .verify_access = &amdgpu_verify_access,
 916         .move_notify = &amdgpu_bo_move_notify,
 917         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 918         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 919         .io_mem_free = &amdgpu_ttm_io_mem_free,
 920 };
 921
 922 int amdgpu_ttm_init(struct amdgpu_device *adev)
 923 {
 924         int r;
 925
 926         r = amdgpu_ttm_global_init(adev);
 927         if (r) {
 928                 return r;
 929         }
 930         /* No others user of address space so set it to 0 */
 931         r = ttm_bo_device_init(&adev->mman.bdev,
 932                                adev->mman.bo_global_ref.ref.object,
 933                                &amdgpu_bo_driver,
 934                                adev->ddev->anon_inode->i_mapping,
 935                                DRM_FILE_PAGE_OFFSET,
 936                                adev->need_dma32);
 937         if (r) {
 938                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 939                 return r;
 940         }
 941         adev->mman.initialized = true;
 942         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
 943                                 adev->mc.real_vram_size >> PAGE_SHIFT);
 944         if (r) {
 945                 DRM_ERROR("Failed initializing VRAM heap.\n");
 946                 return r;
 947         }
 948         /* Change the size here instead of the init above so only lpfn is affected */
 949         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 950
 951         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
 952                              AMDGPU_GEM_DOMAIN_VRAM,
 953                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 954                              NULL, NULL, &adev->stollen_vga_memory);
 955         if (r) {
 956                 return r;
 957         }
 958         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 959         if (r)
 960                 return r;
 961         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
 962         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 963         if (r) {
 964                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 965                 return r;
 966         }
 967         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 968                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
 969         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
 970                                 adev->mc.gtt_size >> PAGE_SHIFT);
 971         if (r) {
 972                 DRM_ERROR("Failed initializing GTT heap.\n");
 973                 return r;
 974         }
 975         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
 976                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
 977
 978         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
 979         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
 980         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
 981         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
 982         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
 983         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
 984         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
 985         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
 986         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
 987         /* GDS Memory */
 988         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
 989                                 adev->gds.mem.total_size >> PAGE_SHIFT);
 990         if (r) {
 991                 DRM_ERROR("Failed initializing GDS heap.\n");
 992                 return r;
 993         }
 994
 995         /* GWS */
 996         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
 997                                 adev->gds.gws.total_size >> PAGE_SHIFT);
 998         if (r) {
 999                 DRM_ERROR("Failed initializing gws heap.\n");
1000                 return r;
1001         }
1002
1003         /* OA */
1004         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1005                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1006         if (r) {
1007                 DRM_ERROR("Failed initializing oa heap.\n");
1008                 return r;
1009         }
1010
1011         r = amdgpu_ttm_debugfs_init(adev);
1012         if (r) {
1013                 DRM_ERROR("Failed to init debugfs\n");
1014                 return r;
1015         }
1016         return 0;
1017 }
1018
1019 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1020 {
1021         int r;
1022
1023         if (!adev->mman.initialized)
1024                 return;
1025         amdgpu_ttm_debugfs_fini(adev);
1026         if (adev->stollen_vga_memory) {
1027                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1028                 if (r == 0) {
1029                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1030                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1031                 }
1032                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1033         }
1034         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1035         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1036         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1037         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1038         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1039         ttm_bo_device_release(&adev->mman.bdev);
1040         amdgpu_gart_fini(adev);
1041         amdgpu_ttm_global_fini(adev);
1042         adev->mman.initialized = false;
1043         DRM_INFO("amdgpu: ttm finalized\n");
1044 }
1045
1046 /* this should only be called at bootup or when userspace
1047  * isn't running */
1048 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1049 {
1050         struct ttm_mem_type_manager *man;
1051
1052         if (!adev->mman.initialized)
1053                 return;
1054
1055         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1056         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1057         man->size = size >> PAGE_SHIFT;
1058 }
1059
1060 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1061 {
1062         struct drm_file *file_priv;
1063         struct amdgpu_device *adev;
1064
1065         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1066                 return -EINVAL;
1067
1068         file_priv = filp->private_data;
1069         adev = file_priv->minor->dev->dev_private;
1070         if (adev == NULL)
1071                 return -EINVAL;
1072
1073         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1074 }
1075
1076 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1077                        uint64_t src_offset,
1078                        uint64_t dst_offset,
1079                        uint32_t byte_count,
1080                        struct reservation_object *resv,
1081                        struct fence **fence)
1082 {
1083         struct amdgpu_device *adev = ring->adev;
1084         struct amdgpu_job *job;
1085
1086         uint32_t max_bytes;
1087         unsigned num_loops, num_dw;
1088         unsigned i;
1089         int r;
1090
1091         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1092         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1093         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1094
1095         /* for IB padding */
1096         while (num_dw & 0x7)
1097                 num_dw++;
1098
1099         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1100         if (r)
1101                 return r;
1102
1103         if (resv) {
1104                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1105                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1106                 if (r) {
1107                         DRM_ERROR("sync failed (%d).\n", r);
1108                         goto error_free;
1109                 }
1110         }
1111
1112         for (i = 0; i < num_loops; i++) {
1113                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1114
1115                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1116                                         dst_offset, cur_size_in_bytes);
1117
1118                 src_offset += cur_size_in_bytes;
1119                 dst_offset += cur_size_in_bytes;
1120                 byte_count -= cur_size_in_bytes;
1121         }
1122
1123         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1124         WARN_ON(job->ibs[0].length_dw > num_dw);
1125         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1126                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1127         if (r)
1128                 goto error_free;
1129
1130         return 0;
1131
1132 error_free:
1133         amdgpu_job_free(job);
1134         return r;
1135 }
1136
1137 #if defined(CONFIG_DEBUG_FS)
1138
1139 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1140 {
1141         struct drm_info_node *node = (struct drm_info_node *)m->private;
1142         unsigned ttm_pl = *(int *)node->info_ent->data;
1143         struct drm_device *dev = node->minor->dev;
1144         struct amdgpu_device *adev = dev->dev_private;
1145         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1146         int ret;
1147         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1148
1149         spin_lock(&glob->lru_lock);
1150         ret = drm_mm_dump_table(m, mm);
1151         spin_unlock(&glob->lru_lock);
1152         if (ttm_pl == TTM_PL_VRAM)
1153                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1154                            adev->mman.bdev.man[ttm_pl].size,
1155                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1156                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1157         return ret;
1158 }
1159
1160 static int ttm_pl_vram = TTM_PL_VRAM;
1161 static int ttm_pl_tt = TTM_PL_TT;
1162
1163 static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1164         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1165         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1166         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1167 #ifdef CONFIG_SWIOTLB
1168         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1169 #endif
1170 };
1171
1172 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1173                                     size_t size, loff_t *pos)
1174 {
1175         struct amdgpu_device *adev = f->f_inode->i_private;
1176         ssize_t result = 0;
1177         int r;
1178
1179         if (size & 0x3 || *pos & 0x3)
1180                 return -EINVAL;
1181
1182         while (size) {
1183                 unsigned long flags;
1184                 uint32_t value;
1185
1186                 if (*pos >= adev->mc.mc_vram_size)
1187                         return result;
1188
1189                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1190                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1191                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1192                 value = RREG32(mmMM_DATA);
1193                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1194
1195                 r = put_user(value, (uint32_t *)buf);
1196                 if (r)
1197                         return r;
1198
1199                 result += 4;
1200                 buf += 4;
1201                 *pos += 4;
1202                 size -= 4;
1203         }
1204
1205         return result;
1206 }
1207
1208 static const struct file_operations amdgpu_ttm_vram_fops = {
1209         .owner = THIS_MODULE,
1210         .read = amdgpu_ttm_vram_read,
1211         .llseek = default_llseek
1212 };
1213
1214 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1215                                    size_t size, loff_t *pos)
1216 {
1217         struct amdgpu_device *adev = f->f_inode->i_private;
1218         ssize_t result = 0;
1219         int r;
1220
1221         while (size) {
1222                 loff_t p = *pos / PAGE_SIZE;
1223                 unsigned off = *pos & ~PAGE_MASK;
1224                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1225                 struct page *page;
1226                 void *ptr;
1227
1228                 if (p >= adev->gart.num_cpu_pages)
1229                         return result;
1230
1231                 page = adev->gart.pages[p];
1232                 if (page) {
1233                         ptr = kmap(page);
1234                         ptr += off;
1235
1236                         r = copy_to_user(buf, ptr, cur_size);
1237                         kunmap(adev->gart.pages[p]);
1238                 } else
1239                         r = clear_user(buf, cur_size);
1240
1241                 if (r)
1242                         return -EFAULT;
1243
1244                 result += cur_size;
1245                 buf += cur_size;
1246                 *pos += cur_size;
1247                 size -= cur_size;
1248         }
1249
1250         return result;
1251 }
1252
1253 static const struct file_operations amdgpu_ttm_gtt_fops = {
1254         .owner = THIS_MODULE,
1255         .read = amdgpu_ttm_gtt_read,
1256         .llseek = default_llseek
1257 };
1258
1259 #endif
1260
1261 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1262 {
1263 #if defined(CONFIG_DEBUG_FS)
1264         unsigned count;
1265
1266         struct drm_minor *minor = adev->ddev->primary;
1267         struct dentry *ent, *root = minor->debugfs_root;
1268
1269         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1270                                   adev, &amdgpu_ttm_vram_fops);
1271         if (IS_ERR(ent))
1272                 return PTR_ERR(ent);
1273         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1274         adev->mman.vram = ent;
1275
1276         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1277                                   adev, &amdgpu_ttm_gtt_fops);
1278         if (IS_ERR(ent))
1279                 return PTR_ERR(ent);
1280         i_size_write(ent->d_inode, adev->mc.gtt_size);
1281         adev->mman.gtt = ent;
1282
1283         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1284
1285 #ifdef CONFIG_SWIOTLB
1286         if (!swiotlb_nr_tbl())
1287                 --count;
1288 #endif
1289
1290         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1291 #else
1292
1293         return 0;
1294 #endif
1295 }
1296
1297 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1298 {
1299 #if defined(CONFIG_DEBUG_FS)
1300
1301         debugfs_remove(adev->mman.vram);
1302         adev->mman.vram = NULL;
1303
1304         debugfs_remove(adev->mman.gtt);
1305         adev->mman.gtt = NULL;
1306 #endif
1307 }