drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include "amdgpu.h"
  35 #include "atom.h"
  36
  37 /*
  38  * Rings
  39  * Most engines on the GPU are fed via ring buffers.  Ring
  40  * buffers are areas of GPU accessible memory that the host
  41  * writes commands into and the GPU reads commands out of.
  42  * There is a rptr (read pointer) that determines where the
  43  * GPU is currently reading, and a wptr (write pointer)
  44  * which determines where the host has written.  When the
  45  * pointers are equal, the ring is idle.  When the host
  46  * writes commands to the ring buffer, it increments the
  47  * wptr.  The GPU then starts fetching commands and executes
  48  * them until the pointers are equal again.
  49  */
  50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
  51                                     struct amdgpu_ring *ring);
  52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
  53
  54 /**
  55  * amdgpu_ring_alloc - allocate space on the ring buffer
  56  *
  57  * @adev: amdgpu_device pointer
  58  * @ring: amdgpu_ring structure holding ring information
  59  * @ndw: number of dwords to allocate in the ring buffer
  60  *
  61  * Allocate @ndw dwords in the ring buffer (all asics).
  62  * Returns 0 on success, error on failure.
  63  */
  64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
  65 {
  66         /* Align requested size with padding so unlock_commit can
  67          * pad safely */
  68         ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
  69
  70         /* Make sure we aren't trying to allocate more space
  71          * than the maximum for one submission
  72          */
  73         if (WARN_ON_ONCE(ndw > ring->max_dw))
  74                 return -ENOMEM;
  75
  76         ring->count_dw = ndw;
  77         ring->wptr_old = ring->wptr;
  78
  79         if (ring->funcs->begin_use)
  80                 ring->funcs->begin_use(ring);
  81
  82         return 0;
  83 }
  84
  85 /** amdgpu_ring_insert_nop - insert NOP packets
  86  *
  87  * @ring: amdgpu_ring structure holding ring information
  88  * @count: the number of NOP packets to insert
  89  *
  90  * This is the generic insert_nop function for rings except SDMA
  91  */
  92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  93 {
  94         int i;
  95
  96         for (i = 0; i < count; i++)
  97                 amdgpu_ring_write(ring, ring->funcs->nop);
  98 }
  99
 100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
 101  *
 102  * @ring: amdgpu_ring structure holding ring information
 103  * @ib: IB to add NOP packets to
 104  *
 105  * This is the generic pad_ib function for rings except SDMA
 106  */
 107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 108 {
 109         while (ib->length_dw & ring->funcs->align_mask)
 110                 ib->ptr[ib->length_dw++] = ring->funcs->nop;
 111 }
 112
 113 /**
 114  * amdgpu_ring_commit - tell the GPU to execute the new
 115  * commands on the ring buffer
 116  *
 117  * @adev: amdgpu_device pointer
 118  * @ring: amdgpu_ring structure holding ring information
 119  *
 120  * Update the wptr (write pointer) to tell the GPU to
 121  * execute new commands on the ring buffer (all asics).
 122  */
 123 void amdgpu_ring_commit(struct amdgpu_ring *ring)
 124 {
 125         uint32_t count;
 126
 127         /* We pad to match fetch size */
 128         count = ring->funcs->align_mask + 1 -
 129                 (ring->wptr & ring->funcs->align_mask);
 130         count %= ring->funcs->align_mask + 1;
 131         ring->funcs->insert_nop(ring, count);
 132
 133         mb();
 134         amdgpu_ring_set_wptr(ring);
 135
 136         if (ring->funcs->end_use)
 137                 ring->funcs->end_use(ring);
 138
 139         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
 140                 amdgpu_ring_lru_touch(ring->adev, ring);
 141 }
 142
 143 /**
 144  * amdgpu_ring_undo - reset the wptr
 145  *
 146  * @ring: amdgpu_ring structure holding ring information
 147  *
 148  * Reset the driver's copy of the wptr (all asics).
 149  */
 150 void amdgpu_ring_undo(struct amdgpu_ring *ring)
 151 {
 152         ring->wptr = ring->wptr_old;
 153
 154         if (ring->funcs->end_use)
 155                 ring->funcs->end_use(ring);
 156 }
 157
 158 /**
 159  * amdgpu_ring_priority_put - restore a ring's priority
 160  *
 161  * @ring: amdgpu_ring structure holding the information
 162  * @priority: target priority
 163  *
 164  * Release a request for executing at @priority
 165  */
 166 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
 167                               enum drm_sched_priority priority)
 168 {
 169         int i;
 170
 171         if (!ring->funcs->set_priority)
 172                 return;
 173
 174         if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
 175                 return;
 176
 177         /* no need to restore if the job is already at the lowest priority */
 178         if (priority == DRM_SCHED_PRIORITY_NORMAL)
 179                 return;
 180
 181         mutex_lock(&ring->priority_mutex);
 182         /* something higher prio is executing, no need to decay */
 183         if (ring->priority > priority)
 184                 goto out_unlock;
 185
 186         /* decay priority to the next level with a job available */
 187         for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
 188                 if (i == DRM_SCHED_PRIORITY_NORMAL
 189                                 || atomic_read(&ring->num_jobs[i])) {
 190                         ring->priority = i;
 191                         ring->funcs->set_priority(ring, i);
 192                         break;
 193                 }
 194         }
 195
 196 out_unlock:
 197         mutex_unlock(&ring->priority_mutex);
 198 }
 199
 200 /**
 201  * amdgpu_ring_priority_get - change the ring's priority
 202  *
 203  * @ring: amdgpu_ring structure holding the information
 204  * @priority: target priority
 205  *
 206  * Request a ring's priority to be raised to @priority (refcounted).
 207  */
 208 void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
 209                               enum drm_sched_priority priority)
 210 {
 211         if (!ring->funcs->set_priority)
 212                 return;
 213
 214         atomic_inc(&ring->num_jobs[priority]);
 215
 216         mutex_lock(&ring->priority_mutex);
 217         if (priority <= ring->priority)
 218                 goto out_unlock;
 219
 220         ring->priority = priority;
 221         ring->funcs->set_priority(ring, priority);
 222
 223 out_unlock:
 224         mutex_unlock(&ring->priority_mutex);
 225 }
 226
 227 /**
 228  * amdgpu_ring_init - init driver ring struct.
 229  *
 230  * @adev: amdgpu_device pointer
 231  * @ring: amdgpu_ring structure holding ring information
 232  * @max_ndw: maximum number of dw for ring alloc
 233  * @nop: nop packet for this ring
 234  *
 235  * Initialize the driver information for the selected ring (all asics).
 236  * Returns 0 on success, error on failure.
 237  */
 238 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 239                      unsigned max_dw, struct amdgpu_irq_src *irq_src,
 240                      unsigned irq_type)
 241 {
 242         int r, i;
 243         int sched_hw_submission = amdgpu_sched_hw_submission;
 244
 245         /* Set the hw submission limit higher for KIQ because
 246          * it's used for a number of gfx/compute tasks by both
 247          * KFD and KGD which may have outstanding fences and
 248          * it doesn't really use the gpu scheduler anyway;
 249          * KIQ tasks get submitted directly to the ring.
 250          */
 251         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 252                 sched_hw_submission = max(sched_hw_submission, 256);
 253
 254         if (ring->adev == NULL) {
 255                 if (adev->num_rings >= AMDGPU_MAX_RINGS)
 256                         return -EINVAL;
 257
 258                 ring->adev = adev;
 259                 ring->idx = adev->num_rings++;
 260                 adev->rings[ring->idx] = ring;
 261                 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
 262                 if (r)
 263                         return r;
 264         }
 265
 266         r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
 267         if (r) {
 268                 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
 269                 return r;
 270         }
 271
 272         r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
 273         if (r) {
 274                 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
 275                 return r;
 276         }
 277
 278         r = amdgpu_device_wb_get(adev, &ring->fence_offs);
 279         if (r) {
 280                 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
 281                 return r;
 282         }
 283
 284         r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
 285         if (r) {
 286                 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
 287                 return r;
 288         }
 289         ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
 290         ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
 291         /* always set cond_exec_polling to CONTINUE */
 292         *ring->cond_exe_cpu_addr = 1;
 293
 294         r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
 295         if (r) {
 296                 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
 297                 return r;
 298         }
 299
 300         ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 301
 302         ring->buf_mask = (ring->ring_size / 4) - 1;
 303         ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
 304                 0xffffffffffffffff : ring->buf_mask;
 305         /* Allocate ring buffer */
 306         if (ring->ring_obj == NULL) {
 307                 r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 308                                             AMDGPU_GEM_DOMAIN_GTT,
 309                                             &ring->ring_obj,
 310                                             &ring->gpu_addr,
 311                                             (void **)&ring->ring);
 312                 if (r) {
 313                         dev_err(adev->dev, "(%d) ring create failed\n", r);
 314                         return r;
 315                 }
 316                 amdgpu_ring_clear_ring(ring);
 317         }
 318
 319         ring->max_dw = max_dw;
 320         ring->priority = DRM_SCHED_PRIORITY_NORMAL;
 321         mutex_init(&ring->priority_mutex);
 322         INIT_LIST_HEAD(&ring->lru_list);
 323         amdgpu_ring_lru_touch(adev, ring);
 324
 325         for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
 326                 atomic_set(&ring->num_jobs[i], 0);
 327
 328         if (amdgpu_debugfs_ring_init(adev, ring)) {
 329                 DRM_ERROR("Failed to register debugfs file for rings !\n");
 330         }
 331
 332         return 0;
 333 }
 334
 335 /**
 336  * amdgpu_ring_fini - tear down the driver ring struct.
 337  *
 338  * @adev: amdgpu_device pointer
 339  * @ring: amdgpu_ring structure holding ring information
 340  *
 341  * Tear down the driver information for the selected ring (all asics).
 342  */
 343 void amdgpu_ring_fini(struct amdgpu_ring *ring)
 344 {
 345         ring->ready = false;
 346
 347         /* Not to finish a ring which is not initialized */
 348         if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
 349                 return;
 350
 351         amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
 352         amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
 353
 354         amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
 355         amdgpu_device_wb_free(ring->adev, ring->fence_offs);
 356
 357         amdgpu_bo_free_kernel(&ring->ring_obj,
 358                               &ring->gpu_addr,
 359                               (void **)&ring->ring);
 360
 361         amdgpu_debugfs_ring_fini(ring);
 362
 363         ring->adev->rings[ring->idx] = NULL;
 364 }
 365
 366 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev,
 367                                          struct amdgpu_ring *ring)
 368 {
 369         /* list_move_tail handles the case where ring isn't part of the list */
 370         list_move_tail(&ring->lru_list, &adev->ring_lru_list);
 371 }
 372
 373 static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
 374                                        int *blacklist, int num_blacklist)
 375 {
 376         int i;
 377
 378         for (i = 0; i < num_blacklist; i++) {
 379                 if (ring->idx == blacklist[i])
 380                         return true;
 381         }
 382
 383         return false;
 384 }
 385
 386 /**
 387  * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
 388  *
 389  * @adev: amdgpu_device pointer
 390  * @type: amdgpu_ring_type enum
 391  * @blacklist: blacklisted ring ids array
 392  * @num_blacklist: number of entries in @blacklist
 393  * @lru_pipe_order: find a ring from the least recently used pipe
 394  * @ring: output ring
 395  *
 396  * Retrieve the amdgpu_ring structure for the least recently used ring of
 397  * a specific IP block (all asics).
 398  * Returns 0 on success, error on failure.
 399  */
 400 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
 401                         int *blacklist, int num_blacklist,
 402                         bool lru_pipe_order, struct amdgpu_ring **ring)
 403 {
 404         struct amdgpu_ring *entry;
 405
 406         /* List is sorted in LRU order, find first entry corresponding
 407          * to the desired HW IP */
 408         *ring = NULL;
 409         spin_lock(&adev->ring_lru_list_lock);
 410         list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
 411                 if (entry->funcs->type != type)
 412                         continue;
 413
 414                 if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
 415                         continue;
 416
 417                 if (!*ring) {
 418                         *ring = entry;
 419
 420                         /* We are done for ring LRU */
 421                         if (!lru_pipe_order)
 422                                 break;
 423                 }
 424
 425                 /* Move all rings on the same pipe to the end of the list */
 426                 if (entry->pipe == (*ring)->pipe)
 427                         amdgpu_ring_lru_touch_locked(adev, entry);
 428         }
 429
 430         /* Move the ring we found to the end of the list */
 431         if (*ring)
 432                 amdgpu_ring_lru_touch_locked(adev, *ring);
 433
 434         spin_unlock(&adev->ring_lru_list_lock);
 435
 436         if (!*ring) {
 437                 DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
 438                 return -EINVAL;
 439         }
 440
 441         return 0;
 442 }
 443
 444 /**
 445  * amdgpu_ring_lru_touch - mark a ring as recently being used
 446  *
 447  * @adev: amdgpu_device pointer
 448  * @ring: ring to touch
 449  *
 450  * Move @ring to the tail of the lru list
 451  */
 452 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 453 {
 454         spin_lock(&adev->ring_lru_list_lock);
 455         amdgpu_ring_lru_touch_locked(adev, ring);
 456         spin_unlock(&adev->ring_lru_list_lock);
 457 }
 458
 459 /*
 460  * Debugfs info
 461  */
 462 #if defined(CONFIG_DEBUG_FS)
 463
 464 /* Layout of file is 12 bytes consisting of
 465  * - rptr
 466  * - wptr
 467  * - driver's copy of wptr
 468  *
 469  * followed by n-words of ring data
 470  */
 471 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 472                                         size_t size, loff_t *pos)
 473 {
 474         struct amdgpu_ring *ring = file_inode(f)->i_private;
 475         int r, i;
 476         uint32_t value, result, early[3];
 477
 478         if (*pos & 3 || size & 3)
 479                 return -EINVAL;
 480
 481         result = 0;
 482
 483         if (*pos < 12) {
 484                 early[0] = amdgpu_ring_get_rptr(ring);
 485                 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
 486                 early[2] = ring->wptr & ring->buf_mask;
 487                 for (i = *pos / 4; i < 3 && size; i++) {
 488                         r = put_user(early[i], (uint32_t *)buf);
 489                         if (r)
 490                                 return r;
 491                         buf += 4;
 492                         result += 4;
 493                         size -= 4;
 494                         *pos += 4;
 495                 }
 496         }
 497
 498         while (size) {
 499                 if (*pos >= (ring->ring_size + 12))
 500                         return result;
 501
 502                 value = ring->ring[(*pos - 12)/4];
 503                 r = put_user(value, (uint32_t*)buf);
 504                 if (r)
 505                         return r;
 506                 buf += 4;
 507                 result += 4;
 508                 size -= 4;
 509                 *pos += 4;
 510         }
 511
 512         return result;
 513 }
 514
 515 static const struct file_operations amdgpu_debugfs_ring_fops = {
 516         .owner = THIS_MODULE,
 517         .read = amdgpu_debugfs_ring_read,
 518         .llseek = default_llseek
 519 };
 520
 521 #endif
 522
 523 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 524                                     struct amdgpu_ring *ring)
 525 {
 526 #if defined(CONFIG_DEBUG_FS)
 527         struct drm_minor *minor = adev->ddev->primary;
 528         struct dentry *ent, *root = minor->debugfs_root;
 529         char name[32];
 530
 531         sprintf(name, "amdgpu_ring_%s", ring->name);
 532
 533         ent = debugfs_create_file(name,
 534                                   S_IFREG | S_IRUGO, root,
 535                                   ring, &amdgpu_debugfs_ring_fops);
 536         if (!ent)
 537                 return -ENOMEM;
 538
 539         i_size_write(ent->d_inode, ring->ring_size + 12);
 540         ring->ent = ent;
 541 #endif
 542         return 0;
 543 }
 544
 545 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
 546 {
 547 #if defined(CONFIG_DEBUG_FS)
 548         debugfs_remove(ring->ent);
 549 #endif
 550 }