drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 #ifndef __AMDGPU_PSP_H__
  26 #define __AMDGPU_PSP_H__
  27
  28 #include "amdgpu.h"
  29 #include "psp_gfx_if.h"
  30 #include "ta_xgmi_if.h"
  31 #include "ta_ras_if.h"
  32 #include "ta_rap_if.h"
  33 #include "ta_secureDisplay_if.h"
  34
  35 #define PSP_FENCE_BUFFER_SIZE   0x1000
  36 #define PSP_CMD_BUFFER_SIZE     0x1000
  37 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
  38 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
  39 #define PSP_1_MEG               0x100000
  40 #define PSP_TMR_SIZE(adev)      ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
  41 #define PSP_HDCP_SHARED_MEM_SIZE        0x4000
  42 #define PSP_DTM_SHARED_MEM_SIZE 0x4000
  43 #define PSP_RAP_SHARED_MEM_SIZE 0x4000
  44 #define PSP_SECUREDISPLAY_SHARED_MEM_SIZE       0x4000
  45 #define PSP_SHARED_MEM_SIZE             0x4000
  46 #define PSP_FW_NAME_LEN         0x24
  47
  48 struct psp_context;
  49 struct psp_xgmi_node_info;
  50 struct psp_xgmi_topology_info;
  51
  52 enum psp_bootloader_cmd {
  53         PSP_BL__LOAD_SYSDRV             = 0x10000,
  54         PSP_BL__LOAD_SOSDRV             = 0x20000,
  55         PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
  56         PSP_BL__DRAM_LONG_TRAIN         = 0x100000,
  57         PSP_BL__DRAM_SHORT_TRAIN        = 0x200000,
  58         PSP_BL__LOAD_TOS_SPL_TABLE      = 0x10000000,
  59 };
  60
  61 enum psp_ring_type
  62 {
  63         PSP_RING_TYPE__INVALID = 0,
  64         /*
  65          * These values map to the way the PSP kernel identifies the
  66          * rings.
  67          */
  68         PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
  69         PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
  70 };
  71
  72 struct psp_ring
  73 {
  74         enum psp_ring_type              ring_type;
  75         struct psp_gfx_rb_frame         *ring_mem;
  76         uint64_t                        ring_mem_mc_addr;
  77         void                            *ring_mem_handle;
  78         uint32_t                        ring_size;
  79 };
  80
  81 /* More registers may will be supported */
  82 enum psp_reg_prog_id {
  83         PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
  84         PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
  85         PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
  86         PSP_REG_LAST
  87 };
  88
  89 struct psp_funcs
  90 {
  91         int (*init_microcode)(struct psp_context *psp);
  92         int (*bootloader_load_kdb)(struct psp_context *psp);
  93         int (*bootloader_load_spl)(struct psp_context *psp);
  94         int (*bootloader_load_sysdrv)(struct psp_context *psp);
  95         int (*bootloader_load_sos)(struct psp_context *psp);
  96         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
  97         int (*ring_create)(struct psp_context *psp,
  98                            enum psp_ring_type ring_type);
  99         int (*ring_stop)(struct psp_context *psp,
 100                             enum psp_ring_type ring_type);
 101         int (*ring_destroy)(struct psp_context *psp,
 102                             enum psp_ring_type ring_type);
 103         bool (*smu_reload_quirk)(struct psp_context *psp);
 104         int (*mode1_reset)(struct psp_context *psp);
 105         int (*mem_training)(struct psp_context *psp, uint32_t ops);
 106         uint32_t (*ring_get_wptr)(struct psp_context *psp);
 107         void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
 108         int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr);
 109         int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
 110 };
 111
 112 #define AMDGPU_XGMI_MAX_CONNECTED_NODES         64
 113 struct psp_xgmi_node_info {
 114         uint64_t                                node_id;
 115         uint8_t                                 num_hops;
 116         uint8_t                                 is_sharing_enabled;
 117         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
 118 };
 119
 120 struct psp_xgmi_topology_info {
 121         uint32_t                        num_nodes;
 122         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 123 };
 124
 125 struct psp_asd_context {
 126         bool                    asd_initialized;
 127         uint32_t                session_id;
 128 };
 129
 130 struct psp_xgmi_context {
 131         uint8_t                         initialized;
 132         uint32_t                        session_id;
 133         struct amdgpu_bo                *xgmi_shared_bo;
 134         uint64_t                        xgmi_shared_mc_addr;
 135         void                            *xgmi_shared_buf;
 136         struct psp_xgmi_topology_info   top_info;
 137 };
 138
 139 struct psp_ras_context {
 140         /*ras fw*/
 141         bool                    ras_initialized;
 142         uint32_t                session_id;
 143         struct amdgpu_bo        *ras_shared_bo;
 144         uint64_t                ras_shared_mc_addr;
 145         void                    *ras_shared_buf;
 146         struct amdgpu_ras       *ras;
 147 };
 148
 149 struct psp_hdcp_context {
 150         bool                    hdcp_initialized;
 151         uint32_t                session_id;
 152         struct amdgpu_bo        *hdcp_shared_bo;
 153         uint64_t                hdcp_shared_mc_addr;
 154         void                    *hdcp_shared_buf;
 155         struct mutex            mutex;
 156 };
 157
 158 struct psp_dtm_context {
 159         bool                    dtm_initialized;
 160         uint32_t                session_id;
 161         struct amdgpu_bo        *dtm_shared_bo;
 162         uint64_t                dtm_shared_mc_addr;
 163         void                    *dtm_shared_buf;
 164         struct mutex            mutex;
 165 };
 166
 167 struct psp_rap_context {
 168         bool                    rap_initialized;
 169         uint32_t                session_id;
 170         struct amdgpu_bo        *rap_shared_bo;
 171         uint64_t                rap_shared_mc_addr;
 172         void                    *rap_shared_buf;
 173         struct mutex            mutex;
 174 };
 175
 176 struct psp_securedisplay_context {
 177         bool                    securedisplay_initialized;
 178         uint32_t                session_id;
 179         struct amdgpu_bo        *securedisplay_shared_bo;
 180         uint64_t                securedisplay_shared_mc_addr;
 181         void                    *securedisplay_shared_buf;
 182         struct mutex            mutex;
 183 };
 184
 185 #define MEM_TRAIN_SYSTEM_SIGNATURE              0x54534942
 186 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES   0x1000
 187 #define GDDR6_MEM_TRAINING_OFFSET               0x8000
 188 /*Define the VRAM size that will be encroached by BIST training.*/
 189 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE      0x2000000
 190
 191 enum psp_memory_training_init_flag {
 192         PSP_MEM_TRAIN_NOT_SUPPORT       = 0x0,
 193         PSP_MEM_TRAIN_SUPPORT           = 0x1,
 194         PSP_MEM_TRAIN_INIT_FAILED       = 0x2,
 195         PSP_MEM_TRAIN_RESERVE_SUCCESS   = 0x4,
 196         PSP_MEM_TRAIN_INIT_SUCCESS      = 0x8,
 197 };
 198
 199 enum psp_memory_training_ops {
 200         PSP_MEM_TRAIN_SEND_LONG_MSG     = 0x1,
 201         PSP_MEM_TRAIN_SAVE              = 0x2,
 202         PSP_MEM_TRAIN_RESTORE           = 0x4,
 203         PSP_MEM_TRAIN_SEND_SHORT_MSG    = 0x8,
 204         PSP_MEM_TRAIN_COLD_BOOT         = PSP_MEM_TRAIN_SEND_LONG_MSG,
 205         PSP_MEM_TRAIN_RESUME            = PSP_MEM_TRAIN_SEND_SHORT_MSG,
 206 };
 207
 208 struct psp_memory_training_context {
 209         /*training data size*/
 210         u64 train_data_size;
 211         /*
 212          * sys_cache
 213          * cpu virtual address
 214          * system memory buffer that used to store the training data.
 215          */
 216         void *sys_cache;
 217
 218         /*vram offset of the p2c training data*/
 219         u64 p2c_train_data_offset;
 220
 221         /*vram offset of the c2p training data*/
 222         u64 c2p_train_data_offset;
 223         struct amdgpu_bo *c2p_bo;
 224
 225         enum psp_memory_training_init_flag init;
 226         u32 training_cnt;
 227 };
 228
 229 struct psp_context
 230 {
 231         struct amdgpu_device            *adev;
 232         struct psp_ring                 km_ring;
 233         struct psp_gfx_cmd_resp         *cmd;
 234
 235         const struct psp_funcs          *funcs;
 236
 237         /* firmware buffer */
 238         struct amdgpu_bo                *fw_pri_bo;
 239         uint64_t                        fw_pri_mc_addr;
 240         void                            *fw_pri_buf;
 241
 242         /* sos firmware */
 243         const struct firmware           *sos_fw;
 244         uint32_t                        sos_fw_version;
 245         uint32_t                        sos_feature_version;
 246         uint32_t                        sys_bin_size;
 247         uint32_t                        sos_bin_size;
 248         uint32_t                        toc_bin_size;
 249         uint32_t                        kdb_bin_size;
 250         uint32_t                        spl_bin_size;
 251         uint32_t                        rl_bin_size;
 252         uint8_t                         *sys_start_addr;
 253         uint8_t                         *sos_start_addr;
 254         uint8_t                         *toc_start_addr;
 255         uint8_t                         *kdb_start_addr;
 256         uint8_t                         *spl_start_addr;
 257         uint8_t                         *rl_start_addr;
 258
 259         /* tmr buffer */
 260         struct amdgpu_bo                *tmr_bo;
 261         uint64_t                        tmr_mc_addr;
 262
 263         /* asd firmware */
 264         const struct firmware           *asd_fw;
 265         uint32_t                        asd_fw_version;
 266         uint32_t                        asd_feature_version;
 267         uint32_t                        asd_ucode_size;
 268         uint8_t                         *asd_start_addr;
 269
 270         /* toc firmware */
 271         const struct firmware           *toc_fw;
 272         uint32_t                        toc_fw_version;
 273         uint32_t                        toc_feature_version;
 274
 275         /* fence buffer */
 276         struct amdgpu_bo                *fence_buf_bo;
 277         uint64_t                        fence_buf_mc_addr;
 278         void                            *fence_buf;
 279
 280         /* cmd buffer */
 281         struct amdgpu_bo                *cmd_buf_bo;
 282         uint64_t                        cmd_buf_mc_addr;
 283         struct psp_gfx_cmd_resp         *cmd_buf_mem;
 284
 285         /* fence value associated with cmd buffer */
 286         atomic_t                        fence_value;
 287         /* flag to mark whether gfx fw autoload is supported or not */
 288         bool                            autoload_supported;
 289         /* flag to mark whether df cstate management centralized to PMFW */
 290         bool                            pmfw_centralized_cstate_management;
 291
 292         /* xgmi ta firmware and buffer */
 293         const struct firmware           *ta_fw;
 294         uint32_t                        ta_fw_version;
 295         uint32_t                        ta_xgmi_ucode_version;
 296         uint32_t                        ta_xgmi_ucode_size;
 297         uint8_t                         *ta_xgmi_start_addr;
 298         uint32_t                        ta_ras_ucode_version;
 299         uint32_t                        ta_ras_ucode_size;
 300         uint8_t                         *ta_ras_start_addr;
 301
 302         uint32_t                        ta_hdcp_ucode_version;
 303         uint32_t                        ta_hdcp_ucode_size;
 304         uint8_t                         *ta_hdcp_start_addr;
 305
 306         uint32_t                        ta_dtm_ucode_version;
 307         uint32_t                        ta_dtm_ucode_size;
 308         uint8_t                         *ta_dtm_start_addr;
 309
 310         uint32_t                        ta_rap_ucode_version;
 311         uint32_t                        ta_rap_ucode_size;
 312         uint8_t                         *ta_rap_start_addr;
 313
 314         uint32_t                        ta_securedisplay_ucode_version;
 315         uint32_t                        ta_securedisplay_ucode_size;
 316         uint8_t                         *ta_securedisplay_start_addr;
 317
 318         struct psp_asd_context          asd_context;
 319         struct psp_xgmi_context         xgmi_context;
 320         struct psp_ras_context          ras;
 321         struct psp_hdcp_context         hdcp_context;
 322         struct psp_dtm_context          dtm_context;
 323         struct psp_rap_context          rap_context;
 324         struct psp_securedisplay_context        securedisplay_context;
 325         struct mutex                    mutex;
 326         struct psp_memory_training_context mem_train_ctx;
 327 };
 328
 329 struct amdgpu_psp_funcs {
 330         bool (*check_fw_loading_status)(struct amdgpu_device *adev,
 331                                         enum AMDGPU_UCODE_ID);
 332 };
 333
 334
 335 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 336 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 337 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 338 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
 339 #define psp_init_microcode(psp) \
 340                 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
 341 #define psp_bootloader_load_kdb(psp) \
 342                 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 343 #define psp_bootloader_load_spl(psp) \
 344                 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
 345 #define psp_bootloader_load_sysdrv(psp) \
 346                 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 347 #define psp_bootloader_load_sos(psp) \
 348                 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 349 #define psp_smu_reload_quirk(psp) \
 350                 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
 351 #define psp_mode1_reset(psp) \
 352                 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
 353 #define psp_mem_training(psp, ops) \
 354         ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
 355
 356 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
 357 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
 358
 359 #define psp_load_usbc_pd_fw(psp, dma_addr) \
 360         ((psp)->funcs->load_usbc_pd_fw ? \
 361         (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL)
 362
 363 #define psp_read_usbc_pd_fw(psp, fw_ver) \
 364         ((psp)->funcs->read_usbc_pd_fw ? \
 365         (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
 366
 367 extern const struct amd_ip_funcs psp_ip_funcs;
 368
 369 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
 370 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 371 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 372 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 373 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
 374
 375 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 376                         uint32_t field_val, uint32_t mask, bool check_changed);
 377
 378 int psp_gpu_reset(struct amdgpu_device *adev);
 379 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
 380                         uint64_t cmd_gpu_addr, int cmd_size);
 381
 382 int psp_xgmi_initialize(struct psp_context *psp);
 383 int psp_xgmi_terminate(struct psp_context *psp);
 384 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 385 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
 386 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
 387 int psp_xgmi_get_topology_info(struct psp_context *psp,
 388                                int number_devices,
 389                                struct psp_xgmi_topology_info *topology);
 390 int psp_xgmi_set_topology_info(struct psp_context *psp,
 391                                int number_devices,
 392                                struct psp_xgmi_topology_info *topology);
 393
 394 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 395 int psp_ras_enable_features(struct psp_context *psp,
 396                 union ta_ras_cmd_input *info, bool enable);
 397 int psp_ras_trigger_error(struct psp_context *psp,
 398                           struct ta_ras_trigger_error_input *info);
 399
 400 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 401 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 402 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
 403 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 404
 405 int psp_rlc_autoload_start(struct psp_context *psp);
 406
 407 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 408                 uint32_t value);
 409 int psp_ring_cmd_submit(struct psp_context *psp,
 410                         uint64_t cmd_buf_mc_addr,
 411                         uint64_t fence_mc_addr,
 412                         int index);
 413 int psp_init_asd_microcode(struct psp_context *psp,
 414                            const char *chip_name);
 415 int psp_init_toc_microcode(struct psp_context *psp,
 416                            const char *chip_name);
 417 int psp_init_sos_microcode(struct psp_context *psp,
 418                            const char *chip_name);
 419 int psp_init_ta_microcode(struct psp_context *psp,
 420                           const char *chip_name);
 421 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 422                                         uint64_t *output_ptr);
 423
 424 int psp_load_fw_list(struct psp_context *psp,
 425                      struct amdgpu_firmware_info **ucode_list, int ucode_count);
 426 #endif