2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
42 #include "amdgpu_ras.h"
43 #include "amdgpu_securedisplay.h"
44 #include "amdgpu_atomfirmware.h"
46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
48 static int psp_sysfs_init(struct amdgpu_device *adev);
49 static void psp_sysfs_fini(struct amdgpu_device *adev);
51 static int psp_load_smu_fw(struct psp_context *psp);
52 static int psp_rap_terminate(struct psp_context *psp);
53 static int psp_securedisplay_terminate(struct psp_context *psp);
55 static int psp_ring_init(struct psp_context *psp,
56 enum psp_ring_type ring_type)
59 struct psp_ring *ring;
60 struct amdgpu_device *adev = psp->adev;
64 ring->ring_type = ring_type;
66 /* allocate 4k Page of Local Frame Buffer memory for ring */
67 ring->ring_size = 0x1000;
68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
69 AMDGPU_GEM_DOMAIN_VRAM |
70 AMDGPU_GEM_DOMAIN_GTT,
72 &ring->ring_mem_mc_addr,
73 (void **)&ring->ring_mem);
83 * Due to DF Cstate management centralized to PMFW, the firmware
84 * loading sequence will be updated as below:
90 * - Load other non-psp fw
92 * - Load XGMI/RAS/HDCP/DTM TA if any
94 * This new sequence is required for
95 * - Arcturus and onwards
97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
99 struct amdgpu_device *adev = psp->adev;
101 if (amdgpu_sriov_vf(adev)) {
102 psp->pmfw_centralized_cstate_management = false;
106 switch (adev->ip_versions[MP0_HWIP][0]) {
107 case IP_VERSION(11, 0, 0):
108 case IP_VERSION(11, 0, 4):
109 case IP_VERSION(11, 0, 5):
110 case IP_VERSION(11, 0, 7):
111 case IP_VERSION(11, 0, 9):
112 case IP_VERSION(11, 0, 11):
113 case IP_VERSION(11, 0, 12):
114 case IP_VERSION(11, 0, 13):
115 case IP_VERSION(13, 0, 0):
116 case IP_VERSION(13, 0, 2):
117 case IP_VERSION(13, 0, 7):
118 psp->pmfw_centralized_cstate_management = true;
121 psp->pmfw_centralized_cstate_management = false;
126 static int psp_init_sriov_microcode(struct psp_context *psp)
128 struct amdgpu_device *adev = psp->adev;
129 char ucode_prefix[30];
132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
134 switch (adev->ip_versions[MP0_HWIP][0]) {
135 case IP_VERSION(9, 0, 0):
136 case IP_VERSION(11, 0, 7):
137 case IP_VERSION(11, 0, 9):
138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
139 ret = psp_init_cap_microcode(psp, ucode_prefix);
141 case IP_VERSION(13, 0, 2):
142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
143 ret = psp_init_cap_microcode(psp, ucode_prefix);
144 ret &= psp_init_ta_microcode(psp, ucode_prefix);
146 case IP_VERSION(13, 0, 0):
147 adev->virt.autoload_ucode_id = 0;
149 case IP_VERSION(13, 0, 6):
150 ret = psp_init_cap_microcode(psp, ucode_prefix);
152 case IP_VERSION(13, 0, 10):
153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
154 ret = psp_init_cap_microcode(psp, ucode_prefix);
162 static int psp_early_init(void *handle)
164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
165 struct psp_context *psp = &adev->psp;
167 switch (adev->ip_versions[MP0_HWIP][0]) {
168 case IP_VERSION(9, 0, 0):
169 psp_v3_1_set_psp_funcs(psp);
170 psp->autoload_supported = false;
172 case IP_VERSION(10, 0, 0):
173 case IP_VERSION(10, 0, 1):
174 psp_v10_0_set_psp_funcs(psp);
175 psp->autoload_supported = false;
177 case IP_VERSION(11, 0, 2):
178 case IP_VERSION(11, 0, 4):
179 psp_v11_0_set_psp_funcs(psp);
180 psp->autoload_supported = false;
182 case IP_VERSION(11, 0, 0):
183 case IP_VERSION(11, 0, 5):
184 case IP_VERSION(11, 0, 9):
185 case IP_VERSION(11, 0, 7):
186 case IP_VERSION(11, 0, 11):
187 case IP_VERSION(11, 5, 0):
188 case IP_VERSION(11, 0, 12):
189 case IP_VERSION(11, 0, 13):
190 psp_v11_0_set_psp_funcs(psp);
191 psp->autoload_supported = true;
193 case IP_VERSION(11, 0, 3):
194 case IP_VERSION(12, 0, 1):
195 psp_v12_0_set_psp_funcs(psp);
197 case IP_VERSION(13, 0, 2):
198 case IP_VERSION(13, 0, 6):
199 psp_v13_0_set_psp_funcs(psp);
201 case IP_VERSION(13, 0, 1):
202 case IP_VERSION(13, 0, 3):
203 case IP_VERSION(13, 0, 5):
204 case IP_VERSION(13, 0, 8):
205 case IP_VERSION(13, 0, 10):
206 case IP_VERSION(13, 0, 11):
207 psp_v13_0_set_psp_funcs(psp);
208 psp->autoload_supported = true;
210 case IP_VERSION(11, 0, 8):
211 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
212 psp_v11_0_8_set_psp_funcs(psp);
213 psp->autoload_supported = false;
216 case IP_VERSION(13, 0, 0):
217 case IP_VERSION(13, 0, 7):
218 psp_v13_0_set_psp_funcs(psp);
219 psp->autoload_supported = true;
221 case IP_VERSION(13, 0, 4):
222 psp_v13_0_4_set_psp_funcs(psp);
223 psp->autoload_supported = true;
231 psp_check_pmfw_centralized_cstate_management(psp);
233 if (amdgpu_sriov_vf(adev))
234 return psp_init_sriov_microcode(psp);
236 return psp_init_microcode(psp);
239 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
241 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
242 &mem_ctx->shared_buf);
243 mem_ctx->shared_bo = NULL;
246 static void psp_free_shared_bufs(struct psp_context *psp)
251 /* free TMR memory buffer */
252 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
253 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
256 /* free xgmi shared memory */
257 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
259 /* free ras shared memory */
260 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
262 /* free hdcp shared memory */
263 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
265 /* free dtm shared memory */
266 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
268 /* free rap shared memory */
269 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
271 /* free securedisplay shared memory */
272 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
277 static void psp_memory_training_fini(struct psp_context *psp)
279 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
281 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
282 kfree(ctx->sys_cache);
283 ctx->sys_cache = NULL;
286 static int psp_memory_training_init(struct psp_context *psp)
289 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
291 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
292 DRM_DEBUG("memory training is not supported!\n");
296 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
297 if (ctx->sys_cache == NULL) {
298 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
303 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
304 ctx->train_data_size,
305 ctx->p2c_train_data_offset,
306 ctx->c2p_train_data_offset);
307 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
311 psp_memory_training_fini(psp);
316 * Helper funciton to query psp runtime database entry
318 * @adev: amdgpu_device pointer
319 * @entry_type: the type of psp runtime database entry
320 * @db_entry: runtime database entry pointer
322 * Return false if runtime database doesn't exit or entry is invalid
323 * or true if the specific database entry is found, and copy to @db_entry
325 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
326 enum psp_runtime_entry_type entry_type,
329 uint64_t db_header_pos, db_dir_pos;
330 struct psp_runtime_data_header db_header = {0};
331 struct psp_runtime_data_directory db_dir = {0};
335 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6))
338 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
339 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
341 /* read runtime db header from vram */
342 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
343 sizeof(struct psp_runtime_data_header), false);
345 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
346 /* runtime db doesn't exist, exit */
347 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
351 /* read runtime database entry from vram */
352 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
353 sizeof(struct psp_runtime_data_directory), false);
355 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
356 /* invalid db entry count, exit */
357 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
361 /* look up for requested entry type */
362 for (i = 0; i < db_dir.entry_count && !ret; i++) {
363 if (db_dir.entry_list[i].entry_type == entry_type) {
364 switch (entry_type) {
365 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
366 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
367 /* invalid db entry size */
368 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
371 /* read runtime database entry */
372 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
373 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
376 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
377 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
378 /* invalid db entry size */
379 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
382 /* read runtime database entry */
383 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
384 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
397 static int psp_sw_init(void *handle)
399 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
400 struct psp_context *psp = &adev->psp;
402 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
403 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
404 struct psp_runtime_scpm_entry scpm_entry;
406 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
408 DRM_ERROR("Failed to allocate memory to command buffer!\n");
412 adev->psp.xgmi_context.supports_extended_data =
413 !adev->gmc.xgmi.connected_to_cpu &&
414 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
416 memset(&scpm_entry, 0, sizeof(scpm_entry));
417 if ((psp_get_runtime_db_entry(adev,
418 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
420 (scpm_entry.scpm_status != SCPM_DISABLE)) {
421 adev->scpm_enabled = true;
422 adev->scpm_status = scpm_entry.scpm_status;
424 adev->scpm_enabled = false;
425 adev->scpm_status = SCPM_DISABLE;
428 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
430 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
431 if (psp_get_runtime_db_entry(adev,
432 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
434 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
435 if ((psp->boot_cfg_bitmask) &
436 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
437 /* If psp runtime database exists, then
438 * only enable two stage memory training
439 * when TWO_STAGE_DRAM_TRAINING bit is set
440 * in runtime database */
441 mem_training_ctx->enable_mem_training = true;
445 /* If psp runtime database doesn't exist or
446 * is invalid, force enable two stage memory
448 mem_training_ctx->enable_mem_training = true;
451 if (mem_training_ctx->enable_mem_training) {
452 ret = psp_memory_training_init(psp);
454 DRM_ERROR("Failed to initialize memory training!\n");
458 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
460 DRM_ERROR("Failed to process memory training!\n");
465 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
466 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
467 ret = psp_sysfs_init(adev);
472 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
473 amdgpu_sriov_vf(adev) ?
474 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
476 &psp->fw_pri_mc_addr,
481 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
482 AMDGPU_GEM_DOMAIN_VRAM |
483 AMDGPU_GEM_DOMAIN_GTT,
485 &psp->fence_buf_mc_addr,
490 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
491 AMDGPU_GEM_DOMAIN_VRAM |
492 AMDGPU_GEM_DOMAIN_GTT,
493 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
494 (void **)&psp->cmd_buf_mem);
501 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
502 &psp->fence_buf_mc_addr, &psp->fence_buf);
504 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
505 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
509 static int psp_sw_fini(void *handle)
511 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
512 struct psp_context *psp = &adev->psp;
513 struct psp_gfx_cmd_resp *cmd = psp->cmd;
515 psp_memory_training_fini(psp);
517 amdgpu_ucode_release(&psp->sos_fw);
518 amdgpu_ucode_release(&psp->asd_fw);
519 amdgpu_ucode_release(&psp->ta_fw);
520 amdgpu_ucode_release(&psp->cap_fw);
521 amdgpu_ucode_release(&psp->toc_fw);
523 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
524 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
525 psp_sysfs_fini(adev);
530 psp_free_shared_bufs(psp);
532 if (psp->km_ring.ring_mem)
533 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
534 &psp->km_ring.ring_mem_mc_addr,
535 (void **)&psp->km_ring.ring_mem);
537 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
538 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
539 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
540 &psp->fence_buf_mc_addr, &psp->fence_buf);
541 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
542 (void **)&psp->cmd_buf_mem);
547 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
548 uint32_t reg_val, uint32_t mask, bool check_changed)
552 struct amdgpu_device *adev = psp->adev;
554 if (psp->adev->no_hw_access)
557 for (i = 0; i < adev->usec_timeout; i++) {
558 val = RREG32(reg_index);
563 if ((val & mask) == reg_val)
572 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
573 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
577 struct amdgpu_device *adev = psp->adev;
579 if (psp->adev->no_hw_access)
582 for (i = 0; i < msec_timeout; i++) {
583 val = RREG32(reg_index);
584 if ((val & mask) == reg_val)
592 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
595 case GFX_CMD_ID_LOAD_TA:
597 case GFX_CMD_ID_UNLOAD_TA:
599 case GFX_CMD_ID_INVOKE_CMD:
601 case GFX_CMD_ID_LOAD_ASD:
603 case GFX_CMD_ID_SETUP_TMR:
605 case GFX_CMD_ID_LOAD_IP_FW:
607 case GFX_CMD_ID_DESTROY_TMR:
608 return "DESTROY_TMR";
609 case GFX_CMD_ID_SAVE_RESTORE:
610 return "SAVE_RESTORE_IP_FW";
611 case GFX_CMD_ID_SETUP_VMR:
613 case GFX_CMD_ID_DESTROY_VMR:
614 return "DESTROY_VMR";
615 case GFX_CMD_ID_PROG_REG:
617 case GFX_CMD_ID_GET_FW_ATTESTATION:
618 return "GET_FW_ATTESTATION";
619 case GFX_CMD_ID_LOAD_TOC:
620 return "ID_LOAD_TOC";
621 case GFX_CMD_ID_AUTOLOAD_RLC:
622 return "AUTOLOAD_RLC";
623 case GFX_CMD_ID_BOOT_CFG:
626 return "UNKNOWN CMD";
631 psp_cmd_submit_buf(struct psp_context *psp,
632 struct amdgpu_firmware_info *ucode,
633 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
638 bool ras_intr = false;
639 bool skip_unsupport = false;
641 if (psp->adev->no_hw_access)
644 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
646 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
648 index = atomic_inc_return(&psp->fence_value);
649 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
651 atomic_dec(&psp->fence_value);
655 amdgpu_device_invalidate_hdp(psp->adev, NULL);
656 while (*((unsigned int *)psp->fence_buf) != index) {
660 * Shouldn't wait for timeout when err_event_athub occurs,
661 * because gpu reset thread triggered and lock resource should
662 * be released for psp resume sequence.
664 ras_intr = amdgpu_ras_intr_triggered();
667 usleep_range(10, 100);
668 amdgpu_device_invalidate_hdp(psp->adev, NULL);
671 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
672 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
673 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
675 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
677 /* In some cases, psp response status is not 0 even there is no
678 * problem while the command is submitted. Some version of PSP FW
679 * doesn't write 0 to that field.
680 * So here we would like to only print a warning instead of an error
681 * during psp initialization to avoid breaking hw_init and it doesn't
684 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
686 DRM_WARN("failed to load ucode %s(0x%X) ",
687 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
688 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
689 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
690 psp->cmd_buf_mem->resp.status);
691 /* If any firmware (including CAP) load fails under SRIOV, it should
692 * return failure to stop the VF from initializing.
693 * Also return failure in case of timeout
695 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
702 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
703 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
710 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
712 struct psp_gfx_cmd_resp *cmd = psp->cmd;
714 mutex_lock(&psp->mutex);
716 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
721 static void release_psp_cmd_buf(struct psp_context *psp)
723 mutex_unlock(&psp->mutex);
726 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
727 struct psp_gfx_cmd_resp *cmd,
728 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
730 struct amdgpu_device *adev = psp->adev;
735 size = amdgpu_bo_size(tmr_bo);
736 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
739 if (amdgpu_sriov_vf(psp->adev))
740 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
742 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
743 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
744 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
745 cmd->cmd.cmd_setup_tmr.buf_size = size;
746 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
747 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
748 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
751 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
752 uint64_t pri_buf_mc, uint32_t size)
754 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
755 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
756 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
757 cmd->cmd.cmd_load_toc.toc_size = size;
760 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
761 static int psp_load_toc(struct psp_context *psp,
765 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
767 /* Copy toc to psp firmware private buffer */
768 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
770 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
772 ret = psp_cmd_submit_buf(psp, NULL, cmd,
773 psp->fence_buf_mc_addr);
775 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
777 release_psp_cmd_buf(psp);
782 static bool psp_boottime_tmr(struct psp_context *psp)
784 switch (psp->adev->ip_versions[MP0_HWIP][0]) {
785 case IP_VERSION(13, 0, 6):
792 /* Set up Trusted Memory Region */
793 static int psp_tmr_init(struct psp_context *psp)
801 * According to HW engineer, they prefer the TMR address be "naturally
802 * aligned" , e.g. the start address be an integer divide of TMR size.
804 * Note: this memory need be reserved till the driver
807 tmr_size = PSP_TMR_SIZE(psp->adev);
809 /* For ASICs support RLC autoload, psp will parse the toc
810 * and calculate the total size of TMR needed */
811 if (!amdgpu_sriov_vf(psp->adev) &&
812 psp->toc.start_addr &&
813 psp->toc.size_bytes &&
815 ret = psp_load_toc(psp, &tmr_size);
817 DRM_ERROR("Failed to load toc\n");
823 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
824 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
826 AMDGPU_HAS_VRAM(psp->adev) ?
827 AMDGPU_GEM_DOMAIN_VRAM :
828 AMDGPU_GEM_DOMAIN_GTT,
829 &psp->tmr_bo, &psp->tmr_mc_addr,
836 static bool psp_skip_tmr(struct psp_context *psp)
838 switch (psp->adev->ip_versions[MP0_HWIP][0]) {
839 case IP_VERSION(11, 0, 9):
840 case IP_VERSION(11, 0, 7):
841 case IP_VERSION(13, 0, 2):
842 case IP_VERSION(13, 0, 6):
843 case IP_VERSION(13, 0, 10):
850 static int psp_tmr_load(struct psp_context *psp)
853 struct psp_gfx_cmd_resp *cmd;
855 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
856 * Already set up by host driver.
858 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
861 cmd = acquire_psp_cmd_buf(psp);
863 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
865 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
866 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
868 ret = psp_cmd_submit_buf(psp, NULL, cmd,
869 psp->fence_buf_mc_addr);
871 release_psp_cmd_buf(psp);
876 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
877 struct psp_gfx_cmd_resp *cmd)
879 if (amdgpu_sriov_vf(psp->adev))
880 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
882 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
885 static int psp_tmr_unload(struct psp_context *psp)
888 struct psp_gfx_cmd_resp *cmd;
890 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
891 * as TMR is not loaded at all
893 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
896 cmd = acquire_psp_cmd_buf(psp);
898 psp_prep_tmr_unload_cmd_buf(psp, cmd);
899 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
901 ret = psp_cmd_submit_buf(psp, NULL, cmd,
902 psp->fence_buf_mc_addr);
904 release_psp_cmd_buf(psp);
909 static int psp_tmr_terminate(struct psp_context *psp)
911 return psp_tmr_unload(psp);
914 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
915 uint64_t *output_ptr)
918 struct psp_gfx_cmd_resp *cmd;
923 if (amdgpu_sriov_vf(psp->adev))
926 cmd = acquire_psp_cmd_buf(psp);
928 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
930 ret = psp_cmd_submit_buf(psp, NULL, cmd,
931 psp->fence_buf_mc_addr);
934 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
935 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
938 release_psp_cmd_buf(psp);
943 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
945 struct psp_context *psp = &adev->psp;
946 struct psp_gfx_cmd_resp *cmd;
949 if (amdgpu_sriov_vf(adev))
952 cmd = acquire_psp_cmd_buf(psp);
954 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
955 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
957 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
960 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
963 release_psp_cmd_buf(psp);
968 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
971 struct psp_context *psp = &adev->psp;
972 struct psp_gfx_cmd_resp *cmd;
974 if (amdgpu_sriov_vf(adev))
977 cmd = acquire_psp_cmd_buf(psp);
979 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
980 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
981 cmd->cmd.boot_cfg.boot_config = boot_cfg;
982 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
984 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
986 release_psp_cmd_buf(psp);
991 static int psp_rl_load(struct amdgpu_device *adev)
994 struct psp_context *psp = &adev->psp;
995 struct psp_gfx_cmd_resp *cmd;
997 if (!is_psp_fw_valid(psp->rl))
1000 cmd = acquire_psp_cmd_buf(psp);
1002 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1003 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
1005 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1006 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1007 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1008 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1009 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1011 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1013 release_psp_cmd_buf(psp);
1018 int psp_spatial_partition(struct psp_context *psp, int mode)
1020 struct psp_gfx_cmd_resp *cmd;
1023 if (amdgpu_sriov_vf(psp->adev))
1026 cmd = acquire_psp_cmd_buf(psp);
1028 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1029 cmd->cmd.cmd_spatial_part.mode = mode;
1031 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1032 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1034 release_psp_cmd_buf(psp);
1039 static int psp_asd_initialize(struct psp_context *psp)
1043 /* If PSP version doesn't match ASD version, asd loading will be failed.
1044 * add workaround to bypass it for sriov now.
1045 * TODO: add version check to make it common
1047 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1050 psp->asd_context.mem_context.shared_mc_addr = 0;
1051 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1052 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
1054 ret = psp_ta_load(psp, &psp->asd_context);
1056 psp->asd_context.initialized = true;
1061 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1062 uint32_t session_id)
1064 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1065 cmd->cmd.cmd_unload_ta.session_id = session_id;
1068 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1071 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1073 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1075 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1077 context->resp_status = cmd->resp.status;
1079 release_psp_cmd_buf(psp);
1084 static int psp_asd_terminate(struct psp_context *psp)
1088 if (amdgpu_sriov_vf(psp->adev))
1091 if (!psp->asd_context.initialized)
1094 ret = psp_ta_unload(psp, &psp->asd_context);
1096 psp->asd_context.initialized = false;
1101 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1102 uint32_t id, uint32_t value)
1104 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1105 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1106 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1109 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1112 struct psp_gfx_cmd_resp *cmd;
1115 if (reg >= PSP_REG_LAST)
1118 cmd = acquire_psp_cmd_buf(psp);
1120 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1121 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1123 DRM_ERROR("PSP failed to program reg id %d", reg);
1125 release_psp_cmd_buf(psp);
1130 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1132 struct ta_context *context)
1134 cmd->cmd_id = context->ta_load_type;
1135 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1136 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1137 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1139 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1140 lower_32_bits(context->mem_context.shared_mc_addr);
1141 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1142 upper_32_bits(context->mem_context.shared_mc_addr);
1143 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1146 int psp_ta_init_shared_buf(struct psp_context *psp,
1147 struct ta_mem_context *mem_ctx)
1150 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1151 * physical) for ta to host memory
1153 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1154 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1155 AMDGPU_GEM_DOMAIN_GTT,
1156 &mem_ctx->shared_bo,
1157 &mem_ctx->shared_mc_addr,
1158 &mem_ctx->shared_buf);
1161 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1163 uint32_t session_id)
1165 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1166 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1167 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1170 int psp_ta_invoke(struct psp_context *psp,
1172 struct ta_context *context)
1175 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1177 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1179 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1180 psp->fence_buf_mc_addr);
1182 context->resp_status = cmd->resp.status;
1184 release_psp_cmd_buf(psp);
1189 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1192 struct psp_gfx_cmd_resp *cmd;
1194 cmd = acquire_psp_cmd_buf(psp);
1196 psp_copy_fw(psp, context->bin_desc.start_addr,
1197 context->bin_desc.size_bytes);
1199 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1201 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1202 psp->fence_buf_mc_addr);
1204 context->resp_status = cmd->resp.status;
1207 context->session_id = cmd->resp.session_id;
1209 release_psp_cmd_buf(psp);
1214 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1216 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1219 int psp_xgmi_terminate(struct psp_context *psp)
1222 struct amdgpu_device *adev = psp->adev;
1224 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1225 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1226 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1227 adev->gmc.xgmi.connected_to_cpu))
1230 if (!psp->xgmi_context.context.initialized)
1233 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1235 psp->xgmi_context.context.initialized = false;
1240 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1242 struct ta_xgmi_shared_memory *xgmi_cmd;
1246 !psp->xgmi_context.context.bin_desc.size_bytes ||
1247 !psp->xgmi_context.context.bin_desc.start_addr)
1253 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1254 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1256 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1257 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1263 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1265 psp->xgmi_context.context.initialized = true;
1270 /* Initialize XGMI session */
1271 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1272 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1273 xgmi_cmd->flag_extend_link_record = set_extended_data;
1274 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1276 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1281 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1283 struct ta_xgmi_shared_memory *xgmi_cmd;
1286 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1287 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1289 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1291 /* Invoke xgmi ta to get hive id */
1292 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1296 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1301 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1303 struct ta_xgmi_shared_memory *xgmi_cmd;
1306 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1307 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1309 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1311 /* Invoke xgmi ta to get the node id */
1312 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1316 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1321 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1323 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1324 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1325 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1329 * Chips that support extended topology information require the driver to
1330 * reflect topology information in the opposite direction. This is
1331 * because the TA has already exceeded its link record limit and if the
1332 * TA holds bi-directional information, the driver would have to do
1333 * multiple fetches instead of just two.
1335 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1336 struct psp_xgmi_node_info node_info)
1338 struct amdgpu_device *mirror_adev;
1339 struct amdgpu_hive_info *hive;
1340 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1341 uint64_t dst_node_id = node_info.node_id;
1342 uint8_t dst_num_hops = node_info.num_hops;
1343 uint8_t dst_num_links = node_info.num_links;
1345 hive = amdgpu_get_xgmi_hive(psp->adev);
1346 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1347 struct psp_xgmi_topology_info *mirror_top_info;
1350 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1353 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1354 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1355 if (mirror_top_info->nodes[j].node_id != src_node_id)
1358 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1360 * prevent 0 num_links value re-reflection since reflection
1361 * criteria is based on num_hops (direct or indirect).
1365 mirror_top_info->nodes[j].num_links = dst_num_links;
1373 amdgpu_put_xgmi_hive(hive);
1376 int psp_xgmi_get_topology_info(struct psp_context *psp,
1378 struct psp_xgmi_topology_info *topology,
1379 bool get_extended_data)
1381 struct ta_xgmi_shared_memory *xgmi_cmd;
1382 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1383 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1387 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1390 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1391 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1392 xgmi_cmd->flag_extend_link_record = get_extended_data;
1394 /* Fill in the shared memory with topology information as input */
1395 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1396 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1397 topology_info_input->num_nodes = number_devices;
1399 for (i = 0; i < topology_info_input->num_nodes; i++) {
1400 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1401 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1402 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1403 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1406 /* Invoke xgmi ta to get the topology information */
1407 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1411 /* Read the output topology information from the shared memory */
1412 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1413 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1414 for (i = 0; i < topology->num_nodes; i++) {
1415 /* extended data will either be 0 or equal to non-extended data */
1416 if (topology_info_output->nodes[i].num_hops)
1417 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1419 /* non-extended data gets everything here so no need to update */
1420 if (!get_extended_data) {
1421 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1422 topology->nodes[i].is_sharing_enabled =
1423 topology_info_output->nodes[i].is_sharing_enabled;
1424 topology->nodes[i].sdma_engine =
1425 topology_info_output->nodes[i].sdma_engine;
1430 /* Invoke xgmi ta again to get the link information */
1431 if (psp_xgmi_peer_link_info_supported(psp)) {
1432 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1433 bool requires_reflection =
1434 (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1435 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1437 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1439 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1444 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1445 for (i = 0; i < topology->num_nodes; i++) {
1446 /* accumulate num_links on extended data */
1447 topology->nodes[i].num_links = get_extended_data ?
1448 topology->nodes[i].num_links +
1449 link_info_output->nodes[i].num_links :
1450 ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1451 link_info_output->nodes[i].num_links);
1453 /* reflect the topology information for bi-directionality */
1454 if (requires_reflection && topology->nodes[i].num_hops)
1455 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1462 int psp_xgmi_set_topology_info(struct psp_context *psp,
1464 struct psp_xgmi_topology_info *topology)
1466 struct ta_xgmi_shared_memory *xgmi_cmd;
1467 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1470 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1473 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1474 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1476 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1477 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1478 topology_info_input->num_nodes = number_devices;
1480 for (i = 0; i < topology_info_input->num_nodes; i++) {
1481 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1482 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1483 topology_info_input->nodes[i].is_sharing_enabled = 1;
1484 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1487 /* Invoke xgmi ta to set topology information */
1488 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1492 static void psp_ras_ta_check_status(struct psp_context *psp)
1494 struct ta_ras_shared_memory *ras_cmd =
1495 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1497 switch (ras_cmd->ras_status) {
1498 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1499 dev_warn(psp->adev->dev,
1500 "RAS WARNING: cmd failed due to unsupported ip\n");
1502 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1503 dev_warn(psp->adev->dev,
1504 "RAS WARNING: cmd failed due to unsupported error injection\n");
1506 case TA_RAS_STATUS__SUCCESS:
1508 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1509 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1510 dev_warn(psp->adev->dev,
1511 "RAS WARNING: Inject error to critical region is not allowed\n");
1514 dev_warn(psp->adev->dev,
1515 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1520 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1522 struct ta_ras_shared_memory *ras_cmd;
1525 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1528 * TODO: bypass the loading in sriov for now
1530 if (amdgpu_sriov_vf(psp->adev))
1533 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1535 if (amdgpu_ras_intr_triggered())
1538 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1539 DRM_WARN("RAS: Unsupported Interface");
1544 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1545 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1547 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1548 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1549 dev_warn(psp->adev->dev,
1550 "RAS internal register access blocked\n");
1552 psp_ras_ta_check_status(psp);
1558 int psp_ras_enable_features(struct psp_context *psp,
1559 union ta_ras_cmd_input *info, bool enable)
1561 struct ta_ras_shared_memory *ras_cmd;
1564 if (!psp->ras_context.context.initialized)
1567 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1568 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1571 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1573 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1575 ras_cmd->ras_in_message = *info;
1577 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1584 int psp_ras_terminate(struct psp_context *psp)
1589 * TODO: bypass the terminate in sriov for now
1591 if (amdgpu_sriov_vf(psp->adev))
1594 if (!psp->ras_context.context.initialized)
1597 ret = psp_ta_unload(psp, &psp->ras_context.context);
1599 psp->ras_context.context.initialized = false;
1604 int psp_ras_initialize(struct psp_context *psp)
1607 uint32_t boot_cfg = 0xFF;
1608 struct amdgpu_device *adev = psp->adev;
1609 struct ta_ras_shared_memory *ras_cmd;
1612 * TODO: bypass the initialize in sriov for now
1614 if (amdgpu_sriov_vf(adev))
1617 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1618 !adev->psp.ras_context.context.bin_desc.start_addr) {
1619 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1623 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1624 /* query GECC enablement status from boot config
1625 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1627 ret = psp_boot_config_get(adev, &boot_cfg);
1629 dev_warn(adev->dev, "PSP get boot config failed\n");
1631 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1633 dev_info(adev->dev, "GECC is disabled\n");
1635 /* disable GECC in next boot cycle if ras is
1636 * disabled by module parameter amdgpu_ras_enable
1637 * and/or amdgpu_ras_mask, or boot_config_get call
1640 ret = psp_boot_config_set(adev, 0);
1642 dev_warn(adev->dev, "PSP set boot config failed\n");
1644 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1647 if (boot_cfg == 1) {
1648 dev_info(adev->dev, "GECC is enabled\n");
1650 /* enable GECC in next boot cycle if it is disabled
1651 * in boot config, or force enable GECC if failed to
1652 * get boot configuration
1654 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1656 dev_warn(adev->dev, "PSP set boot config failed\n");
1658 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1663 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1664 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1666 if (!psp->ras_context.context.mem_context.shared_buf) {
1667 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1672 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1673 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1675 if (amdgpu_ras_is_poison_mode_supported(adev))
1676 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1677 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1678 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1679 ras_cmd->ras_in_message.init_flags.xcc_mask =
1681 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1683 ret = psp_ta_load(psp, &psp->ras_context.context);
1685 if (!ret && !ras_cmd->ras_status)
1686 psp->ras_context.context.initialized = true;
1688 if (ras_cmd->ras_status)
1689 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1691 /* fail to load RAS TA */
1692 psp->ras_context.context.initialized = false;
1698 int psp_ras_trigger_error(struct psp_context *psp,
1699 struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1701 struct ta_ras_shared_memory *ras_cmd;
1702 struct amdgpu_device *adev = psp->adev;
1706 if (!psp->ras_context.context.initialized)
1709 switch (info->block_id) {
1710 case TA_RAS_BLOCK__GFX:
1711 dev_mask = GET_MASK(GC, instance_mask);
1713 case TA_RAS_BLOCK__SDMA:
1714 dev_mask = GET_MASK(SDMA0, instance_mask);
1716 case TA_RAS_BLOCK__VCN:
1717 case TA_RAS_BLOCK__JPEG:
1718 dev_mask = GET_MASK(VCN, instance_mask);
1721 dev_mask = instance_mask;
1725 /* reuse sub_block_index for backward compatibility */
1726 dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1727 dev_mask &= AMDGPU_RAS_INST_MASK;
1728 info->sub_block_index |= dev_mask;
1730 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1731 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1733 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1734 ras_cmd->ras_in_message.trigger_error = *info;
1736 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1740 /* If err_event_athub occurs error inject was successful, however
1741 return status from TA is no long reliable */
1742 if (amdgpu_ras_intr_triggered())
1745 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1747 else if (ras_cmd->ras_status)
1755 static int psp_hdcp_initialize(struct psp_context *psp)
1760 * TODO: bypass the initialize in sriov for now
1762 if (amdgpu_sriov_vf(psp->adev))
1765 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1766 !psp->hdcp_context.context.bin_desc.start_addr) {
1767 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1771 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1772 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1774 if (!psp->hdcp_context.context.mem_context.shared_buf) {
1775 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1780 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1782 psp->hdcp_context.context.initialized = true;
1783 mutex_init(&psp->hdcp_context.mutex);
1789 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1792 * TODO: bypass the loading in sriov for now
1794 if (amdgpu_sriov_vf(psp->adev))
1797 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1800 static int psp_hdcp_terminate(struct psp_context *psp)
1805 * TODO: bypass the terminate in sriov for now
1807 if (amdgpu_sriov_vf(psp->adev))
1810 if (!psp->hdcp_context.context.initialized)
1813 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1815 psp->hdcp_context.context.initialized = false;
1822 static int psp_dtm_initialize(struct psp_context *psp)
1827 * TODO: bypass the initialize in sriov for now
1829 if (amdgpu_sriov_vf(psp->adev))
1832 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1833 !psp->dtm_context.context.bin_desc.start_addr) {
1834 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1838 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1839 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1841 if (!psp->dtm_context.context.mem_context.shared_buf) {
1842 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1847 ret = psp_ta_load(psp, &psp->dtm_context.context);
1849 psp->dtm_context.context.initialized = true;
1850 mutex_init(&psp->dtm_context.mutex);
1856 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1859 * TODO: bypass the loading in sriov for now
1861 if (amdgpu_sriov_vf(psp->adev))
1864 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1867 static int psp_dtm_terminate(struct psp_context *psp)
1872 * TODO: bypass the terminate in sriov for now
1874 if (amdgpu_sriov_vf(psp->adev))
1877 if (!psp->dtm_context.context.initialized)
1880 ret = psp_ta_unload(psp, &psp->dtm_context.context);
1882 psp->dtm_context.context.initialized = false;
1889 static int psp_rap_initialize(struct psp_context *psp)
1892 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1895 * TODO: bypass the initialize in sriov for now
1897 if (amdgpu_sriov_vf(psp->adev))
1900 if (!psp->rap_context.context.bin_desc.size_bytes ||
1901 !psp->rap_context.context.bin_desc.start_addr) {
1902 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1906 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1907 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1909 if (!psp->rap_context.context.mem_context.shared_buf) {
1910 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1915 ret = psp_ta_load(psp, &psp->rap_context.context);
1917 psp->rap_context.context.initialized = true;
1918 mutex_init(&psp->rap_context.mutex);
1922 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1923 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1924 psp_rap_terminate(psp);
1925 /* free rap shared memory */
1926 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1928 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1937 static int psp_rap_terminate(struct psp_context *psp)
1941 if (!psp->rap_context.context.initialized)
1944 ret = psp_ta_unload(psp, &psp->rap_context.context);
1946 psp->rap_context.context.initialized = false;
1951 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1953 struct ta_rap_shared_memory *rap_cmd;
1956 if (!psp->rap_context.context.initialized)
1959 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1960 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1963 mutex_lock(&psp->rap_context.mutex);
1965 rap_cmd = (struct ta_rap_shared_memory *)
1966 psp->rap_context.context.mem_context.shared_buf;
1967 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1969 rap_cmd->cmd_id = ta_cmd_id;
1970 rap_cmd->validation_method_id = METHOD_A;
1972 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1977 *status = rap_cmd->rap_status;
1980 mutex_unlock(&psp->rap_context.mutex);
1986 /* securedisplay start */
1987 static int psp_securedisplay_initialize(struct psp_context *psp)
1990 struct ta_securedisplay_cmd *securedisplay_cmd;
1993 * TODO: bypass the initialize in sriov for now
1995 if (amdgpu_sriov_vf(psp->adev))
1998 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1999 !psp->securedisplay_context.context.bin_desc.start_addr) {
2000 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2004 psp->securedisplay_context.context.mem_context.shared_mem_size =
2005 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2006 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2008 if (!psp->securedisplay_context.context.initialized) {
2009 ret = psp_ta_init_shared_buf(psp,
2010 &psp->securedisplay_context.context.mem_context);
2015 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2017 psp->securedisplay_context.context.initialized = true;
2018 mutex_init(&psp->securedisplay_context.mutex);
2022 mutex_lock(&psp->securedisplay_context.mutex);
2024 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2025 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2027 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2029 mutex_unlock(&psp->securedisplay_context.mutex);
2032 psp_securedisplay_terminate(psp);
2033 /* free securedisplay shared memory */
2034 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2035 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2039 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2040 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2041 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2042 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2043 /* don't try again */
2044 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2050 static int psp_securedisplay_terminate(struct psp_context *psp)
2055 * TODO:bypass the terminate in sriov for now
2057 if (amdgpu_sriov_vf(psp->adev))
2060 if (!psp->securedisplay_context.context.initialized)
2063 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2065 psp->securedisplay_context.context.initialized = false;
2070 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2074 if (!psp->securedisplay_context.context.initialized)
2077 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2078 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2081 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2085 /* SECUREDISPLAY end */
2087 static int psp_hw_start(struct psp_context *psp)
2089 struct amdgpu_device *adev = psp->adev;
2092 if (!amdgpu_sriov_vf(adev)) {
2093 if ((is_psp_fw_valid(psp->kdb)) &&
2094 (psp->funcs->bootloader_load_kdb != NULL)) {
2095 ret = psp_bootloader_load_kdb(psp);
2097 DRM_ERROR("PSP load kdb failed!\n");
2102 if ((is_psp_fw_valid(psp->spl)) &&
2103 (psp->funcs->bootloader_load_spl != NULL)) {
2104 ret = psp_bootloader_load_spl(psp);
2106 DRM_ERROR("PSP load spl failed!\n");
2111 if ((is_psp_fw_valid(psp->sys)) &&
2112 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2113 ret = psp_bootloader_load_sysdrv(psp);
2115 DRM_ERROR("PSP load sys drv failed!\n");
2120 if ((is_psp_fw_valid(psp->soc_drv)) &&
2121 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2122 ret = psp_bootloader_load_soc_drv(psp);
2124 DRM_ERROR("PSP load soc drv failed!\n");
2129 if ((is_psp_fw_valid(psp->intf_drv)) &&
2130 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2131 ret = psp_bootloader_load_intf_drv(psp);
2133 DRM_ERROR("PSP load intf drv failed!\n");
2138 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2139 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2140 ret = psp_bootloader_load_dbg_drv(psp);
2142 DRM_ERROR("PSP load dbg drv failed!\n");
2147 if ((is_psp_fw_valid(psp->ras_drv)) &&
2148 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2149 ret = psp_bootloader_load_ras_drv(psp);
2151 DRM_ERROR("PSP load ras_drv failed!\n");
2156 if ((is_psp_fw_valid(psp->sos)) &&
2157 (psp->funcs->bootloader_load_sos != NULL)) {
2158 ret = psp_bootloader_load_sos(psp);
2160 DRM_ERROR("PSP load sos failed!\n");
2166 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2168 DRM_ERROR("PSP create ring failed!\n");
2172 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2175 if (!psp_boottime_tmr(psp)) {
2176 ret = psp_tmr_init(psp);
2178 DRM_ERROR("PSP tmr init failed!\n");
2185 * For ASICs with DF Cstate management centralized
2186 * to PMFW, TMR setup should be performed after PMFW
2187 * loaded and before other non-psp firmware loaded.
2189 if (psp->pmfw_centralized_cstate_management) {
2190 ret = psp_load_smu_fw(psp);
2195 ret = psp_tmr_load(psp);
2197 DRM_ERROR("PSP load tmr failed!\n");
2204 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2205 enum psp_gfx_fw_type *type)
2207 switch (ucode->ucode_id) {
2208 case AMDGPU_UCODE_ID_CAP:
2209 *type = GFX_FW_TYPE_CAP;
2211 case AMDGPU_UCODE_ID_SDMA0:
2212 *type = GFX_FW_TYPE_SDMA0;
2214 case AMDGPU_UCODE_ID_SDMA1:
2215 *type = GFX_FW_TYPE_SDMA1;
2217 case AMDGPU_UCODE_ID_SDMA2:
2218 *type = GFX_FW_TYPE_SDMA2;
2220 case AMDGPU_UCODE_ID_SDMA3:
2221 *type = GFX_FW_TYPE_SDMA3;
2223 case AMDGPU_UCODE_ID_SDMA4:
2224 *type = GFX_FW_TYPE_SDMA4;
2226 case AMDGPU_UCODE_ID_SDMA5:
2227 *type = GFX_FW_TYPE_SDMA5;
2229 case AMDGPU_UCODE_ID_SDMA6:
2230 *type = GFX_FW_TYPE_SDMA6;
2232 case AMDGPU_UCODE_ID_SDMA7:
2233 *type = GFX_FW_TYPE_SDMA7;
2235 case AMDGPU_UCODE_ID_CP_MES:
2236 *type = GFX_FW_TYPE_CP_MES;
2238 case AMDGPU_UCODE_ID_CP_MES_DATA:
2239 *type = GFX_FW_TYPE_MES_STACK;
2241 case AMDGPU_UCODE_ID_CP_MES1:
2242 *type = GFX_FW_TYPE_CP_MES_KIQ;
2244 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2245 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2247 case AMDGPU_UCODE_ID_CP_CE:
2248 *type = GFX_FW_TYPE_CP_CE;
2250 case AMDGPU_UCODE_ID_CP_PFP:
2251 *type = GFX_FW_TYPE_CP_PFP;
2253 case AMDGPU_UCODE_ID_CP_ME:
2254 *type = GFX_FW_TYPE_CP_ME;
2256 case AMDGPU_UCODE_ID_CP_MEC1:
2257 *type = GFX_FW_TYPE_CP_MEC;
2259 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2260 *type = GFX_FW_TYPE_CP_MEC_ME1;
2262 case AMDGPU_UCODE_ID_CP_MEC2:
2263 *type = GFX_FW_TYPE_CP_MEC;
2265 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2266 *type = GFX_FW_TYPE_CP_MEC_ME2;
2268 case AMDGPU_UCODE_ID_RLC_P:
2269 *type = GFX_FW_TYPE_RLC_P;
2271 case AMDGPU_UCODE_ID_RLC_V:
2272 *type = GFX_FW_TYPE_RLC_V;
2274 case AMDGPU_UCODE_ID_RLC_G:
2275 *type = GFX_FW_TYPE_RLC_G;
2277 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2278 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2280 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2281 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2283 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2284 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2286 case AMDGPU_UCODE_ID_RLC_IRAM:
2287 *type = GFX_FW_TYPE_RLC_IRAM;
2289 case AMDGPU_UCODE_ID_RLC_DRAM:
2290 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2292 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2293 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2295 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2296 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2298 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2299 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2301 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2302 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2304 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2305 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2307 case AMDGPU_UCODE_ID_SMC:
2308 *type = GFX_FW_TYPE_SMU;
2310 case AMDGPU_UCODE_ID_PPTABLE:
2311 *type = GFX_FW_TYPE_PPTABLE;
2313 case AMDGPU_UCODE_ID_UVD:
2314 *type = GFX_FW_TYPE_UVD;
2316 case AMDGPU_UCODE_ID_UVD1:
2317 *type = GFX_FW_TYPE_UVD1;
2319 case AMDGPU_UCODE_ID_VCE:
2320 *type = GFX_FW_TYPE_VCE;
2322 case AMDGPU_UCODE_ID_VCN:
2323 *type = GFX_FW_TYPE_VCN;
2325 case AMDGPU_UCODE_ID_VCN1:
2326 *type = GFX_FW_TYPE_VCN1;
2328 case AMDGPU_UCODE_ID_DMCU_ERAM:
2329 *type = GFX_FW_TYPE_DMCU_ERAM;
2331 case AMDGPU_UCODE_ID_DMCU_INTV:
2332 *type = GFX_FW_TYPE_DMCU_ISR;
2334 case AMDGPU_UCODE_ID_VCN0_RAM:
2335 *type = GFX_FW_TYPE_VCN0_RAM;
2337 case AMDGPU_UCODE_ID_VCN1_RAM:
2338 *type = GFX_FW_TYPE_VCN1_RAM;
2340 case AMDGPU_UCODE_ID_DMCUB:
2341 *type = GFX_FW_TYPE_DMUB;
2343 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2344 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2346 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2347 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2349 case AMDGPU_UCODE_ID_IMU_I:
2350 *type = GFX_FW_TYPE_IMU_I;
2352 case AMDGPU_UCODE_ID_IMU_D:
2353 *type = GFX_FW_TYPE_IMU_D;
2355 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2356 *type = GFX_FW_TYPE_RS64_PFP;
2358 case AMDGPU_UCODE_ID_CP_RS64_ME:
2359 *type = GFX_FW_TYPE_RS64_ME;
2361 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2362 *type = GFX_FW_TYPE_RS64_MEC;
2364 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2365 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2367 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2368 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2370 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2371 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2373 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2374 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2376 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2377 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2379 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2380 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2382 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2383 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2385 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2386 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2388 case AMDGPU_UCODE_ID_MAXIMUM:
2396 static void psp_print_fw_hdr(struct psp_context *psp,
2397 struct amdgpu_firmware_info *ucode)
2399 struct amdgpu_device *adev = psp->adev;
2400 struct common_firmware_header *hdr;
2402 switch (ucode->ucode_id) {
2403 case AMDGPU_UCODE_ID_SDMA0:
2404 case AMDGPU_UCODE_ID_SDMA1:
2405 case AMDGPU_UCODE_ID_SDMA2:
2406 case AMDGPU_UCODE_ID_SDMA3:
2407 case AMDGPU_UCODE_ID_SDMA4:
2408 case AMDGPU_UCODE_ID_SDMA5:
2409 case AMDGPU_UCODE_ID_SDMA6:
2410 case AMDGPU_UCODE_ID_SDMA7:
2411 hdr = (struct common_firmware_header *)
2412 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2413 amdgpu_ucode_print_sdma_hdr(hdr);
2415 case AMDGPU_UCODE_ID_CP_CE:
2416 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2417 amdgpu_ucode_print_gfx_hdr(hdr);
2419 case AMDGPU_UCODE_ID_CP_PFP:
2420 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2421 amdgpu_ucode_print_gfx_hdr(hdr);
2423 case AMDGPU_UCODE_ID_CP_ME:
2424 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2425 amdgpu_ucode_print_gfx_hdr(hdr);
2427 case AMDGPU_UCODE_ID_CP_MEC1:
2428 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2429 amdgpu_ucode_print_gfx_hdr(hdr);
2431 case AMDGPU_UCODE_ID_RLC_G:
2432 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2433 amdgpu_ucode_print_rlc_hdr(hdr);
2435 case AMDGPU_UCODE_ID_SMC:
2436 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2437 amdgpu_ucode_print_smc_hdr(hdr);
2444 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2445 struct psp_gfx_cmd_resp *cmd)
2448 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2450 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2451 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2452 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2453 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2455 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2457 DRM_ERROR("Unknown firmware type\n");
2462 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2463 struct amdgpu_firmware_info *ucode)
2466 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2468 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2470 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2471 psp->fence_buf_mc_addr);
2474 release_psp_cmd_buf(psp);
2479 static int psp_load_smu_fw(struct psp_context *psp)
2482 struct amdgpu_device *adev = psp->adev;
2483 struct amdgpu_firmware_info *ucode =
2484 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2485 struct amdgpu_ras *ras = psp->ras_context.ras;
2488 * Skip SMU FW reloading in case of using BACO for runpm only,
2489 * as SMU is always alive.
2491 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2494 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2497 if ((amdgpu_in_reset(adev) &&
2498 ras && adev->ras_enabled &&
2499 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2500 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2501 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2503 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2506 ret = psp_execute_non_psp_fw_load(psp, ucode);
2509 DRM_ERROR("PSP load smu failed!\n");
2514 static bool fw_load_skip_check(struct psp_context *psp,
2515 struct amdgpu_firmware_info *ucode)
2517 if (!ucode->fw || !ucode->ucode_size)
2520 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2521 (psp_smu_reload_quirk(psp) ||
2522 psp->autoload_supported ||
2523 psp->pmfw_centralized_cstate_management))
2526 if (amdgpu_sriov_vf(psp->adev) &&
2527 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2530 if (psp->autoload_supported &&
2531 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2532 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2533 /* skip mec JT when autoload is enabled */
2539 int psp_load_fw_list(struct psp_context *psp,
2540 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2543 struct amdgpu_firmware_info *ucode;
2545 for (i = 0; i < ucode_count; ++i) {
2546 ucode = ucode_list[i];
2547 psp_print_fw_hdr(psp, ucode);
2548 ret = psp_execute_non_psp_fw_load(psp, ucode);
2555 static int psp_load_non_psp_fw(struct psp_context *psp)
2558 struct amdgpu_firmware_info *ucode;
2559 struct amdgpu_device *adev = psp->adev;
2561 if (psp->autoload_supported &&
2562 !psp->pmfw_centralized_cstate_management) {
2563 ret = psp_load_smu_fw(psp);
2568 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2569 ucode = &adev->firmware.ucode[i];
2571 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2572 !fw_load_skip_check(psp, ucode)) {
2573 ret = psp_load_smu_fw(psp);
2579 if (fw_load_skip_check(psp, ucode))
2582 if (psp->autoload_supported &&
2583 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2584 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2585 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2586 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2587 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2588 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2589 /* PSP only receive one SDMA fw for sienna_cichlid,
2590 * as all four sdma fw are same */
2593 psp_print_fw_hdr(psp, ucode);
2595 ret = psp_execute_non_psp_fw_load(psp, ucode);
2599 /* Start rlc autoload after psp recieved all the gfx firmware */
2600 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2601 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2602 ret = psp_rlc_autoload_start(psp);
2604 DRM_ERROR("Failed to start rlc autoload\n");
2613 static int psp_load_fw(struct amdgpu_device *adev)
2616 struct psp_context *psp = &adev->psp;
2618 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2619 /* should not destroy ring, only stop */
2620 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2622 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2624 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2626 DRM_ERROR("PSP ring init failed!\n");
2631 ret = psp_hw_start(psp);
2635 ret = psp_load_non_psp_fw(psp);
2639 ret = psp_asd_initialize(psp);
2641 DRM_ERROR("PSP load asd failed!\n");
2645 ret = psp_rl_load(adev);
2647 DRM_ERROR("PSP load RL failed!\n");
2651 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2652 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2653 ret = psp_xgmi_initialize(psp, false, true);
2654 /* Warning the XGMI seesion initialize failure
2655 * Instead of stop driver initialization
2658 dev_err(psp->adev->dev,
2659 "XGMI: Failed to initialize XGMI session\n");
2664 ret = psp_ras_initialize(psp);
2666 dev_err(psp->adev->dev,
2667 "RAS: Failed to initialize RAS\n");
2669 ret = psp_hdcp_initialize(psp);
2671 dev_err(psp->adev->dev,
2672 "HDCP: Failed to initialize HDCP\n");
2674 ret = psp_dtm_initialize(psp);
2676 dev_err(psp->adev->dev,
2677 "DTM: Failed to initialize DTM\n");
2679 ret = psp_rap_initialize(psp);
2681 dev_err(psp->adev->dev,
2682 "RAP: Failed to initialize RAP\n");
2684 ret = psp_securedisplay_initialize(psp);
2686 dev_err(psp->adev->dev,
2687 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2693 psp_free_shared_bufs(psp);
2696 * all cleanup jobs (xgmi terminate, ras terminate,
2697 * ring destroy, cmd/fence/fw buffers destory,
2698 * psp->cmd destory) are delayed to psp_hw_fini
2700 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2704 static int psp_hw_init(void *handle)
2707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2709 mutex_lock(&adev->firmware.mutex);
2711 * This sequence is just used on hw_init only once, no need on
2714 ret = amdgpu_ucode_init_bo(adev);
2718 ret = psp_load_fw(adev);
2720 DRM_ERROR("PSP firmware loading failed\n");
2724 mutex_unlock(&adev->firmware.mutex);
2728 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2729 mutex_unlock(&adev->firmware.mutex);
2733 static int psp_hw_fini(void *handle)
2735 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2736 struct psp_context *psp = &adev->psp;
2739 psp_ras_terminate(psp);
2740 psp_securedisplay_terminate(psp);
2741 psp_rap_terminate(psp);
2742 psp_dtm_terminate(psp);
2743 psp_hdcp_terminate(psp);
2745 if (adev->gmc.xgmi.num_physical_nodes > 1)
2746 psp_xgmi_terminate(psp);
2749 psp_asd_terminate(psp);
2750 psp_tmr_terminate(psp);
2752 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2757 static int psp_suspend(void *handle)
2760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2761 struct psp_context *psp = &adev->psp;
2763 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2764 psp->xgmi_context.context.initialized) {
2765 ret = psp_xgmi_terminate(psp);
2767 DRM_ERROR("Failed to terminate xgmi ta\n");
2773 ret = psp_ras_terminate(psp);
2775 DRM_ERROR("Failed to terminate ras ta\n");
2778 ret = psp_hdcp_terminate(psp);
2780 DRM_ERROR("Failed to terminate hdcp ta\n");
2783 ret = psp_dtm_terminate(psp);
2785 DRM_ERROR("Failed to terminate dtm ta\n");
2788 ret = psp_rap_terminate(psp);
2790 DRM_ERROR("Failed to terminate rap ta\n");
2793 ret = psp_securedisplay_terminate(psp);
2795 DRM_ERROR("Failed to terminate securedisplay ta\n");
2800 ret = psp_asd_terminate(psp);
2802 DRM_ERROR("Failed to terminate asd\n");
2806 ret = psp_tmr_terminate(psp);
2808 DRM_ERROR("Failed to terminate tmr\n");
2812 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2814 DRM_ERROR("PSP ring stop failed\n");
2820 static int psp_resume(void *handle)
2823 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2824 struct psp_context *psp = &adev->psp;
2826 DRM_INFO("PSP is resuming...\n");
2828 if (psp->mem_train_ctx.enable_mem_training) {
2829 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2831 DRM_ERROR("Failed to process memory training!\n");
2836 mutex_lock(&adev->firmware.mutex);
2838 ret = psp_hw_start(psp);
2842 ret = psp_load_non_psp_fw(psp);
2846 ret = psp_asd_initialize(psp);
2848 DRM_ERROR("PSP load asd failed!\n");
2852 ret = psp_rl_load(adev);
2854 dev_err(adev->dev, "PSP load RL failed!\n");
2858 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2859 ret = psp_xgmi_initialize(psp, false, true);
2860 /* Warning the XGMI seesion initialize failure
2861 * Instead of stop driver initialization
2864 dev_err(psp->adev->dev,
2865 "XGMI: Failed to initialize XGMI session\n");
2869 ret = psp_ras_initialize(psp);
2871 dev_err(psp->adev->dev,
2872 "RAS: Failed to initialize RAS\n");
2874 ret = psp_hdcp_initialize(psp);
2876 dev_err(psp->adev->dev,
2877 "HDCP: Failed to initialize HDCP\n");
2879 ret = psp_dtm_initialize(psp);
2881 dev_err(psp->adev->dev,
2882 "DTM: Failed to initialize DTM\n");
2884 ret = psp_rap_initialize(psp);
2886 dev_err(psp->adev->dev,
2887 "RAP: Failed to initialize RAP\n");
2889 ret = psp_securedisplay_initialize(psp);
2891 dev_err(psp->adev->dev,
2892 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2895 mutex_unlock(&adev->firmware.mutex);
2900 DRM_ERROR("PSP resume failed\n");
2901 mutex_unlock(&adev->firmware.mutex);
2905 int psp_gpu_reset(struct amdgpu_device *adev)
2909 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2912 mutex_lock(&adev->psp.mutex);
2913 ret = psp_mode1_reset(&adev->psp);
2914 mutex_unlock(&adev->psp.mutex);
2919 int psp_rlc_autoload_start(struct psp_context *psp)
2922 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2924 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2926 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2927 psp->fence_buf_mc_addr);
2929 release_psp_cmd_buf(psp);
2934 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2935 uint64_t cmd_gpu_addr, int cmd_size)
2937 struct amdgpu_firmware_info ucode = {0};
2939 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2940 AMDGPU_UCODE_ID_VCN0_RAM;
2941 ucode.mc_addr = cmd_gpu_addr;
2942 ucode.ucode_size = cmd_size;
2944 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2947 int psp_ring_cmd_submit(struct psp_context *psp,
2948 uint64_t cmd_buf_mc_addr,
2949 uint64_t fence_mc_addr,
2952 unsigned int psp_write_ptr_reg = 0;
2953 struct psp_gfx_rb_frame *write_frame;
2954 struct psp_ring *ring = &psp->km_ring;
2955 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2956 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2957 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2958 struct amdgpu_device *adev = psp->adev;
2959 uint32_t ring_size_dw = ring->ring_size / 4;
2960 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2962 /* KM (GPCOM) prepare write pointer */
2963 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2965 /* Update KM RB frame pointer to new frame */
2966 /* write_frame ptr increments by size of rb_frame in bytes */
2967 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2968 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2969 write_frame = ring_buffer_start;
2971 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2972 /* Check invalid write_frame ptr address */
2973 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2974 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2975 ring_buffer_start, ring_buffer_end, write_frame);
2976 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2980 /* Initialize KM RB frame */
2981 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2983 /* Update KM RB frame */
2984 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2985 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2986 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2987 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2988 write_frame->fence_value = index;
2989 amdgpu_device_flush_hdp(adev, NULL);
2991 /* Update the write Pointer in DWORDs */
2992 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2993 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2997 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2999 struct amdgpu_device *adev = psp->adev;
3000 char fw_name[PSP_FW_NAME_LEN];
3001 const struct psp_firmware_header_v1_0 *asd_hdr;
3004 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
3005 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
3009 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3010 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3011 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3012 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3013 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3014 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3017 amdgpu_ucode_release(&adev->psp.asd_fw);
3021 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3023 struct amdgpu_device *adev = psp->adev;
3024 char fw_name[PSP_FW_NAME_LEN];
3025 const struct psp_firmware_header_v1_0 *toc_hdr;
3028 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3029 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3033 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3034 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3035 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3036 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3037 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3038 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3041 amdgpu_ucode_release(&adev->psp.toc_fw);
3045 static int parse_sos_bin_descriptor(struct psp_context *psp,
3046 const struct psp_fw_bin_desc *desc,
3047 const struct psp_firmware_header_v2_0 *sos_hdr)
3049 uint8_t *ucode_start_addr = NULL;
3051 if (!psp || !desc || !sos_hdr)
3054 ucode_start_addr = (uint8_t *)sos_hdr +
3055 le32_to_cpu(desc->offset_bytes) +
3056 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3058 switch (desc->fw_type) {
3059 case PSP_FW_TYPE_PSP_SOS:
3060 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3061 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3062 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3063 psp->sos.start_addr = ucode_start_addr;
3065 case PSP_FW_TYPE_PSP_SYS_DRV:
3066 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3067 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3068 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3069 psp->sys.start_addr = ucode_start_addr;
3071 case PSP_FW_TYPE_PSP_KDB:
3072 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3073 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3074 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3075 psp->kdb.start_addr = ucode_start_addr;
3077 case PSP_FW_TYPE_PSP_TOC:
3078 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3079 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3080 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3081 psp->toc.start_addr = ucode_start_addr;
3083 case PSP_FW_TYPE_PSP_SPL:
3084 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3085 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3086 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3087 psp->spl.start_addr = ucode_start_addr;
3089 case PSP_FW_TYPE_PSP_RL:
3090 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3091 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3092 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3093 psp->rl.start_addr = ucode_start_addr;
3095 case PSP_FW_TYPE_PSP_SOC_DRV:
3096 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3097 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3098 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3099 psp->soc_drv.start_addr = ucode_start_addr;
3101 case PSP_FW_TYPE_PSP_INTF_DRV:
3102 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3103 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3104 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3105 psp->intf_drv.start_addr = ucode_start_addr;
3107 case PSP_FW_TYPE_PSP_DBG_DRV:
3108 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3109 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3110 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3111 psp->dbg_drv.start_addr = ucode_start_addr;
3113 case PSP_FW_TYPE_PSP_RAS_DRV:
3114 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3115 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3116 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3117 psp->ras_drv.start_addr = ucode_start_addr;
3120 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3127 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3129 const struct psp_firmware_header_v1_0 *sos_hdr;
3130 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3131 uint8_t *ucode_array_start_addr;
3133 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3134 ucode_array_start_addr = (uint8_t *)sos_hdr +
3135 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3137 if (adev->gmc.xgmi.connected_to_cpu ||
3138 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3139 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3140 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3142 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3143 adev->psp.sys.start_addr = ucode_array_start_addr;
3145 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3146 adev->psp.sos.start_addr = ucode_array_start_addr +
3147 le32_to_cpu(sos_hdr->sos.offset_bytes);
3149 /* Load alternate PSP SOS FW */
3150 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3152 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3153 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3155 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3156 adev->psp.sys.start_addr = ucode_array_start_addr +
3157 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3159 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3160 adev->psp.sos.start_addr = ucode_array_start_addr +
3161 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3164 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3165 dev_warn(adev->dev, "PSP SOS FW not available");
3172 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3174 struct amdgpu_device *adev = psp->adev;
3175 char fw_name[PSP_FW_NAME_LEN];
3176 const struct psp_firmware_header_v1_0 *sos_hdr;
3177 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3178 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3179 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3180 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3182 uint8_t *ucode_array_start_addr;
3185 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3186 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3190 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3191 ucode_array_start_addr = (uint8_t *)sos_hdr +
3192 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3193 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3195 switch (sos_hdr->header.header_version_major) {
3197 err = psp_init_sos_base_fw(adev);
3201 if (sos_hdr->header.header_version_minor == 1) {
3202 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3203 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3204 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3205 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3206 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3207 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3208 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3210 if (sos_hdr->header.header_version_minor == 2) {
3211 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3212 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3213 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3214 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3216 if (sos_hdr->header.header_version_minor == 3) {
3217 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3218 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3219 adev->psp.toc.start_addr = ucode_array_start_addr +
3220 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3221 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3222 adev->psp.kdb.start_addr = ucode_array_start_addr +
3223 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3224 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3225 adev->psp.spl.start_addr = ucode_array_start_addr +
3226 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3227 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3228 adev->psp.rl.start_addr = ucode_array_start_addr +
3229 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3233 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3235 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3236 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3241 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3242 err = parse_sos_bin_descriptor(psp,
3243 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3251 "unsupported psp sos firmware\n");
3258 amdgpu_ucode_release(&adev->psp.sos_fw);
3263 static int parse_ta_bin_descriptor(struct psp_context *psp,
3264 const struct psp_fw_bin_desc *desc,
3265 const struct ta_firmware_header_v2_0 *ta_hdr)
3267 uint8_t *ucode_start_addr = NULL;
3269 if (!psp || !desc || !ta_hdr)
3272 ucode_start_addr = (uint8_t *)ta_hdr +
3273 le32_to_cpu(desc->offset_bytes) +
3274 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3276 switch (desc->fw_type) {
3277 case TA_FW_TYPE_PSP_ASD:
3278 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3279 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3280 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3281 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3283 case TA_FW_TYPE_PSP_XGMI:
3284 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3285 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3286 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3288 case TA_FW_TYPE_PSP_RAS:
3289 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3290 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3291 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3293 case TA_FW_TYPE_PSP_HDCP:
3294 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3295 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3296 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3298 case TA_FW_TYPE_PSP_DTM:
3299 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3300 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3301 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3303 case TA_FW_TYPE_PSP_RAP:
3304 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3305 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3306 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3308 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3309 psp->securedisplay_context.context.bin_desc.fw_version =
3310 le32_to_cpu(desc->fw_version);
3311 psp->securedisplay_context.context.bin_desc.size_bytes =
3312 le32_to_cpu(desc->size_bytes);
3313 psp->securedisplay_context.context.bin_desc.start_addr =
3317 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3324 static int parse_ta_v1_microcode(struct psp_context *psp)
3326 const struct ta_firmware_header_v1_0 *ta_hdr;
3327 struct amdgpu_device *adev = psp->adev;
3329 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3331 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3334 adev->psp.xgmi_context.context.bin_desc.fw_version =
3335 le32_to_cpu(ta_hdr->xgmi.fw_version);
3336 adev->psp.xgmi_context.context.bin_desc.size_bytes =
3337 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3338 adev->psp.xgmi_context.context.bin_desc.start_addr =
3340 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3342 adev->psp.ras_context.context.bin_desc.fw_version =
3343 le32_to_cpu(ta_hdr->ras.fw_version);
3344 adev->psp.ras_context.context.bin_desc.size_bytes =
3345 le32_to_cpu(ta_hdr->ras.size_bytes);
3346 adev->psp.ras_context.context.bin_desc.start_addr =
3347 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3348 le32_to_cpu(ta_hdr->ras.offset_bytes);
3350 adev->psp.hdcp_context.context.bin_desc.fw_version =
3351 le32_to_cpu(ta_hdr->hdcp.fw_version);
3352 adev->psp.hdcp_context.context.bin_desc.size_bytes =
3353 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3354 adev->psp.hdcp_context.context.bin_desc.start_addr =
3356 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3358 adev->psp.dtm_context.context.bin_desc.fw_version =
3359 le32_to_cpu(ta_hdr->dtm.fw_version);
3360 adev->psp.dtm_context.context.bin_desc.size_bytes =
3361 le32_to_cpu(ta_hdr->dtm.size_bytes);
3362 adev->psp.dtm_context.context.bin_desc.start_addr =
3363 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3364 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3366 adev->psp.securedisplay_context.context.bin_desc.fw_version =
3367 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3368 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3369 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3370 adev->psp.securedisplay_context.context.bin_desc.start_addr =
3371 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3372 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3374 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3379 static int parse_ta_v2_microcode(struct psp_context *psp)
3381 const struct ta_firmware_header_v2_0 *ta_hdr;
3382 struct amdgpu_device *adev = psp->adev;
3386 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3388 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3391 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3392 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3396 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3397 err = parse_ta_bin_descriptor(psp,
3398 &ta_hdr->ta_fw_bin[ta_index],
3407 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3409 const struct common_firmware_header *hdr;
3410 struct amdgpu_device *adev = psp->adev;
3411 char fw_name[PSP_FW_NAME_LEN];
3414 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3415 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3419 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3420 switch (le16_to_cpu(hdr->header_version_major)) {
3422 err = parse_ta_v1_microcode(psp);
3425 err = parse_ta_v2_microcode(psp);
3428 dev_err(adev->dev, "unsupported TA header version\n");
3433 amdgpu_ucode_release(&adev->psp.ta_fw);
3438 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3440 struct amdgpu_device *adev = psp->adev;
3441 char fw_name[PSP_FW_NAME_LEN];
3442 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3443 struct amdgpu_firmware_info *info = NULL;
3446 if (!amdgpu_sriov_vf(adev)) {
3447 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3451 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3452 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3454 if (err == -ENODEV) {
3455 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3459 dev_err(adev->dev, "fail to initialize cap microcode\n");
3462 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3463 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3464 info->fw = adev->psp.cap_fw;
3465 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3466 adev->psp.cap_fw->data;
3467 adev->firmware.fw_size += ALIGN(
3468 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3469 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3470 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3471 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3476 amdgpu_ucode_release(&adev->psp.cap_fw);
3480 static int psp_set_clockgating_state(void *handle,
3481 enum amd_clockgating_state state)
3486 static int psp_set_powergating_state(void *handle,
3487 enum amd_powergating_state state)
3492 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3493 struct device_attribute *attr,
3496 struct drm_device *ddev = dev_get_drvdata(dev);
3497 struct amdgpu_device *adev = drm_to_adev(ddev);
3501 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3502 DRM_INFO("PSP block is not ready yet.");
3506 mutex_lock(&adev->psp.mutex);
3507 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3508 mutex_unlock(&adev->psp.mutex);
3511 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3515 return sysfs_emit(buf, "%x\n", fw_ver);
3518 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3519 struct device_attribute *attr,
3523 struct drm_device *ddev = dev_get_drvdata(dev);
3524 struct amdgpu_device *adev = drm_to_adev(ddev);
3527 const struct firmware *usbc_pd_fw;
3528 struct amdgpu_bo *fw_buf_bo = NULL;
3529 uint64_t fw_pri_mc_addr;
3530 void *fw_pri_cpu_addr;
3532 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3533 DRM_INFO("PSP block is not ready yet.");
3537 if (!drm_dev_enter(ddev, &idx))
3540 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3541 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3545 /* LFB address which is aligned to 1MB boundary per PSP request */
3546 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3547 AMDGPU_GEM_DOMAIN_VRAM |
3548 AMDGPU_GEM_DOMAIN_GTT,
3549 &fw_buf_bo, &fw_pri_mc_addr,
3554 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3556 mutex_lock(&adev->psp.mutex);
3557 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3558 mutex_unlock(&adev->psp.mutex);
3560 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3563 release_firmware(usbc_pd_fw);
3566 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3574 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3578 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3581 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3582 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3587 static DEVICE_ATTR(usbc_pd_fw, 0644,
3588 psp_usbc_pd_fw_sysfs_read,
3589 psp_usbc_pd_fw_sysfs_write);
3591 int is_psp_fw_valid(struct psp_bin_desc bin)
3593 return bin.size_bytes;
3596 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3597 struct bin_attribute *bin_attr,
3598 char *buffer, loff_t pos, size_t count)
3600 struct device *dev = kobj_to_dev(kobj);
3601 struct drm_device *ddev = dev_get_drvdata(dev);
3602 struct amdgpu_device *adev = drm_to_adev(ddev);
3604 adev->psp.vbflash_done = false;
3606 /* Safeguard against memory drain */
3607 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3608 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3609 kvfree(adev->psp.vbflash_tmp_buf);
3610 adev->psp.vbflash_tmp_buf = NULL;
3611 adev->psp.vbflash_image_size = 0;
3615 /* TODO Just allocate max for now and optimize to realloc later if needed */
3616 if (!adev->psp.vbflash_tmp_buf) {
3617 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3618 if (!adev->psp.vbflash_tmp_buf)
3622 mutex_lock(&adev->psp.mutex);
3623 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3624 adev->psp.vbflash_image_size += count;
3625 mutex_unlock(&adev->psp.mutex);
3627 dev_info(adev->dev, "VBIOS flash write PSP done");
3632 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3633 struct bin_attribute *bin_attr, char *buffer,
3634 loff_t pos, size_t count)
3636 struct device *dev = kobj_to_dev(kobj);
3637 struct drm_device *ddev = dev_get_drvdata(dev);
3638 struct amdgpu_device *adev = drm_to_adev(ddev);
3639 struct amdgpu_bo *fw_buf_bo = NULL;
3640 uint64_t fw_pri_mc_addr;
3641 void *fw_pri_cpu_addr;
3644 if (adev->psp.vbflash_image_size == 0)
3647 dev_info(adev->dev, "VBIOS flash to PSP started");
3649 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3650 AMDGPU_GPU_PAGE_SIZE,
3651 AMDGPU_GEM_DOMAIN_VRAM,
3658 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3660 mutex_lock(&adev->psp.mutex);
3661 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3662 mutex_unlock(&adev->psp.mutex);
3664 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3667 kvfree(adev->psp.vbflash_tmp_buf);
3668 adev->psp.vbflash_tmp_buf = NULL;
3669 adev->psp.vbflash_image_size = 0;
3672 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3676 dev_info(adev->dev, "VBIOS flash to PSP done");
3680 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3681 struct device_attribute *attr,
3684 struct drm_device *ddev = dev_get_drvdata(dev);
3685 struct amdgpu_device *adev = drm_to_adev(ddev);
3686 uint32_t vbflash_status;
3688 vbflash_status = psp_vbflash_status(&adev->psp);
3689 if (!adev->psp.vbflash_done)
3691 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3694 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3697 static const struct bin_attribute psp_vbflash_bin_attr = {
3698 .attr = {.name = "psp_vbflash", .mode = 0660},
3700 .write = amdgpu_psp_vbflash_write,
3701 .read = amdgpu_psp_vbflash_read,
3704 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3706 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3710 if (amdgpu_sriov_vf(adev))
3713 switch (adev->ip_versions[MP0_HWIP][0]) {
3714 case IP_VERSION(13, 0, 0):
3715 case IP_VERSION(13, 0, 7):
3716 case IP_VERSION(13, 0, 10):
3717 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3719 dev_err(adev->dev, "Failed to create device file psp_vbflash");
3720 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3722 dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3729 const struct amd_ip_funcs psp_ip_funcs = {
3731 .early_init = psp_early_init,
3733 .sw_init = psp_sw_init,
3734 .sw_fini = psp_sw_fini,
3735 .hw_init = psp_hw_init,
3736 .hw_fini = psp_hw_fini,
3737 .suspend = psp_suspend,
3738 .resume = psp_resume,
3740 .check_soft_reset = NULL,
3741 .wait_for_idle = NULL,
3743 .set_clockgating_state = psp_set_clockgating_state,
3744 .set_powergating_state = psp_set_powergating_state,
3747 static int psp_sysfs_init(struct amdgpu_device *adev)
3749 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3752 DRM_ERROR("Failed to create USBC PD FW control file!");
3757 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3759 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3760 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3763 static void psp_sysfs_fini(struct amdgpu_device *adev)
3765 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3768 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3769 .type = AMD_IP_BLOCK_TYPE_PSP,
3773 .funcs = &psp_ip_funcs,
3776 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3777 .type = AMD_IP_BLOCK_TYPE_PSP,
3781 .funcs = &psp_ip_funcs,
3784 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3785 .type = AMD_IP_BLOCK_TYPE_PSP,
3789 .funcs = &psp_ip_funcs,
3792 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3793 .type = AMD_IP_BLOCK_TYPE_PSP,
3797 .funcs = &psp_ip_funcs,
3800 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3801 .type = AMD_IP_BLOCK_TYPE_PSP,
3805 .funcs = &psp_ip_funcs,
3808 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3809 .type = AMD_IP_BLOCK_TYPE_PSP,
3813 .funcs = &psp_ip_funcs,
3816 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3817 .type = AMD_IP_BLOCK_TYPE_PSP,
3821 .funcs = &psp_ip_funcs,