drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40
  41         psp_set_funcs(adev);
  42
  43         return 0;
  44 }
  45
  46 static int psp_sw_init(void *handle)
  47 {
  48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  49         struct psp_context *psp = &adev->psp;
  50         int ret;
  51
  52         switch (adev->asic_type) {
  53         case CHIP_VEGA10:
  54                 psp->init_microcode = psp_v3_1_init_microcode;
  55                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  56                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  57                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  58                 psp->ring_init = psp_v3_1_ring_init;
  59                 psp->ring_create = psp_v3_1_ring_create;
  60                 psp->ring_stop = psp_v3_1_ring_stop;
  61                 psp->ring_destroy = psp_v3_1_ring_destroy;
  62                 psp->cmd_submit = psp_v3_1_cmd_submit;
  63                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  64                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  65                 psp->mode1_reset = psp_v3_1_mode1_reset;
  66                 break;
  67         case CHIP_RAVEN:
  68                 psp->init_microcode = psp_v10_0_init_microcode;
  69                 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
  70                 psp->ring_init = psp_v10_0_ring_init;
  71                 psp->ring_create = psp_v10_0_ring_create;
  72                 psp->ring_stop = psp_v10_0_ring_stop;
  73                 psp->ring_destroy = psp_v10_0_ring_destroy;
  74                 psp->cmd_submit = psp_v10_0_cmd_submit;
  75                 psp->compare_sram_data = psp_v10_0_compare_sram_data;
  76                 psp->mode1_reset = psp_v10_0_mode1_reset;
  77                 break;
  78         default:
  79                 return -EINVAL;
  80         }
  81
  82         psp->adev = adev;
  83
  84         ret = psp_init_microcode(psp);
  85         if (ret) {
  86                 DRM_ERROR("Failed to load psp firmware!\n");
  87                 return ret;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int psp_sw_fini(void *handle)
  94 {
  95         return 0;
  96 }
  97
  98 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  99                  uint32_t reg_val, uint32_t mask, bool check_changed)
 100 {
 101         uint32_t val;
 102         int i;
 103         struct amdgpu_device *adev = psp->adev;
 104
 105         for (i = 0; i < adev->usec_timeout; i++) {
 106                 val = RREG32(reg_index);
 107                 if (check_changed) {
 108                         if (val != reg_val)
 109                                 return 0;
 110                 } else {
 111                         if ((val & mask) == reg_val)
 112                                 return 0;
 113                 }
 114                 udelay(1);
 115         }
 116
 117         return -ETIME;
 118 }
 119
 120 static int
 121 psp_cmd_submit_buf(struct psp_context *psp,
 122                    struct amdgpu_firmware_info *ucode,
 123                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 124                    int index)
 125 {
 126         int ret;
 127
 128         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 129
 130         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 131
 132         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 133                              fence_mc_addr, index);
 134
 135         while (*((unsigned int *)psp->fence_buf) != index) {
 136                 msleep(1);
 137         }
 138
 139         return ret;
 140 }
 141
 142 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 143                                  uint64_t tmr_mc, uint32_t size)
 144 {
 145         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 146         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 147         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 148         cmd->cmd.cmd_setup_tmr.buf_size = size;
 149 }
 150
 151 /* Set up Trusted Memory Region */
 152 static int psp_tmr_init(struct psp_context *psp)
 153 {
 154         int ret;
 155
 156         /*
 157          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 158          * physical).
 159          *
 160          * Note: this memory need be reserved till the driver
 161          * uninitializes.
 162          */
 163         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 164                                       AMDGPU_GEM_DOMAIN_VRAM,
 165                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 166
 167         return ret;
 168 }
 169
 170 static int psp_tmr_load(struct psp_context *psp)
 171 {
 172         int ret;
 173         struct psp_gfx_cmd_resp *cmd;
 174
 175         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 176         if (!cmd)
 177                 return -ENOMEM;
 178
 179         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 180
 181         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 182                                  psp->fence_buf_mc_addr, 1);
 183         if (ret)
 184                 goto failed;
 185
 186         kfree(cmd);
 187
 188         return 0;
 189
 190 failed:
 191         kfree(cmd);
 192         return ret;
 193 }
 194
 195 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 196                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 197                                  uint32_t size, uint32_t shared_size)
 198 {
 199         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 200         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 201         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 202         cmd->cmd.cmd_load_ta.app_len = size;
 203
 204         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 205         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 206         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 207 }
 208
 209 static int psp_asd_init(struct psp_context *psp)
 210 {
 211         int ret;
 212
 213         /*
 214          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 215          * physical) for shared ASD <-> Driver
 216          */
 217         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 218                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 219                                       &psp->asd_shared_bo,
 220                                       &psp->asd_shared_mc_addr,
 221                                       &psp->asd_shared_buf);
 222
 223         return ret;
 224 }
 225
 226 static int psp_asd_load(struct psp_context *psp)
 227 {
 228         int ret;
 229         struct psp_gfx_cmd_resp *cmd;
 230
 231         /* If PSP version doesn't match ASD version, asd loading will be failed.
 232          * add workaround to bypass it for sriov now.
 233          * TODO: add version check to make it common
 234          */
 235         if (amdgpu_sriov_vf(psp->adev))
 236                 return 0;
 237
 238         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 239         if (!cmd)
 240                 return -ENOMEM;
 241
 242         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 243         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 244
 245         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 246                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 247
 248         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 249                                  psp->fence_buf_mc_addr, 2);
 250
 251         kfree(cmd);
 252
 253         return ret;
 254 }
 255
 256 static int psp_hw_start(struct psp_context *psp)
 257 {
 258         struct amdgpu_device *adev = psp->adev;
 259         int ret;
 260
 261         if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
 262                 ret = psp_bootloader_load_sysdrv(psp);
 263                 if (ret)
 264                         return ret;
 265
 266                 ret = psp_bootloader_load_sos(psp);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 272         if (ret)
 273                 return ret;
 274
 275         ret = psp_tmr_load(psp);
 276         if (ret)
 277                 return ret;
 278
 279         ret = psp_asd_load(psp);
 280         if (ret)
 281                 return ret;
 282
 283         return 0;
 284 }
 285
 286 static int psp_np_fw_load(struct psp_context *psp)
 287 {
 288         int i, ret;
 289         struct amdgpu_firmware_info *ucode;
 290         struct amdgpu_device* adev = psp->adev;
 291
 292         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 293                 ucode = &adev->firmware.ucode[i];
 294                 if (!ucode->fw)
 295                         continue;
 296
 297                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 298                     psp_smu_reload_quirk(psp))
 299                         continue;
 300                 if (amdgpu_sriov_vf(adev) &&
 301                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 302                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 303                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 304                         /*skip ucode loading in SRIOV VF */
 305                         continue;
 306
 307                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 308                 if (ret)
 309                         return ret;
 310
 311                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 312                                          psp->fence_buf_mc_addr, i + 3);
 313                 if (ret)
 314                         return ret;
 315
 316 #if 0
 317                 /* check if firmware loaded sucessfully */
 318                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 319                         return -EINVAL;
 320 #endif
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int psp_load_fw(struct amdgpu_device *adev)
 327 {
 328         int ret;
 329         struct psp_context *psp = &adev->psp;
 330
 331         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 332         if (!psp->cmd)
 333                 return -ENOMEM;
 334
 335         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 336                                       AMDGPU_GEM_DOMAIN_GTT,
 337                                       &psp->fw_pri_bo,
 338                                       &psp->fw_pri_mc_addr,
 339                                       &psp->fw_pri_buf);
 340         if (ret)
 341                 goto failed;
 342
 343         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 344                                       AMDGPU_GEM_DOMAIN_VRAM,
 345                                       &psp->fence_buf_bo,
 346                                       &psp->fence_buf_mc_addr,
 347                                       &psp->fence_buf);
 348         if (ret)
 349                 goto failed_mem2;
 350
 351         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 352                                       AMDGPU_GEM_DOMAIN_VRAM,
 353                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 354                                       (void **)&psp->cmd_buf_mem);
 355         if (ret)
 356                 goto failed_mem1;
 357
 358         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 359
 360         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 361         if (ret)
 362                 goto failed_mem;
 363
 364         ret = psp_tmr_init(psp);
 365         if (ret)
 366                 goto failed_mem;
 367
 368         ret = psp_asd_init(psp);
 369         if (ret)
 370                 goto failed_mem;
 371
 372         ret = psp_hw_start(psp);
 373         if (ret)
 374                 goto failed_mem;
 375
 376         ret = psp_np_fw_load(psp);
 377         if (ret)
 378                 goto failed_mem;
 379
 380         return 0;
 381
 382 failed_mem:
 383         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 384                               &psp->cmd_buf_mc_addr,
 385                               (void **)&psp->cmd_buf_mem);
 386 failed_mem1:
 387         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 388                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 389 failed_mem2:
 390         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 391                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 392 failed:
 393         kfree(psp->cmd);
 394         psp->cmd = NULL;
 395         return ret;
 396 }
 397
 398 static int psp_hw_init(void *handle)
 399 {
 400         int ret;
 401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 402
 403
 404         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 405                 return 0;
 406
 407         mutex_lock(&adev->firmware.mutex);
 408         /*
 409          * This sequence is just used on hw_init only once, no need on
 410          * resume.
 411          */
 412         ret = amdgpu_ucode_init_bo(adev);
 413         if (ret)
 414                 goto failed;
 415
 416         ret = psp_load_fw(adev);
 417         if (ret) {
 418                 DRM_ERROR("PSP firmware loading failed\n");
 419                 goto failed;
 420         }
 421
 422         mutex_unlock(&adev->firmware.mutex);
 423         return 0;
 424
 425 failed:
 426         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 427         mutex_unlock(&adev->firmware.mutex);
 428         return -EINVAL;
 429 }
 430
 431 static int psp_hw_fini(void *handle)
 432 {
 433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 434         struct psp_context *psp = &adev->psp;
 435
 436         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 437                 return 0;
 438
 439         amdgpu_ucode_fini_bo(adev);
 440
 441         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 442
 443         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 444         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 445                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 446         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 447                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 448         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 449                               &psp->asd_shared_buf);
 450         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 451                               (void **)&psp->cmd_buf_mem);
 452
 453         kfree(psp->cmd);
 454         psp->cmd = NULL;
 455
 456         return 0;
 457 }
 458
 459 static int psp_suspend(void *handle)
 460 {
 461         int ret;
 462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 463         struct psp_context *psp = &adev->psp;
 464
 465         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 466         if (ret) {
 467                 DRM_ERROR("PSP ring stop failed\n");
 468                 return ret;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static int psp_resume(void *handle)
 475 {
 476         int ret;
 477         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 478         struct psp_context *psp = &adev->psp;
 479
 480         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 481                 return 0;
 482
 483         DRM_INFO("PSP is resuming...\n");
 484
 485         mutex_lock(&adev->firmware.mutex);
 486
 487         ret = psp_hw_start(psp);
 488         if (ret)
 489                 goto failed;
 490
 491         ret = psp_np_fw_load(psp);
 492         if (ret)
 493                 goto failed;
 494
 495         mutex_unlock(&adev->firmware.mutex);
 496
 497         return 0;
 498
 499 failed:
 500         DRM_ERROR("PSP resume failed\n");
 501         mutex_unlock(&adev->firmware.mutex);
 502         return ret;
 503 }
 504
 505 static bool psp_check_reset(void* handle)
 506 {
 507         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 508
 509         if (adev->flags & AMD_IS_APU)
 510                 return true;
 511
 512         return false;
 513 }
 514
 515 static int psp_reset(void* handle)
 516 {
 517         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 518         return psp_mode1_reset(&adev->psp);
 519 }
 520
 521 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 522                                         enum AMDGPU_UCODE_ID ucode_type)
 523 {
 524         struct amdgpu_firmware_info *ucode = NULL;
 525
 526         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 527                 DRM_INFO("firmware is not loaded by PSP\n");
 528                 return true;
 529         }
 530
 531         if (!adev->firmware.fw_size)
 532                 return false;
 533
 534         ucode = &adev->firmware.ucode[ucode_type];
 535         if (!ucode->fw || !ucode->ucode_size)
 536                 return false;
 537
 538         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 539 }
 540
 541 static int psp_set_clockgating_state(void *handle,
 542                                      enum amd_clockgating_state state)
 543 {
 544         return 0;
 545 }
 546
 547 static int psp_set_powergating_state(void *handle,
 548                                      enum amd_powergating_state state)
 549 {
 550         return 0;
 551 }
 552
 553 const struct amd_ip_funcs psp_ip_funcs = {
 554         .name = "psp",
 555         .early_init = psp_early_init,
 556         .late_init = NULL,
 557         .sw_init = psp_sw_init,
 558         .sw_fini = psp_sw_fini,
 559         .hw_init = psp_hw_init,
 560         .hw_fini = psp_hw_fini,
 561         .suspend = psp_suspend,
 562         .resume = psp_resume,
 563         .is_idle = NULL,
 564         .check_soft_reset = psp_check_reset,
 565         .wait_for_idle = NULL,
 566         .soft_reset = psp_reset,
 567         .set_clockgating_state = psp_set_clockgating_state,
 568         .set_powergating_state = psp_set_powergating_state,
 569 };
 570
 571 static const struct amdgpu_psp_funcs psp_funcs = {
 572         .check_fw_loading_status = psp_check_fw_loading_status,
 573 };
 574
 575 static void psp_set_funcs(struct amdgpu_device *adev)
 576 {
 577         if (NULL == adev->firmware.funcs)
 578                 adev->firmware.funcs = &psp_funcs;
 579 }
 580
 581 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 582 {
 583         .type = AMD_IP_BLOCK_TYPE_PSP,
 584         .major = 3,
 585         .minor = 1,
 586         .rev = 0,
 587         .funcs = &psp_ip_funcs,
 588 };
 589
 590 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 591 {
 592         .type = AMD_IP_BLOCK_TYPE_PSP,
 593         .major = 10,
 594         .minor = 0,
 595         .rev = 0,
 596         .funcs = &psp_ip_funcs,
 597 };