drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 break;
 152         default:
 153                 return -EINVAL;
 154         }
 155         return ret;
 156 }
 157
 158 static int psp_early_init(void *handle)
 159 {
 160         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 161         struct psp_context *psp = &adev->psp;
 162
 163         switch (adev->ip_versions[MP0_HWIP][0]) {
 164         case IP_VERSION(9, 0, 0):
 165                 psp_v3_1_set_psp_funcs(psp);
 166                 psp->autoload_supported = false;
 167                 break;
 168         case IP_VERSION(10, 0, 0):
 169         case IP_VERSION(10, 0, 1):
 170                 psp_v10_0_set_psp_funcs(psp);
 171                 psp->autoload_supported = false;
 172                 break;
 173         case IP_VERSION(11, 0, 2):
 174         case IP_VERSION(11, 0, 4):
 175                 psp_v11_0_set_psp_funcs(psp);
 176                 psp->autoload_supported = false;
 177                 break;
 178         case IP_VERSION(11, 0, 0):
 179         case IP_VERSION(11, 0, 5):
 180         case IP_VERSION(11, 0, 9):
 181         case IP_VERSION(11, 0, 7):
 182         case IP_VERSION(11, 0, 11):
 183         case IP_VERSION(11, 5, 0):
 184         case IP_VERSION(11, 0, 12):
 185         case IP_VERSION(11, 0, 13):
 186                 psp_v11_0_set_psp_funcs(psp);
 187                 psp->autoload_supported = true;
 188                 break;
 189         case IP_VERSION(11, 0, 3):
 190         case IP_VERSION(12, 0, 1):
 191                 psp_v12_0_set_psp_funcs(psp);
 192                 break;
 193         case IP_VERSION(13, 0, 2):
 194         case IP_VERSION(13, 0, 6):
 195                 psp_v13_0_set_psp_funcs(psp);
 196                 break;
 197         case IP_VERSION(13, 0, 1):
 198         case IP_VERSION(13, 0, 3):
 199         case IP_VERSION(13, 0, 5):
 200         case IP_VERSION(13, 0, 8):
 201         case IP_VERSION(13, 0, 10):
 202         case IP_VERSION(13, 0, 11):
 203                 psp_v13_0_set_psp_funcs(psp);
 204                 psp->autoload_supported = true;
 205                 break;
 206         case IP_VERSION(11, 0, 8):
 207                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 208                         psp_v11_0_8_set_psp_funcs(psp);
 209                         psp->autoload_supported = false;
 210                 }
 211                 break;
 212         case IP_VERSION(13, 0, 0):
 213         case IP_VERSION(13, 0, 7):
 214                 psp_v13_0_set_psp_funcs(psp);
 215                 psp->autoload_supported = true;
 216                 break;
 217         case IP_VERSION(13, 0, 4):
 218                 psp_v13_0_4_set_psp_funcs(psp);
 219                 psp->autoload_supported = true;
 220                 break;
 221         default:
 222                 return -EINVAL;
 223         }
 224
 225         psp->adev = adev;
 226
 227         psp_check_pmfw_centralized_cstate_management(psp);
 228
 229         if (amdgpu_sriov_vf(adev))
 230                 return psp_init_sriov_microcode(psp);
 231         else
 232                 return psp_init_microcode(psp);
 233 }
 234
 235 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 236 {
 237         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 238                               &mem_ctx->shared_buf);
 239         mem_ctx->shared_bo = NULL;
 240 }
 241
 242 static void psp_free_shared_bufs(struct psp_context *psp)
 243 {
 244         void *tmr_buf;
 245         void **pptr;
 246
 247         /* free TMR memory buffer */
 248         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 249         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 250         psp->tmr_bo = NULL;
 251
 252         /* free xgmi shared memory */
 253         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 254
 255         /* free ras shared memory */
 256         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 257
 258         /* free hdcp shared memory */
 259         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 260
 261         /* free dtm shared memory */
 262         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 263
 264         /* free rap shared memory */
 265         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 266
 267         /* free securedisplay shared memory */
 268         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 269
 270
 271 }
 272
 273 static void psp_memory_training_fini(struct psp_context *psp)
 274 {
 275         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 276
 277         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 278         kfree(ctx->sys_cache);
 279         ctx->sys_cache = NULL;
 280 }
 281
 282 static int psp_memory_training_init(struct psp_context *psp)
 283 {
 284         int ret;
 285         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 286
 287         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 288                 DRM_DEBUG("memory training is not supported!\n");
 289                 return 0;
 290         }
 291
 292         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 293         if (ctx->sys_cache == NULL) {
 294                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 295                 ret = -ENOMEM;
 296                 goto Err_out;
 297         }
 298
 299         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 300                   ctx->train_data_size,
 301                   ctx->p2c_train_data_offset,
 302                   ctx->c2p_train_data_offset);
 303         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 304         return 0;
 305
 306 Err_out:
 307         psp_memory_training_fini(psp);
 308         return ret;
 309 }
 310
 311 /*
 312  * Helper funciton to query psp runtime database entry
 313  *
 314  * @adev: amdgpu_device pointer
 315  * @entry_type: the type of psp runtime database entry
 316  * @db_entry: runtime database entry pointer
 317  *
 318  * Return false if runtime database doesn't exit or entry is invalid
 319  * or true if the specific database entry is found, and copy to @db_entry
 320  */
 321 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 322                                      enum psp_runtime_entry_type entry_type,
 323                                      void *db_entry)
 324 {
 325         uint64_t db_header_pos, db_dir_pos;
 326         struct psp_runtime_data_header db_header = {0};
 327         struct psp_runtime_data_directory db_dir = {0};
 328         bool ret = false;
 329         int i;
 330
 331         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 332         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 333
 334         /* read runtime db header from vram */
 335         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 336                         sizeof(struct psp_runtime_data_header), false);
 337
 338         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 339                 /* runtime db doesn't exist, exit */
 340                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 341                 return false;
 342         }
 343
 344         /* read runtime database entry from vram */
 345         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 346                         sizeof(struct psp_runtime_data_directory), false);
 347
 348         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 349                 /* invalid db entry count, exit */
 350                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 351                 return false;
 352         }
 353
 354         /* look up for requested entry type */
 355         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 356                 if (db_dir.entry_list[i].entry_type == entry_type) {
 357                         switch (entry_type) {
 358                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 359                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 360                                         /* invalid db entry size */
 361                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 362                                         return false;
 363                                 }
 364                                 /* read runtime database entry */
 365                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 366                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 367                                 ret = true;
 368                                 break;
 369                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 370                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 371                                         /* invalid db entry size */
 372                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 373                                         return false;
 374                                 }
 375                                 /* read runtime database entry */
 376                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 377                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 378                                 ret = true;
 379                                 break;
 380                         default:
 381                                 ret = false;
 382                                 break;
 383                         }
 384                 }
 385         }
 386
 387         return ret;
 388 }
 389
 390 static int psp_sw_init(void *handle)
 391 {
 392         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 393         struct psp_context *psp = &adev->psp;
 394         int ret;
 395         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 396         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 397         struct psp_runtime_scpm_entry scpm_entry;
 398
 399         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 400         if (!psp->cmd) {
 401                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 402                 ret = -ENOMEM;
 403         }
 404
 405         adev->psp.xgmi_context.supports_extended_data =
 406                 !adev->gmc.xgmi.connected_to_cpu &&
 407                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 408
 409         memset(&scpm_entry, 0, sizeof(scpm_entry));
 410         if ((psp_get_runtime_db_entry(adev,
 411                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 412                                 &scpm_entry)) &&
 413             (SCPM_DISABLE != scpm_entry.scpm_status)) {
 414                 adev->scpm_enabled = true;
 415                 adev->scpm_status = scpm_entry.scpm_status;
 416         } else {
 417                 adev->scpm_enabled = false;
 418                 adev->scpm_status = SCPM_DISABLE;
 419         }
 420
 421         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 422
 423         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 424         if (psp_get_runtime_db_entry(adev,
 425                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 426                                 &boot_cfg_entry)) {
 427                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 428                 if ((psp->boot_cfg_bitmask) &
 429                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 430                         /* If psp runtime database exists, then
 431                          * only enable two stage memory training
 432                          * when TWO_STAGE_DRAM_TRAINING bit is set
 433                          * in runtime database */
 434                         mem_training_ctx->enable_mem_training = true;
 435                 }
 436
 437         } else {
 438                 /* If psp runtime database doesn't exist or
 439                  * is invalid, force enable two stage memory
 440                  * training */
 441                 mem_training_ctx->enable_mem_training = true;
 442         }
 443
 444         if (mem_training_ctx->enable_mem_training) {
 445                 ret = psp_memory_training_init(psp);
 446                 if (ret) {
 447                         DRM_ERROR("Failed to initialize memory training!\n");
 448                         return ret;
 449                 }
 450
 451                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 452                 if (ret) {
 453                         DRM_ERROR("Failed to process memory training!\n");
 454                         return ret;
 455                 }
 456         }
 457
 458         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 459             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 460                 ret= psp_sysfs_init(adev);
 461                 if (ret) {
 462                         return ret;
 463                 }
 464         }
 465
 466         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 467                                       amdgpu_sriov_vf(adev) ?
 468                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 469                                       &psp->fw_pri_bo,
 470                                       &psp->fw_pri_mc_addr,
 471                                       &psp->fw_pri_buf);
 472         if (ret)
 473                 return ret;
 474
 475         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 476                                       AMDGPU_GEM_DOMAIN_VRAM,
 477                                       &psp->fence_buf_bo,
 478                                       &psp->fence_buf_mc_addr,
 479                                       &psp->fence_buf);
 480         if (ret)
 481                 goto failed1;
 482
 483         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 484                                       AMDGPU_GEM_DOMAIN_VRAM,
 485                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 486                                       (void **)&psp->cmd_buf_mem);
 487         if (ret)
 488                 goto failed2;
 489
 490         return 0;
 491
 492 failed2:
 493         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 494                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 495 failed1:
 496         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 497                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 498         return ret;
 499 }
 500
 501 static int psp_sw_fini(void *handle)
 502 {
 503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 504         struct psp_context *psp = &adev->psp;
 505         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 506
 507         psp_memory_training_fini(psp);
 508
 509         amdgpu_ucode_release(&psp->sos_fw);
 510         amdgpu_ucode_release(&psp->asd_fw);
 511         amdgpu_ucode_release(&psp->ta_fw);
 512         amdgpu_ucode_release(&psp->cap_fw);
 513         amdgpu_ucode_release(&psp->toc_fw);
 514
 515         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 516             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 517                 psp_sysfs_fini(adev);
 518
 519         kfree(cmd);
 520         cmd = NULL;
 521
 522         if (psp->km_ring.ring_mem)
 523                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 524                                       &psp->km_ring.ring_mem_mc_addr,
 525                                       (void **)&psp->km_ring.ring_mem);
 526
 527         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 528                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 529         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 530                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 531         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 532                               (void **)&psp->cmd_buf_mem);
 533
 534         return 0;
 535 }
 536
 537 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 538                  uint32_t reg_val, uint32_t mask, bool check_changed)
 539 {
 540         uint32_t val;
 541         int i;
 542         struct amdgpu_device *adev = psp->adev;
 543
 544         if (psp->adev->no_hw_access)
 545                 return 0;
 546
 547         for (i = 0; i < adev->usec_timeout; i++) {
 548                 val = RREG32(reg_index);
 549                 if (check_changed) {
 550                         if (val != reg_val)
 551                                 return 0;
 552                 } else {
 553                         if ((val & mask) == reg_val)
 554                                 return 0;
 555                 }
 556                 udelay(1);
 557         }
 558
 559         return -ETIME;
 560 }
 561
 562 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 563 {
 564         switch (cmd_id) {
 565         case GFX_CMD_ID_LOAD_TA:
 566                 return "LOAD_TA";
 567         case GFX_CMD_ID_UNLOAD_TA:
 568                 return "UNLOAD_TA";
 569         case GFX_CMD_ID_INVOKE_CMD:
 570                 return "INVOKE_CMD";
 571         case GFX_CMD_ID_LOAD_ASD:
 572                 return "LOAD_ASD";
 573         case GFX_CMD_ID_SETUP_TMR:
 574                 return "SETUP_TMR";
 575         case GFX_CMD_ID_LOAD_IP_FW:
 576                 return "LOAD_IP_FW";
 577         case GFX_CMD_ID_DESTROY_TMR:
 578                 return "DESTROY_TMR";
 579         case GFX_CMD_ID_SAVE_RESTORE:
 580                 return "SAVE_RESTORE_IP_FW";
 581         case GFX_CMD_ID_SETUP_VMR:
 582                 return "SETUP_VMR";
 583         case GFX_CMD_ID_DESTROY_VMR:
 584                 return "DESTROY_VMR";
 585         case GFX_CMD_ID_PROG_REG:
 586                 return "PROG_REG";
 587         case GFX_CMD_ID_GET_FW_ATTESTATION:
 588                 return "GET_FW_ATTESTATION";
 589         case GFX_CMD_ID_LOAD_TOC:
 590                 return "ID_LOAD_TOC";
 591         case GFX_CMD_ID_AUTOLOAD_RLC:
 592                 return "AUTOLOAD_RLC";
 593         case GFX_CMD_ID_BOOT_CFG:
 594                 return "BOOT_CFG";
 595         default:
 596                 return "UNKNOWN CMD";
 597         }
 598 }
 599
 600 static int
 601 psp_cmd_submit_buf(struct psp_context *psp,
 602                    struct amdgpu_firmware_info *ucode,
 603                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 604 {
 605         int ret;
 606         int index;
 607         int timeout = 20000;
 608         bool ras_intr = false;
 609         bool skip_unsupport = false;
 610
 611         if (psp->adev->no_hw_access)
 612                 return 0;
 613
 614         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 615
 616         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 617
 618         index = atomic_inc_return(&psp->fence_value);
 619         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 620         if (ret) {
 621                 atomic_dec(&psp->fence_value);
 622                 goto exit;
 623         }
 624
 625         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 626         while (*((unsigned int *)psp->fence_buf) != index) {
 627                 if (--timeout == 0)
 628                         break;
 629                 /*
 630                  * Shouldn't wait for timeout when err_event_athub occurs,
 631                  * because gpu reset thread triggered and lock resource should
 632                  * be released for psp resume sequence.
 633                  */
 634                 ras_intr = amdgpu_ras_intr_triggered();
 635                 if (ras_intr)
 636                         break;
 637                 usleep_range(10, 100);
 638                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 639         }
 640
 641         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 642         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 643                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 644
 645         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 646
 647         /* In some cases, psp response status is not 0 even there is no
 648          * problem while the command is submitted. Some version of PSP FW
 649          * doesn't write 0 to that field.
 650          * So here we would like to only print a warning instead of an error
 651          * during psp initialization to avoid breaking hw_init and it doesn't
 652          * return -EINVAL.
 653          */
 654         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 655                 if (ucode)
 656                         DRM_WARN("failed to load ucode %s(0x%X) ",
 657                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 658                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 659                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 660                          psp->cmd_buf_mem->resp.status);
 661                 /* If any firmware (including CAP) load fails under SRIOV, it should
 662                  * return failure to stop the VF from initializing.
 663                  * Also return failure in case of timeout
 664                  */
 665                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 666                         ret = -EINVAL;
 667                         goto exit;
 668                 }
 669         }
 670
 671         if (ucode) {
 672                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 673                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 674         }
 675
 676 exit:
 677         return ret;
 678 }
 679
 680 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 681 {
 682         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 683
 684         mutex_lock(&psp->mutex);
 685
 686         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 687
 688         return cmd;
 689 }
 690
 691 static void release_psp_cmd_buf(struct psp_context *psp)
 692 {
 693         mutex_unlock(&psp->mutex);
 694 }
 695
 696 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 697                                  struct psp_gfx_cmd_resp *cmd,
 698                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 699 {
 700         struct amdgpu_device *adev = psp->adev;
 701         uint32_t size = amdgpu_bo_size(tmr_bo);
 702         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 703
 704         if (amdgpu_sriov_vf(psp->adev))
 705                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 706         else
 707                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 708         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 709         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 710         cmd->cmd.cmd_setup_tmr.buf_size = size;
 711         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 712         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 713         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 714 }
 715
 716 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 717                                       uint64_t pri_buf_mc, uint32_t size)
 718 {
 719         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 720         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 721         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 722         cmd->cmd.cmd_load_toc.toc_size = size;
 723 }
 724
 725 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 726 static int psp_load_toc(struct psp_context *psp,
 727                         uint32_t *tmr_size)
 728 {
 729         int ret;
 730         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 731
 732         /* Copy toc to psp firmware private buffer */
 733         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 734
 735         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 736
 737         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 738                                  psp->fence_buf_mc_addr);
 739         if (!ret)
 740                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 741
 742         release_psp_cmd_buf(psp);
 743
 744         return ret;
 745 }
 746
 747 /* Set up Trusted Memory Region */
 748 static int psp_tmr_init(struct psp_context *psp)
 749 {
 750         int ret = 0;
 751         int tmr_size;
 752         void *tmr_buf;
 753         void **pptr;
 754
 755         /*
 756          * According to HW engineer, they prefer the TMR address be "naturally
 757          * aligned" , e.g. the start address be an integer divide of TMR size.
 758          *
 759          * Note: this memory need be reserved till the driver
 760          * uninitializes.
 761          */
 762         tmr_size = PSP_TMR_SIZE(psp->adev);
 763
 764         /* For ASICs support RLC autoload, psp will parse the toc
 765          * and calculate the total size of TMR needed */
 766         if (!amdgpu_sriov_vf(psp->adev) &&
 767             psp->toc.start_addr &&
 768             psp->toc.size_bytes &&
 769             psp->fw_pri_buf) {
 770                 ret = psp_load_toc(psp, &tmr_size);
 771                 if (ret) {
 772                         DRM_ERROR("Failed to load toc\n");
 773                         return ret;
 774                 }
 775         }
 776
 777         if (!psp->tmr_bo) {
 778                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 779                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 780                                               PSP_TMR_ALIGNMENT,
 781                                               AMDGPU_HAS_VRAM(psp->adev) ?
 782                                               AMDGPU_GEM_DOMAIN_VRAM :
 783                                               AMDGPU_GEM_DOMAIN_GTT,
 784                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 785                                               pptr);
 786         }
 787
 788         return ret;
 789 }
 790
 791 static bool psp_skip_tmr(struct psp_context *psp)
 792 {
 793         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 794         case IP_VERSION(11, 0, 9):
 795         case IP_VERSION(11, 0, 7):
 796         case IP_VERSION(13, 0, 2):
 797         case IP_VERSION(13, 0, 10):
 798                 return true;
 799         default:
 800                 return false;
 801         }
 802 }
 803
 804 static int psp_tmr_load(struct psp_context *psp)
 805 {
 806         int ret;
 807         struct psp_gfx_cmd_resp *cmd;
 808
 809         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 810          * Already set up by host driver.
 811          */
 812         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 813                 return 0;
 814
 815         cmd = acquire_psp_cmd_buf(psp);
 816
 817         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 818         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 819                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 820
 821         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 822                                  psp->fence_buf_mc_addr);
 823
 824         release_psp_cmd_buf(psp);
 825
 826         return ret;
 827 }
 828
 829 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 830                                         struct psp_gfx_cmd_resp *cmd)
 831 {
 832         if (amdgpu_sriov_vf(psp->adev))
 833                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 834         else
 835                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 836 }
 837
 838 static int psp_tmr_unload(struct psp_context *psp)
 839 {
 840         int ret;
 841         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 842
 843         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 844         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 845
 846         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 847                                  psp->fence_buf_mc_addr);
 848
 849         release_psp_cmd_buf(psp);
 850
 851         return ret;
 852 }
 853
 854 static int psp_tmr_terminate(struct psp_context *psp)
 855 {
 856         return psp_tmr_unload(psp);
 857 }
 858
 859 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 860                                         uint64_t *output_ptr)
 861 {
 862         int ret;
 863         struct psp_gfx_cmd_resp *cmd;
 864
 865         if (!output_ptr)
 866                 return -EINVAL;
 867
 868         if (amdgpu_sriov_vf(psp->adev))
 869                 return 0;
 870
 871         cmd = acquire_psp_cmd_buf(psp);
 872
 873         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 874
 875         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 876                                  psp->fence_buf_mc_addr);
 877
 878         if (!ret) {
 879                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 880                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 881         }
 882
 883         release_psp_cmd_buf(psp);
 884
 885         return ret;
 886 }
 887
 888 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 889 {
 890         struct psp_context *psp = &adev->psp;
 891         struct psp_gfx_cmd_resp *cmd;
 892         int ret;
 893
 894         if (amdgpu_sriov_vf(adev))
 895                 return 0;
 896
 897         cmd = acquire_psp_cmd_buf(psp);
 898
 899         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 900         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 901
 902         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 903         if (!ret) {
 904                 *boot_cfg =
 905                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 906         }
 907
 908         release_psp_cmd_buf(psp);
 909
 910         return ret;
 911 }
 912
 913 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 914 {
 915         int ret;
 916         struct psp_context *psp = &adev->psp;
 917         struct psp_gfx_cmd_resp *cmd;
 918
 919         if (amdgpu_sriov_vf(adev))
 920                 return 0;
 921
 922         cmd = acquire_psp_cmd_buf(psp);
 923
 924         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 925         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 926         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 927         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 928
 929         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 930
 931         release_psp_cmd_buf(psp);
 932
 933         return ret;
 934 }
 935
 936 static int psp_rl_load(struct amdgpu_device *adev)
 937 {
 938         int ret;
 939         struct psp_context *psp = &adev->psp;
 940         struct psp_gfx_cmd_resp *cmd;
 941
 942         if (!is_psp_fw_valid(psp->rl))
 943                 return 0;
 944
 945         cmd = acquire_psp_cmd_buf(psp);
 946
 947         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 948         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 949
 950         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 951         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 952         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 953         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 954         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 955
 956         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 957
 958         release_psp_cmd_buf(psp);
 959
 960         return ret;
 961 }
 962
 963 static int psp_asd_initialize(struct psp_context *psp)
 964 {
 965         int ret;
 966
 967         /* If PSP version doesn't match ASD version, asd loading will be failed.
 968          * add workaround to bypass it for sriov now.
 969          * TODO: add version check to make it common
 970          */
 971         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 972                 return 0;
 973
 974         psp->asd_context.mem_context.shared_mc_addr  = 0;
 975         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 976         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 977
 978         ret = psp_ta_load(psp, &psp->asd_context);
 979         if (!ret)
 980                 psp->asd_context.initialized = true;
 981
 982         return ret;
 983 }
 984
 985 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 986                                        uint32_t session_id)
 987 {
 988         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 989         cmd->cmd.cmd_unload_ta.session_id = session_id;
 990 }
 991
 992 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
 993 {
 994         int ret;
 995         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 996
 997         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
 998
 999         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1000
1001         context->resp_status = cmd->resp.status;
1002
1003         release_psp_cmd_buf(psp);
1004
1005         return ret;
1006 }
1007
1008 static int psp_asd_terminate(struct psp_context *psp)
1009 {
1010         int ret;
1011
1012         if (amdgpu_sriov_vf(psp->adev))
1013                 return 0;
1014
1015         if (!psp->asd_context.initialized)
1016                 return 0;
1017
1018         ret = psp_ta_unload(psp, &psp->asd_context);
1019         if (!ret)
1020                 psp->asd_context.initialized = false;
1021
1022         return ret;
1023 }
1024
1025 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1026                 uint32_t id, uint32_t value)
1027 {
1028         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1029         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1030         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1031 }
1032
1033 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1034                 uint32_t value)
1035 {
1036         struct psp_gfx_cmd_resp *cmd;
1037         int ret = 0;
1038
1039         if (reg >= PSP_REG_LAST)
1040                 return -EINVAL;
1041
1042         cmd = acquire_psp_cmd_buf(psp);
1043
1044         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1045         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1046         if (ret)
1047                 DRM_ERROR("PSP failed to program reg id %d", reg);
1048
1049         release_psp_cmd_buf(psp);
1050
1051         return ret;
1052 }
1053
1054 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1055                                      uint64_t ta_bin_mc,
1056                                      struct ta_context *context)
1057 {
1058         cmd->cmd_id                             = context->ta_load_type;
1059         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1060         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1061         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1062
1063         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1064                 lower_32_bits(context->mem_context.shared_mc_addr);
1065         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1066                 upper_32_bits(context->mem_context.shared_mc_addr);
1067         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1068 }
1069
1070 int psp_ta_init_shared_buf(struct psp_context *psp,
1071                                   struct ta_mem_context *mem_ctx)
1072 {
1073         /*
1074         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1075         * physical) for ta to host memory
1076         */
1077         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1078                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1079                                       AMDGPU_GEM_DOMAIN_GTT,
1080                                       &mem_ctx->shared_bo,
1081                                       &mem_ctx->shared_mc_addr,
1082                                       &mem_ctx->shared_buf);
1083 }
1084
1085 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1086                                        uint32_t ta_cmd_id,
1087                                        uint32_t session_id)
1088 {
1089         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1090         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1091         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1092 }
1093
1094 int psp_ta_invoke(struct psp_context *psp,
1095                   uint32_t ta_cmd_id,
1096                   struct ta_context *context)
1097 {
1098         int ret;
1099         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1100
1101         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1102
1103         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1104                                  psp->fence_buf_mc_addr);
1105
1106         context->resp_status = cmd->resp.status;
1107
1108         release_psp_cmd_buf(psp);
1109
1110         return ret;
1111 }
1112
1113 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1114 {
1115         int ret;
1116         struct psp_gfx_cmd_resp *cmd;
1117
1118         cmd = acquire_psp_cmd_buf(psp);
1119
1120         psp_copy_fw(psp, context->bin_desc.start_addr,
1121                     context->bin_desc.size_bytes);
1122
1123         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1124
1125         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1126                                  psp->fence_buf_mc_addr);
1127
1128         context->resp_status = cmd->resp.status;
1129
1130         if (!ret) {
1131                 context->session_id = cmd->resp.session_id;
1132         }
1133
1134         release_psp_cmd_buf(psp);
1135
1136         return ret;
1137 }
1138
1139 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1140 {
1141         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1142 }
1143
1144 int psp_xgmi_terminate(struct psp_context *psp)
1145 {
1146         int ret;
1147         struct amdgpu_device *adev = psp->adev;
1148
1149         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1150         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1151             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1152              adev->gmc.xgmi.connected_to_cpu))
1153                 return 0;
1154
1155         if (!psp->xgmi_context.context.initialized)
1156                 return 0;
1157
1158         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1159
1160         psp->xgmi_context.context.initialized = false;
1161
1162         return ret;
1163 }
1164
1165 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1166 {
1167         struct ta_xgmi_shared_memory *xgmi_cmd;
1168         int ret;
1169
1170         if (!psp->ta_fw ||
1171             !psp->xgmi_context.context.bin_desc.size_bytes ||
1172             !psp->xgmi_context.context.bin_desc.start_addr)
1173                 return -ENOENT;
1174
1175         if (!load_ta)
1176                 goto invoke;
1177
1178         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1179         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1180
1181         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1182                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1183                 if (ret)
1184                         return ret;
1185         }
1186
1187         /* Load XGMI TA */
1188         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1189         if (!ret)
1190                 psp->xgmi_context.context.initialized = true;
1191         else
1192                 return ret;
1193
1194 invoke:
1195         /* Initialize XGMI session */
1196         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1197         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1198         xgmi_cmd->flag_extend_link_record = set_extended_data;
1199         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1200
1201         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1202
1203         return ret;
1204 }
1205
1206 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1207 {
1208         struct ta_xgmi_shared_memory *xgmi_cmd;
1209         int ret;
1210
1211         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1212         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1213
1214         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1215
1216         /* Invoke xgmi ta to get hive id */
1217         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1218         if (ret)
1219                 return ret;
1220
1221         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1222
1223         return 0;
1224 }
1225
1226 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1227 {
1228         struct ta_xgmi_shared_memory *xgmi_cmd;
1229         int ret;
1230
1231         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1232         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1233
1234         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1235
1236         /* Invoke xgmi ta to get the node id */
1237         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1238         if (ret)
1239                 return ret;
1240
1241         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1242
1243         return 0;
1244 }
1245
1246 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1247 {
1248         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1249                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1250 }
1251
1252 /*
1253  * Chips that support extended topology information require the driver to
1254  * reflect topology information in the opposite direction.  This is
1255  * because the TA has already exceeded its link record limit and if the
1256  * TA holds bi-directional information, the driver would have to do
1257  * multiple fetches instead of just two.
1258  */
1259 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1260                                         struct psp_xgmi_node_info node_info)
1261 {
1262         struct amdgpu_device *mirror_adev;
1263         struct amdgpu_hive_info *hive;
1264         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1265         uint64_t dst_node_id = node_info.node_id;
1266         uint8_t dst_num_hops = node_info.num_hops;
1267         uint8_t dst_num_links = node_info.num_links;
1268
1269         hive = amdgpu_get_xgmi_hive(psp->adev);
1270         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1271                 struct psp_xgmi_topology_info *mirror_top_info;
1272                 int j;
1273
1274                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1275                         continue;
1276
1277                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1278                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1279                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1280                                 continue;
1281
1282                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1283                         /*
1284                          * prevent 0 num_links value re-reflection since reflection
1285                          * criteria is based on num_hops (direct or indirect).
1286                          *
1287                          */
1288                         if (dst_num_links)
1289                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1290
1291                         break;
1292                 }
1293
1294                 break;
1295         }
1296
1297         amdgpu_put_xgmi_hive(hive);
1298 }
1299
1300 int psp_xgmi_get_topology_info(struct psp_context *psp,
1301                                int number_devices,
1302                                struct psp_xgmi_topology_info *topology,
1303                                bool get_extended_data)
1304 {
1305         struct ta_xgmi_shared_memory *xgmi_cmd;
1306         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1307         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1308         int i;
1309         int ret;
1310
1311         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1312                 return -EINVAL;
1313
1314         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1315         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1316         xgmi_cmd->flag_extend_link_record = get_extended_data;
1317
1318         /* Fill in the shared memory with topology information as input */
1319         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1320         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1321         topology_info_input->num_nodes = number_devices;
1322
1323         for (i = 0; i < topology_info_input->num_nodes; i++) {
1324                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1325                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1326                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1327                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1328         }
1329
1330         /* Invoke xgmi ta to get the topology information */
1331         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1332         if (ret)
1333                 return ret;
1334
1335         /* Read the output topology information from the shared memory */
1336         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1337         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1338         for (i = 0; i < topology->num_nodes; i++) {
1339                 /* extended data will either be 0 or equal to non-extended data */
1340                 if (topology_info_output->nodes[i].num_hops)
1341                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1342
1343                 /* non-extended data gets everything here so no need to update */
1344                 if (!get_extended_data) {
1345                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1346                         topology->nodes[i].is_sharing_enabled =
1347                                         topology_info_output->nodes[i].is_sharing_enabled;
1348                         topology->nodes[i].sdma_engine =
1349                                         topology_info_output->nodes[i].sdma_engine;
1350                 }
1351
1352         }
1353
1354         /* Invoke xgmi ta again to get the link information */
1355         if (psp_xgmi_peer_link_info_supported(psp)) {
1356                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1357
1358                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1359
1360                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1361
1362                 if (ret)
1363                         return ret;
1364
1365                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1366                 for (i = 0; i < topology->num_nodes; i++) {
1367                         /* accumulate num_links on extended data */
1368                         topology->nodes[i].num_links = get_extended_data ?
1369                                         topology->nodes[i].num_links +
1370                                                         link_info_output->nodes[i].num_links :
1371                                         link_info_output->nodes[i].num_links;
1372
1373                         /* reflect the topology information for bi-directionality */
1374                         if (psp->xgmi_context.supports_extended_data &&
1375                                         get_extended_data && topology->nodes[i].num_hops)
1376                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1377                 }
1378         }
1379
1380         return 0;
1381 }
1382
1383 int psp_xgmi_set_topology_info(struct psp_context *psp,
1384                                int number_devices,
1385                                struct psp_xgmi_topology_info *topology)
1386 {
1387         struct ta_xgmi_shared_memory *xgmi_cmd;
1388         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1389         int i;
1390
1391         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1392                 return -EINVAL;
1393
1394         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1395         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1396
1397         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1398         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1399         topology_info_input->num_nodes = number_devices;
1400
1401         for (i = 0; i < topology_info_input->num_nodes; i++) {
1402                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1403                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1404                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1405                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1406         }
1407
1408         /* Invoke xgmi ta to set topology information */
1409         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1410 }
1411
1412 // ras begin
1413 static void psp_ras_ta_check_status(struct psp_context *psp)
1414 {
1415         struct ta_ras_shared_memory *ras_cmd =
1416                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1417
1418         switch (ras_cmd->ras_status) {
1419         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1420                 dev_warn(psp->adev->dev,
1421                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1422                 break;
1423         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1424                 dev_warn(psp->adev->dev,
1425                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1426                 break;
1427         case TA_RAS_STATUS__SUCCESS:
1428                 break;
1429         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1430                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1431                         dev_warn(psp->adev->dev,
1432                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1433                 break;
1434         default:
1435                 dev_warn(psp->adev->dev,
1436                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1437                 break;
1438         }
1439 }
1440
1441 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1442 {
1443         struct ta_ras_shared_memory *ras_cmd;
1444         int ret;
1445
1446         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1447
1448         /*
1449          * TODO: bypass the loading in sriov for now
1450          */
1451         if (amdgpu_sriov_vf(psp->adev))
1452                 return 0;
1453
1454         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1455
1456         if (amdgpu_ras_intr_triggered())
1457                 return ret;
1458
1459         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1460         {
1461                 DRM_WARN("RAS: Unsupported Interface");
1462                 return -EINVAL;
1463         }
1464
1465         if (!ret) {
1466                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1467                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1468
1469                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1470                 }
1471                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1472                         dev_warn(psp->adev->dev,
1473                                  "RAS internal register access blocked\n");
1474
1475                 psp_ras_ta_check_status(psp);
1476         }
1477
1478         return ret;
1479 }
1480
1481 int psp_ras_enable_features(struct psp_context *psp,
1482                 union ta_ras_cmd_input *info, bool enable)
1483 {
1484         struct ta_ras_shared_memory *ras_cmd;
1485         int ret;
1486
1487         if (!psp->ras_context.context.initialized)
1488                 return -EINVAL;
1489
1490         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1491         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1492
1493         if (enable)
1494                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1495         else
1496                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1497
1498         ras_cmd->ras_in_message = *info;
1499
1500         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1501         if (ret)
1502                 return -EINVAL;
1503
1504         return 0;
1505 }
1506
1507 int psp_ras_terminate(struct psp_context *psp)
1508 {
1509         int ret;
1510
1511         /*
1512          * TODO: bypass the terminate in sriov for now
1513          */
1514         if (amdgpu_sriov_vf(psp->adev))
1515                 return 0;
1516
1517         if (!psp->ras_context.context.initialized)
1518                 return 0;
1519
1520         ret = psp_ta_unload(psp, &psp->ras_context.context);
1521
1522         psp->ras_context.context.initialized = false;
1523
1524         return ret;
1525 }
1526
1527 int psp_ras_initialize(struct psp_context *psp)
1528 {
1529         int ret;
1530         uint32_t boot_cfg = 0xFF;
1531         struct amdgpu_device *adev = psp->adev;
1532         struct ta_ras_shared_memory *ras_cmd;
1533
1534         /*
1535          * TODO: bypass the initialize in sriov for now
1536          */
1537         if (amdgpu_sriov_vf(adev))
1538                 return 0;
1539
1540         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1541             !adev->psp.ras_context.context.bin_desc.start_addr) {
1542                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1543                 return 0;
1544         }
1545
1546         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1547                 /* query GECC enablement status from boot config
1548                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1549                  */
1550                 ret = psp_boot_config_get(adev, &boot_cfg);
1551                 if (ret)
1552                         dev_warn(adev->dev, "PSP get boot config failed\n");
1553
1554                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1555                         if (!boot_cfg) {
1556                                 dev_info(adev->dev, "GECC is disabled\n");
1557                         } else {
1558                                 /* disable GECC in next boot cycle if ras is
1559                                  * disabled by module parameter amdgpu_ras_enable
1560                                  * and/or amdgpu_ras_mask, or boot_config_get call
1561                                  * is failed
1562                                  */
1563                                 ret = psp_boot_config_set(adev, 0);
1564                                 if (ret)
1565                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1566                                 else
1567                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1568                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1569                         }
1570                 } else {
1571                         if (1 == boot_cfg) {
1572                                 dev_info(adev->dev, "GECC is enabled\n");
1573                         } else {
1574                                 /* enable GECC in next boot cycle if it is disabled
1575                                  * in boot config, or force enable GECC if failed to
1576                                  * get boot configuration
1577                                  */
1578                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1579                                 if (ret)
1580                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1581                                 else
1582                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1583                         }
1584                 }
1585         }
1586
1587         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1588         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1589
1590         if (!psp->ras_context.context.mem_context.shared_buf) {
1591                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1592                 if (ret)
1593                         return ret;
1594         }
1595
1596         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1597         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1598
1599         if (amdgpu_ras_is_poison_mode_supported(adev))
1600                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1601         if (!adev->gmc.xgmi.connected_to_cpu)
1602                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1603
1604         ret = psp_ta_load(psp, &psp->ras_context.context);
1605
1606         if (!ret && !ras_cmd->ras_status)
1607                 psp->ras_context.context.initialized = true;
1608         else {
1609                 if (ras_cmd->ras_status)
1610                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1611
1612                 /* fail to load RAS TA */
1613                 psp->ras_context.context.initialized = false;
1614         }
1615
1616         return ret;
1617 }
1618
1619 int psp_ras_trigger_error(struct psp_context *psp,
1620                           struct ta_ras_trigger_error_input *info)
1621 {
1622         struct ta_ras_shared_memory *ras_cmd;
1623         int ret;
1624
1625         if (!psp->ras_context.context.initialized)
1626                 return -EINVAL;
1627
1628         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1629         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1630
1631         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1632         ras_cmd->ras_in_message.trigger_error = *info;
1633
1634         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1635         if (ret)
1636                 return -EINVAL;
1637
1638         /* If err_event_athub occurs error inject was successful, however
1639            return status from TA is no long reliable */
1640         if (amdgpu_ras_intr_triggered())
1641                 return 0;
1642
1643         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1644                 return -EACCES;
1645         else if (ras_cmd->ras_status)
1646                 return -EINVAL;
1647
1648         return 0;
1649 }
1650 // ras end
1651
1652 // HDCP start
1653 static int psp_hdcp_initialize(struct psp_context *psp)
1654 {
1655         int ret;
1656
1657         /*
1658          * TODO: bypass the initialize in sriov for now
1659          */
1660         if (amdgpu_sriov_vf(psp->adev))
1661                 return 0;
1662
1663         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1664             !psp->hdcp_context.context.bin_desc.start_addr) {
1665                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1666                 return 0;
1667         }
1668
1669         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1670         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1671
1672         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1673                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1674                 if (ret)
1675                         return ret;
1676         }
1677
1678         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1679         if (!ret) {
1680                 psp->hdcp_context.context.initialized = true;
1681                 mutex_init(&psp->hdcp_context.mutex);
1682         }
1683
1684         return ret;
1685 }
1686
1687 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1688 {
1689         /*
1690          * TODO: bypass the loading in sriov for now
1691          */
1692         if (amdgpu_sriov_vf(psp->adev))
1693                 return 0;
1694
1695         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1696 }
1697
1698 static int psp_hdcp_terminate(struct psp_context *psp)
1699 {
1700         int ret;
1701
1702         /*
1703          * TODO: bypass the terminate in sriov for now
1704          */
1705         if (amdgpu_sriov_vf(psp->adev))
1706                 return 0;
1707
1708         if (!psp->hdcp_context.context.initialized)
1709                 return 0;
1710
1711         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1712
1713         psp->hdcp_context.context.initialized = false;
1714
1715         return ret;
1716 }
1717 // HDCP end
1718
1719 // DTM start
1720 static int psp_dtm_initialize(struct psp_context *psp)
1721 {
1722         int ret;
1723
1724         /*
1725          * TODO: bypass the initialize in sriov for now
1726          */
1727         if (amdgpu_sriov_vf(psp->adev))
1728                 return 0;
1729
1730         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1731             !psp->dtm_context.context.bin_desc.start_addr) {
1732                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1733                 return 0;
1734         }
1735
1736         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1737         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1738
1739         if (!psp->dtm_context.context.mem_context.shared_buf) {
1740                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1741                 if (ret)
1742                         return ret;
1743         }
1744
1745         ret = psp_ta_load(psp, &psp->dtm_context.context);
1746         if (!ret) {
1747                 psp->dtm_context.context.initialized = true;
1748                 mutex_init(&psp->dtm_context.mutex);
1749         }
1750
1751         return ret;
1752 }
1753
1754 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1755 {
1756         /*
1757          * TODO: bypass the loading in sriov for now
1758          */
1759         if (amdgpu_sriov_vf(psp->adev))
1760                 return 0;
1761
1762         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1763 }
1764
1765 static int psp_dtm_terminate(struct psp_context *psp)
1766 {
1767         int ret;
1768
1769         /*
1770          * TODO: bypass the terminate in sriov for now
1771          */
1772         if (amdgpu_sriov_vf(psp->adev))
1773                 return 0;
1774
1775         if (!psp->dtm_context.context.initialized)
1776                 return 0;
1777
1778         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1779
1780         psp->dtm_context.context.initialized = false;
1781
1782         return ret;
1783 }
1784 // DTM end
1785
1786 // RAP start
1787 static int psp_rap_initialize(struct psp_context *psp)
1788 {
1789         int ret;
1790         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1791
1792         /*
1793          * TODO: bypass the initialize in sriov for now
1794          */
1795         if (amdgpu_sriov_vf(psp->adev))
1796                 return 0;
1797
1798         if (!psp->rap_context.context.bin_desc.size_bytes ||
1799             !psp->rap_context.context.bin_desc.start_addr) {
1800                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1801                 return 0;
1802         }
1803
1804         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1805         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1806
1807         if (!psp->rap_context.context.mem_context.shared_buf) {
1808                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1809                 if (ret)
1810                         return ret;
1811         }
1812
1813         ret = psp_ta_load(psp, &psp->rap_context.context);
1814         if (!ret) {
1815                 psp->rap_context.context.initialized = true;
1816                 mutex_init(&psp->rap_context.mutex);
1817         } else
1818                 return ret;
1819
1820         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1821         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1822                 psp_rap_terminate(psp);
1823                 /* free rap shared memory */
1824                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1825
1826                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1827                          ret, status);
1828
1829                 return ret;
1830         }
1831
1832         return 0;
1833 }
1834
1835 static int psp_rap_terminate(struct psp_context *psp)
1836 {
1837         int ret;
1838
1839         if (!psp->rap_context.context.initialized)
1840                 return 0;
1841
1842         ret = psp_ta_unload(psp, &psp->rap_context.context);
1843
1844         psp->rap_context.context.initialized = false;
1845
1846         return ret;
1847 }
1848
1849 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1850 {
1851         struct ta_rap_shared_memory *rap_cmd;
1852         int ret = 0;
1853
1854         if (!psp->rap_context.context.initialized)
1855                 return 0;
1856
1857         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1858             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1859                 return -EINVAL;
1860
1861         mutex_lock(&psp->rap_context.mutex);
1862
1863         rap_cmd = (struct ta_rap_shared_memory *)
1864                   psp->rap_context.context.mem_context.shared_buf;
1865         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1866
1867         rap_cmd->cmd_id = ta_cmd_id;
1868         rap_cmd->validation_method_id = METHOD_A;
1869
1870         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1871         if (ret)
1872                 goto out_unlock;
1873
1874         if (status)
1875                 *status = rap_cmd->rap_status;
1876
1877 out_unlock:
1878         mutex_unlock(&psp->rap_context.mutex);
1879
1880         return ret;
1881 }
1882 // RAP end
1883
1884 /* securedisplay start */
1885 static int psp_securedisplay_initialize(struct psp_context *psp)
1886 {
1887         int ret;
1888         struct ta_securedisplay_cmd *securedisplay_cmd;
1889
1890         /*
1891          * TODO: bypass the initialize in sriov for now
1892          */
1893         if (amdgpu_sriov_vf(psp->adev))
1894                 return 0;
1895
1896         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1897             !psp->securedisplay_context.context.bin_desc.start_addr) {
1898                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1899                 return 0;
1900         }
1901
1902         psp->securedisplay_context.context.mem_context.shared_mem_size =
1903                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1904         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1905
1906         if (!psp->securedisplay_context.context.initialized) {
1907                 ret = psp_ta_init_shared_buf(psp,
1908                                              &psp->securedisplay_context.context.mem_context);
1909                 if (ret)
1910                         return ret;
1911         }
1912
1913         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1914         if (!ret) {
1915                 psp->securedisplay_context.context.initialized = true;
1916                 mutex_init(&psp->securedisplay_context.mutex);
1917         } else
1918                 return ret;
1919
1920         mutex_lock(&psp->securedisplay_context.mutex);
1921
1922         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1923                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1924
1925         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1926
1927         mutex_unlock(&psp->securedisplay_context.mutex);
1928
1929         if (ret) {
1930                 psp_securedisplay_terminate(psp);
1931                 /* free securedisplay shared memory */
1932                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1933                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1934                 return -EINVAL;
1935         }
1936
1937         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1938                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1939                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1940                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1941         }
1942
1943         return 0;
1944 }
1945
1946 static int psp_securedisplay_terminate(struct psp_context *psp)
1947 {
1948         int ret;
1949
1950         /*
1951          * TODO:bypass the terminate in sriov for now
1952          */
1953         if (amdgpu_sriov_vf(psp->adev))
1954                 return 0;
1955
1956         if (!psp->securedisplay_context.context.initialized)
1957                 return 0;
1958
1959         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1960
1961         psp->securedisplay_context.context.initialized = false;
1962
1963         return ret;
1964 }
1965
1966 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1967 {
1968         int ret;
1969
1970         if (!psp->securedisplay_context.context.initialized)
1971                 return -EINVAL;
1972
1973         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1974             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1975                 return -EINVAL;
1976
1977         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1978
1979         return ret;
1980 }
1981 /* SECUREDISPLAY end */
1982
1983 static int psp_hw_start(struct psp_context *psp)
1984 {
1985         struct amdgpu_device *adev = psp->adev;
1986         int ret;
1987
1988         if (!amdgpu_sriov_vf(adev)) {
1989                 if ((is_psp_fw_valid(psp->kdb)) &&
1990                     (psp->funcs->bootloader_load_kdb != NULL)) {
1991                         ret = psp_bootloader_load_kdb(psp);
1992                         if (ret) {
1993                                 DRM_ERROR("PSP load kdb failed!\n");
1994                                 return ret;
1995                         }
1996                 }
1997
1998                 if ((is_psp_fw_valid(psp->spl)) &&
1999                     (psp->funcs->bootloader_load_spl != NULL)) {
2000                         ret = psp_bootloader_load_spl(psp);
2001                         if (ret) {
2002                                 DRM_ERROR("PSP load spl failed!\n");
2003                                 return ret;
2004                         }
2005                 }
2006
2007                 if ((is_psp_fw_valid(psp->sys)) &&
2008                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2009                         ret = psp_bootloader_load_sysdrv(psp);
2010                         if (ret) {
2011                                 DRM_ERROR("PSP load sys drv failed!\n");
2012                                 return ret;
2013                         }
2014                 }
2015
2016                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2017                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2018                         ret = psp_bootloader_load_soc_drv(psp);
2019                         if (ret) {
2020                                 DRM_ERROR("PSP load soc drv failed!\n");
2021                                 return ret;
2022                         }
2023                 }
2024
2025                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2026                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2027                         ret = psp_bootloader_load_intf_drv(psp);
2028                         if (ret) {
2029                                 DRM_ERROR("PSP load intf drv failed!\n");
2030                                 return ret;
2031                         }
2032                 }
2033
2034                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2035                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2036                         ret = psp_bootloader_load_dbg_drv(psp);
2037                         if (ret) {
2038                                 DRM_ERROR("PSP load dbg drv failed!\n");
2039                                 return ret;
2040                         }
2041                 }
2042
2043                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2044                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2045                         ret = psp_bootloader_load_ras_drv(psp);
2046                         if (ret) {
2047                                 DRM_ERROR("PSP load ras_drv failed!\n");
2048                                 return ret;
2049                         }
2050                 }
2051
2052                 if ((is_psp_fw_valid(psp->sos)) &&
2053                     (psp->funcs->bootloader_load_sos != NULL)) {
2054                         ret = psp_bootloader_load_sos(psp);
2055                         if (ret) {
2056                                 DRM_ERROR("PSP load sos failed!\n");
2057                                 return ret;
2058                         }
2059                 }
2060         }
2061
2062         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2063         if (ret) {
2064                 DRM_ERROR("PSP create ring failed!\n");
2065                 return ret;
2066         }
2067
2068         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2069                 goto skip_pin_bo;
2070
2071         ret = psp_tmr_init(psp);
2072         if (ret) {
2073                 DRM_ERROR("PSP tmr init failed!\n");
2074                 return ret;
2075         }
2076
2077 skip_pin_bo:
2078         /*
2079          * For ASICs with DF Cstate management centralized
2080          * to PMFW, TMR setup should be performed after PMFW
2081          * loaded and before other non-psp firmware loaded.
2082          */
2083         if (psp->pmfw_centralized_cstate_management) {
2084                 ret = psp_load_smu_fw(psp);
2085                 if (ret)
2086                         return ret;
2087         }
2088
2089         ret = psp_tmr_load(psp);
2090         if (ret) {
2091                 DRM_ERROR("PSP load tmr failed!\n");
2092                 return ret;
2093         }
2094
2095         return 0;
2096 }
2097
2098 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2099                            enum psp_gfx_fw_type *type)
2100 {
2101         switch (ucode->ucode_id) {
2102         case AMDGPU_UCODE_ID_CAP:
2103                 *type = GFX_FW_TYPE_CAP;
2104                 break;
2105         case AMDGPU_UCODE_ID_SDMA0:
2106                 *type = GFX_FW_TYPE_SDMA0;
2107                 break;
2108         case AMDGPU_UCODE_ID_SDMA1:
2109                 *type = GFX_FW_TYPE_SDMA1;
2110                 break;
2111         case AMDGPU_UCODE_ID_SDMA2:
2112                 *type = GFX_FW_TYPE_SDMA2;
2113                 break;
2114         case AMDGPU_UCODE_ID_SDMA3:
2115                 *type = GFX_FW_TYPE_SDMA3;
2116                 break;
2117         case AMDGPU_UCODE_ID_SDMA4:
2118                 *type = GFX_FW_TYPE_SDMA4;
2119                 break;
2120         case AMDGPU_UCODE_ID_SDMA5:
2121                 *type = GFX_FW_TYPE_SDMA5;
2122                 break;
2123         case AMDGPU_UCODE_ID_SDMA6:
2124                 *type = GFX_FW_TYPE_SDMA6;
2125                 break;
2126         case AMDGPU_UCODE_ID_SDMA7:
2127                 *type = GFX_FW_TYPE_SDMA7;
2128                 break;
2129         case AMDGPU_UCODE_ID_CP_MES:
2130                 *type = GFX_FW_TYPE_CP_MES;
2131                 break;
2132         case AMDGPU_UCODE_ID_CP_MES_DATA:
2133                 *type = GFX_FW_TYPE_MES_STACK;
2134                 break;
2135         case AMDGPU_UCODE_ID_CP_MES1:
2136                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2137                 break;
2138         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2139                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2140                 break;
2141         case AMDGPU_UCODE_ID_CP_CE:
2142                 *type = GFX_FW_TYPE_CP_CE;
2143                 break;
2144         case AMDGPU_UCODE_ID_CP_PFP:
2145                 *type = GFX_FW_TYPE_CP_PFP;
2146                 break;
2147         case AMDGPU_UCODE_ID_CP_ME:
2148                 *type = GFX_FW_TYPE_CP_ME;
2149                 break;
2150         case AMDGPU_UCODE_ID_CP_MEC1:
2151                 *type = GFX_FW_TYPE_CP_MEC;
2152                 break;
2153         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2154                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2155                 break;
2156         case AMDGPU_UCODE_ID_CP_MEC2:
2157                 *type = GFX_FW_TYPE_CP_MEC;
2158                 break;
2159         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2160                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2161                 break;
2162         case AMDGPU_UCODE_ID_RLC_P:
2163                 *type = GFX_FW_TYPE_RLC_P;
2164                 break;
2165         case AMDGPU_UCODE_ID_RLC_V:
2166                 *type = GFX_FW_TYPE_RLC_V;
2167                 break;
2168         case AMDGPU_UCODE_ID_RLC_G:
2169                 *type = GFX_FW_TYPE_RLC_G;
2170                 break;
2171         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2172                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2173                 break;
2174         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2175                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2176                 break;
2177         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2178                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2179                 break;
2180         case AMDGPU_UCODE_ID_RLC_IRAM:
2181                 *type = GFX_FW_TYPE_RLC_IRAM;
2182                 break;
2183         case AMDGPU_UCODE_ID_RLC_DRAM:
2184                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2185                 break;
2186         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2187                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2188                 break;
2189         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2190                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2191                 break;
2192         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2193                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2194                 break;
2195         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2196                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2197                 break;
2198         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2199                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2200                 break;
2201         case AMDGPU_UCODE_ID_SMC:
2202                 *type = GFX_FW_TYPE_SMU;
2203                 break;
2204         case AMDGPU_UCODE_ID_PPTABLE:
2205                 *type = GFX_FW_TYPE_PPTABLE;
2206                 break;
2207         case AMDGPU_UCODE_ID_UVD:
2208                 *type = GFX_FW_TYPE_UVD;
2209                 break;
2210         case AMDGPU_UCODE_ID_UVD1:
2211                 *type = GFX_FW_TYPE_UVD1;
2212                 break;
2213         case AMDGPU_UCODE_ID_VCE:
2214                 *type = GFX_FW_TYPE_VCE;
2215                 break;
2216         case AMDGPU_UCODE_ID_VCN:
2217                 *type = GFX_FW_TYPE_VCN;
2218                 break;
2219         case AMDGPU_UCODE_ID_VCN1:
2220                 *type = GFX_FW_TYPE_VCN1;
2221                 break;
2222         case AMDGPU_UCODE_ID_DMCU_ERAM:
2223                 *type = GFX_FW_TYPE_DMCU_ERAM;
2224                 break;
2225         case AMDGPU_UCODE_ID_DMCU_INTV:
2226                 *type = GFX_FW_TYPE_DMCU_ISR;
2227                 break;
2228         case AMDGPU_UCODE_ID_VCN0_RAM:
2229                 *type = GFX_FW_TYPE_VCN0_RAM;
2230                 break;
2231         case AMDGPU_UCODE_ID_VCN1_RAM:
2232                 *type = GFX_FW_TYPE_VCN1_RAM;
2233                 break;
2234         case AMDGPU_UCODE_ID_DMCUB:
2235                 *type = GFX_FW_TYPE_DMUB;
2236                 break;
2237         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2238                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2239                 break;
2240         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2241                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2242                 break;
2243         case AMDGPU_UCODE_ID_IMU_I:
2244                 *type = GFX_FW_TYPE_IMU_I;
2245                 break;
2246         case AMDGPU_UCODE_ID_IMU_D:
2247                 *type = GFX_FW_TYPE_IMU_D;
2248                 break;
2249         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2250                 *type = GFX_FW_TYPE_RS64_PFP;
2251                 break;
2252         case AMDGPU_UCODE_ID_CP_RS64_ME:
2253                 *type = GFX_FW_TYPE_RS64_ME;
2254                 break;
2255         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2256                 *type = GFX_FW_TYPE_RS64_MEC;
2257                 break;
2258         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2259                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2260                 break;
2261         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2262                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2263                 break;
2264         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2265                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2266                 break;
2267         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2268                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2269                 break;
2270         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2271                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2272                 break;
2273         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2274                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2275                 break;
2276         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2277                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2278                 break;
2279         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2280                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2281                 break;
2282         case AMDGPU_UCODE_ID_MAXIMUM:
2283         default:
2284                 return -EINVAL;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static void psp_print_fw_hdr(struct psp_context *psp,
2291                              struct amdgpu_firmware_info *ucode)
2292 {
2293         struct amdgpu_device *adev = psp->adev;
2294         struct common_firmware_header *hdr;
2295
2296         switch (ucode->ucode_id) {
2297         case AMDGPU_UCODE_ID_SDMA0:
2298         case AMDGPU_UCODE_ID_SDMA1:
2299         case AMDGPU_UCODE_ID_SDMA2:
2300         case AMDGPU_UCODE_ID_SDMA3:
2301         case AMDGPU_UCODE_ID_SDMA4:
2302         case AMDGPU_UCODE_ID_SDMA5:
2303         case AMDGPU_UCODE_ID_SDMA6:
2304         case AMDGPU_UCODE_ID_SDMA7:
2305                 hdr = (struct common_firmware_header *)
2306                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2307                 amdgpu_ucode_print_sdma_hdr(hdr);
2308                 break;
2309         case AMDGPU_UCODE_ID_CP_CE:
2310                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2311                 amdgpu_ucode_print_gfx_hdr(hdr);
2312                 break;
2313         case AMDGPU_UCODE_ID_CP_PFP:
2314                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2315                 amdgpu_ucode_print_gfx_hdr(hdr);
2316                 break;
2317         case AMDGPU_UCODE_ID_CP_ME:
2318                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2319                 amdgpu_ucode_print_gfx_hdr(hdr);
2320                 break;
2321         case AMDGPU_UCODE_ID_CP_MEC1:
2322                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2323                 amdgpu_ucode_print_gfx_hdr(hdr);
2324                 break;
2325         case AMDGPU_UCODE_ID_RLC_G:
2326                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2327                 amdgpu_ucode_print_rlc_hdr(hdr);
2328                 break;
2329         case AMDGPU_UCODE_ID_SMC:
2330                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2331                 amdgpu_ucode_print_smc_hdr(hdr);
2332                 break;
2333         default:
2334                 break;
2335         }
2336 }
2337
2338 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2339                                        struct psp_gfx_cmd_resp *cmd)
2340 {
2341         int ret;
2342         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2343
2344         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2345         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2346         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2347         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2348
2349         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2350         if (ret)
2351                 DRM_ERROR("Unknown firmware type\n");
2352
2353         return ret;
2354 }
2355
2356 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2357                                   struct amdgpu_firmware_info *ucode)
2358 {
2359         int ret = 0;
2360         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2361
2362         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2363         if (!ret) {
2364                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2365                                          psp->fence_buf_mc_addr);
2366         }
2367
2368         release_psp_cmd_buf(psp);
2369
2370         return ret;
2371 }
2372
2373 static int psp_load_smu_fw(struct psp_context *psp)
2374 {
2375         int ret;
2376         struct amdgpu_device *adev = psp->adev;
2377         struct amdgpu_firmware_info *ucode =
2378                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2379         struct amdgpu_ras *ras = psp->ras_context.ras;
2380
2381         /*
2382          * Skip SMU FW reloading in case of using BACO for runpm only,
2383          * as SMU is always alive.
2384          */
2385         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2386                 return 0;
2387
2388         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2389                 return 0;
2390
2391         if ((amdgpu_in_reset(adev) &&
2392              ras && adev->ras_enabled &&
2393              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2394               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2395                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2396                 if (ret) {
2397                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2398                 }
2399         }
2400
2401         ret = psp_execute_non_psp_fw_load(psp, ucode);
2402
2403         if (ret)
2404                 DRM_ERROR("PSP load smu failed!\n");
2405
2406         return ret;
2407 }
2408
2409 static bool fw_load_skip_check(struct psp_context *psp,
2410                                struct amdgpu_firmware_info *ucode)
2411 {
2412         if (!ucode->fw || !ucode->ucode_size)
2413                 return true;
2414
2415         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2416             (psp_smu_reload_quirk(psp) ||
2417              psp->autoload_supported ||
2418              psp->pmfw_centralized_cstate_management))
2419                 return true;
2420
2421         if (amdgpu_sriov_vf(psp->adev) &&
2422             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2423                 return true;
2424
2425         if (psp->autoload_supported &&
2426             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2427              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2428                 /* skip mec JT when autoload is enabled */
2429                 return true;
2430
2431         return false;
2432 }
2433
2434 int psp_load_fw_list(struct psp_context *psp,
2435                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2436 {
2437         int ret = 0, i;
2438         struct amdgpu_firmware_info *ucode;
2439
2440         for (i = 0; i < ucode_count; ++i) {
2441                 ucode = ucode_list[i];
2442                 psp_print_fw_hdr(psp, ucode);
2443                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2444                 if (ret)
2445                         return ret;
2446         }
2447         return ret;
2448 }
2449
2450 static int psp_load_non_psp_fw(struct psp_context *psp)
2451 {
2452         int i, ret;
2453         struct amdgpu_firmware_info *ucode;
2454         struct amdgpu_device *adev = psp->adev;
2455
2456         if (psp->autoload_supported &&
2457             !psp->pmfw_centralized_cstate_management) {
2458                 ret = psp_load_smu_fw(psp);
2459                 if (ret)
2460                         return ret;
2461         }
2462
2463         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2464                 ucode = &adev->firmware.ucode[i];
2465
2466                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2467                     !fw_load_skip_check(psp, ucode)) {
2468                         ret = psp_load_smu_fw(psp);
2469                         if (ret)
2470                                 return ret;
2471                         continue;
2472                 }
2473
2474                 if (fw_load_skip_check(psp, ucode))
2475                         continue;
2476
2477                 if (psp->autoload_supported &&
2478                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2479                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2480                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2481                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2482                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2483                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2484                         /* PSP only receive one SDMA fw for sienna_cichlid,
2485                          * as all four sdma fw are same */
2486                         continue;
2487
2488                 psp_print_fw_hdr(psp, ucode);
2489
2490                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2491                 if (ret)
2492                         return ret;
2493
2494                 /* Start rlc autoload after psp recieved all the gfx firmware */
2495                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2496                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2497                         ret = psp_rlc_autoload_start(psp);
2498                         if (ret) {
2499                                 DRM_ERROR("Failed to start rlc autoload\n");
2500                                 return ret;
2501                         }
2502                 }
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int psp_load_fw(struct amdgpu_device *adev)
2509 {
2510         int ret;
2511         struct psp_context *psp = &adev->psp;
2512
2513         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2514                 /* should not destroy ring, only stop */
2515                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2516         } else {
2517                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2518
2519                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2520                 if (ret) {
2521                         DRM_ERROR("PSP ring init failed!\n");
2522                         goto failed;
2523                 }
2524         }
2525
2526         ret = psp_hw_start(psp);
2527         if (ret)
2528                 goto failed;
2529
2530         ret = psp_load_non_psp_fw(psp);
2531         if (ret)
2532                 goto failed1;
2533
2534         ret = psp_asd_initialize(psp);
2535         if (ret) {
2536                 DRM_ERROR("PSP load asd failed!\n");
2537                 goto failed1;
2538         }
2539
2540         ret = psp_rl_load(adev);
2541         if (ret) {
2542                 DRM_ERROR("PSP load RL failed!\n");
2543                 goto failed1;
2544         }
2545
2546         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2547                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2548                         ret = psp_xgmi_initialize(psp, false, true);
2549                         /* Warning the XGMI seesion initialize failure
2550                         * Instead of stop driver initialization
2551                         */
2552                         if (ret)
2553                                 dev_err(psp->adev->dev,
2554                                         "XGMI: Failed to initialize XGMI session\n");
2555                 }
2556         }
2557
2558         if (psp->ta_fw) {
2559                 ret = psp_ras_initialize(psp);
2560                 if (ret)
2561                         dev_err(psp->adev->dev,
2562                                         "RAS: Failed to initialize RAS\n");
2563
2564                 ret = psp_hdcp_initialize(psp);
2565                 if (ret)
2566                         dev_err(psp->adev->dev,
2567                                 "HDCP: Failed to initialize HDCP\n");
2568
2569                 ret = psp_dtm_initialize(psp);
2570                 if (ret)
2571                         dev_err(psp->adev->dev,
2572                                 "DTM: Failed to initialize DTM\n");
2573
2574                 ret = psp_rap_initialize(psp);
2575                 if (ret)
2576                         dev_err(psp->adev->dev,
2577                                 "RAP: Failed to initialize RAP\n");
2578
2579                 ret = psp_securedisplay_initialize(psp);
2580                 if (ret)
2581                         dev_err(psp->adev->dev,
2582                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2583         }
2584
2585         return 0;
2586
2587 failed1:
2588         psp_free_shared_bufs(psp);
2589 failed:
2590         /*
2591          * all cleanup jobs (xgmi terminate, ras terminate,
2592          * ring destroy, cmd/fence/fw buffers destory,
2593          * psp->cmd destory) are delayed to psp_hw_fini
2594          */
2595         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2596         return ret;
2597 }
2598
2599 static int psp_hw_init(void *handle)
2600 {
2601         int ret;
2602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2603
2604         mutex_lock(&adev->firmware.mutex);
2605         /*
2606          * This sequence is just used on hw_init only once, no need on
2607          * resume.
2608          */
2609         ret = amdgpu_ucode_init_bo(adev);
2610         if (ret)
2611                 goto failed;
2612
2613         ret = psp_load_fw(adev);
2614         if (ret) {
2615                 DRM_ERROR("PSP firmware loading failed\n");
2616                 goto failed;
2617         }
2618
2619         mutex_unlock(&adev->firmware.mutex);
2620         return 0;
2621
2622 failed:
2623         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2624         mutex_unlock(&adev->firmware.mutex);
2625         return -EINVAL;
2626 }
2627
2628 static int psp_hw_fini(void *handle)
2629 {
2630         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2631         struct psp_context *psp = &adev->psp;
2632
2633         if (psp->ta_fw) {
2634                 psp_ras_terminate(psp);
2635                 psp_securedisplay_terminate(psp);
2636                 psp_rap_terminate(psp);
2637                 psp_dtm_terminate(psp);
2638                 psp_hdcp_terminate(psp);
2639
2640                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2641                         psp_xgmi_terminate(psp);
2642         }
2643
2644         psp_asd_terminate(psp);
2645         psp_tmr_terminate(psp);
2646
2647         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2648
2649         psp_free_shared_bufs(psp);
2650
2651         return 0;
2652 }
2653
2654 static int psp_suspend(void *handle)
2655 {
2656         int ret = 0;
2657         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2658         struct psp_context *psp = &adev->psp;
2659
2660         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2661             psp->xgmi_context.context.initialized) {
2662                 ret = psp_xgmi_terminate(psp);
2663                 if (ret) {
2664                         DRM_ERROR("Failed to terminate xgmi ta\n");
2665                         goto out;
2666                 }
2667         }
2668
2669         if (psp->ta_fw) {
2670                 ret = psp_ras_terminate(psp);
2671                 if (ret) {
2672                         DRM_ERROR("Failed to terminate ras ta\n");
2673                         goto out;
2674                 }
2675                 ret = psp_hdcp_terminate(psp);
2676                 if (ret) {
2677                         DRM_ERROR("Failed to terminate hdcp ta\n");
2678                         goto out;
2679                 }
2680                 ret = psp_dtm_terminate(psp);
2681                 if (ret) {
2682                         DRM_ERROR("Failed to terminate dtm ta\n");
2683                         goto out;
2684                 }
2685                 ret = psp_rap_terminate(psp);
2686                 if (ret) {
2687                         DRM_ERROR("Failed to terminate rap ta\n");
2688                         goto out;
2689                 }
2690                 ret = psp_securedisplay_terminate(psp);
2691                 if (ret) {
2692                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2693                         goto out;
2694                 }
2695         }
2696
2697         ret = psp_asd_terminate(psp);
2698         if (ret) {
2699                 DRM_ERROR("Failed to terminate asd\n");
2700                 goto out;
2701         }
2702
2703         ret = psp_tmr_terminate(psp);
2704         if (ret) {
2705                 DRM_ERROR("Failed to terminate tmr\n");
2706                 goto out;
2707         }
2708
2709         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2710         if (ret) {
2711                 DRM_ERROR("PSP ring stop failed\n");
2712         }
2713
2714 out:
2715         return ret;
2716 }
2717
2718 static int psp_resume(void *handle)
2719 {
2720         int ret;
2721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2722         struct psp_context *psp = &adev->psp;
2723
2724         DRM_INFO("PSP is resuming...\n");
2725
2726         if (psp->mem_train_ctx.enable_mem_training) {
2727                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2728                 if (ret) {
2729                         DRM_ERROR("Failed to process memory training!\n");
2730                         return ret;
2731                 }
2732         }
2733
2734         mutex_lock(&adev->firmware.mutex);
2735
2736         ret = psp_hw_start(psp);
2737         if (ret)
2738                 goto failed;
2739
2740         ret = psp_load_non_psp_fw(psp);
2741         if (ret)
2742                 goto failed;
2743
2744         ret = psp_asd_initialize(psp);
2745         if (ret) {
2746                 DRM_ERROR("PSP load asd failed!\n");
2747                 goto failed;
2748         }
2749
2750         ret = psp_rl_load(adev);
2751         if (ret) {
2752                 dev_err(adev->dev, "PSP load RL failed!\n");
2753                 goto failed;
2754         }
2755
2756         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2757                 ret = psp_xgmi_initialize(psp, false, true);
2758                 /* Warning the XGMI seesion initialize failure
2759                  * Instead of stop driver initialization
2760                  */
2761                 if (ret)
2762                         dev_err(psp->adev->dev,
2763                                 "XGMI: Failed to initialize XGMI session\n");
2764         }
2765
2766         if (psp->ta_fw) {
2767                 ret = psp_ras_initialize(psp);
2768                 if (ret)
2769                         dev_err(psp->adev->dev,
2770                                         "RAS: Failed to initialize RAS\n");
2771
2772                 ret = psp_hdcp_initialize(psp);
2773                 if (ret)
2774                         dev_err(psp->adev->dev,
2775                                 "HDCP: Failed to initialize HDCP\n");
2776
2777                 ret = psp_dtm_initialize(psp);
2778                 if (ret)
2779                         dev_err(psp->adev->dev,
2780                                 "DTM: Failed to initialize DTM\n");
2781
2782                 ret = psp_rap_initialize(psp);
2783                 if (ret)
2784                         dev_err(psp->adev->dev,
2785                                 "RAP: Failed to initialize RAP\n");
2786
2787                 ret = psp_securedisplay_initialize(psp);
2788                 if (ret)
2789                         dev_err(psp->adev->dev,
2790                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2791         }
2792
2793         mutex_unlock(&adev->firmware.mutex);
2794
2795         return 0;
2796
2797 failed:
2798         DRM_ERROR("PSP resume failed\n");
2799         mutex_unlock(&adev->firmware.mutex);
2800         return ret;
2801 }
2802
2803 int psp_gpu_reset(struct amdgpu_device *adev)
2804 {
2805         int ret;
2806
2807         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2808                 return 0;
2809
2810         mutex_lock(&adev->psp.mutex);
2811         ret = psp_mode1_reset(&adev->psp);
2812         mutex_unlock(&adev->psp.mutex);
2813
2814         return ret;
2815 }
2816
2817 int psp_rlc_autoload_start(struct psp_context *psp)
2818 {
2819         int ret;
2820         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2821
2822         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2823
2824         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2825                                  psp->fence_buf_mc_addr);
2826
2827         release_psp_cmd_buf(psp);
2828
2829         return ret;
2830 }
2831
2832 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2833                         uint64_t cmd_gpu_addr, int cmd_size)
2834 {
2835         struct amdgpu_firmware_info ucode = {0};
2836
2837         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2838                 AMDGPU_UCODE_ID_VCN0_RAM;
2839         ucode.mc_addr = cmd_gpu_addr;
2840         ucode.ucode_size = cmd_size;
2841
2842         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2843 }
2844
2845 int psp_ring_cmd_submit(struct psp_context *psp,
2846                         uint64_t cmd_buf_mc_addr,
2847                         uint64_t fence_mc_addr,
2848                         int index)
2849 {
2850         unsigned int psp_write_ptr_reg = 0;
2851         struct psp_gfx_rb_frame *write_frame;
2852         struct psp_ring *ring = &psp->km_ring;
2853         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2854         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2855                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2856         struct amdgpu_device *adev = psp->adev;
2857         uint32_t ring_size_dw = ring->ring_size / 4;
2858         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2859
2860         /* KM (GPCOM) prepare write pointer */
2861         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2862
2863         /* Update KM RB frame pointer to new frame */
2864         /* write_frame ptr increments by size of rb_frame in bytes */
2865         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2866         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2867                 write_frame = ring_buffer_start;
2868         else
2869                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2870         /* Check invalid write_frame ptr address */
2871         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2872                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2873                           ring_buffer_start, ring_buffer_end, write_frame);
2874                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2875                 return -EINVAL;
2876         }
2877
2878         /* Initialize KM RB frame */
2879         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2880
2881         /* Update KM RB frame */
2882         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2883         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2884         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2885         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2886         write_frame->fence_value = index;
2887         amdgpu_device_flush_hdp(adev, NULL);
2888
2889         /* Update the write Pointer in DWORDs */
2890         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2891         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2892         return 0;
2893 }
2894
2895 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2896 {
2897         struct amdgpu_device *adev = psp->adev;
2898         char fw_name[PSP_FW_NAME_LEN];
2899         const struct psp_firmware_header_v1_0 *asd_hdr;
2900         int err = 0;
2901
2902         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2903         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2904         if (err)
2905                 goto out;
2906
2907         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2908         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2909         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2910         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2911         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2912                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2913         return 0;
2914 out:
2915         amdgpu_ucode_release(&adev->psp.asd_fw);
2916         return err;
2917 }
2918
2919 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2920 {
2921         struct amdgpu_device *adev = psp->adev;
2922         char fw_name[PSP_FW_NAME_LEN];
2923         const struct psp_firmware_header_v1_0 *toc_hdr;
2924         int err = 0;
2925
2926         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2927         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
2928         if (err)
2929                 goto out;
2930
2931         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2932         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2933         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2934         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2935         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2936                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2937         return 0;
2938 out:
2939         amdgpu_ucode_release(&adev->psp.toc_fw);
2940         return err;
2941 }
2942
2943 static int parse_sos_bin_descriptor(struct psp_context *psp,
2944                                    const struct psp_fw_bin_desc *desc,
2945                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2946 {
2947         uint8_t *ucode_start_addr  = NULL;
2948
2949         if (!psp || !desc || !sos_hdr)
2950                 return -EINVAL;
2951
2952         ucode_start_addr  = (uint8_t *)sos_hdr +
2953                             le32_to_cpu(desc->offset_bytes) +
2954                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2955
2956         switch (desc->fw_type) {
2957         case PSP_FW_TYPE_PSP_SOS:
2958                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2959                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2960                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2961                 psp->sos.start_addr        = ucode_start_addr;
2962                 break;
2963         case PSP_FW_TYPE_PSP_SYS_DRV:
2964                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2965                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2966                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2967                 psp->sys.start_addr        = ucode_start_addr;
2968                 break;
2969         case PSP_FW_TYPE_PSP_KDB:
2970                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2971                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2972                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2973                 psp->kdb.start_addr        = ucode_start_addr;
2974                 break;
2975         case PSP_FW_TYPE_PSP_TOC:
2976                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2977                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2978                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2979                 psp->toc.start_addr        = ucode_start_addr;
2980                 break;
2981         case PSP_FW_TYPE_PSP_SPL:
2982                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2983                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2984                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2985                 psp->spl.start_addr        = ucode_start_addr;
2986                 break;
2987         case PSP_FW_TYPE_PSP_RL:
2988                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2989                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2990                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
2991                 psp->rl.start_addr         = ucode_start_addr;
2992                 break;
2993         case PSP_FW_TYPE_PSP_SOC_DRV:
2994                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
2995                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
2996                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
2997                 psp->soc_drv.start_addr         = ucode_start_addr;
2998                 break;
2999         case PSP_FW_TYPE_PSP_INTF_DRV:
3000                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3001                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3002                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3003                 psp->intf_drv.start_addr        = ucode_start_addr;
3004                 break;
3005         case PSP_FW_TYPE_PSP_DBG_DRV:
3006                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3007                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3008                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3009                 psp->dbg_drv.start_addr         = ucode_start_addr;
3010                 break;
3011         case PSP_FW_TYPE_PSP_RAS_DRV:
3012                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3013                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3014                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3015                 psp->ras_drv.start_addr         = ucode_start_addr;
3016                 break;
3017         default:
3018                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3019                 break;
3020         }
3021
3022         return 0;
3023 }
3024
3025 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3026 {
3027         const struct psp_firmware_header_v1_0 *sos_hdr;
3028         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3029         uint8_t *ucode_array_start_addr;
3030
3031         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3032         ucode_array_start_addr = (uint8_t *)sos_hdr +
3033                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3034
3035         if (adev->gmc.xgmi.connected_to_cpu ||
3036             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3037                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3038                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3039
3040                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3041                 adev->psp.sys.start_addr = ucode_array_start_addr;
3042
3043                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3044                 adev->psp.sos.start_addr = ucode_array_start_addr +
3045                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3046         } else {
3047                 /* Load alternate PSP SOS FW */
3048                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3049
3050                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3051                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3052
3053                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3054                 adev->psp.sys.start_addr = ucode_array_start_addr +
3055                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3056
3057                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3058                 adev->psp.sos.start_addr = ucode_array_start_addr +
3059                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3060         }
3061
3062         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3063                 dev_warn(adev->dev, "PSP SOS FW not available");
3064                 return -EINVAL;
3065         }
3066
3067         return 0;
3068 }
3069
3070 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3071 {
3072         struct amdgpu_device *adev = psp->adev;
3073         char fw_name[PSP_FW_NAME_LEN];
3074         const struct psp_firmware_header_v1_0 *sos_hdr;
3075         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3076         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3077         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3078         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3079         int err = 0;
3080         uint8_t *ucode_array_start_addr;
3081         int fw_index = 0;
3082
3083         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3084         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3085         if (err)
3086                 goto out;
3087
3088         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3089         ucode_array_start_addr = (uint8_t *)sos_hdr +
3090                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3091         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3092
3093         switch (sos_hdr->header.header_version_major) {
3094         case 1:
3095                 err = psp_init_sos_base_fw(adev);
3096                 if (err)
3097                         goto out;
3098
3099                 if (sos_hdr->header.header_version_minor == 1) {
3100                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3101                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3102                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3103                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3104                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3105                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3106                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3107                 }
3108                 if (sos_hdr->header.header_version_minor == 2) {
3109                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3110                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3111                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3112                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3113                 }
3114                 if (sos_hdr->header.header_version_minor == 3) {
3115                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3116                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3117                         adev->psp.toc.start_addr = ucode_array_start_addr +
3118                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3119                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3120                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3121                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3122                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3123                         adev->psp.spl.start_addr = ucode_array_start_addr +
3124                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3125                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3126                         adev->psp.rl.start_addr = ucode_array_start_addr +
3127                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3128                 }
3129                 break;
3130         case 2:
3131                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3132
3133                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3134                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3135                         err = -EINVAL;
3136                         goto out;
3137                 }
3138
3139                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3140                         err = parse_sos_bin_descriptor(psp,
3141                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3142                                                        sos_hdr_v2_0);
3143                         if (err)
3144                                 goto out;
3145                 }
3146                 break;
3147         default:
3148                 dev_err(adev->dev,
3149                         "unsupported psp sos firmware\n");
3150                 err = -EINVAL;
3151                 goto out;
3152         }
3153
3154         return 0;
3155 out:
3156         amdgpu_ucode_release(&adev->psp.sos_fw);
3157
3158         return err;
3159 }
3160
3161 static int parse_ta_bin_descriptor(struct psp_context *psp,
3162                                    const struct psp_fw_bin_desc *desc,
3163                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3164 {
3165         uint8_t *ucode_start_addr  = NULL;
3166
3167         if (!psp || !desc || !ta_hdr)
3168                 return -EINVAL;
3169
3170         ucode_start_addr  = (uint8_t *)ta_hdr +
3171                             le32_to_cpu(desc->offset_bytes) +
3172                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3173
3174         switch (desc->fw_type) {
3175         case TA_FW_TYPE_PSP_ASD:
3176                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3177                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3178                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3179                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3180                 break;
3181         case TA_FW_TYPE_PSP_XGMI:
3182                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3183                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3184                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3185                 break;
3186         case TA_FW_TYPE_PSP_RAS:
3187                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3188                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3189                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3190                 break;
3191         case TA_FW_TYPE_PSP_HDCP:
3192                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3193                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3194                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3195                 break;
3196         case TA_FW_TYPE_PSP_DTM:
3197                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3198                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3199                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3200                 break;
3201         case TA_FW_TYPE_PSP_RAP:
3202                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3203                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3204                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3205                 break;
3206         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3207                 psp->securedisplay_context.context.bin_desc.fw_version =
3208                         le32_to_cpu(desc->fw_version);
3209                 psp->securedisplay_context.context.bin_desc.size_bytes =
3210                         le32_to_cpu(desc->size_bytes);
3211                 psp->securedisplay_context.context.bin_desc.start_addr =
3212                         ucode_start_addr;
3213                 break;
3214         default:
3215                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3216                 break;
3217         }
3218
3219         return 0;
3220 }
3221
3222 static int parse_ta_v1_microcode(struct psp_context *psp)
3223 {
3224         const struct ta_firmware_header_v1_0 *ta_hdr;
3225         struct amdgpu_device *adev = psp->adev;
3226
3227         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3228
3229         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3230                 return -EINVAL;
3231
3232         adev->psp.xgmi_context.context.bin_desc.fw_version =
3233                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3234         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3235                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3236         adev->psp.xgmi_context.context.bin_desc.start_addr =
3237                 (uint8_t *)ta_hdr +
3238                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3239
3240         adev->psp.ras_context.context.bin_desc.fw_version =
3241                 le32_to_cpu(ta_hdr->ras.fw_version);
3242         adev->psp.ras_context.context.bin_desc.size_bytes =
3243                 le32_to_cpu(ta_hdr->ras.size_bytes);
3244         adev->psp.ras_context.context.bin_desc.start_addr =
3245                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3246                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3247
3248         adev->psp.hdcp_context.context.bin_desc.fw_version =
3249                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3250         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3251                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3252         adev->psp.hdcp_context.context.bin_desc.start_addr =
3253                 (uint8_t *)ta_hdr +
3254                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3255
3256         adev->psp.dtm_context.context.bin_desc.fw_version =
3257                 le32_to_cpu(ta_hdr->dtm.fw_version);
3258         adev->psp.dtm_context.context.bin_desc.size_bytes =
3259                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3260         adev->psp.dtm_context.context.bin_desc.start_addr =
3261                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3262                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3263
3264         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3265                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3266         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3267                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3268         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3269                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3270                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3271
3272         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3273
3274         return 0;
3275 }
3276
3277 static int parse_ta_v2_microcode(struct psp_context *psp)
3278 {
3279         const struct ta_firmware_header_v2_0 *ta_hdr;
3280         struct amdgpu_device *adev = psp->adev;
3281         int err = 0;
3282         int ta_index = 0;
3283
3284         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3285
3286         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3287                 return -EINVAL;
3288
3289         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3290                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3291                 return -EINVAL;
3292         }
3293
3294         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3295                 err = parse_ta_bin_descriptor(psp,
3296                                               &ta_hdr->ta_fw_bin[ta_index],
3297                                               ta_hdr);
3298                 if (err)
3299                         return err;
3300         }
3301
3302         return 0;
3303 }
3304
3305 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3306 {
3307         const struct common_firmware_header *hdr;
3308         struct amdgpu_device *adev = psp->adev;
3309         char fw_name[PSP_FW_NAME_LEN];
3310         int err;
3311
3312         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3313         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3314         if (err)
3315                 return err;
3316
3317         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3318         switch (le16_to_cpu(hdr->header_version_major)) {
3319         case 1:
3320                 err = parse_ta_v1_microcode(psp);
3321                 break;
3322         case 2:
3323                 err = parse_ta_v2_microcode(psp);
3324                 break;
3325         default:
3326                 dev_err(adev->dev, "unsupported TA header version\n");
3327                 err = -EINVAL;
3328         }
3329
3330         if (err)
3331                 amdgpu_ucode_release(&adev->psp.ta_fw);
3332
3333         return err;
3334 }
3335
3336 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3337 {
3338         struct amdgpu_device *adev = psp->adev;
3339         char fw_name[PSP_FW_NAME_LEN];
3340         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3341         struct amdgpu_firmware_info *info = NULL;
3342         int err = 0;
3343
3344         if (!amdgpu_sriov_vf(adev)) {
3345                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3346                 return -EINVAL;
3347         }
3348
3349         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3350         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3351         if (err) {
3352                 if (err == -ENODEV) {
3353                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3354                         err = 0;
3355                         goto out;
3356                 }
3357                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3358         }
3359
3360         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3361         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3362         info->fw = adev->psp.cap_fw;
3363         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3364                 adev->psp.cap_fw->data;
3365         adev->firmware.fw_size += ALIGN(
3366                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3367         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3368         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3369         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3370
3371         return 0;
3372
3373 out:
3374         amdgpu_ucode_release(&adev->psp.cap_fw);
3375         return err;
3376 }
3377
3378 static int psp_set_clockgating_state(void *handle,
3379                                      enum amd_clockgating_state state)
3380 {
3381         return 0;
3382 }
3383
3384 static int psp_set_powergating_state(void *handle,
3385                                      enum amd_powergating_state state)
3386 {
3387         return 0;
3388 }
3389
3390 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3391                                          struct device_attribute *attr,
3392                                          char *buf)
3393 {
3394         struct drm_device *ddev = dev_get_drvdata(dev);
3395         struct amdgpu_device *adev = drm_to_adev(ddev);
3396         uint32_t fw_ver;
3397         int ret;
3398
3399         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3400                 DRM_INFO("PSP block is not ready yet.");
3401                 return -EBUSY;
3402         }
3403
3404         mutex_lock(&adev->psp.mutex);
3405         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3406         mutex_unlock(&adev->psp.mutex);
3407
3408         if (ret) {
3409                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3410                 return ret;
3411         }
3412
3413         return sysfs_emit(buf, "%x\n", fw_ver);
3414 }
3415
3416 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3417                                                        struct device_attribute *attr,
3418                                                        const char *buf,
3419                                                        size_t count)
3420 {
3421         struct drm_device *ddev = dev_get_drvdata(dev);
3422         struct amdgpu_device *adev = drm_to_adev(ddev);
3423         int ret, idx;
3424         char fw_name[100];
3425         const struct firmware *usbc_pd_fw;
3426         struct amdgpu_bo *fw_buf_bo = NULL;
3427         uint64_t fw_pri_mc_addr;
3428         void *fw_pri_cpu_addr;
3429
3430         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3431                 DRM_INFO("PSP block is not ready yet.");
3432                 return -EBUSY;
3433         }
3434
3435         if (!drm_dev_enter(ddev, &idx))
3436                 return -ENODEV;
3437
3438         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3439         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3440         if (ret)
3441                 goto fail;
3442
3443         /* LFB address which is aligned to 1MB boundary per PSP request */
3444         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3445                                       AMDGPU_GEM_DOMAIN_VRAM |
3446                                       AMDGPU_GEM_DOMAIN_GTT,
3447                                       &fw_buf_bo, &fw_pri_mc_addr,
3448                                       &fw_pri_cpu_addr);
3449         if (ret)
3450                 goto rel_buf;
3451
3452         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3453
3454         mutex_lock(&adev->psp.mutex);
3455         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3456         mutex_unlock(&adev->psp.mutex);
3457
3458         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3459
3460 rel_buf:
3461         release_firmware(usbc_pd_fw);
3462 fail:
3463         if (ret) {
3464                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3465                 count = ret;
3466         }
3467
3468         drm_dev_exit(idx);
3469         return count;
3470 }
3471
3472 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3473 {
3474         int idx;
3475
3476         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3477                 return;
3478
3479         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3480         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3481
3482         drm_dev_exit(idx);
3483 }
3484
3485 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3486                    psp_usbc_pd_fw_sysfs_read,
3487                    psp_usbc_pd_fw_sysfs_write);
3488
3489 int is_psp_fw_valid(struct psp_bin_desc bin)
3490 {
3491         return bin.size_bytes;
3492 }
3493
3494 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3495                                         struct bin_attribute *bin_attr,
3496                                         char *buffer, loff_t pos, size_t count)
3497 {
3498         struct device *dev = kobj_to_dev(kobj);
3499         struct drm_device *ddev = dev_get_drvdata(dev);
3500         struct amdgpu_device *adev = drm_to_adev(ddev);
3501
3502         adev->psp.vbflash_done = false;
3503
3504         /* Safeguard against memory drain */
3505         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3506                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3507                 kvfree(adev->psp.vbflash_tmp_buf);
3508                 adev->psp.vbflash_tmp_buf = NULL;
3509                 adev->psp.vbflash_image_size = 0;
3510                 return -ENOMEM;
3511         }
3512
3513         /* TODO Just allocate max for now and optimize to realloc later if needed */
3514         if (!adev->psp.vbflash_tmp_buf) {
3515                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3516                 if (!adev->psp.vbflash_tmp_buf)
3517                         return -ENOMEM;
3518         }
3519
3520         mutex_lock(&adev->psp.mutex);
3521         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3522         adev->psp.vbflash_image_size += count;
3523         mutex_unlock(&adev->psp.mutex);
3524
3525         dev_info(adev->dev, "VBIOS flash write PSP done");
3526
3527         return count;
3528 }
3529
3530 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3531                                        struct bin_attribute *bin_attr, char *buffer,
3532                                        loff_t pos, size_t count)
3533 {
3534         struct device *dev = kobj_to_dev(kobj);
3535         struct drm_device *ddev = dev_get_drvdata(dev);
3536         struct amdgpu_device *adev = drm_to_adev(ddev);
3537         struct amdgpu_bo *fw_buf_bo = NULL;
3538         uint64_t fw_pri_mc_addr;
3539         void *fw_pri_cpu_addr;
3540         int ret;
3541
3542         dev_info(adev->dev, "VBIOS flash to PSP started");
3543
3544         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3545                                         AMDGPU_GPU_PAGE_SIZE,
3546                                         AMDGPU_GEM_DOMAIN_VRAM,
3547                                         &fw_buf_bo,
3548                                         &fw_pri_mc_addr,
3549                                         &fw_pri_cpu_addr);
3550         if (ret)
3551                 goto rel_buf;
3552
3553         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3554
3555         mutex_lock(&adev->psp.mutex);
3556         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3557         mutex_unlock(&adev->psp.mutex);
3558
3559         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3560
3561 rel_buf:
3562         kvfree(adev->psp.vbflash_tmp_buf);
3563         adev->psp.vbflash_tmp_buf = NULL;
3564         adev->psp.vbflash_image_size = 0;
3565
3566         if (ret) {
3567                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3568                 return ret;
3569         }
3570
3571         dev_info(adev->dev, "VBIOS flash to PSP done");
3572         return 0;
3573 }
3574
3575 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3576                                          struct device_attribute *attr,
3577                                          char *buf)
3578 {
3579         struct drm_device *ddev = dev_get_drvdata(dev);
3580         struct amdgpu_device *adev = drm_to_adev(ddev);
3581         uint32_t vbflash_status;
3582
3583         vbflash_status = psp_vbflash_status(&adev->psp);
3584         if (!adev->psp.vbflash_done)
3585                 vbflash_status = 0;
3586         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3587                 vbflash_status = 1;
3588
3589         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3590 }
3591
3592 static const struct bin_attribute psp_vbflash_bin_attr = {
3593         .attr = {.name = "psp_vbflash", .mode = 0664},
3594         .size = 0,
3595         .write = amdgpu_psp_vbflash_write,
3596         .read = amdgpu_psp_vbflash_read,
3597 };
3598
3599 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3600
3601 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3602 {
3603         int ret = 0;
3604         struct psp_context *psp = &adev->psp;
3605
3606         if (amdgpu_sriov_vf(adev))
3607                 return -EINVAL;
3608
3609         switch (adev->ip_versions[MP0_HWIP][0]) {
3610         case IP_VERSION(13, 0, 0):
3611         case IP_VERSION(13, 0, 7):
3612                 if (!psp->adev) {
3613                         psp->adev = adev;
3614                         psp_v13_0_set_psp_funcs(psp);
3615                 }
3616                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3617                 if (ret)
3618                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3619                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3620                 if (ret)
3621                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3622                 return ret;
3623         default:
3624                 return 0;
3625         }
3626 }
3627
3628 const struct amd_ip_funcs psp_ip_funcs = {
3629         .name = "psp",
3630         .early_init = psp_early_init,
3631         .late_init = NULL,
3632         .sw_init = psp_sw_init,
3633         .sw_fini = psp_sw_fini,
3634         .hw_init = psp_hw_init,
3635         .hw_fini = psp_hw_fini,
3636         .suspend = psp_suspend,
3637         .resume = psp_resume,
3638         .is_idle = NULL,
3639         .check_soft_reset = NULL,
3640         .wait_for_idle = NULL,
3641         .soft_reset = NULL,
3642         .set_clockgating_state = psp_set_clockgating_state,
3643         .set_powergating_state = psp_set_powergating_state,
3644 };
3645
3646 static int psp_sysfs_init(struct amdgpu_device *adev)
3647 {
3648         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3649
3650         if (ret)
3651                 DRM_ERROR("Failed to create USBC PD FW control file!");
3652
3653         return ret;
3654 }
3655
3656 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3657 {
3658         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3659         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3660 }
3661
3662 static void psp_sysfs_fini(struct amdgpu_device *adev)
3663 {
3664         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3665 }
3666
3667 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3668 {
3669         .type = AMD_IP_BLOCK_TYPE_PSP,
3670         .major = 3,
3671         .minor = 1,
3672         .rev = 0,
3673         .funcs = &psp_ip_funcs,
3674 };
3675
3676 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3677 {
3678         .type = AMD_IP_BLOCK_TYPE_PSP,
3679         .major = 10,
3680         .minor = 0,
3681         .rev = 0,
3682         .funcs = &psp_ip_funcs,
3683 };
3684
3685 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3686 {
3687         .type = AMD_IP_BLOCK_TYPE_PSP,
3688         .major = 11,
3689         .minor = 0,
3690         .rev = 0,
3691         .funcs = &psp_ip_funcs,
3692 };
3693
3694 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3695         .type = AMD_IP_BLOCK_TYPE_PSP,
3696         .major = 11,
3697         .minor = 0,
3698         .rev = 8,
3699         .funcs = &psp_ip_funcs,
3700 };
3701
3702 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3703 {
3704         .type = AMD_IP_BLOCK_TYPE_PSP,
3705         .major = 12,
3706         .minor = 0,
3707         .rev = 0,
3708         .funcs = &psp_ip_funcs,
3709 };
3710
3711 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3712         .type = AMD_IP_BLOCK_TYPE_PSP,
3713         .major = 13,
3714         .minor = 0,
3715         .rev = 0,
3716         .funcs = &psp_ip_funcs,
3717 };
3718
3719 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3720         .type = AMD_IP_BLOCK_TYPE_PSP,
3721         .major = 13,
3722         .minor = 0,
3723         .rev = 4,
3724         .funcs = &psp_ip_funcs,
3725 };