drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "cik_dpm.h"
  34 #include "vi_dpm.h"
  35
  36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
  37 {
  38         int ret = 0;
  39         struct amd_powerplay *amd_pp;
  40
  41         amd_pp = &(adev->powerplay);
  42
  43         if (adev->pp_enabled) {
  44 #ifdef CONFIG_DRM_AMD_POWERPLAY
  45                 struct amd_pp_init *pp_init;
  46
  47                 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
  48
  49                 if (pp_init == NULL)
  50                         return -ENOMEM;
  51
  52                 pp_init->chip_family = adev->family;
  53                 pp_init->chip_id = adev->asic_type;
  54                 pp_init->device = amdgpu_cgs_create_device(adev);
  55
  56                 ret = amd_powerplay_init(pp_init, amd_pp);
  57                 kfree(pp_init);
  58 #endif
  59         } else {
  60                 amd_pp->pp_handle = (void *)adev;
  61
  62                 switch (adev->asic_type) {
  63 #ifdef CONFIG_DRM_AMDGPU_CIK
  64                 case CHIP_BONAIRE:
  65                 case CHIP_HAWAII:
  66                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  67                         break;
  68                 case CHIP_KABINI:
  69                 case CHIP_MULLINS:
  70                 case CHIP_KAVERI:
  71                         amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  72                         break;
  73 #endif
  74                 case CHIP_TOPAZ:
  75                         amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
  76                         break;
  77                 case CHIP_TONGA:
  78                         amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
  79                         break;
  80                 case CHIP_FIJI:
  81                         amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
  82                         break;
  83                 case CHIP_CARRIZO:
  84                 case CHIP_STONEY:
  85                         amd_pp->ip_funcs = &cz_dpm_ip_funcs;
  86                         break;
  87                 default:
  88                         ret = -EINVAL;
  89                         break;
  90                 }
  91         }
  92         return ret;
  93 }
  94
  95 static int amdgpu_pp_early_init(void *handle)
  96 {
  97         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  98         int ret = 0;
  99
 100 #ifdef CONFIG_DRM_AMD_POWERPLAY
 101         switch (adev->asic_type) {
 102                 case CHIP_TONGA:
 103                 case CHIP_FIJI:
 104                         adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 105                         break;
 106                 default:
 107                         adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
 108                         break;
 109         }
 110 #else
 111         adev->pp_enabled = false;
 112 #endif
 113
 114         ret = amdgpu_powerplay_init(adev);
 115         if (ret)
 116                 return ret;
 117
 118         if (adev->powerplay.ip_funcs->early_init)
 119                 ret = adev->powerplay.ip_funcs->early_init(
 120                                         adev->powerplay.pp_handle);
 121         return ret;
 122 }
 123
 124
 125 static int amdgpu_pp_late_init(void *handle)
 126 {
 127         int ret = 0;
 128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 129
 130         if (adev->powerplay.ip_funcs->late_init)
 131                 ret = adev->powerplay.ip_funcs->late_init(
 132                                         adev->powerplay.pp_handle);
 133
 134         return ret;
 135 }
 136
 137 static int amdgpu_pp_sw_init(void *handle)
 138 {
 139         int ret = 0;
 140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 141
 142         if (adev->powerplay.ip_funcs->sw_init)
 143                 ret = adev->powerplay.ip_funcs->sw_init(
 144                                         adev->powerplay.pp_handle);
 145
 146 #ifdef CONFIG_DRM_AMD_POWERPLAY
 147         if (adev->pp_enabled) {
 148                 adev->pm.dpm_enabled = true;
 149                 amdgpu_pm_sysfs_init(adev);
 150         }
 151 #endif
 152
 153         return ret;
 154 }
 155
 156 static int amdgpu_pp_sw_fini(void *handle)
 157 {
 158         int ret = 0;
 159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 160
 161         if (adev->powerplay.ip_funcs->sw_fini)
 162                 ret = adev->powerplay.ip_funcs->sw_fini(
 163                                         adev->powerplay.pp_handle);
 164         if (ret)
 165                 return ret;
 166
 167 #ifdef CONFIG_DRM_AMD_POWERPLAY
 168         if (adev->pp_enabled) {
 169                 amdgpu_pm_sysfs_fini(adev);
 170                 amd_powerplay_fini(adev->powerplay.pp_handle);
 171         }
 172 #endif
 173
 174         return ret;
 175 }
 176
 177 static int amdgpu_pp_hw_init(void *handle)
 178 {
 179         int ret = 0;
 180         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 181
 182         if (adev->pp_enabled && adev->firmware.smu_load)
 183                 amdgpu_ucode_init_bo(adev);
 184
 185         if (adev->powerplay.ip_funcs->hw_init)
 186                 ret = adev->powerplay.ip_funcs->hw_init(
 187                                         adev->powerplay.pp_handle);
 188
 189         return ret;
 190 }
 191
 192 static int amdgpu_pp_hw_fini(void *handle)
 193 {
 194         int ret = 0;
 195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 196
 197         if (adev->powerplay.ip_funcs->hw_fini)
 198                 ret = adev->powerplay.ip_funcs->hw_fini(
 199                                         adev->powerplay.pp_handle);
 200
 201         if (adev->pp_enabled && adev->firmware.smu_load)
 202                 amdgpu_ucode_fini_bo(adev);
 203
 204         return ret;
 205 }
 206
 207 static int amdgpu_pp_suspend(void *handle)
 208 {
 209         int ret = 0;
 210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 211
 212         if (adev->powerplay.ip_funcs->suspend)
 213                 ret = adev->powerplay.ip_funcs->suspend(
 214                                          adev->powerplay.pp_handle);
 215         return ret;
 216 }
 217
 218 static int amdgpu_pp_resume(void *handle)
 219 {
 220         int ret = 0;
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222
 223         if (adev->powerplay.ip_funcs->resume)
 224                 ret = adev->powerplay.ip_funcs->resume(
 225                                         adev->powerplay.pp_handle);
 226         return ret;
 227 }
 228
 229 static int amdgpu_pp_set_clockgating_state(void *handle,
 230                                         enum amd_clockgating_state state)
 231 {
 232         int ret = 0;
 233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 234
 235         if (adev->powerplay.ip_funcs->set_clockgating_state)
 236                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 237                                 adev->powerplay.pp_handle, state);
 238         return ret;
 239 }
 240
 241 static int amdgpu_pp_set_powergating_state(void *handle,
 242                                         enum amd_powergating_state state)
 243 {
 244         int ret = 0;
 245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 246
 247         if (adev->powerplay.ip_funcs->set_powergating_state)
 248                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 249                                  adev->powerplay.pp_handle, state);
 250         return ret;
 251 }
 252
 253
 254 static bool amdgpu_pp_is_idle(void *handle)
 255 {
 256         bool ret = true;
 257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 258
 259         if (adev->powerplay.ip_funcs->is_idle)
 260                 ret = adev->powerplay.ip_funcs->is_idle(
 261                                         adev->powerplay.pp_handle);
 262         return ret;
 263 }
 264
 265 static int amdgpu_pp_wait_for_idle(void *handle)
 266 {
 267         int ret = 0;
 268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 269
 270         if (adev->powerplay.ip_funcs->wait_for_idle)
 271                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 272                                         adev->powerplay.pp_handle);
 273         return ret;
 274 }
 275
 276 static int amdgpu_pp_soft_reset(void *handle)
 277 {
 278         int ret = 0;
 279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 280
 281         if (adev->powerplay.ip_funcs->soft_reset)
 282                 ret = adev->powerplay.ip_funcs->soft_reset(
 283                                         adev->powerplay.pp_handle);
 284         return ret;
 285 }
 286
 287 static void amdgpu_pp_print_status(void *handle)
 288 {
 289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 290
 291         if (adev->powerplay.ip_funcs->print_status)
 292                 adev->powerplay.ip_funcs->print_status(
 293                                         adev->powerplay.pp_handle);
 294 }
 295
 296 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 297         .early_init = amdgpu_pp_early_init,
 298         .late_init = amdgpu_pp_late_init,
 299         .sw_init = amdgpu_pp_sw_init,
 300         .sw_fini = amdgpu_pp_sw_fini,
 301         .hw_init = amdgpu_pp_hw_init,
 302         .hw_fini = amdgpu_pp_hw_fini,
 303         .suspend = amdgpu_pp_suspend,
 304         .resume = amdgpu_pp_resume,
 305         .is_idle = amdgpu_pp_is_idle,
 306         .wait_for_idle = amdgpu_pp_wait_for_idle,
 307         .soft_reset = amdgpu_pp_soft_reset,
 308         .print_status = amdgpu_pp_print_status,
 309         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 310         .set_powergating_state = amdgpu_pp_set_powergating_state,
 311 };