2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include "amdgpu_pm.h"
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_powerplay.h"
36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
39 struct amd_powerplay *amd_pp;
41 amd_pp = &(adev->powerplay);
43 if (amdgpu_powerplay) {
44 #ifdef CONFIG_DRM_AMD_POWERPLAY
45 struct amd_pp_init *pp_init;
47 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
52 pp_init->chip_family = adev->family;
53 pp_init->chip_id = adev->asic_type;
54 pp_init->device = amdgpu_cgs_create_device(adev);
56 ret = amd_powerplay_init(pp_init, amd_pp);
60 amd_pp->pp_handle = (void *)adev;
62 switch (adev->asic_type) {
63 #ifdef CONFIG_DRM_AMDGPU_CIK
66 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
71 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
75 amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
78 amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
81 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
91 static int amdgpu_pp_early_init(void *handle)
93 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
96 ret = amdgpu_powerplay_init(adev);
100 if (adev->powerplay.ip_funcs->early_init)
101 ret = adev->powerplay.ip_funcs->early_init(
102 adev->powerplay.pp_handle);
106 static int amdgpu_pp_sw_init(void *handle)
109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
111 if (adev->powerplay.ip_funcs->sw_init)
112 ret = adev->powerplay.ip_funcs->sw_init(
113 adev->powerplay.pp_handle);
115 #ifdef CONFIG_DRM_AMD_POWERPLAY
116 if (amdgpu_powerplay) {
117 adev->pm.dpm_enabled = true;
118 amdgpu_pm_sysfs_init(adev);
125 static int amdgpu_pp_sw_fini(void *handle)
128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
130 if (adev->powerplay.ip_funcs->sw_fini)
131 ret = adev->powerplay.ip_funcs->sw_fini(
132 adev->powerplay.pp_handle);
136 #ifdef CONFIG_DRM_AMD_POWERPLAY
137 if (amdgpu_powerplay) {
138 amdgpu_pm_sysfs_fini(adev);
139 amd_powerplay_fini(adev->powerplay.pp_handle);
146 static int amdgpu_pp_hw_init(void *handle)
149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
151 if (amdgpu_powerplay && adev->firmware.smu_load)
152 amdgpu_ucode_init_bo(adev);
154 if (adev->powerplay.ip_funcs->hw_init)
155 ret = adev->powerplay.ip_funcs->hw_init(
156 adev->powerplay.pp_handle);
161 static int amdgpu_pp_hw_fini(void *handle)
164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
166 if (adev->powerplay.ip_funcs->hw_fini)
167 ret = adev->powerplay.ip_funcs->hw_fini(
168 adev->powerplay.pp_handle);
170 if (amdgpu_powerplay && adev->firmware.smu_load)
171 amdgpu_ucode_fini_bo(adev);
176 static int amdgpu_pp_suspend(void *handle)
179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
181 if (adev->powerplay.ip_funcs->suspend)
182 ret = adev->powerplay.ip_funcs->suspend(
183 adev->powerplay.pp_handle);
187 static int amdgpu_pp_resume(void *handle)
190 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
192 if (adev->powerplay.ip_funcs->resume)
193 ret = adev->powerplay.ip_funcs->resume(
194 adev->powerplay.pp_handle);
198 static int amdgpu_pp_set_clockgating_state(void *handle,
199 enum amd_clockgating_state state)
202 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
204 if (adev->powerplay.ip_funcs->set_clockgating_state)
205 ret = adev->powerplay.ip_funcs->set_clockgating_state(
206 adev->powerplay.pp_handle, state);
210 static int amdgpu_pp_set_powergating_state(void *handle,
211 enum amd_powergating_state state)
214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
216 if (adev->powerplay.ip_funcs->set_powergating_state)
217 ret = adev->powerplay.ip_funcs->set_powergating_state(
218 adev->powerplay.pp_handle, state);
223 static bool amdgpu_pp_is_idle(void *handle)
226 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
228 if (adev->powerplay.ip_funcs->is_idle)
229 ret = adev->powerplay.ip_funcs->is_idle(
230 adev->powerplay.pp_handle);
234 static int amdgpu_pp_wait_for_idle(void *handle)
237 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
239 if (adev->powerplay.ip_funcs->wait_for_idle)
240 ret = adev->powerplay.ip_funcs->wait_for_idle(
241 adev->powerplay.pp_handle);
245 static int amdgpu_pp_soft_reset(void *handle)
248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
250 if (adev->powerplay.ip_funcs->soft_reset)
251 ret = adev->powerplay.ip_funcs->soft_reset(
252 adev->powerplay.pp_handle);
256 static void amdgpu_pp_print_status(void *handle)
258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
260 if (adev->powerplay.ip_funcs->print_status)
261 adev->powerplay.ip_funcs->print_status(
262 adev->powerplay.pp_handle);
265 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
266 .early_init = amdgpu_pp_early_init,
268 .sw_init = amdgpu_pp_sw_init,
269 .sw_fini = amdgpu_pp_sw_fini,
270 .hw_init = amdgpu_pp_hw_init,
271 .hw_fini = amdgpu_pp_hw_fini,
272 .suspend = amdgpu_pp_suspend,
273 .resume = amdgpu_pp_resume,
274 .is_idle = amdgpu_pp_is_idle,
275 .wait_for_idle = amdgpu_pp_wait_for_idle,
276 .soft_reset = amdgpu_pp_soft_reset,
277 .print_status = amdgpu_pp_print_status,
278 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
279 .set_powergating_state = amdgpu_pp_set_powergating_state,