2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include "amdgpu_pm.h"
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_powerplay.h"
36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
39 struct amd_powerplay *amd_pp;
41 amd_pp = &(adev->powerplay);
43 if (adev->pp_enabled) {
44 #ifdef CONFIG_DRM_AMD_POWERPLAY
45 struct amd_pp_init *pp_init;
47 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
52 pp_init->chip_family = adev->family;
53 pp_init->chip_id = adev->asic_type;
54 pp_init->device = amdgpu_cgs_create_device(adev);
56 ret = amd_powerplay_init(pp_init, amd_pp);
60 amd_pp->pp_handle = (void *)adev;
62 switch (adev->asic_type) {
63 #ifdef CONFIG_DRM_AMDGPU_CIK
66 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
71 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
75 amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
78 amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
81 amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
85 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
95 static int amdgpu_pp_early_init(void *handle)
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
100 #ifdef CONFIG_DRM_AMD_POWERPLAY
101 switch (adev->asic_type) {
104 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
108 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
110 /* These chips don't have powerplay implemenations */
118 adev->pp_enabled = false;
122 adev->pp_enabled = false;
125 ret = amdgpu_powerplay_init(adev);
129 if (adev->powerplay.ip_funcs->early_init)
130 ret = adev->powerplay.ip_funcs->early_init(
131 adev->powerplay.pp_handle);
136 static int amdgpu_pp_late_init(void *handle)
139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
141 if (adev->powerplay.ip_funcs->late_init)
142 ret = adev->powerplay.ip_funcs->late_init(
143 adev->powerplay.pp_handle);
145 #ifdef CONFIG_DRM_AMD_POWERPLAY
146 if (adev->pp_enabled && adev->pm.dpm_enabled) {
147 amdgpu_pm_sysfs_init(adev);
148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
154 static int amdgpu_pp_sw_init(void *handle)
157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159 if (adev->powerplay.ip_funcs->sw_init)
160 ret = adev->powerplay.ip_funcs->sw_init(
161 adev->powerplay.pp_handle);
163 #ifdef CONFIG_DRM_AMD_POWERPLAY
164 if (adev->pp_enabled)
165 adev->pm.dpm_enabled = true;
171 static int amdgpu_pp_sw_fini(void *handle)
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
176 if (adev->powerplay.ip_funcs->sw_fini)
177 ret = adev->powerplay.ip_funcs->sw_fini(
178 adev->powerplay.pp_handle);
182 #ifdef CONFIG_DRM_AMD_POWERPLAY
183 if (adev->pp_enabled) {
184 amdgpu_pm_sysfs_fini(adev);
185 amd_powerplay_fini(adev->powerplay.pp_handle);
192 static int amdgpu_pp_hw_init(void *handle)
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197 if (adev->pp_enabled && adev->firmware.smu_load)
198 amdgpu_ucode_init_bo(adev);
200 if (adev->powerplay.ip_funcs->hw_init)
201 ret = adev->powerplay.ip_funcs->hw_init(
202 adev->powerplay.pp_handle);
207 static int amdgpu_pp_hw_fini(void *handle)
210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
212 if (adev->powerplay.ip_funcs->hw_fini)
213 ret = adev->powerplay.ip_funcs->hw_fini(
214 adev->powerplay.pp_handle);
216 if (adev->pp_enabled && adev->firmware.smu_load)
217 amdgpu_ucode_fini_bo(adev);
222 static int amdgpu_pp_suspend(void *handle)
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
227 if (adev->powerplay.ip_funcs->suspend)
228 ret = adev->powerplay.ip_funcs->suspend(
229 adev->powerplay.pp_handle);
233 static int amdgpu_pp_resume(void *handle)
236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
238 if (adev->powerplay.ip_funcs->resume)
239 ret = adev->powerplay.ip_funcs->resume(
240 adev->powerplay.pp_handle);
244 static int amdgpu_pp_set_clockgating_state(void *handle,
245 enum amd_clockgating_state state)
248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
250 if (adev->powerplay.ip_funcs->set_clockgating_state)
251 ret = adev->powerplay.ip_funcs->set_clockgating_state(
252 adev->powerplay.pp_handle, state);
256 static int amdgpu_pp_set_powergating_state(void *handle,
257 enum amd_powergating_state state)
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
262 if (adev->powerplay.ip_funcs->set_powergating_state)
263 ret = adev->powerplay.ip_funcs->set_powergating_state(
264 adev->powerplay.pp_handle, state);
269 static bool amdgpu_pp_is_idle(void *handle)
272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
274 if (adev->powerplay.ip_funcs->is_idle)
275 ret = adev->powerplay.ip_funcs->is_idle(
276 adev->powerplay.pp_handle);
280 static int amdgpu_pp_wait_for_idle(void *handle)
283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
285 if (adev->powerplay.ip_funcs->wait_for_idle)
286 ret = adev->powerplay.ip_funcs->wait_for_idle(
287 adev->powerplay.pp_handle);
291 static int amdgpu_pp_soft_reset(void *handle)
294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
296 if (adev->powerplay.ip_funcs->soft_reset)
297 ret = adev->powerplay.ip_funcs->soft_reset(
298 adev->powerplay.pp_handle);
302 static void amdgpu_pp_print_status(void *handle)
304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
306 if (adev->powerplay.ip_funcs->print_status)
307 adev->powerplay.ip_funcs->print_status(
308 adev->powerplay.pp_handle);
311 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
312 .early_init = amdgpu_pp_early_init,
313 .late_init = amdgpu_pp_late_init,
314 .sw_init = amdgpu_pp_sw_init,
315 .sw_fini = amdgpu_pp_sw_fini,
316 .hw_init = amdgpu_pp_hw_init,
317 .hw_fini = amdgpu_pp_hw_fini,
318 .suspend = amdgpu_pp_suspend,
319 .resume = amdgpu_pp_resume,
320 .is_idle = amdgpu_pp_is_idle,
321 .wait_for_idle = amdgpu_pp_wait_for_idle,
322 .soft_reset = amdgpu_pp_soft_reset,
323 .print_status = amdgpu_pp_print_status,
324 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
325 .set_powergating_state = amdgpu_pp_set_powergating_state,