2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include "amdgpu_pm.h"
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_powerplay.h"
36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
39 struct amd_powerplay *amd_pp;
41 amd_pp = &(adev->powerplay);
43 if (adev->pp_enabled) {
44 #ifdef CONFIG_DRM_AMD_POWERPLAY
45 struct amd_pp_init *pp_init;
47 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
52 pp_init->chip_family = adev->family;
53 pp_init->chip_id = adev->asic_type;
54 pp_init->device = amdgpu_cgs_create_device(adev);
55 pp_init->powercontainment_enabled = amdgpu_powercontainment;
57 ret = amd_powerplay_init(pp_init, amd_pp);
61 amd_pp->pp_handle = (void *)adev;
63 switch (adev->asic_type) {
64 #ifdef CONFIG_DRM_AMDGPU_CIK
67 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
72 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
76 amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
79 amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
82 amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
86 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
96 static int amdgpu_pp_early_init(void *handle)
98 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
101 #ifdef CONFIG_DRM_AMD_POWERPLAY
102 switch (adev->asic_type) {
105 adev->pp_enabled = true;
109 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
113 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
115 /* These chips don't have powerplay implemenations */
123 adev->pp_enabled = false;
127 adev->pp_enabled = false;
130 ret = amdgpu_powerplay_init(adev);
134 if (adev->powerplay.ip_funcs->early_init)
135 ret = adev->powerplay.ip_funcs->early_init(
136 adev->powerplay.pp_handle);
141 static int amdgpu_pp_late_init(void *handle)
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
146 if (adev->powerplay.ip_funcs->late_init)
147 ret = adev->powerplay.ip_funcs->late_init(
148 adev->powerplay.pp_handle);
150 #ifdef CONFIG_DRM_AMD_POWERPLAY
151 if (adev->pp_enabled && adev->pm.dpm_enabled) {
152 amdgpu_pm_sysfs_init(adev);
153 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
159 static int amdgpu_pp_sw_init(void *handle)
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
164 if (adev->powerplay.ip_funcs->sw_init)
165 ret = adev->powerplay.ip_funcs->sw_init(
166 adev->powerplay.pp_handle);
168 #ifdef CONFIG_DRM_AMD_POWERPLAY
169 if (adev->pp_enabled)
170 adev->pm.dpm_enabled = true;
176 static int amdgpu_pp_sw_fini(void *handle)
179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
181 if (adev->powerplay.ip_funcs->sw_fini)
182 ret = adev->powerplay.ip_funcs->sw_fini(
183 adev->powerplay.pp_handle);
190 static int amdgpu_pp_hw_init(void *handle)
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
195 if (adev->pp_enabled && adev->firmware.smu_load)
196 amdgpu_ucode_init_bo(adev);
198 if (adev->powerplay.ip_funcs->hw_init)
199 ret = adev->powerplay.ip_funcs->hw_init(
200 adev->powerplay.pp_handle);
205 static int amdgpu_pp_hw_fini(void *handle)
208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
210 if (adev->powerplay.ip_funcs->hw_fini)
211 ret = adev->powerplay.ip_funcs->hw_fini(
212 adev->powerplay.pp_handle);
214 if (adev->pp_enabled && adev->firmware.smu_load)
215 amdgpu_ucode_fini_bo(adev);
220 static void amdgpu_pp_late_fini(void *handle)
222 #ifdef CONFIG_DRM_AMD_POWERPLAY
223 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
225 if (adev->pp_enabled) {
226 amdgpu_pm_sysfs_fini(adev);
227 amd_powerplay_fini(adev->powerplay.pp_handle);
230 if (adev->powerplay.ip_funcs->late_fini)
231 adev->powerplay.ip_funcs->late_fini(
232 adev->powerplay.pp_handle);
236 static int amdgpu_pp_suspend(void *handle)
239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
241 if (adev->powerplay.ip_funcs->suspend)
242 ret = adev->powerplay.ip_funcs->suspend(
243 adev->powerplay.pp_handle);
247 static int amdgpu_pp_resume(void *handle)
250 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
252 if (adev->powerplay.ip_funcs->resume)
253 ret = adev->powerplay.ip_funcs->resume(
254 adev->powerplay.pp_handle);
258 static int amdgpu_pp_set_clockgating_state(void *handle,
259 enum amd_clockgating_state state)
262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
264 if (adev->powerplay.ip_funcs->set_clockgating_state)
265 ret = adev->powerplay.ip_funcs->set_clockgating_state(
266 adev->powerplay.pp_handle, state);
270 static int amdgpu_pp_set_powergating_state(void *handle,
271 enum amd_powergating_state state)
274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
276 if (adev->powerplay.ip_funcs->set_powergating_state)
277 ret = adev->powerplay.ip_funcs->set_powergating_state(
278 adev->powerplay.pp_handle, state);
283 static bool amdgpu_pp_is_idle(void *handle)
286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
288 if (adev->powerplay.ip_funcs->is_idle)
289 ret = adev->powerplay.ip_funcs->is_idle(
290 adev->powerplay.pp_handle);
294 static int amdgpu_pp_wait_for_idle(void *handle)
297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
299 if (adev->powerplay.ip_funcs->wait_for_idle)
300 ret = adev->powerplay.ip_funcs->wait_for_idle(
301 adev->powerplay.pp_handle);
305 static int amdgpu_pp_soft_reset(void *handle)
308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
310 if (adev->powerplay.ip_funcs->soft_reset)
311 ret = adev->powerplay.ip_funcs->soft_reset(
312 adev->powerplay.pp_handle);
316 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
317 .name = "amdgpu_powerplay",
318 .early_init = amdgpu_pp_early_init,
319 .late_init = amdgpu_pp_late_init,
320 .sw_init = amdgpu_pp_sw_init,
321 .sw_fini = amdgpu_pp_sw_fini,
322 .hw_init = amdgpu_pp_hw_init,
323 .hw_fini = amdgpu_pp_hw_fini,
324 .late_fini = amdgpu_pp_late_fini,
325 .suspend = amdgpu_pp_suspend,
326 .resume = amdgpu_pp_resume,
327 .is_idle = amdgpu_pp_is_idle,
328 .wait_for_idle = amdgpu_pp_wait_for_idle,
329 .soft_reset = amdgpu_pp_soft_reset,
330 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
331 .set_powergating_state = amdgpu_pp_set_powergating_state,