2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <drm/drm_fb_helper.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <linux/hrtimer.h>
45 #include "amdgpu_irq.h"
47 #include <drm/drm_dp_mst_helper.h>
48 #include "modules/inc/mod_freesync.h"
52 struct amdgpu_encoder;
56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
60 #define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base)
62 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base);
64 #define AMDGPU_MAX_HPD_PINS 6
65 #define AMDGPU_MAX_CRTCS 6
66 #define AMDGPU_MAX_PLANES 6
67 #define AMDGPU_MAX_AFMT_BLOCKS 9
69 enum amdgpu_rmx_type {
76 enum amdgpu_underscan_type {
82 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
83 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
92 AMDGPU_HPD_NONE = 0xff,
95 enum amdgpu_crtc_irq {
96 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
97 AMDGPU_CRTC_IRQ_VBLANK2,
98 AMDGPU_CRTC_IRQ_VBLANK3,
99 AMDGPU_CRTC_IRQ_VBLANK4,
100 AMDGPU_CRTC_IRQ_VBLANK5,
101 AMDGPU_CRTC_IRQ_VBLANK6,
102 AMDGPU_CRTC_IRQ_VLINE1,
103 AMDGPU_CRTC_IRQ_VLINE2,
104 AMDGPU_CRTC_IRQ_VLINE3,
105 AMDGPU_CRTC_IRQ_VLINE4,
106 AMDGPU_CRTC_IRQ_VLINE5,
107 AMDGPU_CRTC_IRQ_VLINE6,
108 AMDGPU_CRTC_IRQ_NONE = 0xff
111 enum amdgpu_pageflip_irq {
112 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
113 AMDGPU_PAGEFLIP_IRQ_D2,
114 AMDGPU_PAGEFLIP_IRQ_D3,
115 AMDGPU_PAGEFLIP_IRQ_D4,
116 AMDGPU_PAGEFLIP_IRQ_D5,
117 AMDGPU_PAGEFLIP_IRQ_D6,
118 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
121 enum amdgpu_flip_status {
124 AMDGPU_FLIP_SUBMITTED
127 #define AMDGPU_MAX_I2C_BUS 16
129 /* amdgpu gpio-based i2c
130 * 1. "mask" reg and bits
131 * grabs the gpio pins for software use
133 * 2. "a" reg and bits
136 * 3. "en" reg and bits
137 * sets the pin direction
139 * 4. "y" reg and bits
143 struct amdgpu_i2c_bus_rec {
145 /* id used by atom */
147 /* id used by atom */
148 enum amdgpu_hpd_id hpd;
149 /* can be used with hw i2c engine */
151 /* uses multi-media i2c engine */
154 uint32_t mask_clk_reg;
155 uint32_t mask_data_reg;
159 uint32_t en_data_reg;
162 uint32_t mask_clk_mask;
163 uint32_t mask_data_mask;
165 uint32_t a_data_mask;
166 uint32_t en_clk_mask;
167 uint32_t en_data_mask;
169 uint32_t y_data_mask;
172 #define AMDGPU_MAX_BIOS_CONNECTOR 16
175 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
176 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
177 #define AMDGPU_PLL_USE_REF_DIV (1 << 2)
178 #define AMDGPU_PLL_LEGACY (1 << 3)
179 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
180 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
181 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
182 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
183 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
184 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
185 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
186 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
187 #define AMDGPU_PLL_USE_POST_DIV (1 << 12)
188 #define AMDGPU_PLL_IS_LCD (1 << 13)
189 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
192 /* reference frequency */
193 uint32_t reference_freq;
196 uint32_t reference_div;
199 /* pll in/out limits */
202 uint32_t pll_out_min;
203 uint32_t pll_out_max;
204 uint32_t lcd_pll_out_min;
205 uint32_t lcd_pll_out_max;
209 uint32_t min_ref_div;
210 uint32_t max_ref_div;
211 uint32_t min_post_div;
212 uint32_t max_post_div;
213 uint32_t min_feedback_div;
214 uint32_t max_feedback_div;
215 uint32_t min_frac_feedback_div;
216 uint32_t max_frac_feedback_div;
218 /* flags for the current clock */
225 struct amdgpu_i2c_chan {
226 struct i2c_adapter adapter;
227 struct drm_device *dev;
228 struct i2c_algo_bit_data bit;
229 struct amdgpu_i2c_bus_rec rec;
230 struct drm_dp_aux aux;
240 bool last_buffer_filled_status;
242 struct amdgpu_audio_pin *pin;
248 struct amdgpu_audio_pin {
259 struct amdgpu_audio {
261 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
265 struct amdgpu_display_funcs {
266 /* display watermarks */
267 void (*bandwidth_update)(struct amdgpu_device *adev);
268 /* get frame count */
269 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
270 /* wait for vblank */
271 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
272 /* set backlight level */
273 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
275 /* get backlight level */
276 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
278 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
279 void (*hpd_set_polarity)(struct amdgpu_device *adev,
280 enum amdgpu_hpd_id hpd);
281 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
283 void (*page_flip)(struct amdgpu_device *adev,
284 int crtc_id, u64 crtc_base, bool async);
285 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
286 u32 *vbl, u32 *position);
287 /* display topology setup */
288 void (*add_encoder)(struct amdgpu_device *adev,
289 uint32_t encoder_enum,
290 uint32_t supported_device,
292 void (*add_connector)(struct amdgpu_device *adev,
293 uint32_t connector_id,
294 uint32_t supported_device,
296 struct amdgpu_i2c_bus_rec *i2c_bus,
297 uint16_t connector_object_id,
298 struct amdgpu_hpd *hpd,
299 struct amdgpu_router *router);
300 /* it is used to enter or exit into free sync mode */
301 int (*notify_freesync)(struct drm_device *dev, void *data,
302 struct drm_file *filp);
303 /* it is used to allow enablement of freesync mode */
304 int (*set_freesync_property)(struct drm_connector *connector,
305 struct drm_property *property,
311 struct amdgpu_framebuffer {
312 struct drm_framebuffer base;
313 struct drm_gem_object *obj;
315 /* caching for later use */
319 struct amdgpu_fbdev {
320 struct drm_fb_helper helper;
321 struct amdgpu_framebuffer rfb;
322 struct list_head fbdev_list;
323 struct amdgpu_device *adev;
326 struct amdgpu_mode_info {
327 struct atom_context *atom_context;
328 struct card_info *atom_card_info;
329 bool mode_config_initialized;
330 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
331 struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
332 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
333 /* DVI-I properties */
334 struct drm_property *coherent_mode_property;
335 /* DAC enable load detect */
336 struct drm_property *load_detect_property;
338 struct drm_property *underscan_property;
339 struct drm_property *underscan_hborder_property;
340 struct drm_property *underscan_vborder_property;
342 struct drm_property *audio_property;
344 struct drm_property *dither_property;
345 /* hardcoded DFP edid from BIOS */
346 struct edid *bios_hardcoded_edid;
347 int bios_hardcoded_edid_size;
349 /* pointer to fbdev info structure */
350 struct amdgpu_fbdev *rfbdev;
353 /* pointer to backlight encoder */
354 struct amdgpu_encoder *bl_encoder;
355 u8 bl_level; /* saved backlight level */
356 struct amdgpu_audio audio; /* audio stuff */
357 int num_crtc; /* number of crtcs */
358 int num_hpd; /* number of hpd pins */
359 int num_dig; /* number of dig blocks */
361 const struct amdgpu_display_funcs *funcs;
362 const enum drm_plane_type *plane_type;
365 #define AMDGPU_MAX_BL_LEVEL 0xFF
367 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
369 struct amdgpu_backlight_privdata {
370 struct amdgpu_encoder *encoder;
376 struct amdgpu_atom_ss {
378 uint16_t percentage_divider;
390 struct drm_crtc base;
394 uint32_t crtc_offset;
395 struct drm_gem_object *cursor_bo;
396 uint64_t cursor_addr;
403 int max_cursor_width;
404 int max_cursor_height;
405 enum amdgpu_rmx_type rmx_type;
410 struct drm_display_mode native_mode;
413 struct amdgpu_flip_work *pflip_works;
414 enum amdgpu_flip_status pflip_status;
415 int deferred_flip_completion;
417 struct amdgpu_atom_ss ss;
421 u32 pll_reference_div;
424 struct drm_encoder *encoder;
425 struct drm_connector *connector;
430 u32 lb_vblank_lead_lines;
431 struct drm_display_mode hw_mode;
432 /* for virtual dce */
433 struct hrtimer vblank_timer;
434 enum amdgpu_interrupt_state vsync_timer_enabled;
437 struct drm_pending_vblank_event *event;
440 struct amdgpu_plane {
441 struct drm_plane base;
442 enum drm_plane_type plane_type;
445 struct amdgpu_encoder_atom_dig {
449 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
452 uint16_t panel_pwr_delay;
455 struct drm_display_mode native_mode;
456 struct backlight_device *bl_dev;
458 uint8_t backlight_level;
460 struct amdgpu_afmt *afmt;
463 struct amdgpu_encoder {
464 struct drm_encoder base;
465 uint32_t encoder_enum;
468 uint32_t active_device;
470 uint32_t pixel_clock;
471 enum amdgpu_rmx_type rmx_type;
472 enum amdgpu_underscan_type underscan_type;
473 uint32_t underscan_hborder;
474 uint32_t underscan_vborder;
475 struct drm_display_mode native_mode;
477 int audio_polling_active;
482 struct amdgpu_connector_atom_dig {
484 u8 dpcd[DP_RECEIVER_CAP_SIZE];
491 struct amdgpu_gpio_rec {
500 enum amdgpu_hpd_id hpd;
502 struct amdgpu_gpio_rec gpio;
505 struct amdgpu_router {
507 struct amdgpu_i2c_bus_rec i2c_info;
512 u8 ddc_mux_control_pin;
517 u8 cd_mux_control_pin;
521 enum amdgpu_connector_audio {
522 AMDGPU_AUDIO_DISABLE = 0,
523 AMDGPU_AUDIO_ENABLE = 1,
524 AMDGPU_AUDIO_AUTO = 2
527 enum amdgpu_connector_dither {
528 AMDGPU_FMT_DITHER_DISABLE = 0,
529 AMDGPU_FMT_DITHER_ENABLE = 1,
532 struct amdgpu_dm_dp_aux {
533 struct drm_dp_aux aux;
534 struct ddc_service *ddc_service;
537 struct amdgpu_i2c_adapter {
538 struct i2c_adapter base;
540 struct ddc_service *ddc_service;
543 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
545 struct amdgpu_connector {
546 struct drm_connector base;
547 uint32_t connector_id;
549 struct amdgpu_i2c_chan *ddc_bus;
550 /* some systems have an hdmi and vga port with a shared ddc line */
553 /* we need to mind the EDID between detect
554 and get modes due to analog/digital/tvencoder */
556 /* number of modes generated from EDID at 'dc_sink' */
558 /* The 'old' sink - before an HPD.
559 * The 'current' sink is in dc_link->sink. */
560 struct dc_sink *dc_sink;
561 struct dc_link *dc_link;
562 struct dc_sink *dc_em_sink;
563 const struct dc_stream *stream;
565 bool dac_load_detect;
566 bool detected_by_load; /* if the connection status was determined by load */
567 uint16_t connector_object_id;
568 struct amdgpu_hpd hpd;
569 struct amdgpu_router router;
570 struct amdgpu_i2c_chan *router_bus;
571 enum amdgpu_connector_audio audio;
572 enum amdgpu_connector_dither dither;
573 unsigned pixelclock_for_modeset;
575 struct drm_dp_mst_topology_mgr mst_mgr;
576 struct amdgpu_dm_dp_aux dm_dp_aux;
577 struct drm_dp_mst_port *port;
578 struct amdgpu_connector *mst_port;
579 struct amdgpu_encoder *mst_encoder;
580 struct semaphore mst_sem;
582 /* TODO see if we can merge with ddc_bus or make a dm_connector */
583 struct amdgpu_i2c_adapter *i2c;
585 /* Monitor range limits */
591 struct mod_freesync_caps caps;
593 struct mutex hpd_lock;
597 /* TODO: start to use this struct and remove same field from base one */
598 struct amdgpu_mst_connector {
599 struct amdgpu_connector base;
601 struct drm_dp_mst_topology_mgr mst_mgr;
602 struct amdgpu_dm_dp_aux dm_dp_aux;
603 struct drm_dp_mst_port *port;
604 struct amdgpu_connector *mst_port;
605 bool is_mst_connector;
606 struct amdgpu_encoder *mst_encoder;
609 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
610 ((em) == ATOM_ENCODER_MODE_DP_MST))
612 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
613 #define DRM_SCANOUTPOS_VALID (1 << 0)
614 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
615 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
616 #define USE_REAL_VBLANKSTART (1 << 30)
617 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
619 void amdgpu_link_encoder_connector(struct drm_device *dev);
621 struct drm_connector *
622 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
623 struct drm_connector *
624 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
625 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
628 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
629 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
631 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
633 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
635 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
636 unsigned int flags, int *vpos, int *hpos,
637 ktime_t *stime, ktime_t *etime,
638 const struct drm_display_mode *mode);
640 int amdgpu_framebuffer_init(struct drm_device *dev,
641 struct amdgpu_framebuffer *rfb,
642 const struct drm_mode_fb_cmd2 *mode_cmd,
643 struct drm_gem_object *obj);
645 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
647 void amdgpu_enc_destroy(struct drm_encoder *encoder);
648 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
649 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
650 const struct drm_display_mode *mode,
651 struct drm_display_mode *adjusted_mode);
652 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
653 struct drm_display_mode *adjusted_mode);
654 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
657 int amdgpu_fbdev_init(struct amdgpu_device *adev);
658 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
659 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
660 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
661 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
663 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
665 /* amdgpu_display.c */
666 void amdgpu_print_display_setup(struct drm_device *dev);
667 int amdgpu_modeset_create_props(struct amdgpu_device *adev);
668 int amdgpu_crtc_set_config(struct drm_mode_set *set,
669 struct drm_modeset_acquire_ctx *ctx);
670 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
671 struct drm_framebuffer *fb,
672 struct drm_pending_vblank_event *event,
673 uint32_t page_flip_flags, uint32_t target,
674 struct drm_modeset_acquire_ctx *ctx);
675 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;