2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_IRQ_H__
25 #define __AMDGPU_IRQ_H__
27 #include <linux/irqdomain.h>
28 #include "amdgpu_ih.h"
30 #define AMDGPU_MAX_IRQ_SRC_ID 0x100
33 struct amdgpu_iv_entry;
35 enum amdgpu_interrupt_state {
36 AMDGPU_IRQ_STATE_DISABLE,
37 AMDGPU_IRQ_STATE_ENABLE,
40 struct amdgpu_irq_src {
42 atomic_t *enabled_types;
43 const struct amdgpu_irq_src_funcs *funcs;
47 /* provided by interrupt generating IP blocks */
48 struct amdgpu_irq_src_funcs {
49 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
50 unsigned type, enum amdgpu_interrupt_state state);
52 int (*process)(struct amdgpu_device *adev,
53 struct amdgpu_irq_src *source,
54 struct amdgpu_iv_entry *entry);
60 /* interrupt sources */
61 struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID];
64 bool msi_enabled; /* msi enabled */
67 struct amdgpu_ih_ring ih;
68 const struct amdgpu_ih_funcs *ih_funcs;
71 struct irq_domain *domain; /* GPU irq controller domain */
72 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
73 uint32_t srbm_soft_reset;
76 void amdgpu_irq_preinstall(struct drm_device *dev);
77 int amdgpu_irq_postinstall(struct drm_device *dev);
78 void amdgpu_irq_uninstall(struct drm_device *dev);
79 irqreturn_t amdgpu_irq_handler(int irq, void *arg);
81 int amdgpu_irq_init(struct amdgpu_device *adev);
82 void amdgpu_irq_fini(struct amdgpu_device *adev);
83 int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
84 struct amdgpu_irq_src *source);
85 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
86 struct amdgpu_iv_entry *entry);
87 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
89 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
91 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
93 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
95 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
97 int amdgpu_irq_add_domain(struct amdgpu_device *adev);
98 void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
99 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);