2 * Copyright 2017 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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23 #include "amdgpu_ids.h"
25 #include <linux/idr.h>
26 #include <linux/dma-fence-array.h>
30 #include "amdgpu_trace.h"
35 * PASIDs are global address space identifiers that can be shared
36 * between the GPU, an IOMMU and the driver. VMs on different devices
37 * may use the same PASID if they share the same address
38 * space. Therefore PASIDs are allocated using a global IDA. VMs are
39 * looked up from the PASID per amdgpu_device.
41 static DEFINE_IDA(amdgpu_pasid_ida);
44 * amdgpu_pasid_alloc - Allocate a PASID
45 * @bits: Maximum width of the PASID in bits, must be at least 1
47 * Allocates a PASID of the given width while keeping smaller PASIDs
48 * available if possible.
50 * Returns a positive integer on success. Returns %-EINVAL if bits==0.
51 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
52 * memory allocation failure.
54 int amdgpu_pasid_alloc(unsigned int bits)
58 for (bits = min(bits, 31U); bits > 0; bits--) {
59 pasid = ida_simple_get(&amdgpu_pasid_ida,
60 1U << (bits - 1), 1U << bits,
70 * amdgpu_pasid_free - Free a PASID
71 * @pasid: PASID to free
73 void amdgpu_pasid_free(unsigned int pasid)
75 ida_simple_remove(&amdgpu_pasid_ida, pasid);
81 * VMIDs are a per VMHUB identifier for page tables handling.
85 * amdgpu_vmid_had_gpu_reset - check if reset occured since last use
87 * @adev: amdgpu_device pointer
90 * Check if GPU reset occured since last use of the VMID.
92 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
93 struct amdgpu_vmid *id)
95 return id->current_gpu_reset_count !=
96 atomic_read(&adev->gpu_reset_counter);
99 /* idr_mgr->lock must be held */
100 static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
101 struct amdgpu_ring *ring,
102 struct amdgpu_sync *sync,
103 struct dma_fence *fence,
104 struct amdgpu_job *job)
106 struct amdgpu_device *adev = ring->adev;
107 unsigned vmhub = ring->funcs->vmhub;
108 uint64_t fence_context = adev->fence_context + ring->idx;
109 struct amdgpu_vmid *id = vm->reserved_vmid[vmhub];
110 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
111 struct dma_fence *updates = sync->last_vm_update;
113 struct dma_fence *flushed, *tmp;
114 bool needs_flush = vm->use_cpu_for_update;
116 flushed = id->flushed_updates;
117 if ((amdgpu_vmid_had_gpu_reset(adev, id)) ||
118 (atomic64_read(&id->owner) != vm->client_id) ||
119 (job->vm_pd_addr != id->pd_gpu_addr) ||
120 (updates && (!flushed || updates->context != flushed->context ||
121 dma_fence_is_later(updates, flushed))) ||
122 (!id->last_flush || (id->last_flush->context != fence_context &&
123 !dma_fence_is_signaled(id->last_flush)))) {
125 /* to prevent one context starved by another context */
127 tmp = amdgpu_sync_peek_fence(&id->active, ring);
129 r = amdgpu_sync_fence(adev, sync, tmp, false);
134 /* Good we can use this VMID. Remember this submission as
137 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
141 if (updates && (!flushed || updates->context != flushed->context ||
142 dma_fence_is_later(updates, flushed))) {
143 dma_fence_put(id->flushed_updates);
144 id->flushed_updates = dma_fence_get(updates);
146 id->pd_gpu_addr = job->vm_pd_addr;
147 atomic64_set(&id->owner, vm->client_id);
148 job->vm_needs_flush = needs_flush;
150 dma_fence_put(id->last_flush);
151 id->last_flush = NULL;
153 job->vmid = id - id_mgr->ids;
154 trace_amdgpu_vm_grab_id(vm, ring, job);
160 * amdgpu_vm_grab_id - allocate the next free VMID
162 * @vm: vm to allocate id for
163 * @ring: ring we want to submit job to
164 * @sync: sync object where we add dependencies
165 * @fence: fence protecting ID from reuse
167 * Allocate an id for the vm, adding fences to the sync obj as necessary.
169 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
170 struct amdgpu_sync *sync, struct dma_fence *fence,
171 struct amdgpu_job *job)
173 struct amdgpu_device *adev = ring->adev;
174 unsigned vmhub = ring->funcs->vmhub;
175 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
176 uint64_t fence_context = adev->fence_context + ring->idx;
177 struct dma_fence *updates = sync->last_vm_update;
178 struct amdgpu_vmid *id, *idle;
179 struct dma_fence **fences;
183 mutex_lock(&id_mgr->lock);
184 if (vm->reserved_vmid[vmhub]) {
185 r = amdgpu_vmid_grab_reserved_locked(vm, ring, sync, fence, job);
186 mutex_unlock(&id_mgr->lock);
189 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
191 mutex_unlock(&id_mgr->lock);
194 /* Check if we have an idle VMID */
196 list_for_each_entry(idle, &id_mgr->ids_lru, list) {
197 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
203 /* If we can't find a idle VMID to use, wait till one becomes available */
204 if (&idle->list == &id_mgr->ids_lru) {
205 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
206 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
207 struct dma_fence_array *array;
210 for (j = 0; j < i; ++j)
211 dma_fence_get(fences[j]);
213 array = dma_fence_array_create(i, fences, fence_context,
216 for (j = 0; j < i; ++j)
217 dma_fence_put(fences[j]);
224 r = amdgpu_sync_fence(ring->adev, sync, &array->base, false);
225 dma_fence_put(&array->base);
229 mutex_unlock(&id_mgr->lock);
235 job->vm_needs_flush = vm->use_cpu_for_update;
236 /* Check if we can use a VMID already assigned to this VM */
237 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
238 struct dma_fence *flushed;
239 bool needs_flush = vm->use_cpu_for_update;
241 /* Check all the prerequisites to using this VMID */
242 if (amdgpu_vmid_had_gpu_reset(adev, id))
245 if (atomic64_read(&id->owner) != vm->client_id)
248 if (job->vm_pd_addr != id->pd_gpu_addr)
251 if (!id->last_flush ||
252 (id->last_flush->context != fence_context &&
253 !dma_fence_is_signaled(id->last_flush)))
256 flushed = id->flushed_updates;
257 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
260 /* Concurrent flushes are only possible starting with Vega10 */
261 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
264 /* Good we can use this VMID. Remember this submission as
267 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
271 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
272 dma_fence_put(id->flushed_updates);
273 id->flushed_updates = dma_fence_get(updates);
279 goto no_flush_needed;
283 /* Still no ID to use? Then use the idle one found earlier */
286 /* Remember this submission as user of the VMID */
287 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
291 id->pd_gpu_addr = job->vm_pd_addr;
292 dma_fence_put(id->flushed_updates);
293 id->flushed_updates = dma_fence_get(updates);
294 atomic64_set(&id->owner, vm->client_id);
297 job->vm_needs_flush = true;
298 dma_fence_put(id->last_flush);
299 id->last_flush = NULL;
302 list_move_tail(&id->list, &id_mgr->ids_lru);
304 job->vmid = id - id_mgr->ids;
305 trace_amdgpu_vm_grab_id(vm, ring, job);
308 mutex_unlock(&id_mgr->lock);
312 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
313 struct amdgpu_vm *vm,
316 struct amdgpu_vmid_mgr *id_mgr;
317 struct amdgpu_vmid *idle;
320 id_mgr = &adev->vm_manager.id_mgr[vmhub];
321 mutex_lock(&id_mgr->lock);
322 if (vm->reserved_vmid[vmhub])
324 if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
325 AMDGPU_VM_MAX_RESERVED_VMID) {
326 DRM_ERROR("Over limitation of reserved vmid\n");
327 atomic_dec(&id_mgr->reserved_vmid_num);
331 /* Select the first entry VMID */
332 idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list);
333 list_del_init(&idle->list);
334 vm->reserved_vmid[vmhub] = idle;
335 mutex_unlock(&id_mgr->lock);
339 mutex_unlock(&id_mgr->lock);
343 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
344 struct amdgpu_vm *vm,
347 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
349 mutex_lock(&id_mgr->lock);
350 if (vm->reserved_vmid[vmhub]) {
351 list_add(&vm->reserved_vmid[vmhub]->list,
353 vm->reserved_vmid[vmhub] = NULL;
354 atomic_dec(&id_mgr->reserved_vmid_num);
356 mutex_unlock(&id_mgr->lock);
360 * amdgpu_vmid_reset - reset VMID to zero
362 * @adev: amdgpu device structure
363 * @vmid: vmid number to use
365 * Reset saved GDW, GWS and OA to force switch on next flush.
367 void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
370 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
371 struct amdgpu_vmid *id = &id_mgr->ids[vmid];
373 atomic64_set(&id->owner, 0);
383 * amdgpu_vmid_reset_all - reset VMID to zero
385 * @adev: amdgpu device structure
387 * Reset VMID to force flush on next use
389 void amdgpu_vmid_reset_all(struct amdgpu_device *adev)
393 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
394 struct amdgpu_vmid_mgr *id_mgr =
395 &adev->vm_manager.id_mgr[i];
397 for (j = 1; j < id_mgr->num_ids; ++j)
398 amdgpu_vmid_reset(adev, i, j);
403 * amdgpu_vmid_mgr_init - init the VMID manager
405 * @adev: amdgpu_device pointer
407 * Initialize the VM manager structures
409 void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
413 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
414 struct amdgpu_vmid_mgr *id_mgr =
415 &adev->vm_manager.id_mgr[i];
417 mutex_init(&id_mgr->lock);
418 INIT_LIST_HEAD(&id_mgr->ids_lru);
419 atomic_set(&id_mgr->reserved_vmid_num, 0);
421 /* skip over VMID 0, since it is the system VM */
422 for (j = 1; j < id_mgr->num_ids; ++j) {
423 amdgpu_vmid_reset(adev, i, j);
424 amdgpu_sync_create(&id_mgr->ids[i].active);
425 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
429 adev->vm_manager.fence_context =
430 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
431 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
432 adev->vm_manager.seqno[i] = 0;
436 * amdgpu_vmid_mgr_fini - cleanup VM manager
438 * @adev: amdgpu_device pointer
440 * Cleanup the VM manager and free resources.
442 void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev)
446 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
447 struct amdgpu_vmid_mgr *id_mgr =
448 &adev->vm_manager.id_mgr[i];
450 mutex_destroy(&id_mgr->lock);
451 for (j = 0; j < AMDGPU_NUM_VMID; ++j) {
452 struct amdgpu_vmid *id = &id_mgr->ids[j];
454 amdgpu_sync_free(&id->active);
455 dma_fence_put(id->flushed_updates);
456 dma_fence_put(id->last_flush);