2 * Copyright 2018 Advanced Micro Devices, Inc.
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21 * The above copyright notice and this permission notice (including the
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27 #include <linux/io-64-nonatomic-lo-hi.h>
29 #include <asm/hypervisor.h>
33 #include "amdgpu_gmc.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_xgmi.h"
37 #include <drm/drm_drv.h>
38 #include <drm/ttm/ttm_tt.h>
41 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
43 * @adev: amdgpu_device pointer
45 * Allocate video memory for pdb0 and map it for CPU access
46 * Returns 0 for success, error for failure.
48 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
51 struct amdgpu_bo_param bp;
52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
54 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
56 memset(&bp, 0, sizeof(bp));
57 bp.size = PAGE_ALIGN((npdes + 1) * 8);
58 bp.byte_align = PAGE_SIZE;
59 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
60 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
61 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
62 bp.type = ttm_bo_type_kernel;
64 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
72 goto bo_reserve_failure;
74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
85 amdgpu_bo_unpin(adev->gmc.pdb0_bo);
87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
89 amdgpu_bo_unref(&adev->gmc.pdb0_bo);
94 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
96 * @bo: the BO to get the PDE for
97 * @level: the level in the PD hirarchy
98 * @addr: resulting addr
99 * @flags: resulting flags
101 * Get the address and flags to be used for a PDE (Page Directory Entry).
103 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
104 uint64_t *addr, uint64_t *flags)
106 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
108 switch (bo->tbo.resource->mem_type) {
110 *addr = bo->tbo.ttm->dma_address[0];
113 *addr = amdgpu_bo_gpu_offset(bo);
119 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
120 amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
124 * amdgpu_gmc_pd_addr - return the address of the root directory
126 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
128 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
131 /* TODO: move that into ASIC specific code */
132 if (adev->asic_type >= CHIP_VEGA10) {
133 uint64_t flags = AMDGPU_PTE_VALID;
135 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
138 pd_addr = amdgpu_bo_gpu_offset(bo);
144 * amdgpu_gmc_set_pte_pde - update the page tables using CPU
146 * @adev: amdgpu_device pointer
147 * @cpu_pt_addr: cpu address of the page table
148 * @gpu_page_idx: entry in the page table to update
149 * @addr: dst addr to write into pte/pde
150 * @flags: access flags
152 * Update the page tables using CPU.
154 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
155 uint32_t gpu_page_idx, uint64_t addr,
158 void __iomem *ptr = (void *)cpu_pt_addr;
162 * The following is for PTE only. GART does not have PDEs.
164 value = addr & 0x0000FFFFFFFFF000ULL;
166 writeq(value, ptr + (gpu_page_idx * 8));
172 * amdgpu_gmc_agp_addr - return the address in the AGP address space
174 * @bo: TTM BO which needs the address, must be in GTT domain
176 * Tries to figure out how to access the BO through the AGP aperture. Returns
177 * AMDGPU_BO_INVALID_OFFSET if that is not possible.
179 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
183 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
184 return AMDGPU_BO_INVALID_OFFSET;
186 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
187 return AMDGPU_BO_INVALID_OFFSET;
189 return adev->gmc.agp_start + bo->ttm->dma_address[0];
193 * amdgpu_gmc_vram_location - try to find VRAM location
195 * @adev: amdgpu device structure holding all necessary information
196 * @mc: memory controller structure holding memory information
197 * @base: base address at which to put VRAM
199 * Function will try to place VRAM at base address provided
202 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
205 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;
206 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
208 mc->vram_start = base;
209 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
210 if (limit < mc->real_vram_size)
211 mc->real_vram_size = limit;
213 if (vis_limit && vis_limit < mc->visible_vram_size)
214 mc->visible_vram_size = vis_limit;
216 if (mc->real_vram_size < mc->visible_vram_size)
217 mc->visible_vram_size = mc->real_vram_size;
219 if (mc->xgmi.num_physical_nodes == 0) {
220 mc->fb_start = mc->vram_start;
221 mc->fb_end = mc->vram_end;
223 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
224 mc->mc_vram_size >> 20, mc->vram_start,
225 mc->vram_end, mc->real_vram_size >> 20);
228 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
230 * @adev: amdgpu device structure holding all necessary information
231 * @mc: memory controller structure holding memory information
233 * This function is only used if use GART for FB translation. In such
234 * case, we use sysvm aperture (vmid0 page tables) for both vram
235 * and gart (aka system memory) access.
237 * GPUVM (and our organization of vmid0 page tables) require sysvm
238 * aperture to be placed at a location aligned with 8 times of native
239 * page size. For example, if vm_context0_cntl.page_table_block_size
240 * is 12, then native page size is 8G (2M*2^12), sysvm should start
241 * with a 64G aligned address. For simplicity, we just put sysvm at
242 * address 0. So vram start at address 0 and gart is right after vram.
244 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
246 u64 hive_vram_start = 0;
247 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
248 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
249 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
250 mc->gart_start = hive_vram_end + 1;
251 mc->gart_end = mc->gart_start + mc->gart_size - 1;
252 mc->fb_start = hive_vram_start;
253 mc->fb_end = hive_vram_end;
254 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
255 mc->mc_vram_size >> 20, mc->vram_start,
256 mc->vram_end, mc->real_vram_size >> 20);
257 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
258 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
262 * amdgpu_gmc_gart_location - try to find GART location
264 * @adev: amdgpu device structure holding all necessary information
265 * @mc: memory controller structure holding memory information
267 * Function will place try to place GART before or after VRAM.
268 * If GART size is bigger than space left then we ajust GART size.
269 * Thus function will never fails.
271 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
273 const uint64_t four_gb = 0x100000000ULL;
274 u64 size_af, size_bf;
275 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
276 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
278 /* VCE doesn't like it when BOs cross a 4GB segment, so align
279 * the GART base on a 4GB boundary as well.
281 size_bf = mc->fb_start;
282 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
284 if (mc->gart_size > max(size_bf, size_af)) {
285 dev_warn(adev->dev, "limiting GART\n");
286 mc->gart_size = max(size_bf, size_af);
289 if ((size_bf >= mc->gart_size && size_bf < size_af) ||
290 (size_af < mc->gart_size))
293 mc->gart_start = max_mc_address - mc->gart_size + 1;
295 mc->gart_start &= ~(four_gb - 1);
296 mc->gart_end = mc->gart_start + mc->gart_size - 1;
297 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
298 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
302 * amdgpu_gmc_agp_location - try to find AGP location
303 * @adev: amdgpu device structure holding all necessary information
304 * @mc: memory controller structure holding memory information
306 * Function will place try to find a place for the AGP BAR in the MC address
309 * AGP BAR will be assigned the largest available hole in the address space.
310 * Should be called after VRAM and GART locations are setup.
312 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
314 const uint64_t sixteen_gb = 1ULL << 34;
315 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
316 u64 size_af, size_bf;
318 if (amdgpu_sriov_vf(adev)) {
319 mc->agp_start = 0xffffffffffff;
326 if (mc->fb_start > mc->gart_start) {
327 size_bf = (mc->fb_start & sixteen_gb_mask) -
328 ALIGN(mc->gart_end + 1, sixteen_gb);
329 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
331 size_bf = mc->fb_start & sixteen_gb_mask;
332 size_af = (mc->gart_start & sixteen_gb_mask) -
333 ALIGN(mc->fb_end + 1, sixteen_gb);
336 if (size_bf > size_af) {
337 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
338 mc->agp_size = size_bf;
340 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
341 mc->agp_size = size_af;
344 mc->agp_end = mc->agp_start + mc->agp_size - 1;
345 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
346 mc->agp_size >> 20, mc->agp_start, mc->agp_end);
350 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
352 * @addr: 48 bit physical address, page aligned (36 significant bits)
353 * @pasid: 16 bit process address space identifier
355 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
357 return addr << 4 | pasid;
361 * amdgpu_gmc_filter_faults - filter VM faults
363 * @adev: amdgpu device structure
364 * @ih: interrupt ring that the fault received from
365 * @addr: address of the VM fault
366 * @pasid: PASID of the process causing the fault
367 * @timestamp: timestamp of the fault
370 * True if the fault was filtered and should not be processed further.
371 * False if the fault is a new one and needs to be handled.
373 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
374 struct amdgpu_ih_ring *ih, uint64_t addr,
375 uint16_t pasid, uint64_t timestamp)
377 struct amdgpu_gmc *gmc = &adev->gmc;
378 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
379 struct amdgpu_gmc_fault *fault;
382 /* Stale retry fault if timestamp goes backward */
383 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
386 /* If we don't have space left in the ring buffer return immediately */
387 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
388 AMDGPU_GMC_FAULT_TIMEOUT;
389 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
392 /* Try to find the fault in the hash */
393 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
394 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
395 while (fault->timestamp >= stamp) {
398 if (atomic64_read(&fault->key) == key) {
400 * if we get a fault which is already present in
401 * the fault_ring and the timestamp of
402 * the fault is after the expired timestamp,
403 * then this is a new fault that needs to be added
404 * into the fault ring.
406 if (fault->timestamp_expiry != 0 &&
407 amdgpu_ih_ts_after(fault->timestamp_expiry,
414 tmp = fault->timestamp;
415 fault = &gmc->fault_ring[fault->next];
417 /* Check if the entry was reused */
418 if (fault->timestamp >= tmp)
422 /* Add the fault to the ring */
423 fault = &gmc->fault_ring[gmc->last_fault];
424 atomic64_set(&fault->key, key);
425 fault->timestamp = timestamp;
427 /* And update the hash */
428 fault->next = gmc->fault_hash[hash].idx;
429 gmc->fault_hash[hash].idx = gmc->last_fault++;
434 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
436 * @adev: amdgpu device structure
437 * @addr: address of the VM fault
438 * @pasid: PASID of the process causing the fault
440 * Remove the address from fault filter, then future vm fault on this address
441 * will pass to retry fault handler to recover.
443 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
446 struct amdgpu_gmc *gmc = &adev->gmc;
447 uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
448 struct amdgpu_ih_ring *ih;
449 struct amdgpu_gmc_fault *fault;
455 ih = adev->irq.retry_cam_enabled ? &adev->irq.ih_soft : &adev->irq.ih1;
456 /* Get the WPTR of the last entry in IH ring */
457 last_wptr = amdgpu_ih_get_wptr(adev, ih);
458 /* Order wptr with ring data. */
460 /* Get the timetamp of the last entry in IH ring */
461 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1);
463 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
464 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
466 if (atomic64_read(&fault->key) == key) {
468 * Update the timestamp when this fault
471 fault->timestamp_expiry = last_ts;
475 tmp = fault->timestamp;
476 fault = &gmc->fault_ring[fault->next];
477 } while (fault->timestamp < tmp);
480 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev)
485 r = amdgpu_umc_ras_sw_init(adev);
489 /* mmhub ras block */
490 r = amdgpu_mmhub_ras_sw_init(adev);
495 r = amdgpu_hdp_ras_sw_init(adev);
499 /* mca.x ras block */
500 r = amdgpu_mca_mp0_ras_sw_init(adev);
504 r = amdgpu_mca_mp1_ras_sw_init(adev);
508 r = amdgpu_mca_mpio_ras_sw_init(adev);
513 r = amdgpu_xgmi_ras_sw_init(adev);
520 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
525 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
531 * The latest engine allocation on gfx9/10 is:
532 * Engine 2, 3: firmware
533 * Engine 0, 1, 4~16: amdgpu ring,
534 * subject to change when ring number changes
535 * Engine 17: Gart flushes
537 #define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3
539 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
541 struct amdgpu_ring *ring;
542 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0};
544 unsigned vmhub, inv_eng;
546 /* init the vm inv eng for all vmhubs */
547 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
548 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP;
549 /* reserve engine 5 for firmware */
550 if (adev->enable_mes)
551 vm_inv_engs[i] &= ~(1 << 5);
554 for (i = 0; i < adev->num_rings; ++i) {
555 ring = adev->rings[i];
556 vmhub = ring->vm_hub;
558 if (ring == &adev->mes.ring)
561 inv_eng = ffs(vm_inv_engs[vmhub]);
563 dev_err(adev->dev, "no VM inv eng for ring %s\n",
568 ring->vm_inv_eng = inv_eng - 1;
569 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
571 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
572 ring->name, ring->vm_inv_eng, ring->vm_hub);
579 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
580 * @adev: amdgpu_device pointer
582 * Check and set if an the device @adev supports Trusted Memory
585 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
587 switch (adev->ip_versions[GC_HWIP][0]) {
589 case IP_VERSION(9, 2, 2):
590 case IP_VERSION(9, 1, 0):
591 /* RENOIR looks like RAVEN */
592 case IP_VERSION(9, 3, 0):
594 case IP_VERSION(10, 3, 7):
595 if (amdgpu_tmz == 0) {
596 adev->gmc.tmz_enabled = false;
598 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
600 adev->gmc.tmz_enabled = true;
602 "Trusted Memory Zone (TMZ) feature enabled\n");
605 case IP_VERSION(10, 1, 10):
606 case IP_VERSION(10, 1, 1):
607 case IP_VERSION(10, 1, 2):
608 case IP_VERSION(10, 1, 3):
609 case IP_VERSION(10, 3, 0):
610 case IP_VERSION(10, 3, 2):
611 case IP_VERSION(10, 3, 4):
612 case IP_VERSION(10, 3, 5):
613 case IP_VERSION(10, 3, 6):
615 case IP_VERSION(10, 3, 1):
617 case IP_VERSION(10, 3, 3):
618 case IP_VERSION(11, 0, 1):
619 case IP_VERSION(11, 0, 4):
620 /* Don't enable it by default yet.
622 if (amdgpu_tmz < 1) {
623 adev->gmc.tmz_enabled = false;
625 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
627 adev->gmc.tmz_enabled = true;
629 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
633 adev->gmc.tmz_enabled = false;
635 "Trusted Memory Zone (TMZ) feature not supported\n");
641 * amdgpu_gmc_noretry_set -- set per asic noretry defaults
642 * @adev: amdgpu_device pointer
644 * Set a per asic default for the no-retry parameter.
647 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
649 struct amdgpu_gmc *gmc = &adev->gmc;
650 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
651 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
652 gc_ver == IP_VERSION(9, 3, 0) ||
653 gc_ver == IP_VERSION(9, 4, 0) ||
654 gc_ver == IP_VERSION(9, 4, 1) ||
655 gc_ver == IP_VERSION(9, 4, 2) ||
656 gc_ver == IP_VERSION(9, 4, 3) ||
657 gc_ver >= IP_VERSION(10, 3, 0));
659 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
662 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
665 struct amdgpu_vmhub *hub;
668 hub = &adev->vmhub[hub_type];
669 for (i = 0; i < 16; i++) {
670 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
672 tmp = (hub_type == AMDGPU_GFXHUB(0)) ?
673 RREG32_SOC15_IP(GC, reg) :
674 RREG32_SOC15_IP(MMHUB, reg);
677 tmp |= hub->vm_cntx_cntl_vm_fault;
679 tmp &= ~hub->vm_cntx_cntl_vm_fault;
681 (hub_type == AMDGPU_GFXHUB(0)) ?
682 WREG32_SOC15_IP(GC, reg, tmp) :
683 WREG32_SOC15_IP(MMHUB, reg, tmp);
687 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
692 * Some ASICs need to reserve a region of video memory to avoid access
695 adev->mman.stolen_reserved_offset = 0;
696 adev->mman.stolen_reserved_size = 0;
700 * Currently there is a bug where some memory client outside
701 * of the driver writes to first 8M of VRAM on S3 resume,
702 * this overrides GART which by default gets placed in first 8M and
703 * causes VM_FAULTS once GTT is accessed.
704 * Keep the stolen memory reservation until the while this is not solved.
706 switch (adev->asic_type) {
708 adev->mman.keep_stolen_vga_memory = true;
710 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.
713 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {
714 adev->mman.stolen_reserved_offset = 0x500000;
715 adev->mman.stolen_reserved_size = 0x200000;
721 adev->mman.keep_stolen_vga_memory = true;
723 case CHIP_YELLOW_CARP:
724 if (amdgpu_discovery == 0) {
725 adev->mman.stolen_reserved_offset = 0x1ffb0000;
726 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
730 adev->mman.keep_stolen_vga_memory = false;
734 if (amdgpu_sriov_vf(adev) ||
735 !amdgpu_device_has_display_hardware(adev)) {
738 size = amdgpu_gmc_get_vbios_fb_size(adev);
740 if (adev->mman.keep_stolen_vga_memory)
741 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
744 /* set to 0 if the pre-OS buffer uses up most of vram */
745 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
748 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
749 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
750 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
752 adev->mman.stolen_vga_size = size;
753 adev->mman.stolen_extended_size = 0;
758 * amdgpu_gmc_init_pdb0 - initialize PDB0
760 * @adev: amdgpu_device pointer
762 * This function is only used when GART page table is used
763 * for FB address translatioin. In such a case, we construct
764 * a 2-level system VM page table: PDB0->PTB, to cover both
765 * VRAM of the hive and system memory.
767 * PDB0 is static, initialized once on driver initialization.
768 * The first n entries of PDB0 are used as PTE by setting
769 * P bit to 1, pointing to VRAM. The n+1'th entry points
770 * to a big PTB covering system memory.
773 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
776 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
777 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
779 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
780 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
781 u64 vram_addr = adev->vm_manager.vram_base_offset -
782 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
783 u64 vram_end = vram_addr + vram_size;
784 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
787 if (!drm_dev_enter(adev_to_drm(adev), &idx))
790 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
791 flags |= AMDGPU_PTE_WRITEABLE;
792 flags |= AMDGPU_PTE_SNOOPED;
793 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
794 flags |= AMDGPU_PDE_PTE;
796 /* The first n PDE0 entries are used as PTE,
799 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
800 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
802 /* The n+1'th PDE0 entry points to a huge
803 * PTB who has more than 512 entries each
804 * pointing to a 4K system page
806 flags = AMDGPU_PTE_VALID;
807 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
808 /* Requires gart_ptb_gpu_pa to be 4K aligned */
809 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
814 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
817 * @adev: amdgpu_device pointer
818 * @mc_addr: MC address of buffer
820 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
822 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
826 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
829 * @adev: amdgpu_device pointer
830 * @bo: amdgpu buffer object
832 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
834 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
838 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
841 * @adev: amdgpu_device pointer
842 * @bo: amdgpu buffer object
844 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
846 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
849 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
851 struct amdgpu_bo *vram_bo = NULL;
852 uint64_t vram_gpu = 0;
853 void *vram_ptr = NULL;
855 int ret, size = 0x100000;
858 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
859 AMDGPU_GEM_DOMAIN_VRAM,
866 memset(vram_ptr, 0x86, size);
867 memset(cptr, 0x86, 10);
870 * Check the start, the mid, and the end of the memory if the content of
871 * each byte is the pattern "0x86". If yes, we suppose the vram bo is
874 * Note: If check the each byte of whole 1M bo, it will cost too many
875 * seconds, so here, we just pick up three parts for emulation.
877 ret = memcmp(vram_ptr, cptr, 10);
881 ret = memcmp(vram_ptr + (size / 2), cptr, 10);
885 ret = memcmp(vram_ptr + size - 10, cptr, 10);
889 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,