2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #include "amdgpu_gfx.h"
30 * GPU scratch registers helpers function.
33 * amdgpu_gfx_scratch_get - Allocate a scratch register
35 * @adev: amdgpu_device pointer
36 * @reg: scratch register mmio offset
38 * Allocate a CP scratch register for use by the driver (all asics).
39 * Returns 0 on success or -EINVAL on failure.
41 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
45 i = ffs(adev->gfx.scratch.free_mask);
46 if (i != 0 && i <= adev->gfx.scratch.num_reg) {
48 adev->gfx.scratch.free_mask &= ~(1u << i);
49 *reg = adev->gfx.scratch.reg_base + i;
56 * amdgpu_gfx_scratch_free - Free a scratch register
58 * @adev: amdgpu_device pointer
59 * @reg: scratch register mmio offset
61 * Free a CP scratch register allocated for use by the driver (all asics)
63 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
65 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
69 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
71 * @mask: array in which the per-shader array disable masks will be stored
72 * @max_se: number of SEs
73 * @max_sh: number of SHs
75 * The bitmask of CUs to be disabled in the shader array determined by se and
76 * sh is stored in mask[se * max_sh + sh].
78 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
83 memset(mask, 0, sizeof(*mask) * max_se * max_sh);
85 if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
88 p = amdgpu_disable_cu;
91 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
93 DRM_ERROR("amdgpu: could not parse disable_cu\n");
97 if (se < max_se && sh < max_sh && cu < 16) {
98 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
99 mask[se * max_sh + sh] |= 1u << cu;
101 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
105 next = strchr(p, ',');