2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
39 amdgpu_mn_unregister(robj);
40 amdgpu_bo_unref(&robj);
44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
45 int alignment, u32 initial_domain,
46 u64 flags, bool kernel,
47 struct reservation_object *resv,
48 struct drm_gem_object **obj)
54 /* At least align on page size */
55 if (alignment < PAGE_SIZE) {
56 alignment = PAGE_SIZE;
60 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
61 flags, NULL, resv, 0, &bo);
63 if (r != -ERESTARTSYS) {
64 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
65 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
69 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
70 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
73 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
74 size, initial_domain, alignment, r);
83 void amdgpu_gem_force_release(struct amdgpu_device *adev)
85 struct drm_device *ddev = adev->ddev;
86 struct drm_file *file;
88 mutex_lock(&ddev->filelist_mutex);
90 list_for_each_entry(file, &ddev->filelist, lhead) {
91 struct drm_gem_object *gobj;
94 WARN_ONCE(1, "Still active user space clients!\n");
95 spin_lock(&file->table_lock);
96 idr_for_each_entry(&file->object_idr, gobj, handle) {
97 WARN_ONCE(1, "And also active allocations!\n");
98 drm_gem_object_put_unlocked(gobj);
100 idr_destroy(&file->object_idr);
101 spin_unlock(&file->table_lock);
104 mutex_unlock(&ddev->filelist_mutex);
108 * Call from drm_gem_handle_create which appear in both new and open ioctl
111 int amdgpu_gem_object_open(struct drm_gem_object *obj,
112 struct drm_file *file_priv)
114 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
115 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
116 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
117 struct amdgpu_vm *vm = &fpriv->vm;
118 struct amdgpu_bo_va *bo_va;
119 struct mm_struct *mm;
122 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
123 if (mm && mm != current->mm)
126 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
127 abo->tbo.resv != vm->root.base.bo->tbo.resv)
130 r = amdgpu_bo_reserve(abo, false);
134 bo_va = amdgpu_vm_bo_find(vm, abo);
136 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
140 amdgpu_bo_unreserve(abo);
144 void amdgpu_gem_object_close(struct drm_gem_object *obj,
145 struct drm_file *file_priv)
147 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
148 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
149 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
150 struct amdgpu_vm *vm = &fpriv->vm;
152 struct amdgpu_bo_list_entry vm_pd;
153 struct list_head list, duplicates;
154 struct ttm_validate_buffer tv;
155 struct ww_acquire_ctx ticket;
156 struct amdgpu_bo_va *bo_va;
159 INIT_LIST_HEAD(&list);
160 INIT_LIST_HEAD(&duplicates);
164 list_add(&tv.head, &list);
166 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
168 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
170 dev_err(adev->dev, "leaking bo va because "
171 "we fail to reserve bo (%d)\n", r);
174 bo_va = amdgpu_vm_bo_find(vm, bo);
175 if (bo_va && --bo_va->ref_count == 0) {
176 amdgpu_vm_bo_rmv(adev, bo_va);
178 if (amdgpu_vm_ready(vm)) {
179 struct dma_fence *fence = NULL;
181 r = amdgpu_vm_clear_freed(adev, vm, &fence);
183 dev_err(adev->dev, "failed to clear page "
184 "tables on GEM object close (%d)\n", r);
188 amdgpu_bo_fence(bo, fence, true);
189 dma_fence_put(fence);
193 ttm_eu_backoff_reservation(&ticket, &list);
199 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
200 struct drm_file *filp)
202 struct amdgpu_device *adev = dev->dev_private;
203 struct amdgpu_fpriv *fpriv = filp->driver_priv;
204 struct amdgpu_vm *vm = &fpriv->vm;
205 union drm_amdgpu_gem_create *args = data;
206 uint64_t flags = args->in.domain_flags;
207 uint64_t size = args->in.bo_size;
208 struct reservation_object *resv = NULL;
209 struct drm_gem_object *gobj;
213 /* reject invalid gem flags */
214 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
215 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
216 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
217 AMDGPU_GEM_CREATE_VRAM_CLEARED |
218 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
219 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
223 /* reject invalid gem domains */
224 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
225 AMDGPU_GEM_DOMAIN_GTT |
226 AMDGPU_GEM_DOMAIN_VRAM |
227 AMDGPU_GEM_DOMAIN_GDS |
228 AMDGPU_GEM_DOMAIN_GWS |
229 AMDGPU_GEM_DOMAIN_OA))
232 /* create a gem object to contain this object in */
233 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
234 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
235 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
236 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
237 size = size << AMDGPU_GDS_SHIFT;
238 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
239 size = size << AMDGPU_GWS_SHIFT;
240 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
241 size = size << AMDGPU_OA_SHIFT;
245 size = roundup(size, PAGE_SIZE);
247 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
248 r = amdgpu_bo_reserve(vm->root.base.bo, false);
252 resv = vm->root.base.bo->tbo.resv;
255 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
256 (u32)(0xffffffff & args->in.domains),
257 flags, false, resv, &gobj);
258 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
260 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
262 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
264 amdgpu_bo_unreserve(vm->root.base.bo);
269 r = drm_gem_handle_create(filp, gobj, &handle);
270 /* drop reference from allocate - handle holds it now */
271 drm_gem_object_put_unlocked(gobj);
275 memset(args, 0, sizeof(*args));
276 args->out.handle = handle;
280 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
281 struct drm_file *filp)
283 struct ttm_operation_ctx ctx = { true, false };
284 struct amdgpu_device *adev = dev->dev_private;
285 struct drm_amdgpu_gem_userptr *args = data;
286 struct drm_gem_object *gobj;
287 struct amdgpu_bo *bo;
291 if (offset_in_page(args->addr | args->size))
294 /* reject unknown flag values */
295 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
296 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
297 AMDGPU_GEM_USERPTR_REGISTER))
300 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
301 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
303 /* if we want to write to it we must install a MMU notifier */
307 /* create a gem object to contain this object in */
308 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
313 bo = gem_to_amdgpu_bo(gobj);
314 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
315 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
316 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
320 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
321 r = amdgpu_mn_register(bo, args->addr);
326 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
327 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
332 r = amdgpu_bo_reserve(bo, true);
336 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
337 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
338 amdgpu_bo_unreserve(bo);
343 r = drm_gem_handle_create(filp, gobj, &handle);
344 /* drop reference from allocate - handle holds it now */
345 drm_gem_object_put_unlocked(gobj);
349 args->handle = handle;
353 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
356 drm_gem_object_put_unlocked(gobj);
361 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
362 struct drm_device *dev,
363 uint32_t handle, uint64_t *offset_p)
365 struct drm_gem_object *gobj;
366 struct amdgpu_bo *robj;
368 gobj = drm_gem_object_lookup(filp, handle);
372 robj = gem_to_amdgpu_bo(gobj);
373 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
374 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
375 drm_gem_object_put_unlocked(gobj);
378 *offset_p = amdgpu_bo_mmap_offset(robj);
379 drm_gem_object_put_unlocked(gobj);
383 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
384 struct drm_file *filp)
386 union drm_amdgpu_gem_mmap *args = data;
387 uint32_t handle = args->in.handle;
388 memset(args, 0, sizeof(*args));
389 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
393 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
395 * @timeout_ns: timeout in ns
397 * Calculate the timeout in jiffies from an absolute timeout in ns.
399 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
401 unsigned long timeout_jiffies;
404 /* clamp timeout if it's to large */
405 if (((int64_t)timeout_ns) < 0)
406 return MAX_SCHEDULE_TIMEOUT;
408 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
409 if (ktime_to_ns(timeout) < 0)
412 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
413 /* clamp timeout to avoid unsigned-> signed overflow */
414 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
415 return MAX_SCHEDULE_TIMEOUT - 1;
417 return timeout_jiffies;
420 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
421 struct drm_file *filp)
423 union drm_amdgpu_gem_wait_idle *args = data;
424 struct drm_gem_object *gobj;
425 struct amdgpu_bo *robj;
426 uint32_t handle = args->in.handle;
427 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
431 gobj = drm_gem_object_lookup(filp, handle);
435 robj = gem_to_amdgpu_bo(gobj);
436 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
439 /* ret == 0 means not signaled,
440 * ret > 0 means signaled
441 * ret < 0 means interrupted before timeout
444 memset(args, 0, sizeof(*args));
445 args->out.status = (ret == 0);
449 drm_gem_object_put_unlocked(gobj);
453 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
454 struct drm_file *filp)
456 struct drm_amdgpu_gem_metadata *args = data;
457 struct drm_gem_object *gobj;
458 struct amdgpu_bo *robj;
461 DRM_DEBUG("%d \n", args->handle);
462 gobj = drm_gem_object_lookup(filp, args->handle);
465 robj = gem_to_amdgpu_bo(gobj);
467 r = amdgpu_bo_reserve(robj, false);
468 if (unlikely(r != 0))
471 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
472 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
473 r = amdgpu_bo_get_metadata(robj, args->data.data,
474 sizeof(args->data.data),
475 &args->data.data_size_bytes,
477 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
478 if (args->data.data_size_bytes > sizeof(args->data.data)) {
482 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
484 r = amdgpu_bo_set_metadata(robj, args->data.data,
485 args->data.data_size_bytes,
490 amdgpu_bo_unreserve(robj);
492 drm_gem_object_put_unlocked(gobj);
497 * amdgpu_gem_va_update_vm -update the bo_va in its VM
499 * @adev: amdgpu_device pointer
501 * @bo_va: bo_va to update
502 * @list: validation list
503 * @operation: map, unmap or clear
505 * Update the bo_va directly after setting its address. Errors are not
506 * vital here, so they are not reported back to userspace.
508 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
509 struct amdgpu_vm *vm,
510 struct amdgpu_bo_va *bo_va,
511 struct list_head *list,
516 if (!amdgpu_vm_ready(vm))
519 r = amdgpu_vm_clear_freed(adev, vm, NULL);
523 if (operation == AMDGPU_VA_OP_MAP ||
524 operation == AMDGPU_VA_OP_REPLACE)
525 r = amdgpu_vm_bo_update(adev, bo_va, false);
527 r = amdgpu_vm_update_directories(adev, vm);
532 if (r && r != -ERESTARTSYS)
533 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
536 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
537 struct drm_file *filp)
539 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
540 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
541 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
542 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
545 struct drm_amdgpu_gem_va *args = data;
546 struct drm_gem_object *gobj;
547 struct amdgpu_device *adev = dev->dev_private;
548 struct amdgpu_fpriv *fpriv = filp->driver_priv;
549 struct amdgpu_bo *abo;
550 struct amdgpu_bo_va *bo_va;
551 struct amdgpu_bo_list_entry vm_pd;
552 struct ttm_validate_buffer tv;
553 struct ww_acquire_ctx ticket;
554 struct list_head list, duplicates;
558 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
559 dev_dbg(&dev->pdev->dev,
560 "va_address 0x%LX is in reserved area 0x%LX\n",
561 args->va_address, AMDGPU_VA_RESERVED_SIZE);
565 if (args->va_address >= AMDGPU_VA_HOLE_START &&
566 args->va_address < AMDGPU_VA_HOLE_END) {
567 dev_dbg(&dev->pdev->dev,
568 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
569 args->va_address, AMDGPU_VA_HOLE_START,
574 args->va_address &= AMDGPU_VA_HOLE_MASK;
576 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
577 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
582 switch (args->operation) {
583 case AMDGPU_VA_OP_MAP:
584 case AMDGPU_VA_OP_UNMAP:
585 case AMDGPU_VA_OP_CLEAR:
586 case AMDGPU_VA_OP_REPLACE:
589 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
594 INIT_LIST_HEAD(&list);
595 INIT_LIST_HEAD(&duplicates);
596 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
597 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
598 gobj = drm_gem_object_lookup(filp, args->handle);
601 abo = gem_to_amdgpu_bo(gobj);
604 list_add(&tv.head, &list);
610 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
612 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
617 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
622 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
623 bo_va = fpriv->prt_va;
628 switch (args->operation) {
629 case AMDGPU_VA_OP_MAP:
630 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
635 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
636 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
637 args->offset_in_bo, args->map_size,
640 case AMDGPU_VA_OP_UNMAP:
641 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
644 case AMDGPU_VA_OP_CLEAR:
645 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
649 case AMDGPU_VA_OP_REPLACE:
650 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
655 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
656 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
657 args->offset_in_bo, args->map_size,
663 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
664 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
668 ttm_eu_backoff_reservation(&ticket, &list);
671 drm_gem_object_put_unlocked(gobj);
675 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *filp)
678 struct amdgpu_device *adev = dev->dev_private;
679 struct drm_amdgpu_gem_op *args = data;
680 struct drm_gem_object *gobj;
681 struct amdgpu_bo *robj;
684 gobj = drm_gem_object_lookup(filp, args->handle);
688 robj = gem_to_amdgpu_bo(gobj);
690 r = amdgpu_bo_reserve(robj, false);
695 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
696 struct drm_amdgpu_gem_create_in info;
697 void __user *out = u64_to_user_ptr(args->value);
699 info.bo_size = robj->gem_base.size;
700 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
701 info.domains = robj->preferred_domains;
702 info.domain_flags = robj->flags;
703 amdgpu_bo_unreserve(robj);
704 if (copy_to_user(out, &info, sizeof(info)))
708 case AMDGPU_GEM_OP_SET_PLACEMENT:
709 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
711 amdgpu_bo_unreserve(robj);
714 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
716 amdgpu_bo_unreserve(robj);
719 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
720 AMDGPU_GEM_DOMAIN_GTT |
721 AMDGPU_GEM_DOMAIN_CPU);
722 robj->allowed_domains = robj->preferred_domains;
723 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
724 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
726 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
727 amdgpu_vm_bo_invalidate(adev, robj, true);
729 amdgpu_bo_unreserve(robj);
732 amdgpu_bo_unreserve(robj);
737 drm_gem_object_put_unlocked(gobj);
741 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
742 struct drm_device *dev,
743 struct drm_mode_create_dumb *args)
745 struct amdgpu_device *adev = dev->dev_private;
746 struct drm_gem_object *gobj;
750 args->pitch = amdgpu_align_pitch(adev, args->width,
751 DIV_ROUND_UP(args->bpp, 8), 0);
752 args->size = (u64)args->pitch * args->height;
753 args->size = ALIGN(args->size, PAGE_SIZE);
755 r = amdgpu_gem_object_create(adev, args->size, 0,
756 AMDGPU_GEM_DOMAIN_VRAM,
757 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
762 r = drm_gem_handle_create(file_priv, gobj, &handle);
763 /* drop reference from allocate - handle holds it now */
764 drm_gem_object_put_unlocked(gobj);
768 args->handle = handle;
772 #if defined(CONFIG_DEBUG_FS)
773 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
775 struct drm_gem_object *gobj = ptr;
776 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
777 struct seq_file *m = data;
780 const char *placement;
784 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
786 case AMDGPU_GEM_DOMAIN_VRAM:
789 case AMDGPU_GEM_DOMAIN_GTT:
792 case AMDGPU_GEM_DOMAIN_CPU:
797 seq_printf(m, "\t0x%08x: %12ld byte %s",
798 id, amdgpu_bo_size(bo), placement);
800 offset = READ_ONCE(bo->tbo.mem.start);
801 if (offset != AMDGPU_BO_INVALID_OFFSET)
802 seq_printf(m, " @ 0x%010Lx", offset);
804 pin_count = READ_ONCE(bo->pin_count);
806 seq_printf(m, " pin count %d", pin_count);
812 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
814 struct drm_info_node *node = (struct drm_info_node *)m->private;
815 struct drm_device *dev = node->minor->dev;
816 struct drm_file *file;
819 r = mutex_lock_interruptible(&dev->filelist_mutex);
823 list_for_each_entry(file, &dev->filelist, lhead) {
824 struct task_struct *task;
827 * Although we have a valid reference on file->pid, that does
828 * not guarantee that the task_struct who called get_pid() is
829 * still alive (e.g. get_pid(current) => fork() => exit()).
830 * Therefore, we need to protect this ->comm access using RCU.
833 task = pid_task(file->pid, PIDTYPE_PID);
834 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
835 task ? task->comm : "<unknown>");
838 spin_lock(&file->table_lock);
839 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
840 spin_unlock(&file->table_lock);
843 mutex_unlock(&dev->filelist_mutex);
847 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
848 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
852 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
854 #if defined(CONFIG_DEBUG_FS)
855 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);