2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #include <drm/amdgpu_drm.h>
27 #include <drm/drm_gem.h>
28 #include "amdgpu_drv.h"
30 #include <drm/drm_pciids.h>
31 #include <linux/console.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/vga_switcheroo.h>
35 #include <drm/drm_crtc_helper.h>
38 #include "amdgpu_irq.h"
39 #include "amdgpu_gem.h"
41 #include "amdgpu_amdkfd.h"
46 * - 3.0.0 - initial driver
47 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
48 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
50 * - 3.3.0 - Add VM support for UVD on supported hardware.
51 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
52 * - 3.5.0 - Add support for new UVD_NO_OP register.
53 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
54 * - 3.7.0 - Add support for VCE clock list packet
55 * - 3.8.0 - Add support raster config init in the kernel
56 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
57 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
58 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
59 * - 3.12.0 - Add query for double offchip LDS buffers
60 * - 3.13.0 - Add PRT support
61 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
62 * - 3.15.0 - Export more gpu info for gfx9
63 * - 3.16.0 - Add reserved vmid support
64 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
65 * - 3.18.0 - Export gpu always on cu bitmap
66 * - 3.19.0 - Add support for UVD MJPEG decode
67 * - 3.20.0 - Add support for local BOs
68 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
69 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
70 * - 3.23.0 - Add query for VRAM lost counter
71 * - 3.24.0 - Add high priority compute support for gfx9
72 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
73 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
74 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
76 #define KMS_DRIVER_MAJOR 3
77 #define KMS_DRIVER_MINOR 27
78 #define KMS_DRIVER_PATCHLEVEL 0
80 int amdgpu_vram_limit = 0;
81 int amdgpu_vis_vram_limit = 0;
82 int amdgpu_gart_size = -1; /* auto */
83 int amdgpu_gtt_size = -1; /* auto */
84 int amdgpu_moverate = -1; /* auto */
85 int amdgpu_benchmarking = 0;
86 int amdgpu_testing = 0;
87 int amdgpu_audio = -1;
88 int amdgpu_disp_priority = 0;
89 int amdgpu_hw_i2c = 0;
90 int amdgpu_pcie_gen2 = -1;
92 int amdgpu_lockup_timeout = 10000;
94 int amdgpu_fw_load_type = -1;
96 int amdgpu_runtime_pm = -1;
97 uint amdgpu_ip_block_mask = 0xffffffff;
99 int amdgpu_deep_color = 0;
100 int amdgpu_vm_size = -1;
101 int amdgpu_vm_fragment_size = -1;
102 int amdgpu_vm_block_size = -1;
103 int amdgpu_vm_fault_stop = 0;
104 int amdgpu_vm_debug = 0;
105 int amdgpu_vram_page_split = 512;
106 int amdgpu_vm_update_mode = -1;
107 int amdgpu_exp_hw_support = 0;
109 int amdgpu_sched_jobs = 32;
110 int amdgpu_sched_hw_submission = 2;
111 uint amdgpu_pcie_gen_cap = 0;
112 uint amdgpu_pcie_lane_cap = 0;
113 uint amdgpu_cg_mask = 0xffffffff;
114 uint amdgpu_pg_mask = 0xffffffff;
115 uint amdgpu_sdma_phase_quantum = 32;
116 char *amdgpu_disable_cu = NULL;
117 char *amdgpu_virtual_display = NULL;
118 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
119 uint amdgpu_pp_feature_mask = 0xfffd3fff;
121 int amdgpu_prim_buf_per_se = 0;
122 int amdgpu_pos_buf_per_se = 0;
123 int amdgpu_cntl_sb_buf_per_se = 0;
124 int amdgpu_param_buf_per_se = 0;
125 int amdgpu_job_hang_limit = 0;
126 int amdgpu_lbpw = -1;
127 int amdgpu_compute_multipipe = -1;
128 int amdgpu_gpu_recovery = -1; /* auto */
129 int amdgpu_emu_mode = 0;
130 uint amdgpu_smu_memory_pool_size = 0;
132 int sched_policy = KFD_SCHED_POLICY_HWS;
133 int hws_max_conc_proc = 8;
135 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
140 int halt_if_hws_hang;
143 * DOC: vramlimit (int)
144 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
146 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
147 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
150 * DOC: vis_vramlimit (int)
151 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
153 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
154 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
157 * DOC: gartsize (uint)
158 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
160 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
161 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
165 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
166 * otherwise 3/4 RAM size).
168 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
169 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
172 * DOC: moverate (int)
173 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
175 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
176 module_param_named(moverate, amdgpu_moverate, int, 0600);
179 * DOC: benchmark (int)
180 * Run benchmarks. The default is 0 (Skip benchmarks).
182 MODULE_PARM_DESC(benchmark, "Run benchmark");
183 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
187 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
189 MODULE_PARM_DESC(test, "Run tests");
190 module_param_named(test, amdgpu_testing, int, 0444);
194 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
196 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
197 module_param_named(audio, amdgpu_audio, int, 0444);
200 * DOC: disp_priority (int)
201 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
203 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
204 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
208 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
210 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
211 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
214 * DOC: pcie_gen2 (int)
215 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
217 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
218 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
222 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
224 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
225 module_param_named(msi, amdgpu_msi, int, 0444);
228 * DOC: lockup_timeout (int)
229 * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
230 * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
232 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
233 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
237 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto).
239 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
240 module_param_named(dpm, amdgpu_dpm, int, 0444);
243 * DOC: fw_load_type (int)
244 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
246 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
247 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
251 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
253 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
254 module_param_named(aspm, amdgpu_aspm, int, 0444);
258 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
259 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
261 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
262 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
265 * DOC: ip_block_mask (uint)
266 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
267 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
268 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
269 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
271 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
272 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
276 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
277 * The default -1 (auto, enabled)
279 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
280 module_param_named(bapm, amdgpu_bapm, int, 0444);
283 * DOC: deep_color (int)
284 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
286 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
287 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
291 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
293 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
294 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
297 * DOC: vm_fragment_size (int)
298 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
300 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
301 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
304 * DOC: vm_block_size (int)
305 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
307 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
308 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
311 * DOC: vm_fault_stop (int)
312 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
314 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
315 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
318 * DOC: vm_debug (int)
319 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
321 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
322 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
325 * DOC: vm_update_mode (int)
326 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
327 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
329 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
330 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
333 * DOC: vram_page_split (int)
334 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512.
336 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
337 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
340 * DOC: exp_hw_support (int)
341 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
343 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
344 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
348 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
350 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
351 module_param_named(dc, amdgpu_dc, int, 0444);
354 * DOC: sched_jobs (int)
355 * Override the max number of jobs supported in the sw queue. The default is 32.
357 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
358 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
361 * DOC: sched_hw_submission (int)
362 * Override the max number of HW submissions. The default is 2.
364 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
365 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
368 * DOC: ppfeaturemask (uint)
369 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
370 * The default is the current set of stable power features.
372 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
373 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
376 * DOC: pcie_gen_cap (uint)
377 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
378 * The default is 0 (automatic for each asic).
380 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
381 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
384 * DOC: pcie_lane_cap (uint)
385 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
386 * The default is 0 (automatic for each asic).
388 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
389 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
392 * DOC: cg_mask (uint)
393 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
394 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
396 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
397 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
400 * DOC: pg_mask (uint)
401 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
402 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
404 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
405 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
408 * DOC: sdma_phase_quantum (uint)
409 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
411 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
412 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
415 * DOC: disable_cu (charp)
416 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
418 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
419 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
422 * DOC: virtual_display (charp)
423 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
424 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
425 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
426 * device at 26:00.0. The default is NULL.
428 MODULE_PARM_DESC(virtual_display,
429 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
430 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
434 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
436 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
437 module_param_named(ngg, amdgpu_ngg, int, 0444);
440 * DOC: prim_buf_per_se (int)
441 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
443 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
444 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
447 * DOC: pos_buf_per_se (int)
448 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
450 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
451 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
454 * DOC: cntl_sb_buf_per_se (int)
455 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
457 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
458 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
461 * DOC: param_buf_per_se (int)
462 * Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx).
464 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
465 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
468 * DOC: job_hang_limit (int)
469 * Set how much time allow a job hang and not drop it. The default is 0.
471 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
472 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
476 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
478 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
479 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
481 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
482 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
485 * DOC: gpu_recovery (int)
486 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
488 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
489 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
492 * DOC: emu_mode (int)
493 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
495 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
496 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
499 * DOC: si_support (int)
500 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
501 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
502 * otherwise using amdgpu driver.
504 #ifdef CONFIG_DRM_AMDGPU_SI
506 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
507 int amdgpu_si_support = 0;
508 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
510 int amdgpu_si_support = 1;
511 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
514 module_param_named(si_support, amdgpu_si_support, int, 0444);
518 * DOC: cik_support (int)
519 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
520 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
521 * otherwise using amdgpu driver.
523 #ifdef CONFIG_DRM_AMDGPU_CIK
525 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
526 int amdgpu_cik_support = 0;
527 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
529 int amdgpu_cik_support = 1;
530 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
533 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
537 * DOC: smu_memory_pool_size (uint)
538 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
539 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
541 MODULE_PARM_DESC(smu_memory_pool_size,
542 "reserve gtt for smu debug usage, 0 = disable,"
543 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
544 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
547 * DOC: sched_policy (int)
548 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
549 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
550 * assigns queues to HQDs.
552 module_param(sched_policy, int, 0444);
553 MODULE_PARM_DESC(sched_policy,
554 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
557 * DOC: hws_max_conc_proc (int)
558 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
559 * number of VMIDs assigned to the HWS, which is also the default.
561 module_param(hws_max_conc_proc, int, 0444);
562 MODULE_PARM_DESC(hws_max_conc_proc,
563 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
566 * DOC: cwsr_enable (int)
567 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
568 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
571 module_param(cwsr_enable, int, 0444);
572 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
575 * DOC: max_num_of_queues_per_device (int)
576 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
579 module_param(max_num_of_queues_per_device, int, 0444);
580 MODULE_PARM_DESC(max_num_of_queues_per_device,
581 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
584 * DOC: send_sigterm (int)
585 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
586 * but just print errors on dmesg. Setting 1 enables sending sigterm.
588 module_param(send_sigterm, int, 0444);
589 MODULE_PARM_DESC(send_sigterm,
590 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
593 * DOC: debug_largebar (int)
594 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
595 * system. This limits the VRAM size reported to ROCm applications to the visible
596 * size, usually 256MB.
597 * Default value is 0, diabled.
599 module_param(debug_largebar, int, 0444);
600 MODULE_PARM_DESC(debug_largebar,
601 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
604 * DOC: ignore_crat (int)
605 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
606 * table to get information about AMD APUs. This option can serve as a workaround on
607 * systems with a broken CRAT table.
609 module_param(ignore_crat, int, 0444);
610 MODULE_PARM_DESC(ignore_crat,
611 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
615 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
616 * Setting 1 disables retry.
617 * Retry is needed for recoverable page faults.
619 module_param(noretry, int, 0644);
620 MODULE_PARM_DESC(noretry,
621 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
624 * DOC: halt_if_hws_hang (int)
625 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
626 * Setting 1 enables halt on hang.
628 module_param(halt_if_hws_hang, int, 0644);
629 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
631 static const struct pci_device_id pciidlist[] = {
632 #ifdef CONFIG_DRM_AMDGPU_SI
633 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
634 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
635 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
636 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
637 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
638 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
639 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
640 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
641 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
642 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
643 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
644 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
645 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
646 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
647 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
648 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
649 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
650 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
651 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
652 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
653 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
654 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
655 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
656 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
657 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
658 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
659 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
660 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
661 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
662 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
663 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
664 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
665 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
666 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
667 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
668 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
669 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
670 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
671 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
672 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
673 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
674 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
675 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
676 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
677 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
678 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
679 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
680 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
681 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
682 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
683 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
684 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
685 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
686 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
687 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
688 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
689 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
690 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
691 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
692 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
693 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
694 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
695 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
696 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
697 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
698 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
699 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
700 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
701 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
702 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
703 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
704 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
706 #ifdef CONFIG_DRM_AMDGPU_CIK
708 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
709 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
710 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
711 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
712 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
713 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
714 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
715 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
716 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
717 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
718 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
719 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
720 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
721 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
722 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
723 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
724 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
725 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
726 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
727 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
728 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
729 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
731 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
732 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
733 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
734 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
735 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
736 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
737 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
738 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
739 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
740 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
741 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
743 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
744 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
745 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
746 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
747 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
748 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
749 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
750 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
751 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
752 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
753 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
754 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
756 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
757 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
758 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
759 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
760 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
761 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
762 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
763 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
764 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
765 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
766 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
767 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
768 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
769 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
770 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
771 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
773 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
774 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
775 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
776 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
777 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
778 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
779 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
780 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
781 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
782 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
783 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
784 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
785 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
786 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
787 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
788 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
791 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
792 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
793 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
794 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
795 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
797 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
798 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
799 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
800 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
801 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
802 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
803 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
804 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
805 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
807 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
808 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
810 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
811 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
812 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
813 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
814 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
816 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
818 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
819 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
820 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
821 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
822 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
823 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
824 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
825 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
826 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
828 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
829 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
830 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
831 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
832 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
833 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
834 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
835 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
836 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
837 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
838 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
839 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
841 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
842 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
843 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
844 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
845 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
846 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
847 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
848 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
850 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
851 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
853 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
854 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
855 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
856 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
857 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
858 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
859 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
860 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
861 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
863 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
864 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
865 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
866 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
867 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
869 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
870 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
871 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
872 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
873 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
874 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
876 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
881 MODULE_DEVICE_TABLE(pci, pciidlist);
883 static struct drm_driver kms_driver;
885 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
887 struct apertures_struct *ap;
888 bool primary = false;
890 ap = alloc_apertures(1);
894 ap->ranges[0].base = pci_resource_start(pdev, 0);
895 ap->ranges[0].size = pci_resource_len(pdev, 0);
898 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
900 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
907 static int amdgpu_pci_probe(struct pci_dev *pdev,
908 const struct pci_device_id *ent)
910 struct drm_device *dev;
911 unsigned long flags = ent->driver_data;
913 bool supports_atomic = false;
915 if (!amdgpu_virtual_display &&
916 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
917 supports_atomic = true;
919 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
920 DRM_INFO("This hardware requires experimental hardware support.\n"
921 "See modparam exp_hw_support\n");
926 * Initialize amdkfd before starting radeon. If it was not loaded yet,
927 * defer radeon probing
929 ret = amdgpu_amdkfd_init();
930 if (ret == -EPROBE_DEFER)
933 /* Get rid of things like offb */
934 ret = amdgpu_kick_out_firmware_fb(pdev);
938 /* warn the user if they mix atomic and non-atomic capable GPUs */
939 if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic)
940 DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n");
941 /* support atomic early so the atomic debugfs stuff gets created */
943 kms_driver.driver_features |= DRIVER_ATOMIC;
945 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
949 ret = pci_enable_device(pdev);
955 pci_set_drvdata(pdev, dev);
958 ret = drm_dev_register(dev, ent->driver_data);
959 if (ret == -EAGAIN && ++retry <= 3) {
960 DRM_INFO("retry init %d\n", retry);
961 /* Don't request EX mode too frequently which is attacking */
970 pci_disable_device(pdev);
977 amdgpu_pci_remove(struct pci_dev *pdev)
979 struct drm_device *dev = pci_get_drvdata(pdev);
981 drm_dev_unregister(dev);
983 pci_disable_device(pdev);
984 pci_set_drvdata(pdev, NULL);
988 amdgpu_pci_shutdown(struct pci_dev *pdev)
990 struct drm_device *dev = pci_get_drvdata(pdev);
991 struct amdgpu_device *adev = dev->dev_private;
993 /* if we are running in a VM, make sure the device
994 * torn down properly on reboot/shutdown.
995 * unfortunately we can't detect certain
996 * hypervisors so just do this all the time.
998 amdgpu_device_ip_suspend(adev);
1001 static int amdgpu_pmops_suspend(struct device *dev)
1003 struct pci_dev *pdev = to_pci_dev(dev);
1005 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1006 return amdgpu_device_suspend(drm_dev, true, true);
1009 static int amdgpu_pmops_resume(struct device *dev)
1011 struct pci_dev *pdev = to_pci_dev(dev);
1012 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1014 /* GPU comes up enabled by the bios on resume */
1015 if (amdgpu_device_is_px(drm_dev)) {
1016 pm_runtime_disable(dev);
1017 pm_runtime_set_active(dev);
1018 pm_runtime_enable(dev);
1021 return amdgpu_device_resume(drm_dev, true, true);
1024 static int amdgpu_pmops_freeze(struct device *dev)
1026 struct pci_dev *pdev = to_pci_dev(dev);
1028 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1029 return amdgpu_device_suspend(drm_dev, false, true);
1032 static int amdgpu_pmops_thaw(struct device *dev)
1034 struct pci_dev *pdev = to_pci_dev(dev);
1036 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1037 return amdgpu_device_resume(drm_dev, false, true);
1040 static int amdgpu_pmops_poweroff(struct device *dev)
1042 struct pci_dev *pdev = to_pci_dev(dev);
1044 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1045 return amdgpu_device_suspend(drm_dev, true, true);
1048 static int amdgpu_pmops_restore(struct device *dev)
1050 struct pci_dev *pdev = to_pci_dev(dev);
1052 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1053 return amdgpu_device_resume(drm_dev, false, true);
1056 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1058 struct pci_dev *pdev = to_pci_dev(dev);
1059 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1062 if (!amdgpu_device_is_px(drm_dev)) {
1063 pm_runtime_forbid(dev);
1067 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1068 drm_kms_helper_poll_disable(drm_dev);
1070 ret = amdgpu_device_suspend(drm_dev, false, false);
1071 pci_save_state(pdev);
1072 pci_disable_device(pdev);
1073 pci_ignore_hotplug(pdev);
1074 if (amdgpu_is_atpx_hybrid())
1075 pci_set_power_state(pdev, PCI_D3cold);
1076 else if (!amdgpu_has_atpx_dgpu_power_cntl())
1077 pci_set_power_state(pdev, PCI_D3hot);
1078 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1083 static int amdgpu_pmops_runtime_resume(struct device *dev)
1085 struct pci_dev *pdev = to_pci_dev(dev);
1086 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1089 if (!amdgpu_device_is_px(drm_dev))
1092 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1094 if (amdgpu_is_atpx_hybrid() ||
1095 !amdgpu_has_atpx_dgpu_power_cntl())
1096 pci_set_power_state(pdev, PCI_D0);
1097 pci_restore_state(pdev);
1098 ret = pci_enable_device(pdev);
1101 pci_set_master(pdev);
1103 ret = amdgpu_device_resume(drm_dev, false, false);
1104 drm_kms_helper_poll_enable(drm_dev);
1105 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1109 static int amdgpu_pmops_runtime_idle(struct device *dev)
1111 struct pci_dev *pdev = to_pci_dev(dev);
1112 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1113 struct drm_crtc *crtc;
1115 if (!amdgpu_device_is_px(drm_dev)) {
1116 pm_runtime_forbid(dev);
1120 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1121 if (crtc->enabled) {
1122 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1127 pm_runtime_mark_last_busy(dev);
1128 pm_runtime_autosuspend(dev);
1129 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1133 long amdgpu_drm_ioctl(struct file *filp,
1134 unsigned int cmd, unsigned long arg)
1136 struct drm_file *file_priv = filp->private_data;
1137 struct drm_device *dev;
1139 dev = file_priv->minor->dev;
1140 ret = pm_runtime_get_sync(dev->dev);
1144 ret = drm_ioctl(filp, cmd, arg);
1146 pm_runtime_mark_last_busy(dev->dev);
1147 pm_runtime_put_autosuspend(dev->dev);
1151 static const struct dev_pm_ops amdgpu_pm_ops = {
1152 .suspend = amdgpu_pmops_suspend,
1153 .resume = amdgpu_pmops_resume,
1154 .freeze = amdgpu_pmops_freeze,
1155 .thaw = amdgpu_pmops_thaw,
1156 .poweroff = amdgpu_pmops_poweroff,
1157 .restore = amdgpu_pmops_restore,
1158 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1159 .runtime_resume = amdgpu_pmops_runtime_resume,
1160 .runtime_idle = amdgpu_pmops_runtime_idle,
1163 static int amdgpu_flush(struct file *f, fl_owner_t id)
1165 struct drm_file *file_priv = f->private_data;
1166 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1168 amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr);
1174 static const struct file_operations amdgpu_driver_kms_fops = {
1175 .owner = THIS_MODULE,
1177 .flush = amdgpu_flush,
1178 .release = drm_release,
1179 .unlocked_ioctl = amdgpu_drm_ioctl,
1180 .mmap = amdgpu_mmap,
1183 #ifdef CONFIG_COMPAT
1184 .compat_ioctl = amdgpu_kms_compat_ioctl,
1189 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1190 bool in_vblank_irq, int *vpos, int *hpos,
1191 ktime_t *stime, ktime_t *etime,
1192 const struct drm_display_mode *mode)
1194 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1195 stime, etime, mode);
1198 static struct drm_driver kms_driver = {
1201 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
1202 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1203 .load = amdgpu_driver_load_kms,
1204 .open = amdgpu_driver_open_kms,
1205 .postclose = amdgpu_driver_postclose_kms,
1206 .lastclose = amdgpu_driver_lastclose_kms,
1207 .unload = amdgpu_driver_unload_kms,
1208 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1209 .enable_vblank = amdgpu_enable_vblank_kms,
1210 .disable_vblank = amdgpu_disable_vblank_kms,
1211 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1212 .get_scanout_position = amdgpu_get_crtc_scanout_position,
1213 .irq_handler = amdgpu_irq_handler,
1214 .ioctls = amdgpu_ioctls_kms,
1215 .gem_free_object_unlocked = amdgpu_gem_object_free,
1216 .gem_open_object = amdgpu_gem_object_open,
1217 .gem_close_object = amdgpu_gem_object_close,
1218 .dumb_create = amdgpu_mode_dumb_create,
1219 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1220 .fops = &amdgpu_driver_kms_fops,
1222 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1223 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1224 .gem_prime_export = amdgpu_gem_prime_export,
1225 .gem_prime_import = amdgpu_gem_prime_import,
1226 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
1227 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1228 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1229 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1230 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1231 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1233 .name = DRIVER_NAME,
1234 .desc = DRIVER_DESC,
1235 .date = DRIVER_DATE,
1236 .major = KMS_DRIVER_MAJOR,
1237 .minor = KMS_DRIVER_MINOR,
1238 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1241 static struct drm_driver *driver;
1242 static struct pci_driver *pdriver;
1244 static struct pci_driver amdgpu_kms_pci_driver = {
1245 .name = DRIVER_NAME,
1246 .id_table = pciidlist,
1247 .probe = amdgpu_pci_probe,
1248 .remove = amdgpu_pci_remove,
1249 .shutdown = amdgpu_pci_shutdown,
1250 .driver.pm = &amdgpu_pm_ops,
1255 static int __init amdgpu_init(void)
1259 if (vgacon_text_force()) {
1260 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1264 r = amdgpu_sync_init();
1268 r = amdgpu_fence_slab_init();
1272 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1273 driver = &kms_driver;
1274 pdriver = &amdgpu_kms_pci_driver;
1275 driver->num_ioctls = amdgpu_max_kms_ioctl;
1276 amdgpu_register_atpx_handler();
1277 /* let modprobe override vga console setting */
1278 return pci_register_driver(pdriver);
1287 static void __exit amdgpu_exit(void)
1289 amdgpu_amdkfd_fini();
1290 pci_unregister_driver(pdriver);
1291 amdgpu_unregister_atpx_handler();
1293 amdgpu_fence_slab_fini();
1296 module_init(amdgpu_init);
1297 module_exit(amdgpu_exit);
1299 MODULE_AUTHOR(DRIVER_AUTHOR);
1300 MODULE_DESCRIPTION(DRIVER_DESC);
1301 MODULE_LICENSE("GPL and additional rights");