2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_gem.h>
28 #include <drm/drm_vblank.h>
29 #include "amdgpu_drv.h"
31 #include <drm/drm_pciids.h>
32 #include <linux/console.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
40 #include "amdgpu_irq.h"
41 #include "amdgpu_dma_buf.h"
43 #include "amdgpu_amdkfd.h"
47 * - 3.0.0 - initial driver
48 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
49 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
51 * - 3.3.0 - Add VM support for UVD on supported hardware.
52 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
53 * - 3.5.0 - Add support for new UVD_NO_OP register.
54 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
55 * - 3.7.0 - Add support for VCE clock list packet
56 * - 3.8.0 - Add support raster config init in the kernel
57 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
58 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
59 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
60 * - 3.12.0 - Add query for double offchip LDS buffers
61 * - 3.13.0 - Add PRT support
62 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
63 * - 3.15.0 - Export more gpu info for gfx9
64 * - 3.16.0 - Add reserved vmid support
65 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
66 * - 3.18.0 - Export gpu always on cu bitmap
67 * - 3.19.0 - Add support for UVD MJPEG decode
68 * - 3.20.0 - Add support for local BOs
69 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
70 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
71 * - 3.23.0 - Add query for VRAM lost counter
72 * - 3.24.0 - Add high priority compute support for gfx9
73 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
74 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
75 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
76 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
77 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
78 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
79 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
80 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
81 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
82 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
84 #define KMS_DRIVER_MAJOR 3
85 #define KMS_DRIVER_MINOR 34
86 #define KMS_DRIVER_PATCHLEVEL 0
88 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
90 int amdgpu_vram_limit = 0;
91 int amdgpu_vis_vram_limit = 0;
92 int amdgpu_gart_size = -1; /* auto */
93 int amdgpu_gtt_size = -1; /* auto */
94 int amdgpu_moverate = -1; /* auto */
95 int amdgpu_benchmarking = 0;
96 int amdgpu_testing = 0;
97 int amdgpu_audio = -1;
98 int amdgpu_disp_priority = 0;
99 int amdgpu_hw_i2c = 0;
100 int amdgpu_pcie_gen2 = -1;
102 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
104 int amdgpu_fw_load_type = -1;
105 int amdgpu_aspm = -1;
106 int amdgpu_runtime_pm = -1;
107 uint amdgpu_ip_block_mask = 0xffffffff;
108 int amdgpu_bapm = -1;
109 int amdgpu_deep_color = 0;
110 int amdgpu_vm_size = -1;
111 int amdgpu_vm_fragment_size = -1;
112 int amdgpu_vm_block_size = -1;
113 int amdgpu_vm_fault_stop = 0;
114 int amdgpu_vm_debug = 0;
115 int amdgpu_vm_update_mode = -1;
116 int amdgpu_exp_hw_support = 0;
118 int amdgpu_sched_jobs = 32;
119 int amdgpu_sched_hw_submission = 2;
120 uint amdgpu_pcie_gen_cap = 0;
121 uint amdgpu_pcie_lane_cap = 0;
122 uint amdgpu_cg_mask = 0xffffffff;
123 uint amdgpu_pg_mask = 0xffffffff;
124 uint amdgpu_sdma_phase_quantum = 32;
125 char *amdgpu_disable_cu = NULL;
126 char *amdgpu_virtual_display = NULL;
127 /* OverDrive(bit 14) disabled by default*/
128 uint amdgpu_pp_feature_mask = 0xffffbfff;
130 int amdgpu_prim_buf_per_se = 0;
131 int amdgpu_pos_buf_per_se = 0;
132 int amdgpu_cntl_sb_buf_per_se = 0;
133 int amdgpu_param_buf_per_se = 0;
134 int amdgpu_job_hang_limit = 0;
135 int amdgpu_lbpw = -1;
136 int amdgpu_compute_multipipe = -1;
137 int amdgpu_gpu_recovery = -1; /* auto */
138 int amdgpu_emu_mode = 0;
139 uint amdgpu_smu_memory_pool_size = 0;
140 /* FBC (bit 0) disabled by default*/
141 uint amdgpu_dc_feature_mask = 0;
142 int amdgpu_async_gfx_ring = 1;
144 int amdgpu_discovery = -1;
146 int amdgpu_noretry = 1;
148 struct amdgpu_mgpu_info mgpu_info = {
149 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
151 int amdgpu_ras_enable = -1;
152 uint amdgpu_ras_mask = 0xfffffffb;
155 * DOC: vramlimit (int)
156 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
158 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
159 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
162 * DOC: vis_vramlimit (int)
163 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
165 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
166 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
169 * DOC: gartsize (uint)
170 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
172 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
173 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
177 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
178 * otherwise 3/4 RAM size).
180 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
181 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
184 * DOC: moverate (int)
185 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
187 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
188 module_param_named(moverate, amdgpu_moverate, int, 0600);
191 * DOC: benchmark (int)
192 * Run benchmarks. The default is 0 (Skip benchmarks).
194 MODULE_PARM_DESC(benchmark, "Run benchmark");
195 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
199 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
201 MODULE_PARM_DESC(test, "Run tests");
202 module_param_named(test, amdgpu_testing, int, 0444);
206 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
208 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
209 module_param_named(audio, amdgpu_audio, int, 0444);
212 * DOC: disp_priority (int)
213 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
215 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
216 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
220 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
222 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
223 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
226 * DOC: pcie_gen2 (int)
227 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
229 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
230 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
234 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
236 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
237 module_param_named(msi, amdgpu_msi, int, 0444);
240 * DOC: lockup_timeout (string)
241 * Set GPU scheduler timeout value in ms.
243 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
244 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
245 * to default timeout.
246 * - With one value specified, the setting will apply to all non-compute jobs.
247 * - With multiple values specified, the first one will be for GFX. The second one is for Compute.
248 * And the third and fourth ones are for SDMA and Video.
249 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
250 * jobs is 10000. And there is no timeout enforced on compute jobs.
252 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
253 " 0: keep default value. negative: infinity timeout), "
254 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
255 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
259 * Override for dynamic power management setting
260 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)
261 * The default is -1 (auto).
263 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
264 module_param_named(dpm, amdgpu_dpm, int, 0444);
267 * DOC: fw_load_type (int)
268 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
270 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
271 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
275 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
277 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
278 module_param_named(aspm, amdgpu_aspm, int, 0444);
282 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
283 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
285 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
286 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
289 * DOC: ip_block_mask (uint)
290 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
291 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
292 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
293 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
295 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
296 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
300 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
301 * The default -1 (auto, enabled)
303 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
304 module_param_named(bapm, amdgpu_bapm, int, 0444);
307 * DOC: deep_color (int)
308 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
310 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
311 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
315 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
317 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
318 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
321 * DOC: vm_fragment_size (int)
322 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
324 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
325 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
328 * DOC: vm_block_size (int)
329 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
331 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
332 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
335 * DOC: vm_fault_stop (int)
336 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
338 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
339 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
342 * DOC: vm_debug (int)
343 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
345 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
346 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
349 * DOC: vm_update_mode (int)
350 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
351 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
353 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
354 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
357 * DOC: exp_hw_support (int)
358 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
360 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
361 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
365 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
367 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
368 module_param_named(dc, amdgpu_dc, int, 0444);
371 * DOC: sched_jobs (int)
372 * Override the max number of jobs supported in the sw queue. The default is 32.
374 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
375 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
378 * DOC: sched_hw_submission (int)
379 * Override the max number of HW submissions. The default is 2.
381 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
382 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
385 * DOC: ppfeaturemask (uint)
386 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
387 * The default is the current set of stable power features.
389 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
390 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
393 * DOC: pcie_gen_cap (uint)
394 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
395 * The default is 0 (automatic for each asic).
397 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
398 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
401 * DOC: pcie_lane_cap (uint)
402 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
403 * The default is 0 (automatic for each asic).
405 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
406 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
409 * DOC: cg_mask (uint)
410 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
411 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
413 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
414 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
417 * DOC: pg_mask (uint)
418 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
419 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
421 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
422 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
425 * DOC: sdma_phase_quantum (uint)
426 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
428 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
429 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
432 * DOC: disable_cu (charp)
433 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
435 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
436 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
439 * DOC: virtual_display (charp)
440 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
441 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
442 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
443 * device at 26:00.0. The default is NULL.
445 MODULE_PARM_DESC(virtual_display,
446 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
447 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
451 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
453 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
454 module_param_named(ngg, amdgpu_ngg, int, 0444);
457 * DOC: prim_buf_per_se (int)
458 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
460 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
461 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
464 * DOC: pos_buf_per_se (int)
465 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
467 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
468 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
471 * DOC: cntl_sb_buf_per_se (int)
472 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
474 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
475 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
478 * DOC: param_buf_per_se (int)
479 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
480 * The default is 0 (depending on gfx).
482 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
483 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
486 * DOC: job_hang_limit (int)
487 * Set how much time allow a job hang and not drop it. The default is 0.
489 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
490 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
494 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
496 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
497 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
499 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
500 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
503 * DOC: gpu_recovery (int)
504 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
506 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
507 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
510 * DOC: emu_mode (int)
511 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
513 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
514 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
517 * DOC: ras_enable (int)
518 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
520 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
521 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
524 * DOC: ras_mask (uint)
525 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
526 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
528 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
529 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
532 * DOC: si_support (int)
533 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
534 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
535 * otherwise using amdgpu driver.
537 #ifdef CONFIG_DRM_AMDGPU_SI
539 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
540 int amdgpu_si_support = 0;
541 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
543 int amdgpu_si_support = 1;
544 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
547 module_param_named(si_support, amdgpu_si_support, int, 0444);
551 * DOC: cik_support (int)
552 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
553 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
554 * otherwise using amdgpu driver.
556 #ifdef CONFIG_DRM_AMDGPU_CIK
558 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
559 int amdgpu_cik_support = 0;
560 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
562 int amdgpu_cik_support = 1;
563 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
566 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
570 * DOC: smu_memory_pool_size (uint)
571 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
572 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
574 MODULE_PARM_DESC(smu_memory_pool_size,
575 "reserve gtt for smu debug usage, 0 = disable,"
576 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
577 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
580 * DOC: async_gfx_ring (int)
581 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
583 MODULE_PARM_DESC(async_gfx_ring,
584 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
585 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
589 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
591 MODULE_PARM_DESC(mcbp,
592 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
593 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
596 * DOC: discovery (int)
597 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
598 * (-1 = auto (default), 0 = disabled, 1 = enabled)
600 MODULE_PARM_DESC(discovery,
601 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
602 module_param_named(discovery, amdgpu_discovery, int, 0444);
606 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
607 * (0 = disabled (default), 1 = enabled)
609 MODULE_PARM_DESC(mes,
610 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
611 module_param_named(mes, amdgpu_mes, int, 0444);
613 MODULE_PARM_DESC(noretry,
614 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
615 module_param_named(noretry, amdgpu_noretry, int, 0644);
617 #ifdef CONFIG_HSA_AMD
619 * DOC: sched_policy (int)
620 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
621 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
622 * assigns queues to HQDs.
624 int sched_policy = KFD_SCHED_POLICY_HWS;
625 module_param(sched_policy, int, 0444);
626 MODULE_PARM_DESC(sched_policy,
627 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
630 * DOC: hws_max_conc_proc (int)
631 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
632 * number of VMIDs assigned to the HWS, which is also the default.
634 int hws_max_conc_proc = 8;
635 module_param(hws_max_conc_proc, int, 0444);
636 MODULE_PARM_DESC(hws_max_conc_proc,
637 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
640 * DOC: cwsr_enable (int)
641 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
642 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
646 module_param(cwsr_enable, int, 0444);
647 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
650 * DOC: max_num_of_queues_per_device (int)
651 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
654 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
655 module_param(max_num_of_queues_per_device, int, 0444);
656 MODULE_PARM_DESC(max_num_of_queues_per_device,
657 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
660 * DOC: send_sigterm (int)
661 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
662 * but just print errors on dmesg. Setting 1 enables sending sigterm.
665 module_param(send_sigterm, int, 0444);
666 MODULE_PARM_DESC(send_sigterm,
667 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
670 * DOC: debug_largebar (int)
671 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
672 * system. This limits the VRAM size reported to ROCm applications to the visible
673 * size, usually 256MB.
674 * Default value is 0, diabled.
677 module_param(debug_largebar, int, 0444);
678 MODULE_PARM_DESC(debug_largebar,
679 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
682 * DOC: ignore_crat (int)
683 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
684 * table to get information about AMD APUs. This option can serve as a workaround on
685 * systems with a broken CRAT table.
688 module_param(ignore_crat, int, 0444);
689 MODULE_PARM_DESC(ignore_crat,
690 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
693 * DOC: halt_if_hws_hang (int)
694 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
695 * Setting 1 enables halt on hang.
697 int halt_if_hws_hang;
698 module_param(halt_if_hws_hang, int, 0644);
699 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
702 * DOC: hws_gws_support(bool)
703 * Whether HWS support gws barriers. Default value: false (not supported)
704 * This will be replaced with a MEC firmware version check once firmware
707 bool hws_gws_support;
708 module_param(hws_gws_support, bool, 0444);
709 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)");
712 * DOC: queue_preemption_timeout_ms (int)
713 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
715 int queue_preemption_timeout_ms = 9000;
716 module_param(queue_preemption_timeout_ms, int, 0644);
717 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
721 * DOC: dcfeaturemask (uint)
722 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
723 * The default is the current set of stable display features.
725 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
726 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
729 * DOC: abmlevel (uint)
730 * Override the default ABM (Adaptive Backlight Management) level used for DC
731 * enabled hardware. Requires DMCU to be supported and loaded.
732 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
733 * default. Values 1-4 control the maximum allowable brightness reduction via
734 * the ABM algorithm, with 1 being the least reduction and 4 being the most
737 * Defaults to 0, or disabled. Userspace can still override this level later
740 uint amdgpu_dm_abm_level = 0;
741 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
742 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
744 static const struct pci_device_id pciidlist[] = {
745 #ifdef CONFIG_DRM_AMDGPU_SI
746 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
747 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
748 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
749 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
750 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
751 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
752 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
753 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
754 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
755 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
756 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
757 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
758 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
759 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
760 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
761 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
762 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
763 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
764 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
765 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
766 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
767 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
768 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
769 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
770 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
771 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
772 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
773 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
774 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
775 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
776 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
777 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
778 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
779 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
780 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
781 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
782 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
783 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
784 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
785 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
786 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
787 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
788 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
789 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
790 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
791 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
792 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
793 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
794 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
795 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
796 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
797 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
798 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
799 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
800 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
801 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
802 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
803 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
804 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
805 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
806 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
807 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
808 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
809 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
810 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
811 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
812 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
813 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
814 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
815 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
816 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
817 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
819 #ifdef CONFIG_DRM_AMDGPU_CIK
821 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
822 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
823 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
824 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
825 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
826 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
827 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
828 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
829 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
830 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
831 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
832 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
833 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
834 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
835 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
836 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
837 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
838 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
839 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
840 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
841 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
842 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
844 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
845 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
846 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
847 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
848 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
849 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
850 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
851 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
852 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
853 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
854 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
856 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
857 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
858 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
859 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
860 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
861 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
862 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
863 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
864 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
865 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
866 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
867 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
869 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
870 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
871 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
872 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
873 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
874 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
875 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
876 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
877 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
878 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
879 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
880 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
881 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
882 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
883 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
884 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
886 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
887 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
888 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
889 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
890 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
891 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
892 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
893 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
894 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
895 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
896 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
897 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
898 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
899 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
900 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
901 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
904 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
905 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
906 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
907 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
908 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
910 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
911 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
912 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
913 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
914 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
915 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
916 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
917 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
918 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
920 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
921 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
923 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
924 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
925 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
926 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
927 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
929 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
931 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
932 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
933 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
934 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
935 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
936 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
937 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
938 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
939 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
941 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
942 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
943 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
944 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
945 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
946 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
947 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
948 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
949 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
950 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
951 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
952 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
953 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
955 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
956 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
957 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
958 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
959 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
960 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
961 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
962 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
964 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
965 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
966 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
968 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
969 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
970 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
971 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
972 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
973 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
974 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
975 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
976 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
977 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
978 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
979 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
980 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
981 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
982 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
984 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
985 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
986 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
987 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
988 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
990 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
991 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
992 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
993 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
994 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
995 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
996 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
998 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
999 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1001 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1002 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1003 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1004 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1006 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1007 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1008 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1009 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1010 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1011 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1012 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1014 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1017 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
1022 MODULE_DEVICE_TABLE(pci, pciidlist);
1024 static struct drm_driver kms_driver;
1026 static int amdgpu_pci_probe(struct pci_dev *pdev,
1027 const struct pci_device_id *ent)
1029 struct drm_device *dev;
1030 unsigned long flags = ent->driver_data;
1032 bool supports_atomic = false;
1034 if (!amdgpu_virtual_display &&
1035 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1036 supports_atomic = true;
1038 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1039 DRM_INFO("This hardware requires experimental hardware support.\n"
1040 "See modparam exp_hw_support\n");
1044 /* Get rid of things like offb */
1045 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
1049 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
1051 return PTR_ERR(dev);
1053 if (!supports_atomic)
1054 dev->driver_features &= ~DRIVER_ATOMIC;
1056 ret = pci_enable_device(pdev);
1062 pci_set_drvdata(pdev, dev);
1065 ret = drm_dev_register(dev, ent->driver_data);
1066 if (ret == -EAGAIN && ++retry <= 3) {
1067 DRM_INFO("retry init %d\n", retry);
1068 /* Don't request EX mode too frequently which is attacking */
1077 pci_disable_device(pdev);
1084 amdgpu_pci_remove(struct pci_dev *pdev)
1086 struct drm_device *dev = pci_get_drvdata(pdev);
1088 DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
1089 drm_dev_unplug(dev);
1091 pci_disable_device(pdev);
1092 pci_set_drvdata(pdev, NULL);
1096 amdgpu_pci_shutdown(struct pci_dev *pdev)
1098 struct drm_device *dev = pci_get_drvdata(pdev);
1099 struct amdgpu_device *adev = dev->dev_private;
1101 /* if we are running in a VM, make sure the device
1102 * torn down properly on reboot/shutdown.
1103 * unfortunately we can't detect certain
1104 * hypervisors so just do this all the time.
1106 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1107 amdgpu_device_ip_suspend(adev);
1108 adev->mp1_state = PP_MP1_STATE_NONE;
1111 static int amdgpu_pmops_suspend(struct device *dev)
1113 struct drm_device *drm_dev = dev_get_drvdata(dev);
1115 return amdgpu_device_suspend(drm_dev, true, true);
1118 static int amdgpu_pmops_resume(struct device *dev)
1120 struct drm_device *drm_dev = dev_get_drvdata(dev);
1122 /* GPU comes up enabled by the bios on resume */
1123 if (amdgpu_device_is_px(drm_dev)) {
1124 pm_runtime_disable(dev);
1125 pm_runtime_set_active(dev);
1126 pm_runtime_enable(dev);
1129 return amdgpu_device_resume(drm_dev, true, true);
1132 static int amdgpu_pmops_freeze(struct device *dev)
1134 struct drm_device *drm_dev = dev_get_drvdata(dev);
1136 return amdgpu_device_suspend(drm_dev, false, true);
1139 static int amdgpu_pmops_thaw(struct device *dev)
1141 struct drm_device *drm_dev = dev_get_drvdata(dev);
1143 return amdgpu_device_resume(drm_dev, false, true);
1146 static int amdgpu_pmops_poweroff(struct device *dev)
1148 struct drm_device *drm_dev = dev_get_drvdata(dev);
1150 return amdgpu_device_suspend(drm_dev, true, true);
1153 static int amdgpu_pmops_restore(struct device *dev)
1155 struct drm_device *drm_dev = dev_get_drvdata(dev);
1157 return amdgpu_device_resume(drm_dev, false, true);
1160 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1162 struct pci_dev *pdev = to_pci_dev(dev);
1163 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1166 if (!amdgpu_device_is_px(drm_dev)) {
1167 pm_runtime_forbid(dev);
1171 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1172 drm_kms_helper_poll_disable(drm_dev);
1174 ret = amdgpu_device_suspend(drm_dev, false, false);
1175 pci_save_state(pdev);
1176 pci_disable_device(pdev);
1177 pci_ignore_hotplug(pdev);
1178 if (amdgpu_is_atpx_hybrid())
1179 pci_set_power_state(pdev, PCI_D3cold);
1180 else if (!amdgpu_has_atpx_dgpu_power_cntl())
1181 pci_set_power_state(pdev, PCI_D3hot);
1182 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1187 static int amdgpu_pmops_runtime_resume(struct device *dev)
1189 struct pci_dev *pdev = to_pci_dev(dev);
1190 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1193 if (!amdgpu_device_is_px(drm_dev))
1196 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1198 if (amdgpu_is_atpx_hybrid() ||
1199 !amdgpu_has_atpx_dgpu_power_cntl())
1200 pci_set_power_state(pdev, PCI_D0);
1201 pci_restore_state(pdev);
1202 ret = pci_enable_device(pdev);
1205 pci_set_master(pdev);
1207 ret = amdgpu_device_resume(drm_dev, false, false);
1208 drm_kms_helper_poll_enable(drm_dev);
1209 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1213 static int amdgpu_pmops_runtime_idle(struct device *dev)
1215 struct drm_device *drm_dev = dev_get_drvdata(dev);
1216 struct drm_crtc *crtc;
1218 if (!amdgpu_device_is_px(drm_dev)) {
1219 pm_runtime_forbid(dev);
1223 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1224 if (crtc->enabled) {
1225 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1230 pm_runtime_mark_last_busy(dev);
1231 pm_runtime_autosuspend(dev);
1232 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1236 long amdgpu_drm_ioctl(struct file *filp,
1237 unsigned int cmd, unsigned long arg)
1239 struct drm_file *file_priv = filp->private_data;
1240 struct drm_device *dev;
1242 dev = file_priv->minor->dev;
1243 ret = pm_runtime_get_sync(dev->dev);
1247 ret = drm_ioctl(filp, cmd, arg);
1249 pm_runtime_mark_last_busy(dev->dev);
1250 pm_runtime_put_autosuspend(dev->dev);
1254 static const struct dev_pm_ops amdgpu_pm_ops = {
1255 .suspend = amdgpu_pmops_suspend,
1256 .resume = amdgpu_pmops_resume,
1257 .freeze = amdgpu_pmops_freeze,
1258 .thaw = amdgpu_pmops_thaw,
1259 .poweroff = amdgpu_pmops_poweroff,
1260 .restore = amdgpu_pmops_restore,
1261 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1262 .runtime_resume = amdgpu_pmops_runtime_resume,
1263 .runtime_idle = amdgpu_pmops_runtime_idle,
1266 static int amdgpu_flush(struct file *f, fl_owner_t id)
1268 struct drm_file *file_priv = f->private_data;
1269 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1270 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1272 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1273 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1275 return timeout >= 0 ? 0 : timeout;
1278 static const struct file_operations amdgpu_driver_kms_fops = {
1279 .owner = THIS_MODULE,
1281 .flush = amdgpu_flush,
1282 .release = drm_release,
1283 .unlocked_ioctl = amdgpu_drm_ioctl,
1284 .mmap = amdgpu_mmap,
1287 #ifdef CONFIG_COMPAT
1288 .compat_ioctl = amdgpu_kms_compat_ioctl,
1292 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1294 struct drm_file *file;
1299 if (filp->f_op != &amdgpu_driver_kms_fops) {
1303 file = filp->private_data;
1304 *fpriv = file->driver_priv;
1308 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
1310 char *input = amdgpu_lockup_timeout;
1311 char *timeout_setting = NULL;
1317 * By default timeout for non compute jobs is 10000.
1318 * And there is no timeout enforced on compute jobs.
1320 adev->gfx_timeout = msecs_to_jiffies(10000);
1321 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1322 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
1324 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1325 while ((timeout_setting = strsep(&input, ",")) &&
1326 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1327 ret = kstrtol(timeout_setting, 0, &timeout);
1334 } else if (timeout < 0) {
1335 timeout = MAX_SCHEDULE_TIMEOUT;
1337 timeout = msecs_to_jiffies(timeout);
1342 adev->gfx_timeout = timeout;
1345 adev->compute_timeout = timeout;
1348 adev->sdma_timeout = timeout;
1351 adev->video_timeout = timeout;
1358 * There is only one value specified and
1359 * it should apply to all non-compute jobs.
1362 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1369 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1370 bool in_vblank_irq, int *vpos, int *hpos,
1371 ktime_t *stime, ktime_t *etime,
1372 const struct drm_display_mode *mode)
1374 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1375 stime, etime, mode);
1378 static struct drm_driver kms_driver = {
1380 DRIVER_USE_AGP | DRIVER_ATOMIC |
1382 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1383 .load = amdgpu_driver_load_kms,
1384 .open = amdgpu_driver_open_kms,
1385 .postclose = amdgpu_driver_postclose_kms,
1386 .lastclose = amdgpu_driver_lastclose_kms,
1387 .unload = amdgpu_driver_unload_kms,
1388 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1389 .enable_vblank = amdgpu_enable_vblank_kms,
1390 .disable_vblank = amdgpu_disable_vblank_kms,
1391 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1392 .get_scanout_position = amdgpu_get_crtc_scanout_position,
1393 .irq_handler = amdgpu_irq_handler,
1394 .ioctls = amdgpu_ioctls_kms,
1395 .gem_free_object_unlocked = amdgpu_gem_object_free,
1396 .gem_open_object = amdgpu_gem_object_open,
1397 .gem_close_object = amdgpu_gem_object_close,
1398 .dumb_create = amdgpu_mode_dumb_create,
1399 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1400 .fops = &amdgpu_driver_kms_fops,
1402 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1403 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1404 .gem_prime_export = amdgpu_gem_prime_export,
1405 .gem_prime_import = amdgpu_gem_prime_import,
1406 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1407 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1408 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1409 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1410 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1412 .name = DRIVER_NAME,
1413 .desc = DRIVER_DESC,
1414 .date = DRIVER_DATE,
1415 .major = KMS_DRIVER_MAJOR,
1416 .minor = KMS_DRIVER_MINOR,
1417 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1420 static struct pci_driver amdgpu_kms_pci_driver = {
1421 .name = DRIVER_NAME,
1422 .id_table = pciidlist,
1423 .probe = amdgpu_pci_probe,
1424 .remove = amdgpu_pci_remove,
1425 .shutdown = amdgpu_pci_shutdown,
1426 .driver.pm = &amdgpu_pm_ops,
1431 static int __init amdgpu_init(void)
1435 if (vgacon_text_force()) {
1436 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1440 r = amdgpu_sync_init();
1444 r = amdgpu_fence_slab_init();
1448 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1449 kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1450 amdgpu_register_atpx_handler();
1452 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1453 amdgpu_amdkfd_init();
1455 /* let modprobe override vga console setting */
1456 return pci_register_driver(&amdgpu_kms_pci_driver);
1465 static void __exit amdgpu_exit(void)
1467 amdgpu_amdkfd_fini();
1468 pci_unregister_driver(&amdgpu_kms_pci_driver);
1469 amdgpu_unregister_atpx_handler();
1471 amdgpu_fence_slab_fini();
1474 module_init(amdgpu_init);
1475 module_exit(amdgpu_exit);
1477 MODULE_AUTHOR(DRIVER_AUTHOR);
1478 MODULE_DESCRIPTION(DRIVER_DESC);
1479 MODULE_LICENSE("GPL and additional rights");