drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         for (i = 0; i < work->shared_count; ++i)
  87                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  88                         return;
  89
  90         /* Wait until we're out of the vertical blank period before the one
  91          * targeted by the flip
  92          */
  93         if (amdgpu_crtc->enabled &&
  94             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  95                                                 &vpos, &hpos, NULL, NULL,
  96                                                 &crtc->hwmode)
  97              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
  98             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
  99             (int)(work->target_vblank -
 100                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 101                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 102                 return;
 103         }
 104
 105         /* We borrow the event spin lock for protecting flip_status */
 106         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 107
 108         /* Do the flip (mmio) */
 109         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 110
 111         /* Set the flip status */
 112         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 113         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 114
 115
 116         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 117                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 118
 119 }
 120
 121 /*
 122  * Handle unpin events outside the interrupt handler proper.
 123  */
 124 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 125 {
 126         struct amdgpu_flip_work *work =
 127                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 128         int r;
 129
 130         /* unpin of the old buffer */
 131         r = amdgpu_bo_reserve(work->old_abo, true);
 132         if (likely(r == 0)) {
 133                 amdgpu_bo_unpin(work->old_abo);
 134                 amdgpu_bo_unreserve(work->old_abo);
 135         } else
 136                 DRM_ERROR("failed to reserve buffer after flip\n");
 137
 138         amdgpu_bo_unref(&work->old_abo);
 139         kfree(work->shared);
 140         kfree(work);
 141 }
 142
 143 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 144                                 struct drm_framebuffer *fb,
 145                                 struct drm_pending_vblank_event *event,
 146                                 uint32_t page_flip_flags, uint32_t target,
 147                                 struct drm_modeset_acquire_ctx *ctx)
 148 {
 149         struct drm_device *dev = crtc->dev;
 150         struct amdgpu_device *adev = drm_to_adev(dev);
 151         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 152         struct drm_gem_object *obj;
 153         struct amdgpu_flip_work *work;
 154         struct amdgpu_bo *new_abo;
 155         unsigned long flags;
 156         u64 tiling_flags;
 157         int i, r;
 158
 159         work = kzalloc(sizeof *work, GFP_KERNEL);
 160         if (work == NULL)
 161                 return -ENOMEM;
 162
 163         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 164         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 165
 166         work->event = event;
 167         work->adev = adev;
 168         work->crtc_id = amdgpu_crtc->crtc_id;
 169         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 170
 171         /* schedule unpin of the old buffer */
 172         obj = crtc->primary->fb->obj[0];
 173
 174         /* take a reference to the old object */
 175         work->old_abo = gem_to_amdgpu_bo(obj);
 176         amdgpu_bo_ref(work->old_abo);
 177
 178         obj = fb->obj[0];
 179         new_abo = gem_to_amdgpu_bo(obj);
 180
 181         /* pin the new buffer */
 182         r = amdgpu_bo_reserve(new_abo, false);
 183         if (unlikely(r != 0)) {
 184                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 185                 goto cleanup;
 186         }
 187
 188         if (!adev->enable_virtual_display) {
 189                 r = amdgpu_bo_pin(new_abo,
 190                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 191                 if (unlikely(r != 0)) {
 192                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 193                         goto unreserve;
 194                 }
 195         }
 196
 197         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 198         if (unlikely(r != 0)) {
 199                 DRM_ERROR("%p bind failed\n", new_abo);
 200                 goto unpin;
 201         }
 202
 203         /* TODO: Unify this with other drivers */
 204         r = dma_resv_get_fences(new_abo->tbo.base.resv, true,
 205                                 &work->shared_count,
 206                                 &work->shared);
 207         if (unlikely(r != 0)) {
 208                 DRM_ERROR("failed to get fences for buffer\n");
 209                 goto unpin;
 210         }
 211
 212         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 213         amdgpu_bo_unreserve(new_abo);
 214
 215         if (!adev->enable_virtual_display)
 216                 work->base = amdgpu_bo_gpu_offset(new_abo);
 217         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 218                 amdgpu_get_vblank_counter_kms(crtc);
 219
 220         /* we borrow the event spin lock for protecting flip_wrok */
 221         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 222         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 223                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 224                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 225                 r = -EBUSY;
 226                 goto pflip_cleanup;
 227         }
 228
 229         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 230         amdgpu_crtc->pflip_works = work;
 231
 232
 233         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 234                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 235         /* update crtc fb */
 236         crtc->primary->fb = fb;
 237         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 238         amdgpu_display_flip_work_func(&work->flip_work.work);
 239         return 0;
 240
 241 pflip_cleanup:
 242         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 243                 DRM_ERROR("failed to reserve new abo in error path\n");
 244                 goto cleanup;
 245         }
 246 unpin:
 247         if (!adev->enable_virtual_display)
 248                 amdgpu_bo_unpin(new_abo);
 249
 250 unreserve:
 251         amdgpu_bo_unreserve(new_abo);
 252
 253 cleanup:
 254         amdgpu_bo_unref(&work->old_abo);
 255         for (i = 0; i < work->shared_count; ++i)
 256                 dma_fence_put(work->shared[i]);
 257         kfree(work->shared);
 258         kfree(work);
 259
 260         return r;
 261 }
 262
 263 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 264                                    struct drm_modeset_acquire_ctx *ctx)
 265 {
 266         struct drm_device *dev;
 267         struct amdgpu_device *adev;
 268         struct drm_crtc *crtc;
 269         bool active = false;
 270         int ret;
 271
 272         if (!set || !set->crtc)
 273                 return -EINVAL;
 274
 275         dev = set->crtc->dev;
 276
 277         ret = pm_runtime_get_sync(dev->dev);
 278         if (ret < 0)
 279                 goto out;
 280
 281         ret = drm_crtc_helper_set_config(set, ctx);
 282
 283         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 284                 if (crtc->enabled)
 285                         active = true;
 286
 287         pm_runtime_mark_last_busy(dev->dev);
 288
 289         adev = drm_to_adev(dev);
 290         /* if we have active crtcs and we don't have a power ref,
 291            take the current one */
 292         if (active && !adev->have_disp_power_ref) {
 293                 adev->have_disp_power_ref = true;
 294                 return ret;
 295         }
 296         /* if we have no active crtcs, then drop the power ref
 297            we got before */
 298         if (!active && adev->have_disp_power_ref) {
 299                 pm_runtime_put_autosuspend(dev->dev);
 300                 adev->have_disp_power_ref = false;
 301         }
 302
 303 out:
 304         /* drop the power reference we got coming in here */
 305         pm_runtime_put_autosuspend(dev->dev);
 306         return ret;
 307 }
 308
 309 static const char *encoder_names[41] = {
 310         "NONE",
 311         "INTERNAL_LVDS",
 312         "INTERNAL_TMDS1",
 313         "INTERNAL_TMDS2",
 314         "INTERNAL_DAC1",
 315         "INTERNAL_DAC2",
 316         "INTERNAL_SDVOA",
 317         "INTERNAL_SDVOB",
 318         "SI170B",
 319         "CH7303",
 320         "CH7301",
 321         "INTERNAL_DVO1",
 322         "EXTERNAL_SDVOA",
 323         "EXTERNAL_SDVOB",
 324         "TITFP513",
 325         "INTERNAL_LVTM1",
 326         "VT1623",
 327         "HDMI_SI1930",
 328         "HDMI_INTERNAL",
 329         "INTERNAL_KLDSCP_TMDS1",
 330         "INTERNAL_KLDSCP_DVO1",
 331         "INTERNAL_KLDSCP_DAC1",
 332         "INTERNAL_KLDSCP_DAC2",
 333         "SI178",
 334         "MVPU_FPGA",
 335         "INTERNAL_DDI",
 336         "VT1625",
 337         "HDMI_SI1932",
 338         "DP_AN9801",
 339         "DP_DP501",
 340         "INTERNAL_UNIPHY",
 341         "INTERNAL_KLDSCP_LVTMA",
 342         "INTERNAL_UNIPHY1",
 343         "INTERNAL_UNIPHY2",
 344         "NUTMEG",
 345         "TRAVIS",
 346         "INTERNAL_VCE",
 347         "INTERNAL_UNIPHY3",
 348         "HDMI_ANX9805",
 349         "INTERNAL_AMCLK",
 350         "VIRTUAL",
 351 };
 352
 353 static const char *hpd_names[6] = {
 354         "HPD1",
 355         "HPD2",
 356         "HPD3",
 357         "HPD4",
 358         "HPD5",
 359         "HPD6",
 360 };
 361
 362 void amdgpu_display_print_display_setup(struct drm_device *dev)
 363 {
 364         struct drm_connector *connector;
 365         struct amdgpu_connector *amdgpu_connector;
 366         struct drm_encoder *encoder;
 367         struct amdgpu_encoder *amdgpu_encoder;
 368         struct drm_connector_list_iter iter;
 369         uint32_t devices;
 370         int i = 0;
 371
 372         drm_connector_list_iter_begin(dev, &iter);
 373         DRM_INFO("AMDGPU Display Connectors\n");
 374         drm_for_each_connector_iter(connector, &iter) {
 375                 amdgpu_connector = to_amdgpu_connector(connector);
 376                 DRM_INFO("Connector %d:\n", i);
 377                 DRM_INFO("  %s\n", connector->name);
 378                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 379                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 380                 if (amdgpu_connector->ddc_bus) {
 381                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 382                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 383                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 384                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 385                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 386                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 387                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 388                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 389                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 390                         if (amdgpu_connector->router.ddc_valid)
 391                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 392                                          amdgpu_connector->router.ddc_mux_control_pin,
 393                                          amdgpu_connector->router.ddc_mux_state);
 394                         if (amdgpu_connector->router.cd_valid)
 395                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 396                                          amdgpu_connector->router.cd_mux_control_pin,
 397                                          amdgpu_connector->router.cd_mux_state);
 398                 } else {
 399                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 400                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 401                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 402                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 403                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 404                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 405                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 406                 }
 407                 DRM_INFO("  Encoders:\n");
 408                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 409                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 410                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 411                         if (devices) {
 412                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 413                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 414                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 415                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 416                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 417                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 418                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 419                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 420                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 421                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 422                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 423                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 424                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 425                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 426                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 427                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 428                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 429                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 430                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 431                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 432                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 433                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 434                         }
 435                 }
 436                 i++;
 437         }
 438         drm_connector_list_iter_end(&iter);
 439 }
 440
 441 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 442                               bool use_aux)
 443 {
 444         u8 out = 0x0;
 445         u8 buf[8];
 446         int ret;
 447         struct i2c_msg msgs[] = {
 448                 {
 449                         .addr = DDC_ADDR,
 450                         .flags = 0,
 451                         .len = 1,
 452                         .buf = &out,
 453                 },
 454                 {
 455                         .addr = DDC_ADDR,
 456                         .flags = I2C_M_RD,
 457                         .len = 8,
 458                         .buf = buf,
 459                 }
 460         };
 461
 462         /* on hw with routers, select right port */
 463         if (amdgpu_connector->router.ddc_valid)
 464                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 465
 466         if (use_aux) {
 467                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 468         } else {
 469                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 470         }
 471
 472         if (ret != 2)
 473                 /* Couldn't find an accessible DDC on this connector */
 474                 return false;
 475         /* Probe also for valid EDID header
 476          * EDID header starts with:
 477          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 478          * Only the first 6 bytes must be valid as
 479          * drm_edid_block_valid() can fix the last 2 bytes */
 480         if (drm_edid_header_is_valid(buf) < 6) {
 481                 /* Couldn't find an accessible EDID on this
 482                  * connector */
 483                 return false;
 484         }
 485         return true;
 486 }
 487
 488 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 489         .destroy = drm_gem_fb_destroy,
 490         .create_handle = drm_gem_fb_create_handle,
 491 };
 492
 493 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 494                                           uint64_t bo_flags)
 495 {
 496         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 497
 498 #if defined(CONFIG_DRM_AMD_DC)
 499         /*
 500          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 501          * is not supported for this board. But this mapping is required
 502          * to avoid hang caused by placement of scanout BO in GTT on certain
 503          * APUs. So force the BO placement to VRAM in case this architecture
 504          * will not allow USWC mappings.
 505          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 506          */
 507         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 508             amdgpu_bo_support_uswc(bo_flags) &&
 509             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 510                 switch (adev->asic_type) {
 511                 case CHIP_CARRIZO:
 512                 case CHIP_STONEY:
 513                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 514                         break;
 515                 default:
 516                         switch (adev->ip_versions[DCE_HWIP][0]) {
 517                         case IP_VERSION(1, 0, 0):
 518                         case IP_VERSION(1, 0, 1):
 519                                 /* enable S/G on PCO and RV2 */
 520                                 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 521                                     (adev->apu_flags & AMD_APU_IS_PICASSO))
 522                                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 523                                 break;
 524                         case IP_VERSION(2, 1, 0):
 525                         case IP_VERSION(3, 0, 1):
 526                         case IP_VERSION(3, 1, 2):
 527                         case IP_VERSION(3, 1, 3):
 528                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 529                                 break;
 530                         default:
 531                                 break;
 532                         }
 533                         break;
 534                 }
 535         }
 536 #endif
 537
 538         return domain;
 539 }
 540
 541 static const struct drm_format_info dcc_formats[] = {
 542         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 543           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 544          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 545           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 546         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 547           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 548            .has_alpha = true, },
 549         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 550           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 551           .has_alpha = true, },
 552         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 553           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 554           .has_alpha = true, },
 555         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 556           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 557         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 558           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 559         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 560           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 561           .has_alpha = true, },
 562         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 563           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 564           .has_alpha = true, },
 565         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 566           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 567 };
 568
 569 static const struct drm_format_info dcc_retile_formats[] = {
 570         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 571           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 572          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 573           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 574         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 575           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 576            .has_alpha = true, },
 577         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 578           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 579           .has_alpha = true, },
 580         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 581           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 582           .has_alpha = true, },
 583         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 584           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 585         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 586           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 587         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 588           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 589           .has_alpha = true, },
 590         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 591           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 592           .has_alpha = true, },
 593         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 594           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 595 };
 596
 597 static const struct drm_format_info *
 598 lookup_format_info(const struct drm_format_info formats[],
 599                   int num_formats, u32 format)
 600 {
 601         int i;
 602
 603         for (i = 0; i < num_formats; i++) {
 604                 if (formats[i].format == format)
 605                         return &formats[i];
 606         }
 607
 608         return NULL;
 609 }
 610
 611 const struct drm_format_info *
 612 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 613 {
 614         if (!IS_AMD_FMT_MOD(modifier))
 615                 return NULL;
 616
 617         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 618                 return lookup_format_info(dcc_retile_formats,
 619                                           ARRAY_SIZE(dcc_retile_formats),
 620                                           format);
 621
 622         if (AMD_FMT_MOD_GET(DCC, modifier))
 623                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 624                                           format);
 625
 626         /* returning NULL will cause the default format structs to be used. */
 627         return NULL;
 628 }
 629
 630
 631 /*
 632  * Tries to extract the renderable DCC offset from the opaque metadata attached
 633  * to the buffer.
 634  */
 635 static int
 636 extract_render_dcc_offset(struct amdgpu_device *adev,
 637                           struct drm_gem_object *obj,
 638                           uint64_t *offset)
 639 {
 640         struct amdgpu_bo *rbo;
 641         int r = 0;
 642         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 643         uint32_t size;
 644
 645         rbo = gem_to_amdgpu_bo(obj);
 646         r = amdgpu_bo_reserve(rbo, false);
 647
 648         if (unlikely(r)) {
 649                 /* Don't show error message when returning -ERESTARTSYS */
 650                 if (r != -ERESTARTSYS)
 651                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 652                 return r;
 653         }
 654
 655         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 656         amdgpu_bo_unreserve(rbo);
 657
 658         if (r)
 659                 return r;
 660
 661         /*
 662          * The first word is the metadata version, and we need space for at least
 663          * the version + pci vendor+device id + 8 words for a descriptor.
 664          */
 665         if (size < 40  || metadata[0] != 1)
 666                 return -EINVAL;
 667
 668         if (adev->family >= AMDGPU_FAMILY_NV) {
 669                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 670                 *offset = ((u64)metadata[9] << 16u) |
 671                           ((metadata[8] & 0xFF000000u) >> 16);
 672         } else {
 673                 /* resource word 5/7 META_DATA_ADDRESS */
 674                 *offset = ((u64)metadata[9] << 8u) |
 675                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 676         }
 677
 678         return 0;
 679 }
 680
 681 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 682 {
 683         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 684         uint64_t modifier = 0;
 685
 686         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 687                 modifier = DRM_FORMAT_MOD_LINEAR;
 688         } else {
 689                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 690                 bool has_xor = swizzle >= 16;
 691                 int block_size_bits;
 692                 int version;
 693                 int pipe_xor_bits = 0;
 694                 int bank_xor_bits = 0;
 695                 int packers = 0;
 696                 int rb = 0;
 697                 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 698                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 699
 700                 switch (swizzle >> 2) {
 701                 case 0: /* 256B */
 702                         block_size_bits = 8;
 703                         break;
 704                 case 1: /* 4KiB */
 705                 case 5: /* 4KiB _X */
 706                         block_size_bits = 12;
 707                         break;
 708                 case 2: /* 64KiB */
 709                 case 4: /* 64 KiB _T */
 710                 case 6: /* 64 KiB _X */
 711                         block_size_bits = 16;
 712                         break;
 713                 default:
 714                         /* RESERVED or VAR */
 715                         return -EINVAL;
 716                 }
 717
 718                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 719                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 720                 else if (adev->family == AMDGPU_FAMILY_NV)
 721                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 722                 else
 723                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 724
 725                 switch (swizzle & 3) {
 726                 case 0: /* Z microtiling */
 727                         return -EINVAL;
 728                 case 1: /* S microtiling */
 729                         if (!has_xor)
 730                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 731                         break;
 732                 case 2:
 733                         if (!has_xor && afb->base.format->cpp[0] != 4)
 734                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 735                         break;
 736                 case 3:
 737                         break;
 738                 }
 739
 740                 if (has_xor) {
 741                         switch (version) {
 742                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 743                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 744                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 745                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 746                                 break;
 747                         case AMD_FMT_MOD_TILE_VER_GFX10:
 748                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 749                                 break;
 750                         case AMD_FMT_MOD_TILE_VER_GFX9:
 751                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 752                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 753                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 754                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 755                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 756                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 757                                 break;
 758                         }
 759                 }
 760
 761                 modifier = AMD_FMT_MOD |
 762                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 763                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 764                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 765                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 766                            AMD_FMT_MOD_SET(PACKERS, packers);
 767
 768                 if (dcc_offset != 0) {
 769                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 770                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 771                         const struct drm_format_info *format_info;
 772                         u64 render_dcc_offset;
 773
 774                         /* Enable constant encode on RAVEN2 and later. */
 775                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 776                                                    (adev->asic_type == CHIP_RAVEN &&
 777                                                     adev->external_rev_id >= 0x81);
 778
 779                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 780                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 781                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 782
 783                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 784                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 785                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 786                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 787                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 788
 789                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 790                         afb->base.pitches[1] =
 791                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 792
 793                         /*
 794                          * If the userspace driver uses retiling the tiling flags do not contain
 795                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 796                          * the info so we can try to extract it. The kernel does not use this info
 797                          * but we should convert it to a modifier plane for getfb2, so the
 798                          * userspace driver that gets it doesn't have to juggle around another DCC
 799                          * plane internally.
 800                          */
 801                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 802                                                       &render_dcc_offset) == 0 &&
 803                             render_dcc_offset != 0 &&
 804                             render_dcc_offset != afb->base.offsets[1] &&
 805                             render_dcc_offset < UINT_MAX) {
 806                                 uint32_t dcc_block_bits;  /* of base surface data */
 807
 808                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 809                                 afb->base.offsets[2] = render_dcc_offset;
 810
 811                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 812                                         int extra_pipe = 0;
 813
 814                                         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 815                                             pipes == packers && pipes > 1)
 816                                                 extra_pipe = 1;
 817
 818                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 819                                 } else {
 820                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 821                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 822                                         dcc_block_bits = max(20, 18 + rb);
 823                                 }
 824
 825                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 826                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 827                                                              1u << ((dcc_block_bits + 1) / 2));
 828                         }
 829                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 830                                                                 modifier);
 831                         if (!format_info)
 832                                 return -EINVAL;
 833
 834                         afb->base.format = format_info;
 835                 }
 836         }
 837
 838         afb->base.modifier = modifier;
 839         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 840         return 0;
 841 }
 842
 843 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
 844 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
 845 {
 846         u64 micro_tile_mode;
 847
 848         /* Zero swizzle mode means linear */
 849         if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
 850                 return 0;
 851
 852         micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
 853         switch (micro_tile_mode) {
 854         case 0: /* DISPLAY */
 855         case 3: /* RENDER */
 856                 return 0;
 857         default:
 858                 drm_dbg_kms(afb->base.dev,
 859                             "Micro tile mode %llu not supported for scanout\n",
 860                             micro_tile_mode);
 861                 return -EINVAL;
 862         }
 863 }
 864
 865 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 866                                  unsigned int *width, unsigned int *height)
 867 {
 868         unsigned int cpp_log2 = ilog2(cpp);
 869         unsigned int pixel_log2 = block_log2 - cpp_log2;
 870         unsigned int width_log2 = (pixel_log2 + 1) / 2;
 871         unsigned int height_log2 = pixel_log2 - width_log2;
 872
 873         *width = 1 << width_log2;
 874         *height = 1 << height_log2;
 875 }
 876
 877 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 878                                        bool pipe_aligned)
 879 {
 880         unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 881
 882         switch (ver) {
 883         case AMD_FMT_MOD_TILE_VER_GFX9: {
 884                 /*
 885                  * TODO: for pipe aligned we may need to check the alignment of the
 886                  * total size of the surface, which may need to be bigger than the
 887                  * natural alignment due to some HW workarounds
 888                  */
 889                 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 890         }
 891         case AMD_FMT_MOD_TILE_VER_GFX10:
 892         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
 893                 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 894
 895                 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 896                     AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 897                         ++pipes_log2;
 898
 899                 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
 900         }
 901         default:
 902                 return 0;
 903         }
 904 }
 905
 906 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
 907                                        const struct drm_format_info *format,
 908                                        unsigned int block_width, unsigned int block_height,
 909                                        unsigned int block_size_log2)
 910 {
 911         unsigned int width = rfb->base.width /
 912                 ((plane && plane < format->num_planes) ? format->hsub : 1);
 913         unsigned int height = rfb->base.height /
 914                 ((plane && plane < format->num_planes) ? format->vsub : 1);
 915         unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
 916         unsigned int block_pitch = block_width * cpp;
 917         unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
 918         unsigned int block_size = 1 << block_size_log2;
 919         uint64_t size;
 920
 921         if (rfb->base.pitches[plane] % block_pitch) {
 922                 drm_dbg_kms(rfb->base.dev,
 923                             "pitch %d for plane %d is not a multiple of block pitch %d\n",
 924                             rfb->base.pitches[plane], plane, block_pitch);
 925                 return -EINVAL;
 926         }
 927         if (rfb->base.pitches[plane] < min_pitch) {
 928                 drm_dbg_kms(rfb->base.dev,
 929                             "pitch %d for plane %d is less than minimum pitch %d\n",
 930                             rfb->base.pitches[plane], plane, min_pitch);
 931                 return -EINVAL;
 932         }
 933
 934         /* Force at least natural alignment. */
 935         if (rfb->base.offsets[plane] % block_size) {
 936                 drm_dbg_kms(rfb->base.dev,
 937                             "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
 938                             rfb->base.offsets[plane], plane, block_size);
 939                 return -EINVAL;
 940         }
 941
 942         size = rfb->base.offsets[plane] +
 943                 (uint64_t)rfb->base.pitches[plane] / block_pitch *
 944                 block_size * DIV_ROUND_UP(height, block_height);
 945
 946         if (rfb->base.obj[0]->size < size) {
 947                 drm_dbg_kms(rfb->base.dev,
 948                             "BO size 0x%zx is less than 0x%llx required for plane %d\n",
 949                             rfb->base.obj[0]->size, size, plane);
 950                 return -EINVAL;
 951         }
 952
 953         return 0;
 954 }
 955
 956
 957 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 958 {
 959         const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
 960         uint64_t modifier = rfb->base.modifier;
 961         int ret;
 962         unsigned int i, block_width, block_height, block_size_log2;
 963
 964         if (!rfb->base.dev->mode_config.allow_fb_modifiers)
 965                 return 0;
 966
 967         for (i = 0; i < format_info->num_planes; ++i) {
 968                 if (modifier == DRM_FORMAT_MOD_LINEAR) {
 969                         block_width = 256 / format_info->cpp[i];
 970                         block_height = 1;
 971                         block_size_log2 = 8;
 972                 } else {
 973                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
 974
 975                         switch ((swizzle & ~3) + 1) {
 976                         case DC_SW_256B_S:
 977                                 block_size_log2 = 8;
 978                                 break;
 979                         case DC_SW_4KB_S:
 980                         case DC_SW_4KB_S_X:
 981                                 block_size_log2 = 12;
 982                                 break;
 983                         case DC_SW_64KB_S:
 984                         case DC_SW_64KB_S_T:
 985                         case DC_SW_64KB_S_X:
 986                                 block_size_log2 = 16;
 987                                 break;
 988                         default:
 989                                 drm_dbg_kms(rfb->base.dev,
 990                                             "Swizzle mode with unknown block size: %d\n", swizzle);
 991                                 return -EINVAL;
 992                         }
 993
 994                         get_block_dimensions(block_size_log2, format_info->cpp[i],
 995                                              &block_width, &block_height);
 996                 }
 997
 998                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
 999                                                   block_width, block_height, block_size_log2);
1000                 if (ret)
1001                         return ret;
1002         }
1003
1004         if (AMD_FMT_MOD_GET(DCC, modifier)) {
1005                 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1006                         block_size_log2 = get_dcc_block_size(modifier, false, false);
1007                         get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1008                                              &block_width, &block_height);
1009                         ret = amdgpu_display_verify_plane(rfb, i, format_info,
1010                                                           block_width, block_height,
1011                                                           block_size_log2);
1012                         if (ret)
1013                                 return ret;
1014
1015                         ++i;
1016                         block_size_log2 = get_dcc_block_size(modifier, true, true);
1017                 } else {
1018                         bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1019
1020                         block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1021                 }
1022                 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1023                                      &block_width, &block_height);
1024                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1025                                                   block_width, block_height, block_size_log2);
1026                 if (ret)
1027                         return ret;
1028         }
1029
1030         return 0;
1031 }
1032
1033 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1034                                       uint64_t *tiling_flags, bool *tmz_surface)
1035 {
1036         struct amdgpu_bo *rbo;
1037         int r;
1038
1039         if (!amdgpu_fb) {
1040                 *tiling_flags = 0;
1041                 *tmz_surface = false;
1042                 return 0;
1043         }
1044
1045         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1046         r = amdgpu_bo_reserve(rbo, false);
1047
1048         if (unlikely(r)) {
1049                 /* Don't show error message when returning -ERESTARTSYS */
1050                 if (r != -ERESTARTSYS)
1051                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1052                 return r;
1053         }
1054
1055         if (tiling_flags)
1056                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1057
1058         if (tmz_surface)
1059                 *tmz_surface = amdgpu_bo_encrypted(rbo);
1060
1061         amdgpu_bo_unreserve(rbo);
1062
1063         return r;
1064 }
1065
1066 int amdgpu_display_gem_fb_init(struct drm_device *dev,
1067                                struct amdgpu_framebuffer *rfb,
1068                                const struct drm_mode_fb_cmd2 *mode_cmd,
1069                                struct drm_gem_object *obj)
1070 {
1071         int ret;
1072
1073         rfb->base.obj[0] = obj;
1074         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1075
1076         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1077         if (ret)
1078                 goto err;
1079
1080         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1081         if (ret)
1082                 goto err;
1083
1084         return 0;
1085 err:
1086         drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
1087         rfb->base.obj[0] = NULL;
1088         return ret;
1089 }
1090
1091 int amdgpu_display_gem_fb_verify_and_init(
1092         struct drm_device *dev, struct amdgpu_framebuffer *rfb,
1093         struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
1094         struct drm_gem_object *obj)
1095 {
1096         int ret;
1097
1098         rfb->base.obj[0] = obj;
1099         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1100         /* Verify that the modifier is supported. */
1101         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1102                                       mode_cmd->modifier[0])) {
1103                 drm_dbg_kms(dev,
1104                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1105                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1106
1107                 ret = -EINVAL;
1108                 goto err;
1109         }
1110
1111         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1112         if (ret)
1113                 goto err;
1114
1115         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1116         if (ret)
1117                 goto err;
1118
1119         return 0;
1120 err:
1121         drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1122         rfb->base.obj[0] = NULL;
1123         return ret;
1124 }
1125
1126 int amdgpu_display_framebuffer_init(struct drm_device *dev,
1127                                     struct amdgpu_framebuffer *rfb,
1128                                     const struct drm_mode_fb_cmd2 *mode_cmd,
1129                                     struct drm_gem_object *obj)
1130 {
1131         struct amdgpu_device *adev = drm_to_adev(dev);
1132         int ret, i;
1133
1134         /*
1135          * This needs to happen before modifier conversion as that might change
1136          * the number of planes.
1137          */
1138         for (i = 1; i < rfb->base.format->num_planes; ++i) {
1139                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1140                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1141                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
1142                         ret = -EINVAL;
1143                         return ret;
1144                 }
1145         }
1146
1147         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1148         if (ret)
1149                 return ret;
1150
1151         if (!dev->mode_config.allow_fb_modifiers) {
1152                 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1153                               "GFX9+ requires FB check based on format modifier\n");
1154                 ret = check_tiling_flags_gfx6(rfb);
1155                 if (ret)
1156                         return ret;
1157         }
1158
1159         if (dev->mode_config.allow_fb_modifiers &&
1160             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1161                 ret = convert_tiling_flags_to_modifier(rfb);
1162                 if (ret) {
1163                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1164                                     rfb->tiling_flags);
1165                         return ret;
1166                 }
1167         }
1168
1169         ret = amdgpu_display_verify_sizes(rfb);
1170         if (ret)
1171                 return ret;
1172
1173         for (i = 0; i < rfb->base.format->num_planes; ++i) {
1174                 drm_gem_object_get(rfb->base.obj[0]);
1175                 rfb->base.obj[i] = rfb->base.obj[0];
1176         }
1177
1178         return 0;
1179 }
1180
1181 struct drm_framebuffer *
1182 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1183                                        struct drm_file *file_priv,
1184                                        const struct drm_mode_fb_cmd2 *mode_cmd)
1185 {
1186         struct amdgpu_framebuffer *amdgpu_fb;
1187         struct drm_gem_object *obj;
1188         struct amdgpu_bo *bo;
1189         uint32_t domains;
1190         int ret;
1191
1192         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1193         if (obj ==  NULL) {
1194                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1195                             "can't create framebuffer\n", mode_cmd->handles[0]);
1196                 return ERR_PTR(-ENOENT);
1197         }
1198
1199         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1200         bo = gem_to_amdgpu_bo(obj);
1201         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1202         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1203                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1204                 drm_gem_object_put(obj);
1205                 return ERR_PTR(-EINVAL);
1206         }
1207
1208         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1209         if (amdgpu_fb == NULL) {
1210                 drm_gem_object_put(obj);
1211                 return ERR_PTR(-ENOMEM);
1212         }
1213
1214         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1215                                                     mode_cmd, obj);
1216         if (ret) {
1217                 kfree(amdgpu_fb);
1218                 drm_gem_object_put(obj);
1219                 return ERR_PTR(ret);
1220         }
1221
1222         drm_gem_object_put(obj);
1223         return &amdgpu_fb->base;
1224 }
1225
1226 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1227         .fb_create = amdgpu_display_user_framebuffer_create,
1228         .output_poll_changed = drm_fb_helper_output_poll_changed,
1229 };
1230
1231 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1232 {       { UNDERSCAN_OFF, "off" },
1233         { UNDERSCAN_ON, "on" },
1234         { UNDERSCAN_AUTO, "auto" },
1235 };
1236
1237 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1238 {       { AMDGPU_AUDIO_DISABLE, "off" },
1239         { AMDGPU_AUDIO_ENABLE, "on" },
1240         { AMDGPU_AUDIO_AUTO, "auto" },
1241 };
1242
1243 /* XXX support different dither options? spatial, temporal, both, etc. */
1244 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1245 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
1246         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1247 };
1248
1249 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1250 {
1251         int sz;
1252
1253         adev->mode_info.coherent_mode_property =
1254                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1255         if (!adev->mode_info.coherent_mode_property)
1256                 return -ENOMEM;
1257
1258         adev->mode_info.load_detect_property =
1259                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1260         if (!adev->mode_info.load_detect_property)
1261                 return -ENOMEM;
1262
1263         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1264
1265         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1266         adev->mode_info.underscan_property =
1267                 drm_property_create_enum(adev_to_drm(adev), 0,
1268                                          "underscan",
1269                                          amdgpu_underscan_enum_list, sz);
1270
1271         adev->mode_info.underscan_hborder_property =
1272                 drm_property_create_range(adev_to_drm(adev), 0,
1273                                           "underscan hborder", 0, 128);
1274         if (!adev->mode_info.underscan_hborder_property)
1275                 return -ENOMEM;
1276
1277         adev->mode_info.underscan_vborder_property =
1278                 drm_property_create_range(adev_to_drm(adev), 0,
1279                                           "underscan vborder", 0, 128);
1280         if (!adev->mode_info.underscan_vborder_property)
1281                 return -ENOMEM;
1282
1283         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1284         adev->mode_info.audio_property =
1285                 drm_property_create_enum(adev_to_drm(adev), 0,
1286                                          "audio",
1287                                          amdgpu_audio_enum_list, sz);
1288
1289         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1290         adev->mode_info.dither_property =
1291                 drm_property_create_enum(adev_to_drm(adev), 0,
1292                                          "dither",
1293                                          amdgpu_dither_enum_list, sz);
1294
1295         if (amdgpu_device_has_dc_support(adev)) {
1296                 adev->mode_info.abm_level_property =
1297                         drm_property_create_range(adev_to_drm(adev), 0,
1298                                                   "abm level", 0, 4);
1299                 if (!adev->mode_info.abm_level_property)
1300                         return -ENOMEM;
1301         }
1302
1303         return 0;
1304 }
1305
1306 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1307 {
1308         /* adjustment options for the display watermarks */
1309         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1310                 adev->mode_info.disp_priority = 0;
1311         else
1312                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1313
1314 }
1315
1316 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1317 {
1318         /* try and guess if this is a tv or a monitor */
1319         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1320             (mode->vdisplay == 576) || /* 576p */
1321             (mode->vdisplay == 720) || /* 720p */
1322             (mode->vdisplay == 1080)) /* 1080p */
1323                 return true;
1324         else
1325                 return false;
1326 }
1327
1328 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1329                                         const struct drm_display_mode *mode,
1330                                         struct drm_display_mode *adjusted_mode)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_encoder *encoder;
1334         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1335         struct amdgpu_encoder *amdgpu_encoder;
1336         struct drm_connector *connector;
1337         u32 src_v = 1, dst_v = 1;
1338         u32 src_h = 1, dst_h = 1;
1339
1340         amdgpu_crtc->h_border = 0;
1341         amdgpu_crtc->v_border = 0;
1342
1343         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1344                 if (encoder->crtc != crtc)
1345                         continue;
1346                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1347                 connector = amdgpu_get_connector_for_encoder(encoder);
1348
1349                 /* set scaling */
1350                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1351                         amdgpu_crtc->rmx_type = RMX_OFF;
1352                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1353                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1354                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1355                 else
1356                         amdgpu_crtc->rmx_type = RMX_OFF;
1357                 /* copy native mode */
1358                 memcpy(&amdgpu_crtc->native_mode,
1359                        &amdgpu_encoder->native_mode,
1360                        sizeof(struct drm_display_mode));
1361                 src_v = crtc->mode.vdisplay;
1362                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1363                 src_h = crtc->mode.hdisplay;
1364                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1365
1366                 /* fix up for overscan on hdmi */
1367                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1368                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1369                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1370                       connector->display_info.is_hdmi &&
1371                       amdgpu_display_is_hdtv_mode(mode)))) {
1372                         if (amdgpu_encoder->underscan_hborder != 0)
1373                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1374                         else
1375                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1376                         if (amdgpu_encoder->underscan_vborder != 0)
1377                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1378                         else
1379                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1380                         amdgpu_crtc->rmx_type = RMX_FULL;
1381                         src_v = crtc->mode.vdisplay;
1382                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1383                         src_h = crtc->mode.hdisplay;
1384                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1385                 }
1386         }
1387         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1388                 fixed20_12 a, b;
1389                 a.full = dfixed_const(src_v);
1390                 b.full = dfixed_const(dst_v);
1391                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1392                 a.full = dfixed_const(src_h);
1393                 b.full = dfixed_const(dst_h);
1394                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1395         } else {
1396                 amdgpu_crtc->vsc.full = dfixed_const(1);
1397                 amdgpu_crtc->hsc.full = dfixed_const(1);
1398         }
1399         return true;
1400 }
1401
1402 /*
1403  * Retrieve current video scanout position of crtc on a given gpu, and
1404  * an optional accurate timestamp of when query happened.
1405  *
1406  * \param dev Device to query.
1407  * \param pipe Crtc to query.
1408  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1409  *              For driver internal use only also supports these flags:
1410  *
1411  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1412  *              of a fudged earlier start of vblank.
1413  *
1414  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1415  *              fudged earlier start of vblank in *vpos and the distance
1416  *              to true start of vblank in *hpos.
1417  *
1418  * \param *vpos Location where vertical scanout position should be stored.
1419  * \param *hpos Location where horizontal scanout position should go.
1420  * \param *stime Target location for timestamp taken immediately before
1421  *               scanout position query. Can be NULL to skip timestamp.
1422  * \param *etime Target location for timestamp taken immediately after
1423  *               scanout position query. Can be NULL to skip timestamp.
1424  *
1425  * Returns vpos as a positive number while in active scanout area.
1426  * Returns vpos as a negative number inside vblank, counting the number
1427  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1428  * until start of active scanout / end of vblank."
1429  *
1430  * \return Flags, or'ed together as follows:
1431  *
1432  * DRM_SCANOUTPOS_VALID = Query successful.
1433  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1434  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1435  * this flag means that returned position may be offset by a constant but
1436  * unknown small number of scanlines wrt. real scanout position.
1437  *
1438  */
1439 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1440                         unsigned int pipe, unsigned int flags, int *vpos,
1441                         int *hpos, ktime_t *stime, ktime_t *etime,
1442                         const struct drm_display_mode *mode)
1443 {
1444         u32 vbl = 0, position = 0;
1445         int vbl_start, vbl_end, vtotal, ret = 0;
1446         bool in_vbl = true;
1447
1448         struct amdgpu_device *adev = drm_to_adev(dev);
1449
1450         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1451
1452         /* Get optional system timestamp before query. */
1453         if (stime)
1454                 *stime = ktime_get();
1455
1456         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1457                 ret |= DRM_SCANOUTPOS_VALID;
1458
1459         /* Get optional system timestamp after query. */
1460         if (etime)
1461                 *etime = ktime_get();
1462
1463         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1464
1465         /* Decode into vertical and horizontal scanout position. */
1466         *vpos = position & 0x1fff;
1467         *hpos = (position >> 16) & 0x1fff;
1468
1469         /* Valid vblank area boundaries from gpu retrieved? */
1470         if (vbl > 0) {
1471                 /* Yes: Decode. */
1472                 ret |= DRM_SCANOUTPOS_ACCURATE;
1473                 vbl_start = vbl & 0x1fff;
1474                 vbl_end = (vbl >> 16) & 0x1fff;
1475         }
1476         else {
1477                 /* No: Fake something reasonable which gives at least ok results. */
1478                 vbl_start = mode->crtc_vdisplay;
1479                 vbl_end = 0;
1480         }
1481
1482         /* Called from driver internal vblank counter query code? */
1483         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1484             /* Caller wants distance from real vbl_start in *hpos */
1485             *hpos = *vpos - vbl_start;
1486         }
1487
1488         /* Fudge vblank to start a few scanlines earlier to handle the
1489          * problem that vblank irqs fire a few scanlines before start
1490          * of vblank. Some driver internal callers need the true vblank
1491          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1492          *
1493          * The cause of the "early" vblank irq is that the irq is triggered
1494          * by the line buffer logic when the line buffer read position enters
1495          * the vblank, whereas our crtc scanout position naturally lags the
1496          * line buffer read position.
1497          */
1498         if (!(flags & USE_REAL_VBLANKSTART))
1499                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1500
1501         /* Test scanout position against vblank region. */
1502         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1503                 in_vbl = false;
1504
1505         /* In vblank? */
1506         if (in_vbl)
1507             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1508
1509         /* Called from driver internal vblank counter query code? */
1510         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1511                 /* Caller wants distance from fudged earlier vbl_start */
1512                 *vpos -= vbl_start;
1513                 return ret;
1514         }
1515
1516         /* Check if inside vblank area and apply corrective offsets:
1517          * vpos will then be >=0 in video scanout area, but negative
1518          * within vblank area, counting down the number of lines until
1519          * start of scanout.
1520          */
1521
1522         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1523         if (in_vbl && (*vpos >= vbl_start)) {
1524                 vtotal = mode->crtc_vtotal;
1525
1526                 /* With variable refresh rate displays the vpos can exceed
1527                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1528                  * of guessing the remaining number of lines until scanout.
1529                  */
1530                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1531         }
1532
1533         /* Correct for shifted end of vbl at vbl_end. */
1534         *vpos = *vpos - vbl_end;
1535
1536         return ret;
1537 }
1538
1539 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1540 {
1541         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1542                 return AMDGPU_CRTC_IRQ_NONE;
1543
1544         switch (crtc) {
1545         case 0:
1546                 return AMDGPU_CRTC_IRQ_VBLANK1;
1547         case 1:
1548                 return AMDGPU_CRTC_IRQ_VBLANK2;
1549         case 2:
1550                 return AMDGPU_CRTC_IRQ_VBLANK3;
1551         case 3:
1552                 return AMDGPU_CRTC_IRQ_VBLANK4;
1553         case 4:
1554                 return AMDGPU_CRTC_IRQ_VBLANK5;
1555         case 5:
1556                 return AMDGPU_CRTC_IRQ_VBLANK6;
1557         default:
1558                 return AMDGPU_CRTC_IRQ_NONE;
1559         }
1560 }
1561
1562 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1563                         bool in_vblank_irq, int *vpos,
1564                         int *hpos, ktime_t *stime, ktime_t *etime,
1565                         const struct drm_display_mode *mode)
1566 {
1567         struct drm_device *dev = crtc->dev;
1568         unsigned int pipe = crtc->index;
1569
1570         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1571                                                   stime, etime, mode);
1572 }
1573
1574 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1575 {
1576         struct drm_device *dev = adev_to_drm(adev);
1577         struct drm_crtc *crtc;
1578         struct drm_connector *connector;
1579         struct drm_connector_list_iter iter;
1580         int r;
1581
1582         /* turn off display hw */
1583         drm_modeset_lock_all(dev);
1584         drm_connector_list_iter_begin(dev, &iter);
1585         drm_for_each_connector_iter(connector, &iter)
1586                 drm_helper_connector_dpms(connector,
1587                                           DRM_MODE_DPMS_OFF);
1588         drm_connector_list_iter_end(&iter);
1589         drm_modeset_unlock_all(dev);
1590         /* unpin the front buffers and cursors */
1591         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1592                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1593                 struct drm_framebuffer *fb = crtc->primary->fb;
1594                 struct amdgpu_bo *robj;
1595
1596                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1597                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1598                         r = amdgpu_bo_reserve(aobj, true);
1599                         if (r == 0) {
1600                                 amdgpu_bo_unpin(aobj);
1601                                 amdgpu_bo_unreserve(aobj);
1602                         }
1603                 }
1604
1605                 if (fb == NULL || fb->obj[0] == NULL) {
1606                         continue;
1607                 }
1608                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1609                 r = amdgpu_bo_reserve(robj, true);
1610                 if (r == 0) {
1611                         amdgpu_bo_unpin(robj);
1612                         amdgpu_bo_unreserve(robj);
1613                 }
1614         }
1615         return 0;
1616 }
1617
1618 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1619 {
1620         struct drm_device *dev = adev_to_drm(adev);
1621         struct drm_connector *connector;
1622         struct drm_connector_list_iter iter;
1623         struct drm_crtc *crtc;
1624         int r;
1625
1626         /* pin cursors */
1627         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1628                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1629
1630                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1631                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1632                         r = amdgpu_bo_reserve(aobj, true);
1633                         if (r == 0) {
1634                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1635                                 if (r != 0)
1636                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1637                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1638                                 amdgpu_bo_unreserve(aobj);
1639                         }
1640                 }
1641         }
1642
1643         drm_helper_resume_force_mode(dev);
1644
1645         /* turn on display hw */
1646         drm_modeset_lock_all(dev);
1647
1648         drm_connector_list_iter_begin(dev, &iter);
1649         drm_for_each_connector_iter(connector, &iter)
1650                 drm_helper_connector_dpms(connector,
1651                                           DRM_MODE_DPMS_ON);
1652         drm_connector_list_iter_end(&iter);
1653
1654         drm_modeset_unlock_all(dev);
1655
1656         return 0;
1657 }
1658