2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
38 #include "amdgpu_i2c.h"
40 #include "amdgpu_atombios.h"
42 #ifdef CONFIG_DRM_AMDGPU_CIK
46 #include "bif/bif_4_1_d.h"
48 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
49 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
51 static const char *amdgpu_asic_name[] = {
65 #if defined(CONFIG_VGA_SWITCHEROO)
66 bool amdgpu_has_atpx_dgpu_power_cntl(void);
68 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
71 bool amdgpu_device_is_px(struct drm_device *dev)
73 struct amdgpu_device *adev = dev->dev_private;
75 if (adev->flags & AMD_IS_PX)
81 * MMIO register access helper functions.
83 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
86 if ((reg * 4) < adev->rmmio_size && !always_indirect)
87 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
92 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
93 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
94 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
95 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
101 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
102 bool always_indirect)
104 if ((reg * 4) < adev->rmmio_size && !always_indirect)
105 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
109 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
110 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
111 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
112 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
116 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
118 if ((reg * 4) < adev->rio_mem_size)
119 return ioread32(adev->rio_mem + (reg * 4));
121 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
122 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
126 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
129 if ((reg * 4) < adev->rio_mem_size)
130 iowrite32(v, adev->rio_mem + (reg * 4));
132 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
133 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
138 * amdgpu_mm_rdoorbell - read a doorbell dword
140 * @adev: amdgpu_device pointer
141 * @index: doorbell index
143 * Returns the value in the doorbell aperture at the
144 * requested doorbell index (CIK).
146 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
148 if (index < adev->doorbell.num_doorbells) {
149 return readl(adev->doorbell.ptr + index);
151 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
157 * amdgpu_mm_wdoorbell - write a doorbell dword
159 * @adev: amdgpu_device pointer
160 * @index: doorbell index
163 * Writes @v to the doorbell aperture at the
164 * requested doorbell index (CIK).
166 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
168 if (index < adev->doorbell.num_doorbells) {
169 writel(v, adev->doorbell.ptr + index);
171 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
176 * amdgpu_invalid_rreg - dummy reg read function
178 * @adev: amdgpu device pointer
179 * @reg: offset of register
181 * Dummy register read function. Used for register blocks
182 * that certain asics don't have (all asics).
183 * Returns the value in the register.
185 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
187 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
193 * amdgpu_invalid_wreg - dummy reg write function
195 * @adev: amdgpu device pointer
196 * @reg: offset of register
197 * @v: value to write to the register
199 * Dummy register read function. Used for register blocks
200 * that certain asics don't have (all asics).
202 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
204 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
210 * amdgpu_block_invalid_rreg - dummy reg read function
212 * @adev: amdgpu device pointer
213 * @block: offset of instance
214 * @reg: offset of register
216 * Dummy register read function. Used for register blocks
217 * that certain asics don't have (all asics).
218 * Returns the value in the register.
220 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
221 uint32_t block, uint32_t reg)
223 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
230 * amdgpu_block_invalid_wreg - dummy reg write function
232 * @adev: amdgpu device pointer
233 * @block: offset of instance
234 * @reg: offset of register
235 * @v: value to write to the register
237 * Dummy register read function. Used for register blocks
238 * that certain asics don't have (all asics).
240 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
242 uint32_t reg, uint32_t v)
244 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
249 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
253 if (adev->vram_scratch.robj == NULL) {
254 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
255 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
256 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
257 NULL, NULL, &adev->vram_scratch.robj);
263 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
264 if (unlikely(r != 0))
266 r = amdgpu_bo_pin(adev->vram_scratch.robj,
267 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
269 amdgpu_bo_unreserve(adev->vram_scratch.robj);
272 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
273 (void **)&adev->vram_scratch.ptr);
275 amdgpu_bo_unpin(adev->vram_scratch.robj);
276 amdgpu_bo_unreserve(adev->vram_scratch.robj);
281 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
285 if (adev->vram_scratch.robj == NULL) {
288 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
289 if (likely(r == 0)) {
290 amdgpu_bo_kunmap(adev->vram_scratch.robj);
291 amdgpu_bo_unpin(adev->vram_scratch.robj);
292 amdgpu_bo_unreserve(adev->vram_scratch.robj);
294 amdgpu_bo_unref(&adev->vram_scratch.robj);
298 * amdgpu_program_register_sequence - program an array of registers.
300 * @adev: amdgpu_device pointer
301 * @registers: pointer to the register array
302 * @array_size: size of the register array
304 * Programs an array or registers with and and or masks.
305 * This is a helper for setting golden registers.
307 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
308 const u32 *registers,
309 const u32 array_size)
311 u32 tmp, reg, and_mask, or_mask;
317 for (i = 0; i < array_size; i +=3) {
318 reg = registers[i + 0];
319 and_mask = registers[i + 1];
320 or_mask = registers[i + 2];
322 if (and_mask == 0xffffffff) {
333 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
335 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
339 * GPU doorbell aperture helpers function.
342 * amdgpu_doorbell_init - Init doorbell driver information.
344 * @adev: amdgpu_device pointer
346 * Init doorbell driver information (CIK)
347 * Returns 0 on success, error on failure.
349 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
351 /* doorbell bar mapping */
352 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
353 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
355 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
356 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
357 if (adev->doorbell.num_doorbells == 0)
360 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
361 if (adev->doorbell.ptr == NULL) {
364 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
365 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
371 * amdgpu_doorbell_fini - Tear down doorbell driver information.
373 * @adev: amdgpu_device pointer
375 * Tear down doorbell driver information (CIK)
377 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
379 iounmap(adev->doorbell.ptr);
380 adev->doorbell.ptr = NULL;
384 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
387 * @adev: amdgpu_device pointer
388 * @aperture_base: output returning doorbell aperture base physical address
389 * @aperture_size: output returning doorbell aperture size in bytes
390 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
392 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
393 * takes doorbells required for its own rings and reports the setup to amdkfd.
394 * amdgpu reserved doorbells are at the start of the doorbell aperture.
396 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
397 phys_addr_t *aperture_base,
398 size_t *aperture_size,
399 size_t *start_offset)
402 * The first num_doorbells are used by amdgpu.
403 * amdkfd takes whatever's left in the aperture.
405 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
406 *aperture_base = adev->doorbell.base;
407 *aperture_size = adev->doorbell.size;
408 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
418 * Writeback is the the method by which the the GPU updates special pages
419 * in memory with the status of certain GPU events (fences, ring pointers,
424 * amdgpu_wb_fini - Disable Writeback and free memory
426 * @adev: amdgpu_device pointer
428 * Disables Writeback and frees the Writeback memory (all asics).
429 * Used at driver shutdown.
431 static void amdgpu_wb_fini(struct amdgpu_device *adev)
433 if (adev->wb.wb_obj) {
434 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
435 amdgpu_bo_kunmap(adev->wb.wb_obj);
436 amdgpu_bo_unpin(adev->wb.wb_obj);
437 amdgpu_bo_unreserve(adev->wb.wb_obj);
439 amdgpu_bo_unref(&adev->wb.wb_obj);
441 adev->wb.wb_obj = NULL;
446 * amdgpu_wb_init- Init Writeback driver info and allocate memory
448 * @adev: amdgpu_device pointer
450 * Disables Writeback and frees the Writeback memory (all asics).
451 * Used at driver startup.
452 * Returns 0 on success or an -error on failure.
454 static int amdgpu_wb_init(struct amdgpu_device *adev)
458 if (adev->wb.wb_obj == NULL) {
459 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
460 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
463 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
466 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
467 if (unlikely(r != 0)) {
468 amdgpu_wb_fini(adev);
471 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
474 amdgpu_bo_unreserve(adev->wb.wb_obj);
475 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
476 amdgpu_wb_fini(adev);
479 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
480 amdgpu_bo_unreserve(adev->wb.wb_obj);
482 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
483 amdgpu_wb_fini(adev);
487 adev->wb.num_wb = AMDGPU_MAX_WB;
488 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
490 /* clear wb memory */
491 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
498 * amdgpu_wb_get - Allocate a wb entry
500 * @adev: amdgpu_device pointer
503 * Allocate a wb slot for use by the driver (all asics).
504 * Returns 0 on success or -EINVAL on failure.
506 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
508 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
509 if (offset < adev->wb.num_wb) {
510 __set_bit(offset, adev->wb.used);
519 * amdgpu_wb_free - Free a wb entry
521 * @adev: amdgpu_device pointer
524 * Free a wb slot allocated for use by the driver (all asics)
526 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
528 if (wb < adev->wb.num_wb)
529 __clear_bit(wb, adev->wb.used);
533 * amdgpu_vram_location - try to find VRAM location
534 * @adev: amdgpu device structure holding all necessary informations
535 * @mc: memory controller structure holding memory informations
536 * @base: base address at which to put VRAM
538 * Function will place try to place VRAM at base address provided
539 * as parameter (which is so far either PCI aperture address or
540 * for IGP TOM base address).
542 * If there is not enough space to fit the unvisible VRAM in the 32bits
543 * address space then we limit the VRAM size to the aperture.
545 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
546 * this shouldn't be a problem as we are using the PCI aperture as a reference.
547 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
550 * Note: we use mc_vram_size as on some board we need to program the mc to
551 * cover the whole aperture even if VRAM size is inferior to aperture size
552 * Novell bug 204882 + along with lots of ubuntu ones
554 * Note: when limiting vram it's safe to overwritte real_vram_size because
555 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
556 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
559 * Note: IGP TOM addr should be the same as the aperture addr, we don't
560 * explicitly check for that thought.
562 * FIXME: when reducing VRAM size align new size on power of 2.
564 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
566 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
568 mc->vram_start = base;
569 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
570 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
571 mc->real_vram_size = mc->aper_size;
572 mc->mc_vram_size = mc->aper_size;
574 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
575 if (limit && limit < mc->real_vram_size)
576 mc->real_vram_size = limit;
577 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
578 mc->mc_vram_size >> 20, mc->vram_start,
579 mc->vram_end, mc->real_vram_size >> 20);
583 * amdgpu_gtt_location - try to find GTT location
584 * @adev: amdgpu device structure holding all necessary informations
585 * @mc: memory controller structure holding memory informations
587 * Function will place try to place GTT before or after VRAM.
589 * If GTT size is bigger than space left then we ajust GTT size.
590 * Thus function will never fails.
592 * FIXME: when reducing GTT size align new size on power of 2.
594 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
596 u64 size_af, size_bf;
598 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
599 size_bf = mc->vram_start & ~mc->gtt_base_align;
600 if (size_bf > size_af) {
601 if (mc->gtt_size > size_bf) {
602 dev_warn(adev->dev, "limiting GTT\n");
603 mc->gtt_size = size_bf;
605 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
607 if (mc->gtt_size > size_af) {
608 dev_warn(adev->dev, "limiting GTT\n");
609 mc->gtt_size = size_af;
611 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
613 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
614 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
615 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
619 * GPU helpers function.
622 * amdgpu_card_posted - check if the hw has already been initialized
624 * @adev: amdgpu_device pointer
626 * Check if the asic has been initialized (all asics).
627 * Used at driver startup.
628 * Returns true if initialized or false if not.
630 bool amdgpu_card_posted(struct amdgpu_device *adev)
634 /* then check MEM_SIZE, in case the crtcs are off */
635 reg = RREG32(mmCONFIG_MEMSIZE);
645 * amdgpu_dummy_page_init - init dummy page used by the driver
647 * @adev: amdgpu_device pointer
649 * Allocate the dummy page used by the driver (all asics).
650 * This dummy page is used by the driver as a filler for gart entries
651 * when pages are taken out of the GART
652 * Returns 0 on sucess, -ENOMEM on failure.
654 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
656 if (adev->dummy_page.page)
658 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
659 if (adev->dummy_page.page == NULL)
661 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
662 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
663 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
664 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
665 __free_page(adev->dummy_page.page);
666 adev->dummy_page.page = NULL;
673 * amdgpu_dummy_page_fini - free dummy page used by the driver
675 * @adev: amdgpu_device pointer
677 * Frees the dummy page used by the driver (all asics).
679 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
681 if (adev->dummy_page.page == NULL)
683 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
684 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
685 __free_page(adev->dummy_page.page);
686 adev->dummy_page.page = NULL;
690 /* ATOM accessor methods */
692 * ATOM is an interpreted byte code stored in tables in the vbios. The
693 * driver registers callbacks to access registers and the interpreter
694 * in the driver parses the tables and executes then to program specific
695 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
696 * atombios.h, and atom.c
700 * cail_pll_read - read PLL register
702 * @info: atom card_info pointer
703 * @reg: PLL register offset
705 * Provides a PLL register accessor for the atom interpreter (r4xx+).
706 * Returns the value of the PLL register.
708 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
714 * cail_pll_write - write PLL register
716 * @info: atom card_info pointer
717 * @reg: PLL register offset
718 * @val: value to write to the pll register
720 * Provides a PLL register accessor for the atom interpreter (r4xx+).
722 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
728 * cail_mc_read - read MC (Memory Controller) register
730 * @info: atom card_info pointer
731 * @reg: MC register offset
733 * Provides an MC register accessor for the atom interpreter (r4xx+).
734 * Returns the value of the MC register.
736 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
742 * cail_mc_write - write MC (Memory Controller) register
744 * @info: atom card_info pointer
745 * @reg: MC register offset
746 * @val: value to write to the pll register
748 * Provides a MC register accessor for the atom interpreter (r4xx+).
750 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
756 * cail_reg_write - write MMIO register
758 * @info: atom card_info pointer
759 * @reg: MMIO register offset
760 * @val: value to write to the pll register
762 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
764 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
766 struct amdgpu_device *adev = info->dev->dev_private;
772 * cail_reg_read - read MMIO register
774 * @info: atom card_info pointer
775 * @reg: MMIO register offset
777 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
778 * Returns the value of the MMIO register.
780 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
782 struct amdgpu_device *adev = info->dev->dev_private;
790 * cail_ioreg_write - write IO register
792 * @info: atom card_info pointer
793 * @reg: IO register offset
794 * @val: value to write to the pll register
796 * Provides a IO register accessor for the atom interpreter (r4xx+).
798 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
800 struct amdgpu_device *adev = info->dev->dev_private;
806 * cail_ioreg_read - read IO register
808 * @info: atom card_info pointer
809 * @reg: IO register offset
811 * Provides an IO register accessor for the atom interpreter (r4xx+).
812 * Returns the value of the IO register.
814 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
816 struct amdgpu_device *adev = info->dev->dev_private;
824 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
826 * @adev: amdgpu_device pointer
828 * Frees the driver info and register access callbacks for the ATOM
829 * interpreter (r4xx+).
830 * Called at driver shutdown.
832 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
834 if (adev->mode_info.atom_context)
835 kfree(adev->mode_info.atom_context->scratch);
836 kfree(adev->mode_info.atom_context);
837 adev->mode_info.atom_context = NULL;
838 kfree(adev->mode_info.atom_card_info);
839 adev->mode_info.atom_card_info = NULL;
843 * amdgpu_atombios_init - init the driver info and callbacks for atombios
845 * @adev: amdgpu_device pointer
847 * Initializes the driver info and register access callbacks for the
848 * ATOM interpreter (r4xx+).
849 * Returns 0 on sucess, -ENOMEM on failure.
850 * Called at driver startup.
852 static int amdgpu_atombios_init(struct amdgpu_device *adev)
854 struct card_info *atom_card_info =
855 kzalloc(sizeof(struct card_info), GFP_KERNEL);
860 adev->mode_info.atom_card_info = atom_card_info;
861 atom_card_info->dev = adev->ddev;
862 atom_card_info->reg_read = cail_reg_read;
863 atom_card_info->reg_write = cail_reg_write;
864 /* needed for iio ops */
866 atom_card_info->ioreg_read = cail_ioreg_read;
867 atom_card_info->ioreg_write = cail_ioreg_write;
869 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
870 atom_card_info->ioreg_read = cail_reg_read;
871 atom_card_info->ioreg_write = cail_reg_write;
873 atom_card_info->mc_read = cail_mc_read;
874 atom_card_info->mc_write = cail_mc_write;
875 atom_card_info->pll_read = cail_pll_read;
876 atom_card_info->pll_write = cail_pll_write;
878 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
879 if (!adev->mode_info.atom_context) {
880 amdgpu_atombios_fini(adev);
884 mutex_init(&adev->mode_info.atom_context->mutex);
885 amdgpu_atombios_scratch_regs_init(adev);
886 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
890 /* if we get transitioned to only one device, take VGA back */
892 * amdgpu_vga_set_decode - enable/disable vga decode
894 * @cookie: amdgpu_device pointer
895 * @state: enable/disable vga decode
897 * Enable/disable vga decode (all asics).
898 * Returns VGA resource flags.
900 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
902 struct amdgpu_device *adev = cookie;
903 amdgpu_asic_set_vga_state(adev, state);
905 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
906 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
908 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
912 * amdgpu_check_pot_argument - check that argument is a power of two
914 * @arg: value to check
916 * Validates that a certain argument is a power of two (all asics).
917 * Returns true if argument is valid.
919 static bool amdgpu_check_pot_argument(int arg)
921 return (arg & (arg - 1)) == 0;
925 * amdgpu_check_arguments - validate module params
927 * @adev: amdgpu_device pointer
929 * Validates certain module parameters and updates
930 * the associated values used by the driver (all asics).
932 static void amdgpu_check_arguments(struct amdgpu_device *adev)
934 if (amdgpu_sched_jobs < 4) {
935 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
937 amdgpu_sched_jobs = 4;
938 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
939 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
941 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
944 if (amdgpu_gart_size != -1) {
945 /* gtt size must be power of two and greater or equal to 32M */
946 if (amdgpu_gart_size < 32) {
947 dev_warn(adev->dev, "gart size (%d) too small\n",
949 amdgpu_gart_size = -1;
950 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
951 dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
953 amdgpu_gart_size = -1;
957 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
958 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
963 if (amdgpu_vm_size < 1) {
964 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
970 * Max GPUVM size for Cayman, SI and CI are 40 bits.
972 if (amdgpu_vm_size > 1024) {
973 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
978 /* defines number of bits in page table versus page directory,
979 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
980 * page table and the remaining bits are in the page directory */
981 if (amdgpu_vm_block_size == -1) {
983 /* Total bits covered by PD + PTs */
984 unsigned bits = ilog2(amdgpu_vm_size) + 18;
986 /* Make sure the PD is 4K in size up to 8GB address space.
987 Above that split equal between PD and PTs */
988 if (amdgpu_vm_size <= 8)
989 amdgpu_vm_block_size = bits - 9;
991 amdgpu_vm_block_size = (bits + 3) / 2;
993 } else if (amdgpu_vm_block_size < 9) {
994 dev_warn(adev->dev, "VM page table size (%d) too small\n",
995 amdgpu_vm_block_size);
996 amdgpu_vm_block_size = 9;
999 if (amdgpu_vm_block_size > 24 ||
1000 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1001 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1002 amdgpu_vm_block_size);
1003 amdgpu_vm_block_size = 9;
1008 * amdgpu_switcheroo_set_state - set switcheroo state
1010 * @pdev: pci dev pointer
1011 * @state: vga_switcheroo state
1013 * Callback for the switcheroo driver. Suspends or resumes the
1014 * the asics before or after it is powered up using ACPI methods.
1016 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1018 struct drm_device *dev = pci_get_drvdata(pdev);
1020 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1023 if (state == VGA_SWITCHEROO_ON) {
1024 unsigned d3_delay = dev->pdev->d3_delay;
1026 printk(KERN_INFO "amdgpu: switched on\n");
1027 /* don't suspend or resume card normally */
1028 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1030 amdgpu_resume_kms(dev, true, true);
1032 dev->pdev->d3_delay = d3_delay;
1034 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1035 drm_kms_helper_poll_enable(dev);
1037 printk(KERN_INFO "amdgpu: switched off\n");
1038 drm_kms_helper_poll_disable(dev);
1039 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1040 amdgpu_suspend_kms(dev, true, true);
1041 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1046 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1048 * @pdev: pci dev pointer
1050 * Callback for the switcheroo driver. Check of the switcheroo
1051 * state can be changed.
1052 * Returns true if the state can be changed, false if not.
1054 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1056 struct drm_device *dev = pci_get_drvdata(pdev);
1059 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1060 * locking inversion with the driver load path. And the access here is
1061 * completely racy anyway. So don't bother with locking for now.
1063 return dev->open_count == 0;
1066 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1067 .set_gpu_state = amdgpu_switcheroo_set_state,
1069 .can_switch = amdgpu_switcheroo_can_switch,
1072 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1073 enum amd_ip_block_type block_type,
1074 enum amd_clockgating_state state)
1078 for (i = 0; i < adev->num_ip_blocks; i++) {
1079 if (adev->ip_blocks[i].type == block_type) {
1080 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1089 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1090 enum amd_ip_block_type block_type,
1091 enum amd_powergating_state state)
1095 for (i = 0; i < adev->num_ip_blocks; i++) {
1096 if (adev->ip_blocks[i].type == block_type) {
1097 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1106 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1107 struct amdgpu_device *adev,
1108 enum amd_ip_block_type type)
1112 for (i = 0; i < adev->num_ip_blocks; i++)
1113 if (adev->ip_blocks[i].type == type)
1114 return &adev->ip_blocks[i];
1120 * amdgpu_ip_block_version_cmp
1122 * @adev: amdgpu_device pointer
1123 * @type: enum amd_ip_block_type
1124 * @major: major version
1125 * @minor: minor version
1127 * return 0 if equal or greater
1128 * return 1 if smaller or the ip_block doesn't exist
1130 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1131 enum amd_ip_block_type type,
1132 u32 major, u32 minor)
1134 const struct amdgpu_ip_block_version *ip_block;
1135 ip_block = amdgpu_get_ip_block(adev, type);
1137 if (ip_block && ((ip_block->major > major) ||
1138 ((ip_block->major == major) &&
1139 (ip_block->minor >= minor))))
1145 static int amdgpu_early_init(struct amdgpu_device *adev)
1149 switch (adev->asic_type) {
1155 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1156 adev->family = AMDGPU_FAMILY_CZ;
1158 adev->family = AMDGPU_FAMILY_VI;
1160 r = vi_set_ip_blocks(adev);
1164 #ifdef CONFIG_DRM_AMDGPU_CIK
1170 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1171 adev->family = AMDGPU_FAMILY_CI;
1173 adev->family = AMDGPU_FAMILY_KV;
1175 r = cik_set_ip_blocks(adev);
1181 /* FIXME: not supported yet */
1185 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1186 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1187 if (adev->ip_block_status == NULL)
1190 if (adev->ip_blocks == NULL) {
1191 DRM_ERROR("No IP blocks found!\n");
1195 for (i = 0; i < adev->num_ip_blocks; i++) {
1196 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1197 DRM_ERROR("disabled ip block: %d\n", i);
1198 adev->ip_block_status[i].valid = false;
1200 if (adev->ip_blocks[i].funcs->early_init) {
1201 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1203 adev->ip_block_status[i].valid = false;
1205 DRM_ERROR("early_init %d failed %d\n", i, r);
1208 adev->ip_block_status[i].valid = true;
1211 adev->ip_block_status[i].valid = true;
1219 static int amdgpu_init(struct amdgpu_device *adev)
1223 for (i = 0; i < adev->num_ip_blocks; i++) {
1224 if (!adev->ip_block_status[i].valid)
1226 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1228 DRM_ERROR("sw_init %d failed %d\n", i, r);
1231 adev->ip_block_status[i].sw = true;
1232 /* need to do gmc hw init early so we can allocate gpu mem */
1233 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1234 r = amdgpu_vram_scratch_init(adev);
1236 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1239 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1241 DRM_ERROR("hw_init %d failed %d\n", i, r);
1244 r = amdgpu_wb_init(adev);
1246 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1249 adev->ip_block_status[i].hw = true;
1253 for (i = 0; i < adev->num_ip_blocks; i++) {
1254 if (!adev->ip_block_status[i].sw)
1256 /* gmc hw init is done early */
1257 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1259 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1261 DRM_ERROR("hw_init %d failed %d\n", i, r);
1264 adev->ip_block_status[i].hw = true;
1270 static int amdgpu_late_init(struct amdgpu_device *adev)
1274 for (i = 0; i < adev->num_ip_blocks; i++) {
1275 if (!adev->ip_block_status[i].valid)
1277 /* enable clockgating to save power */
1278 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1281 DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
1284 if (adev->ip_blocks[i].funcs->late_init) {
1285 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1287 DRM_ERROR("late_init %d failed %d\n", i, r);
1296 static int amdgpu_fini(struct amdgpu_device *adev)
1300 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1301 if (!adev->ip_block_status[i].hw)
1303 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1304 amdgpu_wb_fini(adev);
1305 amdgpu_vram_scratch_fini(adev);
1307 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1308 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1309 AMD_CG_STATE_UNGATE);
1311 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1314 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1315 /* XXX handle errors */
1317 DRM_DEBUG("hw_fini %d failed %d\n", i, r);
1319 adev->ip_block_status[i].hw = false;
1322 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1323 if (!adev->ip_block_status[i].sw)
1325 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1326 /* XXX handle errors */
1328 DRM_DEBUG("sw_fini %d failed %d\n", i, r);
1330 adev->ip_block_status[i].sw = false;
1331 adev->ip_block_status[i].valid = false;
1337 static int amdgpu_suspend(struct amdgpu_device *adev)
1341 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1342 if (!adev->ip_block_status[i].valid)
1344 /* ungate blocks so that suspend can properly shut them down */
1345 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1346 AMD_CG_STATE_UNGATE);
1348 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1350 /* XXX handle errors */
1351 r = adev->ip_blocks[i].funcs->suspend(adev);
1352 /* XXX handle errors */
1354 DRM_ERROR("suspend %d failed %d\n", i, r);
1361 static int amdgpu_resume(struct amdgpu_device *adev)
1365 for (i = 0; i < adev->num_ip_blocks; i++) {
1366 if (!adev->ip_block_status[i].valid)
1368 r = adev->ip_blocks[i].funcs->resume(adev);
1370 DRM_ERROR("resume %d failed %d\n", i, r);
1379 * amdgpu_device_init - initialize the driver
1381 * @adev: amdgpu_device pointer
1382 * @pdev: drm dev pointer
1383 * @pdev: pci dev pointer
1384 * @flags: driver flags
1386 * Initializes the driver info and hw (all asics).
1387 * Returns 0 for success or an error on failure.
1388 * Called at driver startup.
1390 int amdgpu_device_init(struct amdgpu_device *adev,
1391 struct drm_device *ddev,
1392 struct pci_dev *pdev,
1396 bool runtime = false;
1398 adev->shutdown = false;
1399 adev->dev = &pdev->dev;
1402 adev->flags = flags;
1403 adev->asic_type = flags & AMD_ASIC_MASK;
1404 adev->is_atom_bios = false;
1405 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1406 adev->mc.gtt_size = 512 * 1024 * 1024;
1407 adev->accel_working = false;
1408 adev->num_rings = 0;
1409 adev->mman.buffer_funcs = NULL;
1410 adev->mman.buffer_funcs_ring = NULL;
1411 adev->vm_manager.vm_pte_funcs = NULL;
1412 adev->vm_manager.vm_pte_num_rings = 0;
1413 adev->gart.gart_funcs = NULL;
1414 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1416 adev->smc_rreg = &amdgpu_invalid_rreg;
1417 adev->smc_wreg = &amdgpu_invalid_wreg;
1418 adev->pcie_rreg = &amdgpu_invalid_rreg;
1419 adev->pcie_wreg = &amdgpu_invalid_wreg;
1420 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1421 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1422 adev->didt_rreg = &amdgpu_invalid_rreg;
1423 adev->didt_wreg = &amdgpu_invalid_wreg;
1424 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1425 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1427 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1428 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1429 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1431 /* mutex initialization are all done here so we
1432 * can recall function without having locking issues */
1433 mutex_init(&adev->vm_manager.lock);
1434 atomic_set(&adev->irq.ih.lock, 0);
1435 mutex_init(&adev->pm.mutex);
1436 mutex_init(&adev->gfx.gpu_clock_mutex);
1437 mutex_init(&adev->srbm_mutex);
1438 mutex_init(&adev->grbm_idx_mutex);
1439 mutex_init(&adev->mn_lock);
1440 hash_init(adev->mn_hash);
1442 amdgpu_check_arguments(adev);
1444 /* Registers mapping */
1445 /* TODO: block userspace mapping of io register */
1446 spin_lock_init(&adev->mmio_idx_lock);
1447 spin_lock_init(&adev->smc_idx_lock);
1448 spin_lock_init(&adev->pcie_idx_lock);
1449 spin_lock_init(&adev->uvd_ctx_idx_lock);
1450 spin_lock_init(&adev->didt_idx_lock);
1451 spin_lock_init(&adev->audio_endpt_idx_lock);
1453 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1454 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1455 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1456 if (adev->rmmio == NULL) {
1459 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1460 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1462 /* doorbell bar mapping */
1463 amdgpu_doorbell_init(adev);
1465 /* io port mapping */
1466 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1467 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1468 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1469 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1473 if (adev->rio_mem == NULL)
1474 DRM_ERROR("Unable to find PCI I/O BAR\n");
1476 /* early init functions */
1477 r = amdgpu_early_init(adev);
1481 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1482 /* this will fail for cards that aren't VGA class devices, just
1484 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1486 if (amdgpu_runtime_pm == 1)
1488 if (amdgpu_device_is_px(ddev) && amdgpu_has_atpx_dgpu_power_cntl())
1490 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1492 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1495 if (!amdgpu_get_bios(adev))
1497 /* Must be an ATOMBIOS */
1498 if (!adev->is_atom_bios) {
1499 dev_err(adev->dev, "Expecting atombios for GPU\n");
1502 r = amdgpu_atombios_init(adev);
1504 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1508 /* See if the asic supports SR-IOV */
1509 adev->virtualization.supports_sr_iov =
1510 amdgpu_atombios_has_gpu_virtualization_table(adev);
1512 /* Post card if necessary */
1513 if (!amdgpu_card_posted(adev) ||
1514 adev->virtualization.supports_sr_iov) {
1516 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1519 DRM_INFO("GPU not posted. posting now...\n");
1520 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1523 /* Initialize clocks */
1524 r = amdgpu_atombios_get_clock_info(adev);
1526 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1529 /* init i2c buses */
1530 amdgpu_atombios_i2c_init(adev);
1533 r = amdgpu_fence_driver_init(adev);
1535 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1539 /* init the mode config */
1540 drm_mode_config_init(adev->ddev);
1542 r = amdgpu_init(adev);
1544 dev_err(adev->dev, "amdgpu_init failed\n");
1549 adev->accel_working = true;
1551 amdgpu_fbdev_init(adev);
1553 r = amdgpu_ib_pool_init(adev);
1555 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1559 r = amdgpu_ib_ring_tests(adev);
1561 DRM_ERROR("ib ring test failed (%d).\n", r);
1563 r = amdgpu_gem_debugfs_init(adev);
1565 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1568 r = amdgpu_debugfs_regs_init(adev);
1570 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1573 if ((amdgpu_testing & 1)) {
1574 if (adev->accel_working)
1575 amdgpu_test_moves(adev);
1577 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1579 if ((amdgpu_testing & 2)) {
1580 if (adev->accel_working)
1581 amdgpu_test_syncing(adev);
1583 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1585 if (amdgpu_benchmarking) {
1586 if (adev->accel_working)
1587 amdgpu_benchmark(adev, amdgpu_benchmarking);
1589 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1592 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1593 * explicit gating rather than handling it automatically.
1595 r = amdgpu_late_init(adev);
1597 dev_err(adev->dev, "amdgpu_late_init failed\n");
1604 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1607 * amdgpu_device_fini - tear down the driver
1609 * @adev: amdgpu_device pointer
1611 * Tear down the driver info (all asics).
1612 * Called at driver shutdown.
1614 void amdgpu_device_fini(struct amdgpu_device *adev)
1618 DRM_INFO("amdgpu: finishing device.\n");
1619 adev->shutdown = true;
1620 /* evict vram memory */
1621 amdgpu_bo_evict_vram(adev);
1622 amdgpu_ib_pool_fini(adev);
1623 amdgpu_fence_driver_fini(adev);
1624 amdgpu_fbdev_fini(adev);
1625 r = amdgpu_fini(adev);
1626 kfree(adev->ip_block_status);
1627 adev->ip_block_status = NULL;
1628 adev->accel_working = false;
1629 /* free i2c buses */
1630 amdgpu_i2c_fini(adev);
1631 amdgpu_atombios_fini(adev);
1634 vga_switcheroo_unregister_client(adev->pdev);
1635 vga_client_register(adev->pdev, NULL, NULL, NULL);
1637 pci_iounmap(adev->pdev, adev->rio_mem);
1638 adev->rio_mem = NULL;
1639 iounmap(adev->rmmio);
1641 amdgpu_doorbell_fini(adev);
1642 amdgpu_debugfs_regs_cleanup(adev);
1643 amdgpu_debugfs_remove_files(adev);
1651 * amdgpu_suspend_kms - initiate device suspend
1653 * @pdev: drm dev pointer
1654 * @state: suspend state
1656 * Puts the hw in the suspend state (all asics).
1657 * Returns 0 for success or an error on failure.
1658 * Called at driver suspend.
1660 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1662 struct amdgpu_device *adev;
1663 struct drm_crtc *crtc;
1664 struct drm_connector *connector;
1667 if (dev == NULL || dev->dev_private == NULL) {
1671 adev = dev->dev_private;
1673 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1676 drm_kms_helper_poll_disable(dev);
1678 /* turn off display hw */
1679 drm_modeset_lock_all(dev);
1680 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1681 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1683 drm_modeset_unlock_all(dev);
1685 /* unpin the front buffers and cursors */
1686 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1687 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1688 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1689 struct amdgpu_bo *robj;
1691 if (amdgpu_crtc->cursor_bo) {
1692 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1693 r = amdgpu_bo_reserve(aobj, false);
1695 amdgpu_bo_unpin(aobj);
1696 amdgpu_bo_unreserve(aobj);
1700 if (rfb == NULL || rfb->obj == NULL) {
1703 robj = gem_to_amdgpu_bo(rfb->obj);
1704 /* don't unpin kernel fb objects */
1705 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1706 r = amdgpu_bo_reserve(robj, false);
1708 amdgpu_bo_unpin(robj);
1709 amdgpu_bo_unreserve(robj);
1713 /* evict vram memory */
1714 amdgpu_bo_evict_vram(adev);
1716 amdgpu_fence_driver_suspend(adev);
1718 r = amdgpu_suspend(adev);
1720 /* evict remaining vram memory */
1721 amdgpu_bo_evict_vram(adev);
1723 pci_save_state(dev->pdev);
1725 /* Shut down the device */
1726 pci_disable_device(dev->pdev);
1727 pci_set_power_state(dev->pdev, PCI_D3hot);
1732 amdgpu_fbdev_set_suspend(adev, 1);
1739 * amdgpu_resume_kms - initiate device resume
1741 * @pdev: drm dev pointer
1743 * Bring the hw back to operating state (all asics).
1744 * Returns 0 for success or an error on failure.
1745 * Called at driver resume.
1747 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1749 struct drm_connector *connector;
1750 struct amdgpu_device *adev = dev->dev_private;
1751 struct drm_crtc *crtc;
1754 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1761 pci_set_power_state(dev->pdev, PCI_D0);
1762 pci_restore_state(dev->pdev);
1763 if (pci_enable_device(dev->pdev)) {
1771 if (!amdgpu_card_posted(adev))
1772 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1774 r = amdgpu_resume(adev);
1776 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1778 amdgpu_fence_driver_resume(adev);
1781 r = amdgpu_ib_ring_tests(adev);
1783 DRM_ERROR("ib ring test failed (%d).\n", r);
1786 r = amdgpu_late_init(adev);
1791 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1792 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1794 if (amdgpu_crtc->cursor_bo) {
1795 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1796 r = amdgpu_bo_reserve(aobj, false);
1798 r = amdgpu_bo_pin(aobj,
1799 AMDGPU_GEM_DOMAIN_VRAM,
1800 &amdgpu_crtc->cursor_addr);
1802 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1803 amdgpu_bo_unreserve(aobj);
1808 /* blat the mode back in */
1810 drm_helper_resume_force_mode(dev);
1811 /* turn on display hw */
1812 drm_modeset_lock_all(dev);
1813 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1814 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1816 drm_modeset_unlock_all(dev);
1819 drm_kms_helper_poll_enable(dev);
1820 drm_helper_hpd_irq_event(dev);
1823 amdgpu_fbdev_set_suspend(adev, 0);
1831 * amdgpu_gpu_reset - reset the asic
1833 * @adev: amdgpu device pointer
1835 * Attempt the reset the GPU if it has hung (all asics).
1836 * Returns 0 for success or an error on failure.
1838 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1840 unsigned ring_sizes[AMDGPU_MAX_RINGS];
1841 uint32_t *ring_data[AMDGPU_MAX_RINGS];
1848 atomic_inc(&adev->gpu_reset_counter);
1851 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1853 r = amdgpu_suspend(adev);
1855 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1856 struct amdgpu_ring *ring = adev->rings[i];
1860 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1861 if (ring_sizes[i]) {
1863 dev_info(adev->dev, "Saved %d dwords of commands "
1864 "on ring %d.\n", ring_sizes[i], i);
1869 r = amdgpu_asic_reset(adev);
1871 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1874 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1875 r = amdgpu_resume(adev);
1879 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1880 struct amdgpu_ring *ring = adev->rings[i];
1884 amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1886 ring_data[i] = NULL;
1889 r = amdgpu_ib_ring_tests(adev);
1891 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1894 r = amdgpu_suspend(adev);
1899 amdgpu_fence_driver_force_completion(adev);
1900 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1902 kfree(ring_data[i]);
1906 drm_helper_resume_force_mode(adev->ddev);
1908 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1910 /* bad news, how to tell it to userspace ? */
1911 dev_info(adev->dev, "GPU reset failed\n");
1917 #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1918 #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1920 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1925 if (amdgpu_pcie_gen_cap)
1926 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1928 if (amdgpu_pcie_lane_cap)
1929 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1931 /* covers APUs as well */
1932 if (pci_is_root_bus(adev->pdev->bus)) {
1933 if (adev->pm.pcie_gen_mask == 0)
1934 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1935 if (adev->pm.pcie_mlw_mask == 0)
1936 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1940 if (adev->pm.pcie_gen_mask == 0) {
1941 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1943 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1944 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1945 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1947 if (mask & DRM_PCIE_SPEED_25)
1948 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1949 if (mask & DRM_PCIE_SPEED_50)
1950 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1951 if (mask & DRM_PCIE_SPEED_80)
1952 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1954 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1957 if (adev->pm.pcie_mlw_mask == 0) {
1958 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1962 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1963 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1964 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1965 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1966 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1967 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1971 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1972 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1975 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1976 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1979 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1980 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1986 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1989 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1992 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1997 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1998 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2001 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2007 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2015 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2016 struct drm_info_list *files,
2021 for (i = 0; i < adev->debugfs_count; i++) {
2022 if (adev->debugfs[i].files == files) {
2023 /* Already registered */
2028 i = adev->debugfs_count + 1;
2029 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2030 DRM_ERROR("Reached maximum number of debugfs components.\n");
2031 DRM_ERROR("Report so we increase "
2032 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2035 adev->debugfs[adev->debugfs_count].files = files;
2036 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2037 adev->debugfs_count = i;
2038 #if defined(CONFIG_DEBUG_FS)
2039 drm_debugfs_create_files(files, nfiles,
2040 adev->ddev->control->debugfs_root,
2041 adev->ddev->control);
2042 drm_debugfs_create_files(files, nfiles,
2043 adev->ddev->primary->debugfs_root,
2044 adev->ddev->primary);
2049 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2051 #if defined(CONFIG_DEBUG_FS)
2054 for (i = 0; i < adev->debugfs_count; i++) {
2055 drm_debugfs_remove_files(adev->debugfs[i].files,
2056 adev->debugfs[i].num_files,
2057 adev->ddev->control);
2058 drm_debugfs_remove_files(adev->debugfs[i].files,
2059 adev->debugfs[i].num_files,
2060 adev->ddev->primary);
2065 #if defined(CONFIG_DEBUG_FS)
2067 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2068 size_t size, loff_t *pos)
2070 struct amdgpu_device *adev = f->f_inode->i_private;
2074 if (size & 0x3 || *pos & 0x3)
2080 if (*pos > adev->rmmio_size)
2083 value = RREG32(*pos >> 2);
2084 r = put_user(value, (uint32_t *)buf);
2097 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2098 size_t size, loff_t *pos)
2100 struct amdgpu_device *adev = f->f_inode->i_private;
2104 if (size & 0x3 || *pos & 0x3)
2110 if (*pos > adev->rmmio_size)
2113 r = get_user(value, (uint32_t *)buf);
2117 WREG32(*pos >> 2, value);
2128 static const struct file_operations amdgpu_debugfs_regs_fops = {
2129 .owner = THIS_MODULE,
2130 .read = amdgpu_debugfs_regs_read,
2131 .write = amdgpu_debugfs_regs_write,
2132 .llseek = default_llseek
2135 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2137 struct drm_minor *minor = adev->ddev->primary;
2138 struct dentry *ent, *root = minor->debugfs_root;
2140 ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2141 adev, &amdgpu_debugfs_regs_fops);
2143 return PTR_ERR(ent);
2144 i_size_write(ent->d_inode, adev->rmmio_size);
2145 adev->debugfs_regs = ent;
2150 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2152 debugfs_remove(adev->debugfs_regs);
2153 adev->debugfs_regs = NULL;
2156 int amdgpu_debugfs_init(struct drm_minor *minor)
2161 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2165 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2169 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }