drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amdgpu_atomfirmware.h"
  44 #include "amd_pcie.h"
  45 #ifdef CONFIG_DRM_AMDGPU_SI
  46 #include "si.h"
  47 #endif
  48 #ifdef CONFIG_DRM_AMDGPU_CIK
  49 #include "cik.h"
  50 #endif
  51 #include "vi.h"
  52 #include "soc15.h"
  53 #include "bif/bif_4_1_d.h"
  54 #include <linux/pci.h>
  55 #include <linux/firmware.h>
  56 #include "amdgpu_vf_error.h"
  57
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_pm.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  63
  64 #define AMDGPU_RESUME_MS                2000
  65
  66 static const char *amdgpu_asic_name[] = {
  67         "TAHITI",
  68         "PITCAIRN",
  69         "VERDE",
  70         "OLAND",
  71         "HAINAN",
  72         "BONAIRE",
  73         "KAVERI",
  74         "KABINI",
  75         "HAWAII",
  76         "MULLINS",
  77         "TOPAZ",
  78         "TONGA",
  79         "FIJI",
  80         "CARRIZO",
  81         "STONEY",
  82         "POLARIS10",
  83         "POLARIS11",
  84         "POLARIS12",
  85         "VEGA10",
  86         "RAVEN",
  87         "LAST",
  88 };
  89
  90 bool amdgpu_device_is_px(struct drm_device *dev)
  91 {
  92         struct amdgpu_device *adev = dev->dev_private;
  93
  94         if (adev->flags & AMD_IS_PX)
  95                 return true;
  96         return false;
  97 }
  98
  99 /*
 100  * MMIO register access helper functions.
 101  */
 102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 103                         uint32_t acc_flags)
 104 {
 105         uint32_t ret;
 106
 107         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 108                 return amdgpu_virt_kiq_rreg(adev, reg);
 109
 110         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 111                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 112         else {
 113                 unsigned long flags;
 114
 115                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 116                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 117                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 118                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 119         }
 120         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 121         return ret;
 122 }
 123
 124 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 125                     uint32_t acc_flags)
 126 {
 127         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 128
 129         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 130                 adev->last_mm_index = v;
 131         }
 132
 133         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 134                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 135
 136         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 137                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 138         else {
 139                 unsigned long flags;
 140
 141                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 142                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 143                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 144                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 145         }
 146
 147         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 148                 udelay(500);
 149         }
 150 }
 151
 152 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 153 {
 154         if ((reg * 4) < adev->rio_mem_size)
 155                 return ioread32(adev->rio_mem + (reg * 4));
 156         else {
 157                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 158                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 159         }
 160 }
 161
 162 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 163 {
 164         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 165                 adev->last_mm_index = v;
 166         }
 167
 168         if ((reg * 4) < adev->rio_mem_size)
 169                 iowrite32(v, adev->rio_mem + (reg * 4));
 170         else {
 171                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 172                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 173         }
 174
 175         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 176                 udelay(500);
 177         }
 178 }
 179
 180 /**
 181  * amdgpu_mm_rdoorbell - read a doorbell dword
 182  *
 183  * @adev: amdgpu_device pointer
 184  * @index: doorbell index
 185  *
 186  * Returns the value in the doorbell aperture at the
 187  * requested doorbell index (CIK).
 188  */
 189 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 190 {
 191         if (index < adev->doorbell.num_doorbells) {
 192                 return readl(adev->doorbell.ptr + index);
 193         } else {
 194                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 195                 return 0;
 196         }
 197 }
 198
 199 /**
 200  * amdgpu_mm_wdoorbell - write a doorbell dword
 201  *
 202  * @adev: amdgpu_device pointer
 203  * @index: doorbell index
 204  * @v: value to write
 205  *
 206  * Writes @v to the doorbell aperture at the
 207  * requested doorbell index (CIK).
 208  */
 209 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 210 {
 211         if (index < adev->doorbell.num_doorbells) {
 212                 writel(v, adev->doorbell.ptr + index);
 213         } else {
 214                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 215         }
 216 }
 217
 218 /**
 219  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 220  *
 221  * @adev: amdgpu_device pointer
 222  * @index: doorbell index
 223  *
 224  * Returns the value in the doorbell aperture at the
 225  * requested doorbell index (VEGA10+).
 226  */
 227 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 228 {
 229         if (index < adev->doorbell.num_doorbells) {
 230                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 231         } else {
 232                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 233                 return 0;
 234         }
 235 }
 236
 237 /**
 238  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 239  *
 240  * @adev: amdgpu_device pointer
 241  * @index: doorbell index
 242  * @v: value to write
 243  *
 244  * Writes @v to the doorbell aperture at the
 245  * requested doorbell index (VEGA10+).
 246  */
 247 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 248 {
 249         if (index < adev->doorbell.num_doorbells) {
 250                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 251         } else {
 252                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 253         }
 254 }
 255
 256 /**
 257  * amdgpu_invalid_rreg - dummy reg read function
 258  *
 259  * @adev: amdgpu device pointer
 260  * @reg: offset of register
 261  *
 262  * Dummy register read function.  Used for register blocks
 263  * that certain asics don't have (all asics).
 264  * Returns the value in the register.
 265  */
 266 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 267 {
 268         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 269         BUG();
 270         return 0;
 271 }
 272
 273 /**
 274  * amdgpu_invalid_wreg - dummy reg write function
 275  *
 276  * @adev: amdgpu device pointer
 277  * @reg: offset of register
 278  * @v: value to write to the register
 279  *
 280  * Dummy register read function.  Used for register blocks
 281  * that certain asics don't have (all asics).
 282  */
 283 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 284 {
 285         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 286                   reg, v);
 287         BUG();
 288 }
 289
 290 /**
 291  * amdgpu_block_invalid_rreg - dummy reg read function
 292  *
 293  * @adev: amdgpu device pointer
 294  * @block: offset of instance
 295  * @reg: offset of register
 296  *
 297  * Dummy register read function.  Used for register blocks
 298  * that certain asics don't have (all asics).
 299  * Returns the value in the register.
 300  */
 301 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 302                                           uint32_t block, uint32_t reg)
 303 {
 304         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 305                   reg, block);
 306         BUG();
 307         return 0;
 308 }
 309
 310 /**
 311  * amdgpu_block_invalid_wreg - dummy reg write function
 312  *
 313  * @adev: amdgpu device pointer
 314  * @block: offset of instance
 315  * @reg: offset of register
 316  * @v: value to write to the register
 317  *
 318  * Dummy register read function.  Used for register blocks
 319  * that certain asics don't have (all asics).
 320  */
 321 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 322                                       uint32_t block,
 323                                       uint32_t reg, uint32_t v)
 324 {
 325         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 326                   reg, block, v);
 327         BUG();
 328 }
 329
 330 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 331 {
 332         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 333                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 334                                        &adev->vram_scratch.robj,
 335                                        &adev->vram_scratch.gpu_addr,
 336                                        (void **)&adev->vram_scratch.ptr);
 337 }
 338
 339 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 340 {
 341         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 342 }
 343
 344 /**
 345  * amdgpu_device_program_register_sequence - program an array of registers.
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @registers: pointer to the register array
 349  * @array_size: size of the register array
 350  *
 351  * Programs an array or registers with and and or masks.
 352  * This is a helper for setting golden registers.
 353  */
 354 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 355                                              const u32 *registers,
 356                                              const u32 array_size)
 357 {
 358         u32 tmp, reg, and_mask, or_mask;
 359         int i;
 360
 361         if (array_size % 3)
 362                 return;
 363
 364         for (i = 0; i < array_size; i +=3) {
 365                 reg = registers[i + 0];
 366                 and_mask = registers[i + 1];
 367                 or_mask = registers[i + 2];
 368
 369                 if (and_mask == 0xffffffff) {
 370                         tmp = or_mask;
 371                 } else {
 372                         tmp = RREG32(reg);
 373                         tmp &= ~and_mask;
 374                         tmp |= or_mask;
 375                 }
 376                 WREG32(reg, tmp);
 377         }
 378 }
 379
 380 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 381 {
 382         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 383 }
 384
 385 /*
 386  * GPU doorbell aperture helpers function.
 387  */
 388 /**
 389  * amdgpu_device_doorbell_init - Init doorbell driver information.
 390  *
 391  * @adev: amdgpu_device pointer
 392  *
 393  * Init doorbell driver information (CIK)
 394  * Returns 0 on success, error on failure.
 395  */
 396 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 397 {
 398         /* No doorbell on SI hardware generation */
 399         if (adev->asic_type < CHIP_BONAIRE) {
 400                 adev->doorbell.base = 0;
 401                 adev->doorbell.size = 0;
 402                 adev->doorbell.num_doorbells = 0;
 403                 adev->doorbell.ptr = NULL;
 404                 return 0;
 405         }
 406
 407         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 408                 return -EINVAL;
 409
 410         /* doorbell bar mapping */
 411         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 412         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 413
 414         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 415                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 416         if (adev->doorbell.num_doorbells == 0)
 417                 return -EINVAL;
 418
 419         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 420                                      adev->doorbell.num_doorbells *
 421                                      sizeof(u32));
 422         if (adev->doorbell.ptr == NULL)
 423                 return -ENOMEM;
 424
 425         return 0;
 426 }
 427
 428 /**
 429  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 430  *
 431  * @adev: amdgpu_device pointer
 432  *
 433  * Tear down doorbell driver information (CIK)
 434  */
 435 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 436 {
 437         iounmap(adev->doorbell.ptr);
 438         adev->doorbell.ptr = NULL;
 439 }
 440
 441
 442
 443 /*
 444  * amdgpu_device_wb_*()
 445  * Writeback is the method by which the GPU updates special pages in memory
 446  * with the status of certain GPU events (fences, ring pointers,etc.).
 447  */
 448
 449 /**
 450  * amdgpu_device_wb_fini - Disable Writeback and free memory
 451  *
 452  * @adev: amdgpu_device pointer
 453  *
 454  * Disables Writeback and frees the Writeback memory (all asics).
 455  * Used at driver shutdown.
 456  */
 457 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 458 {
 459         if (adev->wb.wb_obj) {
 460                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 461                                       &adev->wb.gpu_addr,
 462                                       (void **)&adev->wb.wb);
 463                 adev->wb.wb_obj = NULL;
 464         }
 465 }
 466
 467 /**
 468  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 469  *
 470  * @adev: amdgpu_device pointer
 471  *
 472  * Initializes writeback and allocates writeback memory (all asics).
 473  * Used at driver startup.
 474  * Returns 0 on success or an -error on failure.
 475  */
 476 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 477 {
 478         int r;
 479
 480         if (adev->wb.wb_obj == NULL) {
 481                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 482                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 483                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 484                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 485                                             (void **)&adev->wb.wb);
 486                 if (r) {
 487                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 488                         return r;
 489                 }
 490
 491                 adev->wb.num_wb = AMDGPU_MAX_WB;
 492                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 493
 494                 /* clear wb memory */
 495                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 496         }
 497
 498         return 0;
 499 }
 500
 501 /**
 502  * amdgpu_device_wb_get - Allocate a wb entry
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @wb: wb index
 506  *
 507  * Allocate a wb slot for use by the driver (all asics).
 508  * Returns 0 on success or -EINVAL on failure.
 509  */
 510 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 511 {
 512         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 513
 514         if (offset < adev->wb.num_wb) {
 515                 __set_bit(offset, adev->wb.used);
 516                 *wb = offset << 3; /* convert to dw offset */
 517                 return 0;
 518         } else {
 519                 return -EINVAL;
 520         }
 521 }
 522
 523 /**
 524  * amdgpu_device_wb_free - Free a wb entry
 525  *
 526  * @adev: amdgpu_device pointer
 527  * @wb: wb index
 528  *
 529  * Free a wb slot allocated for use by the driver (all asics)
 530  */
 531 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 532 {
 533         wb >>= 3;
 534         if (wb < adev->wb.num_wb)
 535                 __clear_bit(wb, adev->wb.used);
 536 }
 537
 538 /**
 539  * amdgpu_device_vram_location - try to find VRAM location
 540  * @adev: amdgpu device structure holding all necessary informations
 541  * @mc: memory controller structure holding memory informations
 542  * @base: base address at which to put VRAM
 543  *
 544  * Function will try to place VRAM at base address provided
 545  * as parameter.
 546  */
 547 void amdgpu_device_vram_location(struct amdgpu_device *adev,
 548                                  struct amdgpu_gmc *mc, u64 base)
 549 {
 550         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 551
 552         mc->vram_start = base;
 553         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 554         if (limit && limit < mc->real_vram_size)
 555                 mc->real_vram_size = limit;
 556         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 557                         mc->mc_vram_size >> 20, mc->vram_start,
 558                         mc->vram_end, mc->real_vram_size >> 20);
 559 }
 560
 561 /**
 562  * amdgpu_device_gart_location - try to find GTT location
 563  * @adev: amdgpu device structure holding all necessary informations
 564  * @mc: memory controller structure holding memory informations
 565  *
 566  * Function will place try to place GTT before or after VRAM.
 567  *
 568  * If GTT size is bigger than space left then we ajust GTT size.
 569  * Thus function will never fails.
 570  *
 571  * FIXME: when reducing GTT size align new size on power of 2.
 572  */
 573 void amdgpu_device_gart_location(struct amdgpu_device *adev,
 574                                  struct amdgpu_gmc *mc)
 575 {
 576         u64 size_af, size_bf;
 577
 578         size_af = adev->gmc.mc_mask - mc->vram_end;
 579         size_bf = mc->vram_start;
 580         if (size_bf > size_af) {
 581                 if (mc->gart_size > size_bf) {
 582                         dev_warn(adev->dev, "limiting GTT\n");
 583                         mc->gart_size = size_bf;
 584                 }
 585                 mc->gart_start = 0;
 586         } else {
 587                 if (mc->gart_size > size_af) {
 588                         dev_warn(adev->dev, "limiting GTT\n");
 589                         mc->gart_size = size_af;
 590                 }
 591                 /* VCE doesn't like it when BOs cross a 4GB segment, so align
 592                  * the GART base on a 4GB boundary as well.
 593                  */
 594                 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
 595         }
 596         mc->gart_end = mc->gart_start + mc->gart_size - 1;
 597         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 598                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 599 }
 600
 601 /**
 602  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 603  *
 604  * @adev: amdgpu_device pointer
 605  *
 606  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 607  * to fail, but if any of the BARs is not accessible after the size we abort
 608  * driver loading by returning -ENODEV.
 609  */
 610 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 611 {
 612         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 613         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 614         struct pci_bus *root;
 615         struct resource *res;
 616         unsigned i;
 617         u16 cmd;
 618         int r;
 619
 620         /* Bypass for VF */
 621         if (amdgpu_sriov_vf(adev))
 622                 return 0;
 623
 624         /* Check if the root BUS has 64bit memory resources */
 625         root = adev->pdev->bus;
 626         while (root->parent)
 627                 root = root->parent;
 628
 629         pci_bus_for_each_resource(root, res, i) {
 630                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 631                     res->start > 0x100000000ull)
 632                         break;
 633         }
 634
 635         /* Trying to resize is pointless without a root hub window above 4GB */
 636         if (!res)
 637                 return 0;
 638
 639         /* Disable memory decoding while we change the BAR addresses and size */
 640         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 641         pci_write_config_word(adev->pdev, PCI_COMMAND,
 642                               cmd & ~PCI_COMMAND_MEMORY);
 643
 644         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 645         amdgpu_device_doorbell_fini(adev);
 646         if (adev->asic_type >= CHIP_BONAIRE)
 647                 pci_release_resource(adev->pdev, 2);
 648
 649         pci_release_resource(adev->pdev, 0);
 650
 651         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 652         if (r == -ENOSPC)
 653                 DRM_INFO("Not enough PCI address space for a large BAR.");
 654         else if (r && r != -ENOTSUPP)
 655                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 656
 657         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 658
 659         /* When the doorbell or fb BAR isn't available we have no chance of
 660          * using the device.
 661          */
 662         r = amdgpu_device_doorbell_init(adev);
 663         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 664                 return -ENODEV;
 665
 666         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 667
 668         return 0;
 669 }
 670
 671 /*
 672  * GPU helpers function.
 673  */
 674 /**
 675  * amdgpu_device_need_post - check if the hw need post or not
 676  *
 677  * @adev: amdgpu_device pointer
 678  *
 679  * Check if the asic has been initialized (all asics) at driver startup
 680  * or post is needed if  hw reset is performed.
 681  * Returns true if need or false if not.
 682  */
 683 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 684 {
 685         uint32_t reg;
 686
 687         if (amdgpu_sriov_vf(adev))
 688                 return false;
 689
 690         if (amdgpu_passthrough(adev)) {
 691                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 692                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 693                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 694                  * vpost executed for smc version below 22.15
 695                  */
 696                 if (adev->asic_type == CHIP_FIJI) {
 697                         int err;
 698                         uint32_t fw_ver;
 699                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 700                         /* force vPost if error occured */
 701                         if (err)
 702                                 return true;
 703
 704                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 705                         if (fw_ver < 0x00160e00)
 706                                 return true;
 707                 }
 708         }
 709
 710         if (adev->has_hw_reset) {
 711                 adev->has_hw_reset = false;
 712                 return true;
 713         }
 714
 715         /* bios scratch used on CIK+ */
 716         if (adev->asic_type >= CHIP_BONAIRE)
 717                 return amdgpu_atombios_scratch_need_asic_init(adev);
 718
 719         /* check MEM_SIZE for older asics */
 720         reg = amdgpu_asic_get_config_memsize(adev);
 721
 722         if ((reg != 0) && (reg != 0xffffffff))
 723                 return false;
 724
 725         return true;
 726 }
 727
 728 /* if we get transitioned to only one device, take VGA back */
 729 /**
 730  * amdgpu_device_vga_set_decode - enable/disable vga decode
 731  *
 732  * @cookie: amdgpu_device pointer
 733  * @state: enable/disable vga decode
 734  *
 735  * Enable/disable vga decode (all asics).
 736  * Returns VGA resource flags.
 737  */
 738 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 739 {
 740         struct amdgpu_device *adev = cookie;
 741         amdgpu_asic_set_vga_state(adev, state);
 742         if (state)
 743                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 744                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 745         else
 746                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 747 }
 748
 749 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 750 {
 751         /* defines number of bits in page table versus page directory,
 752          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 753          * page table and the remaining bits are in the page directory */
 754         if (amdgpu_vm_block_size == -1)
 755                 return;
 756
 757         if (amdgpu_vm_block_size < 9) {
 758                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 759                          amdgpu_vm_block_size);
 760                 amdgpu_vm_block_size = -1;
 761         }
 762 }
 763
 764 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 765 {
 766         /* no need to check the default value */
 767         if (amdgpu_vm_size == -1)
 768                 return;
 769
 770         if (amdgpu_vm_size < 1) {
 771                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 772                          amdgpu_vm_size);
 773                 amdgpu_vm_size = -1;
 774         }
 775 }
 776
 777 /**
 778  * amdgpu_device_check_arguments - validate module params
 779  *
 780  * @adev: amdgpu_device pointer
 781  *
 782  * Validates certain module parameters and updates
 783  * the associated values used by the driver (all asics).
 784  */
 785 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 786 {
 787         if (amdgpu_sched_jobs < 4) {
 788                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 789                          amdgpu_sched_jobs);
 790                 amdgpu_sched_jobs = 4;
 791         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 792                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 793                          amdgpu_sched_jobs);
 794                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 795         }
 796
 797         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 798                 /* gart size must be greater or equal to 32M */
 799                 dev_warn(adev->dev, "gart size (%d) too small\n",
 800                          amdgpu_gart_size);
 801                 amdgpu_gart_size = -1;
 802         }
 803
 804         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 805                 /* gtt size must be greater or equal to 32M */
 806                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 807                                  amdgpu_gtt_size);
 808                 amdgpu_gtt_size = -1;
 809         }
 810
 811         /* valid range is between 4 and 9 inclusive */
 812         if (amdgpu_vm_fragment_size != -1 &&
 813             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 814                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 815                 amdgpu_vm_fragment_size = -1;
 816         }
 817
 818         amdgpu_device_check_vm_size(adev);
 819
 820         amdgpu_device_check_block_size(adev);
 821
 822         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 823             !is_power_of_2(amdgpu_vram_page_split))) {
 824                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
 825                          amdgpu_vram_page_split);
 826                 amdgpu_vram_page_split = 1024;
 827         }
 828
 829         if (amdgpu_lockup_timeout == 0) {
 830                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
 831                 amdgpu_lockup_timeout = 10000;
 832         }
 833 }
 834
 835 /**
 836  * amdgpu_switcheroo_set_state - set switcheroo state
 837  *
 838  * @pdev: pci dev pointer
 839  * @state: vga_switcheroo state
 840  *
 841  * Callback for the switcheroo driver.  Suspends or resumes the
 842  * the asics before or after it is powered up using ACPI methods.
 843  */
 844 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 845 {
 846         struct drm_device *dev = pci_get_drvdata(pdev);
 847
 848         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 849                 return;
 850
 851         if (state == VGA_SWITCHEROO_ON) {
 852                 pr_info("amdgpu: switched on\n");
 853                 /* don't suspend or resume card normally */
 854                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 855
 856                 amdgpu_device_resume(dev, true, true);
 857
 858                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 859                 drm_kms_helper_poll_enable(dev);
 860         } else {
 861                 pr_info("amdgpu: switched off\n");
 862                 drm_kms_helper_poll_disable(dev);
 863                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 864                 amdgpu_device_suspend(dev, true, true);
 865                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 866         }
 867 }
 868
 869 /**
 870  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
 871  *
 872  * @pdev: pci dev pointer
 873  *
 874  * Callback for the switcheroo driver.  Check of the switcheroo
 875  * state can be changed.
 876  * Returns true if the state can be changed, false if not.
 877  */
 878 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
 879 {
 880         struct drm_device *dev = pci_get_drvdata(pdev);
 881
 882         /*
 883         * FIXME: open_count is protected by drm_global_mutex but that would lead to
 884         * locking inversion with the driver load path. And the access here is
 885         * completely racy anyway. So don't bother with locking for now.
 886         */
 887         return dev->open_count == 0;
 888 }
 889
 890 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
 891         .set_gpu_state = amdgpu_switcheroo_set_state,
 892         .reprobe = NULL,
 893         .can_switch = amdgpu_switcheroo_can_switch,
 894 };
 895
 896 int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
 897                                            enum amd_ip_block_type block_type,
 898                                            enum amd_clockgating_state state)
 899 {
 900         int i, r = 0;
 901
 902         for (i = 0; i < adev->num_ip_blocks; i++) {
 903                 if (!adev->ip_blocks[i].status.valid)
 904                         continue;
 905                 if (adev->ip_blocks[i].version->type != block_type)
 906                         continue;
 907                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
 908                         continue;
 909                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
 910                         (void *)adev, state);
 911                 if (r)
 912                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
 913                                   adev->ip_blocks[i].version->funcs->name, r);
 914         }
 915         return r;
 916 }
 917
 918 int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
 919                                            enum amd_ip_block_type block_type,
 920                                            enum amd_powergating_state state)
 921 {
 922         int i, r = 0;
 923
 924         for (i = 0; i < adev->num_ip_blocks; i++) {
 925                 if (!adev->ip_blocks[i].status.valid)
 926                         continue;
 927                 if (adev->ip_blocks[i].version->type != block_type)
 928                         continue;
 929                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
 930                         continue;
 931                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
 932                         (void *)adev, state);
 933                 if (r)
 934                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
 935                                   adev->ip_blocks[i].version->funcs->name, r);
 936         }
 937         return r;
 938 }
 939
 940 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
 941                                             u32 *flags)
 942 {
 943         int i;
 944
 945         for (i = 0; i < adev->num_ip_blocks; i++) {
 946                 if (!adev->ip_blocks[i].status.valid)
 947                         continue;
 948                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
 949                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
 950         }
 951 }
 952
 953 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
 954                                    enum amd_ip_block_type block_type)
 955 {
 956         int i, r;
 957
 958         for (i = 0; i < adev->num_ip_blocks; i++) {
 959                 if (!adev->ip_blocks[i].status.valid)
 960                         continue;
 961                 if (adev->ip_blocks[i].version->type == block_type) {
 962                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
 963                         if (r)
 964                                 return r;
 965                         break;
 966                 }
 967         }
 968         return 0;
 969
 970 }
 971
 972 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
 973                               enum amd_ip_block_type block_type)
 974 {
 975         int i;
 976
 977         for (i = 0; i < adev->num_ip_blocks; i++) {
 978                 if (!adev->ip_blocks[i].status.valid)
 979                         continue;
 980                 if (adev->ip_blocks[i].version->type == block_type)
 981                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
 982         }
 983         return true;
 984
 985 }
 986
 987 struct amdgpu_ip_block *
 988 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 989                               enum amd_ip_block_type type)
 990 {
 991         int i;
 992
 993         for (i = 0; i < adev->num_ip_blocks; i++)
 994                 if (adev->ip_blocks[i].version->type == type)
 995                         return &adev->ip_blocks[i];
 996
 997         return NULL;
 998 }
 999
1000 /**
1001  * amdgpu_device_ip_block_version_cmp
1002  *
1003  * @adev: amdgpu_device pointer
1004  * @type: enum amd_ip_block_type
1005  * @major: major version
1006  * @minor: minor version
1007  *
1008  * return 0 if equal or greater
1009  * return 1 if smaller or the ip_block doesn't exist
1010  */
1011 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1012                                        enum amd_ip_block_type type,
1013                                        u32 major, u32 minor)
1014 {
1015         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1016
1017         if (ip_block && ((ip_block->version->major > major) ||
1018                         ((ip_block->version->major == major) &&
1019                         (ip_block->version->minor >= minor))))
1020                 return 0;
1021
1022         return 1;
1023 }
1024
1025 /**
1026  * amdgpu_device_ip_block_add
1027  *
1028  * @adev: amdgpu_device pointer
1029  * @ip_block_version: pointer to the IP to add
1030  *
1031  * Adds the IP block driver information to the collection of IPs
1032  * on the asic.
1033  */
1034 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1035                                const struct amdgpu_ip_block_version *ip_block_version)
1036 {
1037         if (!ip_block_version)
1038                 return -EINVAL;
1039
1040         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1041                   ip_block_version->funcs->name);
1042
1043         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1044
1045         return 0;
1046 }
1047
1048 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1049 {
1050         adev->enable_virtual_display = false;
1051
1052         if (amdgpu_virtual_display) {
1053                 struct drm_device *ddev = adev->ddev;
1054                 const char *pci_address_name = pci_name(ddev->pdev);
1055                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1056
1057                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1058                 pciaddstr_tmp = pciaddstr;
1059                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1060                         pciaddname = strsep(&pciaddname_tmp, ",");
1061                         if (!strcmp("all", pciaddname)
1062                             || !strcmp(pci_address_name, pciaddname)) {
1063                                 long num_crtc;
1064                                 int res = -1;
1065
1066                                 adev->enable_virtual_display = true;
1067
1068                                 if (pciaddname_tmp)
1069                                         res = kstrtol(pciaddname_tmp, 10,
1070                                                       &num_crtc);
1071
1072                                 if (!res) {
1073                                         if (num_crtc < 1)
1074                                                 num_crtc = 1;
1075                                         if (num_crtc > 6)
1076                                                 num_crtc = 6;
1077                                         adev->mode_info.num_crtc = num_crtc;
1078                                 } else {
1079                                         adev->mode_info.num_crtc = 1;
1080                                 }
1081                                 break;
1082                         }
1083                 }
1084
1085                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1086                          amdgpu_virtual_display, pci_address_name,
1087                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1088
1089                 kfree(pciaddstr);
1090         }
1091 }
1092
1093 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1094 {
1095         const char *chip_name;
1096         char fw_name[30];
1097         int err;
1098         const struct gpu_info_firmware_header_v1_0 *hdr;
1099
1100         adev->firmware.gpu_info_fw = NULL;
1101
1102         switch (adev->asic_type) {
1103         case CHIP_TOPAZ:
1104         case CHIP_TONGA:
1105         case CHIP_FIJI:
1106         case CHIP_POLARIS11:
1107         case CHIP_POLARIS10:
1108         case CHIP_POLARIS12:
1109         case CHIP_CARRIZO:
1110         case CHIP_STONEY:
1111 #ifdef CONFIG_DRM_AMDGPU_SI
1112         case CHIP_VERDE:
1113         case CHIP_TAHITI:
1114         case CHIP_PITCAIRN:
1115         case CHIP_OLAND:
1116         case CHIP_HAINAN:
1117 #endif
1118 #ifdef CONFIG_DRM_AMDGPU_CIK
1119         case CHIP_BONAIRE:
1120         case CHIP_HAWAII:
1121         case CHIP_KAVERI:
1122         case CHIP_KABINI:
1123         case CHIP_MULLINS:
1124 #endif
1125         default:
1126                 return 0;
1127         case CHIP_VEGA10:
1128                 chip_name = "vega10";
1129                 break;
1130         case CHIP_RAVEN:
1131                 chip_name = "raven";
1132                 break;
1133         }
1134
1135         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1136         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1137         if (err) {
1138                 dev_err(adev->dev,
1139                         "Failed to load gpu_info firmware \"%s\"\n",
1140                         fw_name);
1141                 goto out;
1142         }
1143         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1144         if (err) {
1145                 dev_err(adev->dev,
1146                         "Failed to validate gpu_info firmware \"%s\"\n",
1147                         fw_name);
1148                 goto out;
1149         }
1150
1151         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1152         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1153
1154         switch (hdr->version_major) {
1155         case 1:
1156         {
1157                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1158                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1159                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1160
1161                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1162                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1163                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1164                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1165                 adev->gfx.config.max_texture_channel_caches =
1166                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1167                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1168                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1169                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1170                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1171                 adev->gfx.config.double_offchip_lds_buf =
1172                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1173                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1174                 adev->gfx.cu_info.max_waves_per_simd =
1175                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1176                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1177                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1178                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1179                 break;
1180         }
1181         default:
1182                 dev_err(adev->dev,
1183                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1184                 err = -EINVAL;
1185                 goto out;
1186         }
1187 out:
1188         return err;
1189 }
1190
1191 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1192 {
1193         int i, r;
1194
1195         amdgpu_device_enable_virtual_display(adev);
1196
1197         switch (adev->asic_type) {
1198         case CHIP_TOPAZ:
1199         case CHIP_TONGA:
1200         case CHIP_FIJI:
1201         case CHIP_POLARIS11:
1202         case CHIP_POLARIS10:
1203         case CHIP_POLARIS12:
1204         case CHIP_CARRIZO:
1205         case CHIP_STONEY:
1206                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1207                         adev->family = AMDGPU_FAMILY_CZ;
1208                 else
1209                         adev->family = AMDGPU_FAMILY_VI;
1210
1211                 r = vi_set_ip_blocks(adev);
1212                 if (r)
1213                         return r;
1214                 break;
1215 #ifdef CONFIG_DRM_AMDGPU_SI
1216         case CHIP_VERDE:
1217         case CHIP_TAHITI:
1218         case CHIP_PITCAIRN:
1219         case CHIP_OLAND:
1220         case CHIP_HAINAN:
1221                 adev->family = AMDGPU_FAMILY_SI;
1222                 r = si_set_ip_blocks(adev);
1223                 if (r)
1224                         return r;
1225                 break;
1226 #endif
1227 #ifdef CONFIG_DRM_AMDGPU_CIK
1228         case CHIP_BONAIRE:
1229         case CHIP_HAWAII:
1230         case CHIP_KAVERI:
1231         case CHIP_KABINI:
1232         case CHIP_MULLINS:
1233                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1234                         adev->family = AMDGPU_FAMILY_CI;
1235                 else
1236                         adev->family = AMDGPU_FAMILY_KV;
1237
1238                 r = cik_set_ip_blocks(adev);
1239                 if (r)
1240                         return r;
1241                 break;
1242 #endif
1243         case  CHIP_VEGA10:
1244         case  CHIP_RAVEN:
1245                 if (adev->asic_type == CHIP_RAVEN)
1246                         adev->family = AMDGPU_FAMILY_RV;
1247                 else
1248                         adev->family = AMDGPU_FAMILY_AI;
1249
1250                 r = soc15_set_ip_blocks(adev);
1251                 if (r)
1252                         return r;
1253                 break;
1254         default:
1255                 /* FIXME: not supported yet */
1256                 return -EINVAL;
1257         }
1258
1259         r = amdgpu_device_parse_gpu_info_fw(adev);
1260         if (r)
1261                 return r;
1262
1263         amdgpu_amdkfd_device_probe(adev);
1264
1265         if (amdgpu_sriov_vf(adev)) {
1266                 r = amdgpu_virt_request_full_gpu(adev, true);
1267                 if (r)
1268                         return -EAGAIN;
1269         }
1270
1271         for (i = 0; i < adev->num_ip_blocks; i++) {
1272                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1273                         DRM_ERROR("disabled ip block: %d <%s>\n",
1274                                   i, adev->ip_blocks[i].version->funcs->name);
1275                         adev->ip_blocks[i].status.valid = false;
1276                 } else {
1277                         if (adev->ip_blocks[i].version->funcs->early_init) {
1278                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1279                                 if (r == -ENOENT) {
1280                                         adev->ip_blocks[i].status.valid = false;
1281                                 } else if (r) {
1282                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1283                                                   adev->ip_blocks[i].version->funcs->name, r);
1284                                         return r;
1285                                 } else {
1286                                         adev->ip_blocks[i].status.valid = true;
1287                                 }
1288                         } else {
1289                                 adev->ip_blocks[i].status.valid = true;
1290                         }
1291                 }
1292         }
1293
1294         adev->cg_flags &= amdgpu_cg_mask;
1295         adev->pg_flags &= amdgpu_pg_mask;
1296
1297         return 0;
1298 }
1299
1300 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1301 {
1302         int i, r;
1303
1304         for (i = 0; i < adev->num_ip_blocks; i++) {
1305                 if (!adev->ip_blocks[i].status.valid)
1306                         continue;
1307                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1308                 if (r) {
1309                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1310                                   adev->ip_blocks[i].version->funcs->name, r);
1311                         return r;
1312                 }
1313                 adev->ip_blocks[i].status.sw = true;
1314
1315                 /* need to do gmc hw init early so we can allocate gpu mem */
1316                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1317                         r = amdgpu_device_vram_scratch_init(adev);
1318                         if (r) {
1319                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1320                                 return r;
1321                         }
1322                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1323                         if (r) {
1324                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1325                                 return r;
1326                         }
1327                         r = amdgpu_device_wb_init(adev);
1328                         if (r) {
1329                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1330                                 return r;
1331                         }
1332                         adev->ip_blocks[i].status.hw = true;
1333
1334                         /* right after GMC hw init, we create CSA */
1335                         if (amdgpu_sriov_vf(adev)) {
1336                                 r = amdgpu_allocate_static_csa(adev);
1337                                 if (r) {
1338                                         DRM_ERROR("allocate CSA failed %d\n", r);
1339                                         return r;
1340                                 }
1341                         }
1342                 }
1343         }
1344
1345         for (i = 0; i < adev->num_ip_blocks; i++) {
1346                 if (!adev->ip_blocks[i].status.sw)
1347                         continue;
1348                 if (adev->ip_blocks[i].status.hw)
1349                         continue;
1350                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1351                 if (r) {
1352                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1353                                   adev->ip_blocks[i].version->funcs->name, r);
1354                         return r;
1355                 }
1356                 adev->ip_blocks[i].status.hw = true;
1357         }
1358
1359         amdgpu_amdkfd_device_init(adev);
1360
1361         if (amdgpu_sriov_vf(adev))
1362                 amdgpu_virt_release_full_gpu(adev, true);
1363
1364         return 0;
1365 }
1366
1367 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1368 {
1369         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1370 }
1371
1372 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1373 {
1374         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1375                         AMDGPU_RESET_MAGIC_NUM);
1376 }
1377
1378 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1379 {
1380         int i = 0, r;
1381
1382         if (amdgpu_emu_mode == 1)
1383                 return 0;
1384
1385         for (i = 0; i < adev->num_ip_blocks; i++) {
1386                 if (!adev->ip_blocks[i].status.valid)
1387                         continue;
1388                 /* skip CG for VCE/UVD, it's handled specially */
1389                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1390                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1391                         /* enable clockgating to save power */
1392                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1393                                                                                      AMD_CG_STATE_GATE);
1394                         if (r) {
1395                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1396                                           adev->ip_blocks[i].version->funcs->name, r);
1397                                 return r;
1398                         }
1399                 }
1400         }
1401         return 0;
1402 }
1403
1404 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1405 {
1406         int i = 0, r;
1407
1408         for (i = 0; i < adev->num_ip_blocks; i++) {
1409                 if (!adev->ip_blocks[i].status.valid)
1410                         continue;
1411                 if (adev->ip_blocks[i].version->funcs->late_init) {
1412                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1413                         if (r) {
1414                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1415                                           adev->ip_blocks[i].version->funcs->name, r);
1416                                 return r;
1417                         }
1418                         adev->ip_blocks[i].status.late_initialized = true;
1419                 }
1420         }
1421
1422         mod_delayed_work(system_wq, &adev->late_init_work,
1423                         msecs_to_jiffies(AMDGPU_RESUME_MS));
1424
1425         amdgpu_device_fill_reset_magic(adev);
1426
1427         return 0;
1428 }
1429
1430 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1431 {
1432         int i, r;
1433
1434         amdgpu_amdkfd_device_fini(adev);
1435         /* need to disable SMC first */
1436         for (i = 0; i < adev->num_ip_blocks; i++) {
1437                 if (!adev->ip_blocks[i].status.hw)
1438                         continue;
1439                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1440                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1441                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1442                                                                                      AMD_CG_STATE_UNGATE);
1443                         if (r) {
1444                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1445                                           adev->ip_blocks[i].version->funcs->name, r);
1446                                 return r;
1447                         }
1448                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1449                         /* XXX handle errors */
1450                         if (r) {
1451                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1452                                           adev->ip_blocks[i].version->funcs->name, r);
1453                         }
1454                         adev->ip_blocks[i].status.hw = false;
1455                         break;
1456                 }
1457         }
1458
1459         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1460                 if (!adev->ip_blocks[i].status.hw)
1461                         continue;
1462
1463                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1464                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1465                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1466                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1467                                                                                      AMD_CG_STATE_UNGATE);
1468                         if (r) {
1469                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1470                                           adev->ip_blocks[i].version->funcs->name, r);
1471                                 return r;
1472                         }
1473                 }
1474
1475                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1476                 /* XXX handle errors */
1477                 if (r) {
1478                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1479                                   adev->ip_blocks[i].version->funcs->name, r);
1480                 }
1481
1482                 adev->ip_blocks[i].status.hw = false;
1483         }
1484
1485         /* disable all interrupts */
1486         amdgpu_irq_disable_all(adev);
1487
1488         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1489                 if (!adev->ip_blocks[i].status.sw)
1490                         continue;
1491
1492                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1493                         amdgpu_free_static_csa(adev);
1494                         amdgpu_device_wb_fini(adev);
1495                         amdgpu_device_vram_scratch_fini(adev);
1496                 }
1497
1498                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1499                 /* XXX handle errors */
1500                 if (r) {
1501                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1502                                   adev->ip_blocks[i].version->funcs->name, r);
1503                 }
1504                 adev->ip_blocks[i].status.sw = false;
1505                 adev->ip_blocks[i].status.valid = false;
1506         }
1507
1508         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1509                 if (!adev->ip_blocks[i].status.late_initialized)
1510                         continue;
1511                 if (adev->ip_blocks[i].version->funcs->late_fini)
1512                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1513                 adev->ip_blocks[i].status.late_initialized = false;
1514         }
1515
1516         if (amdgpu_sriov_vf(adev))
1517                 if (amdgpu_virt_release_full_gpu(adev, false))
1518                         DRM_ERROR("failed to release exclusive mode on fini\n");
1519
1520         return 0;
1521 }
1522
1523 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1524 {
1525         struct amdgpu_device *adev =
1526                 container_of(work, struct amdgpu_device, late_init_work.work);
1527         amdgpu_device_ip_late_set_cg_state(adev);
1528 }
1529
1530 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
1531 {
1532         int i, r;
1533
1534         if (amdgpu_sriov_vf(adev))
1535                 amdgpu_virt_request_full_gpu(adev, false);
1536
1537         /* ungate SMC block first */
1538         r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1539                                                    AMD_CG_STATE_UNGATE);
1540         if (r) {
1541                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
1542         }
1543
1544         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1545                 if (!adev->ip_blocks[i].status.valid)
1546                         continue;
1547                 /* ungate blocks so that suspend can properly shut them down */
1548                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1549                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1550                                                                                      AMD_CG_STATE_UNGATE);
1551                         if (r) {
1552                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1553                                           adev->ip_blocks[i].version->funcs->name, r);
1554                         }
1555                 }
1556                 /* XXX handle errors */
1557                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1558                 /* XXX handle errors */
1559                 if (r) {
1560                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1561                                   adev->ip_blocks[i].version->funcs->name, r);
1562                 }
1563         }
1564
1565         if (amdgpu_sriov_vf(adev))
1566                 amdgpu_virt_release_full_gpu(adev, false);
1567
1568         return 0;
1569 }
1570
1571 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
1572 {
1573         int i, r;
1574
1575         static enum amd_ip_block_type ip_order[] = {
1576                 AMD_IP_BLOCK_TYPE_GMC,
1577                 AMD_IP_BLOCK_TYPE_COMMON,
1578                 AMD_IP_BLOCK_TYPE_IH,
1579         };
1580
1581         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1582                 int j;
1583                 struct amdgpu_ip_block *block;
1584
1585                 for (j = 0; j < adev->num_ip_blocks; j++) {
1586                         block = &adev->ip_blocks[j];
1587
1588                         if (block->version->type != ip_order[i] ||
1589                                 !block->status.valid)
1590                                 continue;
1591
1592                         r = block->version->funcs->hw_init(adev);
1593                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1594                 }
1595         }
1596
1597         return 0;
1598 }
1599
1600 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
1601 {
1602         int i, r;
1603
1604         static enum amd_ip_block_type ip_order[] = {
1605                 AMD_IP_BLOCK_TYPE_SMC,
1606                 AMD_IP_BLOCK_TYPE_PSP,
1607                 AMD_IP_BLOCK_TYPE_DCE,
1608                 AMD_IP_BLOCK_TYPE_GFX,
1609                 AMD_IP_BLOCK_TYPE_SDMA,
1610                 AMD_IP_BLOCK_TYPE_UVD,
1611                 AMD_IP_BLOCK_TYPE_VCE
1612         };
1613
1614         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1615                 int j;
1616                 struct amdgpu_ip_block *block;
1617
1618                 for (j = 0; j < adev->num_ip_blocks; j++) {
1619                         block = &adev->ip_blocks[j];
1620
1621                         if (block->version->type != ip_order[i] ||
1622                                 !block->status.valid)
1623                                 continue;
1624
1625                         r = block->version->funcs->hw_init(adev);
1626                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1627                 }
1628         }
1629
1630         return 0;
1631 }
1632
1633 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
1634 {
1635         int i, r;
1636
1637         for (i = 0; i < adev->num_ip_blocks; i++) {
1638                 if (!adev->ip_blocks[i].status.valid)
1639                         continue;
1640                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1641                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1642                                 adev->ip_blocks[i].version->type ==
1643                                 AMD_IP_BLOCK_TYPE_IH) {
1644                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1645                         if (r) {
1646                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1647                                           adev->ip_blocks[i].version->funcs->name, r);
1648                                 return r;
1649                         }
1650                 }
1651         }
1652
1653         return 0;
1654 }
1655
1656 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
1657 {
1658         int i, r;
1659
1660         for (i = 0; i < adev->num_ip_blocks; i++) {
1661                 if (!adev->ip_blocks[i].status.valid)
1662                         continue;
1663                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1664                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1665                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1666                         continue;
1667                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1668                 if (r) {
1669                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1670                                   adev->ip_blocks[i].version->funcs->name, r);
1671                         return r;
1672                 }
1673         }
1674
1675         return 0;
1676 }
1677
1678 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
1679 {
1680         int r;
1681
1682         r = amdgpu_device_ip_resume_phase1(adev);
1683         if (r)
1684                 return r;
1685         r = amdgpu_device_ip_resume_phase2(adev);
1686
1687         return r;
1688 }
1689
1690 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1691 {
1692         if (amdgpu_sriov_vf(adev)) {
1693                 if (adev->is_atom_fw) {
1694                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1695                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1696                 } else {
1697                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1698                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1699                 }
1700
1701                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
1702                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
1703         }
1704 }
1705
1706 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
1707 {
1708         switch (asic_type) {
1709 #if defined(CONFIG_DRM_AMD_DC)
1710         case CHIP_BONAIRE:
1711         case CHIP_HAWAII:
1712         case CHIP_KAVERI:
1713         case CHIP_KABINI:
1714         case CHIP_MULLINS:
1715         case CHIP_CARRIZO:
1716         case CHIP_STONEY:
1717         case CHIP_POLARIS11:
1718         case CHIP_POLARIS10:
1719         case CHIP_POLARIS12:
1720         case CHIP_TONGA:
1721         case CHIP_FIJI:
1722 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
1723                 return amdgpu_dc != 0;
1724 #endif
1725         case CHIP_VEGA10:
1726 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1727         case CHIP_RAVEN:
1728 #endif
1729                 return amdgpu_dc != 0;
1730 #endif
1731         default:
1732                 return false;
1733         }
1734 }
1735
1736 /**
1737  * amdgpu_device_has_dc_support - check if dc is supported
1738  *
1739  * @adev: amdgpu_device_pointer
1740  *
1741  * Returns true for supported, false for not supported
1742  */
1743 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
1744 {
1745         if (amdgpu_sriov_vf(adev))
1746                 return false;
1747
1748         return amdgpu_device_asic_has_dc_support(adev->asic_type);
1749 }
1750
1751 /**
1752  * amdgpu_device_init - initialize the driver
1753  *
1754  * @adev: amdgpu_device pointer
1755  * @pdev: drm dev pointer
1756  * @pdev: pci dev pointer
1757  * @flags: driver flags
1758  *
1759  * Initializes the driver info and hw (all asics).
1760  * Returns 0 for success or an error on failure.
1761  * Called at driver startup.
1762  */
1763 int amdgpu_device_init(struct amdgpu_device *adev,
1764                        struct drm_device *ddev,
1765                        struct pci_dev *pdev,
1766                        uint32_t flags)
1767 {
1768         int r, i;
1769         bool runtime = false;
1770         u32 max_MBps;
1771
1772         adev->shutdown = false;
1773         adev->dev = &pdev->dev;
1774         adev->ddev = ddev;
1775         adev->pdev = pdev;
1776         adev->flags = flags;
1777         adev->asic_type = flags & AMD_ASIC_MASK;
1778         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1779         if (amdgpu_emu_mode == 1)
1780                 adev->usec_timeout *= 2;
1781         adev->gmc.gart_size = 512 * 1024 * 1024;
1782         adev->accel_working = false;
1783         adev->num_rings = 0;
1784         adev->mman.buffer_funcs = NULL;
1785         adev->mman.buffer_funcs_ring = NULL;
1786         adev->vm_manager.vm_pte_funcs = NULL;
1787         adev->vm_manager.vm_pte_num_rings = 0;
1788         adev->gmc.gmc_funcs = NULL;
1789         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1790         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1791
1792         adev->smc_rreg = &amdgpu_invalid_rreg;
1793         adev->smc_wreg = &amdgpu_invalid_wreg;
1794         adev->pcie_rreg = &amdgpu_invalid_rreg;
1795         adev->pcie_wreg = &amdgpu_invalid_wreg;
1796         adev->pciep_rreg = &amdgpu_invalid_rreg;
1797         adev->pciep_wreg = &amdgpu_invalid_wreg;
1798         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1799         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1800         adev->didt_rreg = &amdgpu_invalid_rreg;
1801         adev->didt_wreg = &amdgpu_invalid_wreg;
1802         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1803         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1804         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1805         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1806
1807         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1808                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1809                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1810
1811         /* mutex initialization are all done here so we
1812          * can recall function without having locking issues */
1813         atomic_set(&adev->irq.ih.lock, 0);
1814         mutex_init(&adev->firmware.mutex);
1815         mutex_init(&adev->pm.mutex);
1816         mutex_init(&adev->gfx.gpu_clock_mutex);
1817         mutex_init(&adev->srbm_mutex);
1818         mutex_init(&adev->gfx.pipe_reserve_mutex);
1819         mutex_init(&adev->grbm_idx_mutex);
1820         mutex_init(&adev->mn_lock);
1821         mutex_init(&adev->virt.vf_errors.lock);
1822         hash_init(adev->mn_hash);
1823         mutex_init(&adev->lock_reset);
1824
1825         amdgpu_device_check_arguments(adev);
1826
1827         spin_lock_init(&adev->mmio_idx_lock);
1828         spin_lock_init(&adev->smc_idx_lock);
1829         spin_lock_init(&adev->pcie_idx_lock);
1830         spin_lock_init(&adev->uvd_ctx_idx_lock);
1831         spin_lock_init(&adev->didt_idx_lock);
1832         spin_lock_init(&adev->gc_cac_idx_lock);
1833         spin_lock_init(&adev->se_cac_idx_lock);
1834         spin_lock_init(&adev->audio_endpt_idx_lock);
1835         spin_lock_init(&adev->mm_stats.lock);
1836
1837         INIT_LIST_HEAD(&adev->shadow_list);
1838         mutex_init(&adev->shadow_list_lock);
1839
1840         INIT_LIST_HEAD(&adev->ring_lru_list);
1841         spin_lock_init(&adev->ring_lru_list_lock);
1842
1843         INIT_DELAYED_WORK(&adev->late_init_work,
1844                           amdgpu_device_ip_late_init_func_handler);
1845
1846         /* Registers mapping */
1847         /* TODO: block userspace mapping of io register */
1848         if (adev->asic_type >= CHIP_BONAIRE) {
1849                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1850                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1851         } else {
1852                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1853                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1854         }
1855
1856         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1857         if (adev->rmmio == NULL) {
1858                 return -ENOMEM;
1859         }
1860         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1861         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1862
1863         /* doorbell bar mapping */
1864         amdgpu_device_doorbell_init(adev);
1865
1866         /* io port mapping */
1867         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1868                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1869                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1870                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1871                         break;
1872                 }
1873         }
1874         if (adev->rio_mem == NULL)
1875                 DRM_INFO("PCI I/O BAR is not found.\n");
1876
1877         /* early init functions */
1878         r = amdgpu_device_ip_early_init(adev);
1879         if (r)
1880                 return r;
1881
1882         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1883         /* this will fail for cards that aren't VGA class devices, just
1884          * ignore it */
1885         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
1886
1887         if (amdgpu_device_is_px(ddev))
1888                 runtime = true;
1889         if (!pci_is_thunderbolt_attached(adev->pdev))
1890                 vga_switcheroo_register_client(adev->pdev,
1891                                                &amdgpu_switcheroo_ops, runtime);
1892         if (runtime)
1893                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1894
1895         if (amdgpu_emu_mode == 1) {
1896                 /* post the asic on emulation mode */
1897                 emu_soc_asic_init(adev);
1898                 goto fence_driver_init;
1899         }
1900
1901         /* Read BIOS */
1902         if (!amdgpu_get_bios(adev)) {
1903                 r = -EINVAL;
1904                 goto failed;
1905         }
1906
1907         r = amdgpu_atombios_init(adev);
1908         if (r) {
1909                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1910                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1911                 goto failed;
1912         }
1913
1914         /* detect if we are with an SRIOV vbios */
1915         amdgpu_device_detect_sriov_bios(adev);
1916
1917         /* Post card if necessary */
1918         if (amdgpu_device_need_post(adev)) {
1919                 if (!adev->bios) {
1920                         dev_err(adev->dev, "no vBIOS found\n");
1921                         r = -EINVAL;
1922                         goto failed;
1923                 }
1924                 DRM_INFO("GPU posting now...\n");
1925                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1926                 if (r) {
1927                         dev_err(adev->dev, "gpu post error!\n");
1928                         goto failed;
1929                 }
1930         }
1931
1932         if (adev->is_atom_fw) {
1933                 /* Initialize clocks */
1934                 r = amdgpu_atomfirmware_get_clock_info(adev);
1935                 if (r) {
1936                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
1937                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1938                         goto failed;
1939                 }
1940         } else {
1941                 /* Initialize clocks */
1942                 r = amdgpu_atombios_get_clock_info(adev);
1943                 if (r) {
1944                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1945                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1946                         goto failed;
1947                 }
1948                 /* init i2c buses */
1949                 if (!amdgpu_device_has_dc_support(adev))
1950                         amdgpu_atombios_i2c_init(adev);
1951         }
1952
1953 fence_driver_init:
1954         /* Fence driver */
1955         r = amdgpu_fence_driver_init(adev);
1956         if (r) {
1957                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1958                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
1959                 goto failed;
1960         }
1961
1962         /* init the mode config */
1963         drm_mode_config_init(adev->ddev);
1964
1965         r = amdgpu_device_ip_init(adev);
1966         if (r) {
1967                 /* failed in exclusive mode due to timeout */
1968                 if (amdgpu_sriov_vf(adev) &&
1969                     !amdgpu_sriov_runtime(adev) &&
1970                     amdgpu_virt_mmio_blocked(adev) &&
1971                     !amdgpu_virt_wait_reset(adev)) {
1972                         dev_err(adev->dev, "VF exclusive mode timeout\n");
1973                         /* Don't send request since VF is inactive. */
1974                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
1975                         adev->virt.ops = NULL;
1976                         r = -EAGAIN;
1977                         goto failed;
1978                 }
1979                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
1980                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
1981                 amdgpu_device_ip_fini(adev);
1982                 goto failed;
1983         }
1984
1985         adev->accel_working = true;
1986
1987         amdgpu_vm_check_compute_bug(adev);
1988
1989         /* Initialize the buffer migration limit. */
1990         if (amdgpu_moverate >= 0)
1991                 max_MBps = amdgpu_moverate;
1992         else
1993                 max_MBps = 8; /* Allow 8 MB/s. */
1994         /* Get a log2 for easy divisions. */
1995         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1996
1997         r = amdgpu_ib_pool_init(adev);
1998         if (r) {
1999                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2000                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2001                 goto failed;
2002         }
2003
2004         r = amdgpu_ib_ring_tests(adev);
2005         if (r)
2006                 DRM_ERROR("ib ring test failed (%d).\n", r);
2007
2008         if (amdgpu_sriov_vf(adev))
2009                 amdgpu_virt_init_data_exchange(adev);
2010
2011         amdgpu_fbdev_init(adev);
2012
2013         r = amdgpu_pm_sysfs_init(adev);
2014         if (r)
2015                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2016
2017         r = amdgpu_debugfs_gem_init(adev);
2018         if (r)
2019                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2020
2021         r = amdgpu_debugfs_regs_init(adev);
2022         if (r)
2023                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2024
2025         r = amdgpu_debugfs_firmware_init(adev);
2026         if (r)
2027                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2028
2029         r = amdgpu_debugfs_init(adev);
2030         if (r)
2031                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2032
2033         if ((amdgpu_testing & 1)) {
2034                 if (adev->accel_working)
2035                         amdgpu_test_moves(adev);
2036                 else
2037                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2038         }
2039         if (amdgpu_benchmarking) {
2040                 if (adev->accel_working)
2041                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2042                 else
2043                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2044         }
2045
2046         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2047          * explicit gating rather than handling it automatically.
2048          */
2049         r = amdgpu_device_ip_late_init(adev);
2050         if (r) {
2051                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2052                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2053                 goto failed;
2054         }
2055
2056         return 0;
2057
2058 failed:
2059         amdgpu_vf_error_trans_all(adev);
2060         if (runtime)
2061                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2062
2063         return r;
2064 }
2065
2066 /**
2067  * amdgpu_device_fini - tear down the driver
2068  *
2069  * @adev: amdgpu_device pointer
2070  *
2071  * Tear down the driver info (all asics).
2072  * Called at driver shutdown.
2073  */
2074 void amdgpu_device_fini(struct amdgpu_device *adev)
2075 {
2076         int r;
2077
2078         DRM_INFO("amdgpu: finishing device.\n");
2079         adev->shutdown = true;
2080         if (adev->mode_info.mode_config_initialized)
2081                 drm_crtc_force_disable_all(adev->ddev);
2082
2083         amdgpu_ib_pool_fini(adev);
2084         amdgpu_fence_driver_fini(adev);
2085         amdgpu_fbdev_fini(adev);
2086         r = amdgpu_device_ip_fini(adev);
2087         if (adev->firmware.gpu_info_fw) {
2088                 release_firmware(adev->firmware.gpu_info_fw);
2089                 adev->firmware.gpu_info_fw = NULL;
2090         }
2091         adev->accel_working = false;
2092         cancel_delayed_work_sync(&adev->late_init_work);
2093         /* free i2c buses */
2094         if (!amdgpu_device_has_dc_support(adev))
2095                 amdgpu_i2c_fini(adev);
2096
2097         if (amdgpu_emu_mode != 1)
2098                 amdgpu_atombios_fini(adev);
2099
2100         kfree(adev->bios);
2101         adev->bios = NULL;
2102         if (!pci_is_thunderbolt_attached(adev->pdev))
2103                 vga_switcheroo_unregister_client(adev->pdev);
2104         if (adev->flags & AMD_IS_PX)
2105                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2106         vga_client_register(adev->pdev, NULL, NULL, NULL);
2107         if (adev->rio_mem)
2108                 pci_iounmap(adev->pdev, adev->rio_mem);
2109         adev->rio_mem = NULL;
2110         iounmap(adev->rmmio);
2111         adev->rmmio = NULL;
2112         amdgpu_device_doorbell_fini(adev);
2113         amdgpu_pm_sysfs_fini(adev);
2114         amdgpu_debugfs_regs_cleanup(adev);
2115 }
2116
2117
2118 /*
2119  * Suspend & resume.
2120  */
2121 /**
2122  * amdgpu_device_suspend - initiate device suspend
2123  *
2124  * @pdev: drm dev pointer
2125  * @state: suspend state
2126  *
2127  * Puts the hw in the suspend state (all asics).
2128  * Returns 0 for success or an error on failure.
2129  * Called at driver suspend.
2130  */
2131 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2132 {
2133         struct amdgpu_device *adev;
2134         struct drm_crtc *crtc;
2135         struct drm_connector *connector;
2136         int r;
2137
2138         if (dev == NULL || dev->dev_private == NULL) {
2139                 return -ENODEV;
2140         }
2141
2142         adev = dev->dev_private;
2143
2144         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2145                 return 0;
2146
2147         drm_kms_helper_poll_disable(dev);
2148
2149         if (!amdgpu_device_has_dc_support(adev)) {
2150                 /* turn off display hw */
2151                 drm_modeset_lock_all(dev);
2152                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2153                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2154                 }
2155                 drm_modeset_unlock_all(dev);
2156         }
2157
2158         amdgpu_amdkfd_suspend(adev);
2159
2160         /* unpin the front buffers and cursors */
2161         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2162                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2163                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2164                 struct amdgpu_bo *robj;
2165
2166                 if (amdgpu_crtc->cursor_bo) {
2167                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2168                         r = amdgpu_bo_reserve(aobj, true);
2169                         if (r == 0) {
2170                                 amdgpu_bo_unpin(aobj);
2171                                 amdgpu_bo_unreserve(aobj);
2172                         }
2173                 }
2174
2175                 if (rfb == NULL || rfb->obj == NULL) {
2176                         continue;
2177                 }
2178                 robj = gem_to_amdgpu_bo(rfb->obj);
2179                 /* don't unpin kernel fb objects */
2180                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2181                         r = amdgpu_bo_reserve(robj, true);
2182                         if (r == 0) {
2183                                 amdgpu_bo_unpin(robj);
2184                                 amdgpu_bo_unreserve(robj);
2185                         }
2186                 }
2187         }
2188         /* evict vram memory */
2189         amdgpu_bo_evict_vram(adev);
2190
2191         amdgpu_fence_driver_suspend(adev);
2192
2193         r = amdgpu_device_ip_suspend(adev);
2194
2195         /* evict remaining vram memory
2196          * This second call to evict vram is to evict the gart page table
2197          * using the CPU.
2198          */
2199         amdgpu_bo_evict_vram(adev);
2200
2201         pci_save_state(dev->pdev);
2202         if (suspend) {
2203                 /* Shut down the device */
2204                 pci_disable_device(dev->pdev);
2205                 pci_set_power_state(dev->pdev, PCI_D3hot);
2206         } else {
2207                 r = amdgpu_asic_reset(adev);
2208                 if (r)
2209                         DRM_ERROR("amdgpu asic reset failed\n");
2210         }
2211
2212         if (fbcon) {
2213                 console_lock();
2214                 amdgpu_fbdev_set_suspend(adev, 1);
2215                 console_unlock();
2216         }
2217         return 0;
2218 }
2219
2220 /**
2221  * amdgpu_device_resume - initiate device resume
2222  *
2223  * @pdev: drm dev pointer
2224  *
2225  * Bring the hw back to operating state (all asics).
2226  * Returns 0 for success or an error on failure.
2227  * Called at driver resume.
2228  */
2229 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2230 {
2231         struct drm_connector *connector;
2232         struct amdgpu_device *adev = dev->dev_private;
2233         struct drm_crtc *crtc;
2234         int r = 0;
2235
2236         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2237                 return 0;
2238
2239         if (fbcon)
2240                 console_lock();
2241
2242         if (resume) {
2243                 pci_set_power_state(dev->pdev, PCI_D0);
2244                 pci_restore_state(dev->pdev);
2245                 r = pci_enable_device(dev->pdev);
2246                 if (r)
2247                         goto unlock;
2248         }
2249
2250         /* post card */
2251         if (amdgpu_device_need_post(adev)) {
2252                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2253                 if (r)
2254                         DRM_ERROR("amdgpu asic init failed\n");
2255         }
2256
2257         r = amdgpu_device_ip_resume(adev);
2258         if (r) {
2259                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2260                 goto unlock;
2261         }
2262         amdgpu_fence_driver_resume(adev);
2263
2264         if (resume) {
2265                 r = amdgpu_ib_ring_tests(adev);
2266                 if (r)
2267                         DRM_ERROR("ib ring test failed (%d).\n", r);
2268         }
2269
2270         r = amdgpu_device_ip_late_init(adev);
2271         if (r)
2272                 goto unlock;
2273
2274         /* pin cursors */
2275         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2276                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277
2278                 if (amdgpu_crtc->cursor_bo) {
2279                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2280                         r = amdgpu_bo_reserve(aobj, true);
2281                         if (r == 0) {
2282                                 r = amdgpu_bo_pin(aobj,
2283                                                   AMDGPU_GEM_DOMAIN_VRAM,
2284                                                   &amdgpu_crtc->cursor_addr);
2285                                 if (r != 0)
2286                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2287                                 amdgpu_bo_unreserve(aobj);
2288                         }
2289                 }
2290         }
2291         r = amdgpu_amdkfd_resume(adev);
2292         if (r)
2293                 return r;
2294
2295         /* blat the mode back in */
2296         if (fbcon) {
2297                 if (!amdgpu_device_has_dc_support(adev)) {
2298                         /* pre DCE11 */
2299                         drm_helper_resume_force_mode(dev);
2300
2301                         /* turn on display hw */
2302                         drm_modeset_lock_all(dev);
2303                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2304                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2305                         }
2306                         drm_modeset_unlock_all(dev);
2307                 }
2308         }
2309
2310         drm_kms_helper_poll_enable(dev);
2311
2312         /*
2313          * Most of the connector probing functions try to acquire runtime pm
2314          * refs to ensure that the GPU is powered on when connector polling is
2315          * performed. Since we're calling this from a runtime PM callback,
2316          * trying to acquire rpm refs will cause us to deadlock.
2317          *
2318          * Since we're guaranteed to be holding the rpm lock, it's safe to
2319          * temporarily disable the rpm helpers so this doesn't deadlock us.
2320          */
2321 #ifdef CONFIG_PM
2322         dev->dev->power.disable_depth++;
2323 #endif
2324         if (!amdgpu_device_has_dc_support(adev))
2325                 drm_helper_hpd_irq_event(dev);
2326         else
2327                 drm_kms_helper_hotplug_event(dev);
2328 #ifdef CONFIG_PM
2329         dev->dev->power.disable_depth--;
2330 #endif
2331
2332         if (fbcon)
2333                 amdgpu_fbdev_set_suspend(adev, 0);
2334
2335 unlock:
2336         if (fbcon)
2337                 console_unlock();
2338
2339         return r;
2340 }
2341
2342 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2343 {
2344         int i;
2345         bool asic_hang = false;
2346
2347         if (amdgpu_sriov_vf(adev))
2348                 return true;
2349
2350         for (i = 0; i < adev->num_ip_blocks; i++) {
2351                 if (!adev->ip_blocks[i].status.valid)
2352                         continue;
2353                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2354                         adev->ip_blocks[i].status.hang =
2355                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2356                 if (adev->ip_blocks[i].status.hang) {
2357                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2358                         asic_hang = true;
2359                 }
2360         }
2361         return asic_hang;
2362 }
2363
2364 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2365 {
2366         int i, r = 0;
2367
2368         for (i = 0; i < adev->num_ip_blocks; i++) {
2369                 if (!adev->ip_blocks[i].status.valid)
2370                         continue;
2371                 if (adev->ip_blocks[i].status.hang &&
2372                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2373                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2374                         if (r)
2375                                 return r;
2376                 }
2377         }
2378
2379         return 0;
2380 }
2381
2382 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2383 {
2384         int i;
2385
2386         for (i = 0; i < adev->num_ip_blocks; i++) {
2387                 if (!adev->ip_blocks[i].status.valid)
2388                         continue;
2389                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2390                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2391                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2392                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2393                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2394                         if (adev->ip_blocks[i].status.hang) {
2395                                 DRM_INFO("Some block need full reset!\n");
2396                                 return true;
2397                         }
2398                 }
2399         }
2400         return false;
2401 }
2402
2403 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2404 {
2405         int i, r = 0;
2406
2407         for (i = 0; i < adev->num_ip_blocks; i++) {
2408                 if (!adev->ip_blocks[i].status.valid)
2409                         continue;
2410                 if (adev->ip_blocks[i].status.hang &&
2411                     adev->ip_blocks[i].version->funcs->soft_reset) {
2412                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2413                         if (r)
2414                                 return r;
2415                 }
2416         }
2417
2418         return 0;
2419 }
2420
2421 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
2422 {
2423         int i, r = 0;
2424
2425         for (i = 0; i < adev->num_ip_blocks; i++) {
2426                 if (!adev->ip_blocks[i].status.valid)
2427                         continue;
2428                 if (adev->ip_blocks[i].status.hang &&
2429                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2430                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2431                 if (r)
2432                         return r;
2433         }
2434
2435         return 0;
2436 }
2437
2438 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
2439                                                   struct amdgpu_ring *ring,
2440                                                   struct amdgpu_bo *bo,
2441                                                   struct dma_fence **fence)
2442 {
2443         uint32_t domain;
2444         int r;
2445
2446         if (!bo->shadow)
2447                 return 0;
2448
2449         r = amdgpu_bo_reserve(bo, true);
2450         if (r)
2451                 return r;
2452         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2453         /* if bo has been evicted, then no need to recover */
2454         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2455                 r = amdgpu_bo_validate(bo->shadow);
2456                 if (r) {
2457                         DRM_ERROR("bo validate failed!\n");
2458                         goto err;
2459                 }
2460
2461                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2462                                                  NULL, fence, true);
2463                 if (r) {
2464                         DRM_ERROR("recover page table failed!\n");
2465                         goto err;
2466                 }
2467         }
2468 err:
2469         amdgpu_bo_unreserve(bo);
2470         return r;
2471 }
2472
2473 /*
2474  * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
2475  *
2476  * @adev: amdgpu device pointer
2477  * @reset_flags: output param tells caller the reset result
2478  *
2479  * attempt to do soft-reset or full-reset and reinitialize Asic
2480  * return 0 means successed otherwise failed
2481 */
2482 static int amdgpu_device_reset(struct amdgpu_device *adev,
2483                                uint64_t* reset_flags)
2484 {
2485         bool need_full_reset, vram_lost = 0;
2486         int r;
2487
2488         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
2489
2490         if (!need_full_reset) {
2491                 amdgpu_device_ip_pre_soft_reset(adev);
2492                 r = amdgpu_device_ip_soft_reset(adev);
2493                 amdgpu_device_ip_post_soft_reset(adev);
2494                 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
2495                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2496                         need_full_reset = true;
2497                 }
2498
2499         }
2500
2501         if (need_full_reset) {
2502                 r = amdgpu_device_ip_suspend(adev);
2503
2504 retry:
2505                 r = amdgpu_asic_reset(adev);
2506                 /* post card */
2507                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2508
2509                 if (!r) {
2510                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2511                         r = amdgpu_device_ip_resume_phase1(adev);
2512                         if (r)
2513                                 goto out;
2514
2515                         vram_lost = amdgpu_device_check_vram_lost(adev);
2516                         if (vram_lost) {
2517                                 DRM_ERROR("VRAM is lost!\n");
2518                                 atomic_inc(&adev->vram_lost_counter);
2519                         }
2520
2521                         r = amdgpu_gtt_mgr_recover(
2522                                 &adev->mman.bdev.man[TTM_PL_TT]);
2523                         if (r)
2524                                 goto out;
2525
2526                         r = amdgpu_device_ip_resume_phase2(adev);
2527                         if (r)
2528                                 goto out;
2529
2530                         if (vram_lost)
2531                                 amdgpu_device_fill_reset_magic(adev);
2532                 }
2533         }
2534
2535 out:
2536         if (!r) {
2537                 amdgpu_irq_gpu_reset_resume_helper(adev);
2538                 r = amdgpu_ib_ring_tests(adev);
2539                 if (r) {
2540                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2541                         r = amdgpu_device_ip_suspend(adev);
2542                         need_full_reset = true;
2543                         goto retry;
2544                 }
2545         }
2546
2547         if (reset_flags) {
2548                 if (vram_lost)
2549                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2550
2551                 if (need_full_reset)
2552                         (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2553         }
2554
2555         return r;
2556 }
2557
2558 /*
2559  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
2560  *
2561  * @adev: amdgpu device pointer
2562  * @reset_flags: output param tells caller the reset result
2563  *
2564  * do VF FLR and reinitialize Asic
2565  * return 0 means successed otherwise failed
2566 */
2567 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
2568                                      uint64_t *reset_flags,
2569                                      bool from_hypervisor)
2570 {
2571         int r;
2572
2573         if (from_hypervisor)
2574                 r = amdgpu_virt_request_full_gpu(adev, true);
2575         else
2576                 r = amdgpu_virt_reset_gpu(adev);
2577         if (r)
2578                 return r;
2579
2580         /* Resume IP prior to SMC */
2581         r = amdgpu_device_ip_reinit_early_sriov(adev);
2582         if (r)
2583                 goto error;
2584
2585         /* we need recover gart prior to run SMC/CP/SDMA resume */
2586         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
2587
2588         /* now we are okay to resume SMC/CP/SDMA */
2589         r = amdgpu_device_ip_reinit_late_sriov(adev);
2590         if (r)
2591                 goto error;
2592
2593         amdgpu_irq_gpu_reset_resume_helper(adev);
2594         r = amdgpu_ib_ring_tests(adev);
2595         if (r)
2596                 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2597
2598 error:
2599         /* release full control of GPU after ib test */
2600         amdgpu_virt_release_full_gpu(adev, true);
2601
2602         if (reset_flags) {
2603                 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
2604                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2605                         atomic_inc(&adev->vram_lost_counter);
2606                 }
2607
2608                 /* VF FLR or hotlink reset is always full-reset */
2609                 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2610         }
2611
2612         return r;
2613 }
2614
2615 /**
2616  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
2617  *
2618  * @adev: amdgpu device pointer
2619  * @job: which job trigger hang
2620  * @force forces reset regardless of amdgpu_gpu_recovery
2621  *
2622  * Attempt to reset the GPU if it has hung (all asics).
2623  * Returns 0 for success or an error on failure.
2624  */
2625 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
2626                               struct amdgpu_job *job, bool force)
2627 {
2628         struct drm_atomic_state *state = NULL;
2629         uint64_t reset_flags = 0;
2630         int i, r, resched;
2631
2632         if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
2633                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2634                 return 0;
2635         }
2636
2637         if (!force && (amdgpu_gpu_recovery == 0 ||
2638                         (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))) {
2639                 DRM_INFO("GPU recovery disabled.\n");
2640                 return 0;
2641         }
2642
2643         dev_info(adev->dev, "GPU reset begin!\n");
2644
2645         mutex_lock(&adev->lock_reset);
2646         atomic_inc(&adev->gpu_reset_counter);
2647         adev->in_gpu_reset = 1;
2648
2649         /* block TTM */
2650         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2651
2652         /* store modesetting */
2653         if (amdgpu_device_has_dc_support(adev))
2654                 state = drm_atomic_helper_suspend(adev->ddev);
2655
2656         /* block all schedulers and reset given job's ring */
2657         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2658                 struct amdgpu_ring *ring = adev->rings[i];
2659
2660                 if (!ring || !ring->sched.thread)
2661                         continue;
2662
2663                 kthread_park(ring->sched.thread);
2664
2665                 if (job && job->ring->idx != i)
2666                         continue;
2667
2668                 drm_sched_hw_job_reset(&ring->sched, &job->base);
2669
2670                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2671                 amdgpu_fence_driver_force_completion(ring);
2672         }
2673
2674         if (amdgpu_sriov_vf(adev))
2675                 r = amdgpu_device_reset_sriov(adev, &reset_flags, job ? false : true);
2676         else
2677                 r = amdgpu_device_reset(adev, &reset_flags);
2678
2679         if (!r) {
2680                 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
2681                         (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
2682                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2683                         struct amdgpu_bo *bo, *tmp;
2684                         struct dma_fence *fence = NULL, *next = NULL;
2685
2686                         DRM_INFO("recover vram bo from shadow\n");
2687                         mutex_lock(&adev->shadow_list_lock);
2688                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2689                                 next = NULL;
2690                                 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
2691                                 if (fence) {
2692                                         r = dma_fence_wait(fence, false);
2693                                         if (r) {
2694                                                 WARN(r, "recovery from shadow isn't completed\n");
2695                                                 break;
2696                                         }
2697                                 }
2698
2699                                 dma_fence_put(fence);
2700                                 fence = next;
2701                         }
2702                         mutex_unlock(&adev->shadow_list_lock);
2703                         if (fence) {
2704                                 r = dma_fence_wait(fence, false);
2705                                 if (r)
2706                                         WARN(r, "recovery from shadow isn't completed\n");
2707                         }
2708                         dma_fence_put(fence);
2709                 }
2710         }
2711
2712         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2713                 struct amdgpu_ring *ring = adev->rings[i];
2714
2715                 if (!ring || !ring->sched.thread)
2716                         continue;
2717
2718                 /* only need recovery sched of the given job's ring
2719                  * or all rings (in the case @job is NULL)
2720                  * after above amdgpu_reset accomplished
2721                  */
2722                 if ((!job || job->ring->idx == i) && !r)
2723                         drm_sched_job_recovery(&ring->sched);
2724
2725                 kthread_unpark(ring->sched.thread);
2726         }
2727
2728         if (amdgpu_device_has_dc_support(adev)) {
2729                 if (drm_atomic_helper_resume(adev->ddev, state))
2730                         dev_info(adev->dev, "drm resume failed:%d\n", r);
2731         } else {
2732                 drm_helper_resume_force_mode(adev->ddev);
2733         }
2734
2735         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2736
2737         if (r) {
2738                 /* bad news, how to tell it to userspace ? */
2739                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
2740                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
2741         } else {
2742                 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
2743         }
2744
2745         amdgpu_vf_error_trans_all(adev);
2746         adev->in_gpu_reset = 0;
2747         mutex_unlock(&adev->lock_reset);
2748         return r;
2749 }
2750
2751 void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
2752 {
2753         u32 mask;
2754         int ret;
2755
2756         if (amdgpu_pcie_gen_cap)
2757                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2758
2759         if (amdgpu_pcie_lane_cap)
2760                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2761
2762         /* covers APUs as well */
2763         if (pci_is_root_bus(adev->pdev->bus)) {
2764                 if (adev->pm.pcie_gen_mask == 0)
2765                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2766                 if (adev->pm.pcie_mlw_mask == 0)
2767                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2768                 return;
2769         }
2770
2771         if (adev->pm.pcie_gen_mask == 0) {
2772                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2773                 if (!ret) {
2774                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2775                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2776                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2777
2778                         if (mask & DRM_PCIE_SPEED_25)
2779                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2780                         if (mask & DRM_PCIE_SPEED_50)
2781                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2782                         if (mask & DRM_PCIE_SPEED_80)
2783                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2784                 } else {
2785                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2786                 }
2787         }
2788         if (adev->pm.pcie_mlw_mask == 0) {
2789                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2790                 if (!ret) {
2791                         switch (mask) {
2792                         case 32:
2793                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2794                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2795                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2796                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2797                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2798                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2799                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2800                                 break;
2801                         case 16:
2802                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2803                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2804                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2805                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2806                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2807                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2808                                 break;
2809                         case 12:
2810                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2811                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2812                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2813                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2814                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2815                                 break;
2816                         case 8:
2817                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2818                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2819                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2820                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2821                                 break;
2822                         case 4:
2823                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2824                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2825                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2826                                 break;
2827                         case 2:
2828                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2829                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2830                                 break;
2831                         case 1:
2832                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2833                                 break;
2834                         default:
2835                                 break;
2836                         }
2837                 } else {
2838                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2839                 }
2840         }
2841 }
2842