drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amdgpu_atomfirmware.h"
  44 #include "amd_pcie.h"
  45 #ifdef CONFIG_DRM_AMDGPU_SI
  46 #include "si.h"
  47 #endif
  48 #ifdef CONFIG_DRM_AMDGPU_CIK
  49 #include "cik.h"
  50 #endif
  51 #include "vi.h"
  52 #include "soc15.h"
  53 #include "bif/bif_4_1_d.h"
  54 #include <linux/pci.h>
  55 #include <linux/firmware.h>
  56 #include "amdgpu_vf_error.h"
  57
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_pm.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  63
  64 #define AMDGPU_RESUME_MS                2000
  65
  66 static const char *amdgpu_asic_name[] = {
  67         "TAHITI",
  68         "PITCAIRN",
  69         "VERDE",
  70         "OLAND",
  71         "HAINAN",
  72         "BONAIRE",
  73         "KAVERI",
  74         "KABINI",
  75         "HAWAII",
  76         "MULLINS",
  77         "TOPAZ",
  78         "TONGA",
  79         "FIJI",
  80         "CARRIZO",
  81         "STONEY",
  82         "POLARIS10",
  83         "POLARIS11",
  84         "POLARIS12",
  85         "VEGA10",
  86         "RAVEN",
  87         "LAST",
  88 };
  89
  90 bool amdgpu_device_is_px(struct drm_device *dev)
  91 {
  92         struct amdgpu_device *adev = dev->dev_private;
  93
  94         if (adev->flags & AMD_IS_PX)
  95                 return true;
  96         return false;
  97 }
  98
  99 /*
 100  * MMIO register access helper functions.
 101  */
 102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 103                         uint32_t acc_flags)
 104 {
 105         uint32_t ret;
 106
 107         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 108                 return amdgpu_virt_kiq_rreg(adev, reg);
 109
 110         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 111                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 112         else {
 113                 unsigned long flags;
 114
 115                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 116                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 117                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 118                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 119         }
 120         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 121         return ret;
 122 }
 123
 124 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 125                     uint32_t acc_flags)
 126 {
 127         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 128
 129         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 130                 adev->last_mm_index = v;
 131         }
 132
 133         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 134                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 135
 136         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 137                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 138         else {
 139                 unsigned long flags;
 140
 141                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 142                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 143                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 144                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 145         }
 146
 147         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 148                 udelay(500);
 149         }
 150 }
 151
 152 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 153 {
 154         if ((reg * 4) < adev->rio_mem_size)
 155                 return ioread32(adev->rio_mem + (reg * 4));
 156         else {
 157                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 158                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 159         }
 160 }
 161
 162 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 163 {
 164         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 165                 adev->last_mm_index = v;
 166         }
 167
 168         if ((reg * 4) < adev->rio_mem_size)
 169                 iowrite32(v, adev->rio_mem + (reg * 4));
 170         else {
 171                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 172                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 173         }
 174
 175         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 176                 udelay(500);
 177         }
 178 }
 179
 180 /**
 181  * amdgpu_mm_rdoorbell - read a doorbell dword
 182  *
 183  * @adev: amdgpu_device pointer
 184  * @index: doorbell index
 185  *
 186  * Returns the value in the doorbell aperture at the
 187  * requested doorbell index (CIK).
 188  */
 189 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 190 {
 191         if (index < adev->doorbell.num_doorbells) {
 192                 return readl(adev->doorbell.ptr + index);
 193         } else {
 194                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 195                 return 0;
 196         }
 197 }
 198
 199 /**
 200  * amdgpu_mm_wdoorbell - write a doorbell dword
 201  *
 202  * @adev: amdgpu_device pointer
 203  * @index: doorbell index
 204  * @v: value to write
 205  *
 206  * Writes @v to the doorbell aperture at the
 207  * requested doorbell index (CIK).
 208  */
 209 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 210 {
 211         if (index < adev->doorbell.num_doorbells) {
 212                 writel(v, adev->doorbell.ptr + index);
 213         } else {
 214                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 215         }
 216 }
 217
 218 /**
 219  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 220  *
 221  * @adev: amdgpu_device pointer
 222  * @index: doorbell index
 223  *
 224  * Returns the value in the doorbell aperture at the
 225  * requested doorbell index (VEGA10+).
 226  */
 227 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 228 {
 229         if (index < adev->doorbell.num_doorbells) {
 230                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 231         } else {
 232                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 233                 return 0;
 234         }
 235 }
 236
 237 /**
 238  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 239  *
 240  * @adev: amdgpu_device pointer
 241  * @index: doorbell index
 242  * @v: value to write
 243  *
 244  * Writes @v to the doorbell aperture at the
 245  * requested doorbell index (VEGA10+).
 246  */
 247 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 248 {
 249         if (index < adev->doorbell.num_doorbells) {
 250                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 251         } else {
 252                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 253         }
 254 }
 255
 256 /**
 257  * amdgpu_invalid_rreg - dummy reg read function
 258  *
 259  * @adev: amdgpu device pointer
 260  * @reg: offset of register
 261  *
 262  * Dummy register read function.  Used for register blocks
 263  * that certain asics don't have (all asics).
 264  * Returns the value in the register.
 265  */
 266 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 267 {
 268         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 269         BUG();
 270         return 0;
 271 }
 272
 273 /**
 274  * amdgpu_invalid_wreg - dummy reg write function
 275  *
 276  * @adev: amdgpu device pointer
 277  * @reg: offset of register
 278  * @v: value to write to the register
 279  *
 280  * Dummy register read function.  Used for register blocks
 281  * that certain asics don't have (all asics).
 282  */
 283 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 284 {
 285         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 286                   reg, v);
 287         BUG();
 288 }
 289
 290 /**
 291  * amdgpu_block_invalid_rreg - dummy reg read function
 292  *
 293  * @adev: amdgpu device pointer
 294  * @block: offset of instance
 295  * @reg: offset of register
 296  *
 297  * Dummy register read function.  Used for register blocks
 298  * that certain asics don't have (all asics).
 299  * Returns the value in the register.
 300  */
 301 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 302                                           uint32_t block, uint32_t reg)
 303 {
 304         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 305                   reg, block);
 306         BUG();
 307         return 0;
 308 }
 309
 310 /**
 311  * amdgpu_block_invalid_wreg - dummy reg write function
 312  *
 313  * @adev: amdgpu device pointer
 314  * @block: offset of instance
 315  * @reg: offset of register
 316  * @v: value to write to the register
 317  *
 318  * Dummy register read function.  Used for register blocks
 319  * that certain asics don't have (all asics).
 320  */
 321 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 322                                       uint32_t block,
 323                                       uint32_t reg, uint32_t v)
 324 {
 325         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 326                   reg, block, v);
 327         BUG();
 328 }
 329
 330 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 331 {
 332         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 333                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 334                                        &adev->vram_scratch.robj,
 335                                        &adev->vram_scratch.gpu_addr,
 336                                        (void **)&adev->vram_scratch.ptr);
 337 }
 338
 339 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 340 {
 341         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 342 }
 343
 344 /**
 345  * amdgpu_device_program_register_sequence - program an array of registers.
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @registers: pointer to the register array
 349  * @array_size: size of the register array
 350  *
 351  * Programs an array or registers with and and or masks.
 352  * This is a helper for setting golden registers.
 353  */
 354 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 355                                              const u32 *registers,
 356                                              const u32 array_size)
 357 {
 358         u32 tmp, reg, and_mask, or_mask;
 359         int i;
 360
 361         if (array_size % 3)
 362                 return;
 363
 364         for (i = 0; i < array_size; i +=3) {
 365                 reg = registers[i + 0];
 366                 and_mask = registers[i + 1];
 367                 or_mask = registers[i + 2];
 368
 369                 if (and_mask == 0xffffffff) {
 370                         tmp = or_mask;
 371                 } else {
 372                         tmp = RREG32(reg);
 373                         tmp &= ~and_mask;
 374                         tmp |= or_mask;
 375                 }
 376                 WREG32(reg, tmp);
 377         }
 378 }
 379
 380 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 381 {
 382         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 383 }
 384
 385 /*
 386  * GPU doorbell aperture helpers function.
 387  */
 388 /**
 389  * amdgpu_device_doorbell_init - Init doorbell driver information.
 390  *
 391  * @adev: amdgpu_device pointer
 392  *
 393  * Init doorbell driver information (CIK)
 394  * Returns 0 on success, error on failure.
 395  */
 396 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 397 {
 398         /* No doorbell on SI hardware generation */
 399         if (adev->asic_type < CHIP_BONAIRE) {
 400                 adev->doorbell.base = 0;
 401                 adev->doorbell.size = 0;
 402                 adev->doorbell.num_doorbells = 0;
 403                 adev->doorbell.ptr = NULL;
 404                 return 0;
 405         }
 406
 407         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 408                 return -EINVAL;
 409
 410         /* doorbell bar mapping */
 411         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 412         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 413
 414         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 415                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 416         if (adev->doorbell.num_doorbells == 0)
 417                 return -EINVAL;
 418
 419         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 420                                      adev->doorbell.num_doorbells *
 421                                      sizeof(u32));
 422         if (adev->doorbell.ptr == NULL)
 423                 return -ENOMEM;
 424
 425         return 0;
 426 }
 427
 428 /**
 429  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 430  *
 431  * @adev: amdgpu_device pointer
 432  *
 433  * Tear down doorbell driver information (CIK)
 434  */
 435 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 436 {
 437         iounmap(adev->doorbell.ptr);
 438         adev->doorbell.ptr = NULL;
 439 }
 440
 441
 442
 443 /*
 444  * amdgpu_device_wb_*()
 445  * Writeback is the method by which the GPU updates special pages in memory
 446  * with the status of certain GPU events (fences, ring pointers,etc.).
 447  */
 448
 449 /**
 450  * amdgpu_device_wb_fini - Disable Writeback and free memory
 451  *
 452  * @adev: amdgpu_device pointer
 453  *
 454  * Disables Writeback and frees the Writeback memory (all asics).
 455  * Used at driver shutdown.
 456  */
 457 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 458 {
 459         if (adev->wb.wb_obj) {
 460                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 461                                       &adev->wb.gpu_addr,
 462                                       (void **)&adev->wb.wb);
 463                 adev->wb.wb_obj = NULL;
 464         }
 465 }
 466
 467 /**
 468  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 469  *
 470  * @adev: amdgpu_device pointer
 471  *
 472  * Initializes writeback and allocates writeback memory (all asics).
 473  * Used at driver startup.
 474  * Returns 0 on success or an -error on failure.
 475  */
 476 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 477 {
 478         int r;
 479
 480         if (adev->wb.wb_obj == NULL) {
 481                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 482                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 483                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 484                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 485                                             (void **)&adev->wb.wb);
 486                 if (r) {
 487                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 488                         return r;
 489                 }
 490
 491                 adev->wb.num_wb = AMDGPU_MAX_WB;
 492                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 493
 494                 /* clear wb memory */
 495                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
 496         }
 497
 498         return 0;
 499 }
 500
 501 /**
 502  * amdgpu_device_wb_get - Allocate a wb entry
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @wb: wb index
 506  *
 507  * Allocate a wb slot for use by the driver (all asics).
 508  * Returns 0 on success or -EINVAL on failure.
 509  */
 510 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 511 {
 512         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 513
 514         if (offset < adev->wb.num_wb) {
 515                 __set_bit(offset, adev->wb.used);
 516                 *wb = offset << 3; /* convert to dw offset */
 517                 return 0;
 518         } else {
 519                 return -EINVAL;
 520         }
 521 }
 522
 523 /**
 524  * amdgpu_device_wb_free - Free a wb entry
 525  *
 526  * @adev: amdgpu_device pointer
 527  * @wb: wb index
 528  *
 529  * Free a wb slot allocated for use by the driver (all asics)
 530  */
 531 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 532 {
 533         if (wb < adev->wb.num_wb)
 534                 __clear_bit(wb >> 3, adev->wb.used);
 535 }
 536
 537 /**
 538  * amdgpu_device_vram_location - try to find VRAM location
 539  * @adev: amdgpu device structure holding all necessary informations
 540  * @mc: memory controller structure holding memory informations
 541  * @base: base address at which to put VRAM
 542  *
 543  * Function will try to place VRAM at base address provided
 544  * as parameter.
 545  */
 546 void amdgpu_device_vram_location(struct amdgpu_device *adev,
 547                                  struct amdgpu_gmc *mc, u64 base)
 548 {
 549         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 550
 551         mc->vram_start = base;
 552         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 553         if (limit && limit < mc->real_vram_size)
 554                 mc->real_vram_size = limit;
 555         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 556                         mc->mc_vram_size >> 20, mc->vram_start,
 557                         mc->vram_end, mc->real_vram_size >> 20);
 558 }
 559
 560 /**
 561  * amdgpu_device_gart_location - try to find GTT location
 562  * @adev: amdgpu device structure holding all necessary informations
 563  * @mc: memory controller structure holding memory informations
 564  *
 565  * Function will place try to place GTT before or after VRAM.
 566  *
 567  * If GTT size is bigger than space left then we ajust GTT size.
 568  * Thus function will never fails.
 569  *
 570  * FIXME: when reducing GTT size align new size on power of 2.
 571  */
 572 void amdgpu_device_gart_location(struct amdgpu_device *adev,
 573                                  struct amdgpu_gmc *mc)
 574 {
 575         u64 size_af, size_bf;
 576
 577         size_af = adev->gmc.mc_mask - mc->vram_end;
 578         size_bf = mc->vram_start;
 579         if (size_bf > size_af) {
 580                 if (mc->gart_size > size_bf) {
 581                         dev_warn(adev->dev, "limiting GTT\n");
 582                         mc->gart_size = size_bf;
 583                 }
 584                 mc->gart_start = 0;
 585         } else {
 586                 if (mc->gart_size > size_af) {
 587                         dev_warn(adev->dev, "limiting GTT\n");
 588                         mc->gart_size = size_af;
 589                 }
 590                 /* VCE doesn't like it when BOs cross a 4GB segment, so align
 591                  * the GART base on a 4GB boundary as well.
 592                  */
 593                 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
 594         }
 595         mc->gart_end = mc->gart_start + mc->gart_size - 1;
 596         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 597                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 598 }
 599
 600 /**
 601  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 606  * to fail, but if any of the BARs is not accessible after the size we abort
 607  * driver loading by returning -ENODEV.
 608  */
 609 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 610 {
 611         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 612         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 613         struct pci_bus *root;
 614         struct resource *res;
 615         unsigned i;
 616         u16 cmd;
 617         int r;
 618
 619         /* Bypass for VF */
 620         if (amdgpu_sriov_vf(adev))
 621                 return 0;
 622
 623         /* Check if the root BUS has 64bit memory resources */
 624         root = adev->pdev->bus;
 625         while (root->parent)
 626                 root = root->parent;
 627
 628         pci_bus_for_each_resource(root, res, i) {
 629                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 630                     res->start > 0x100000000ull)
 631                         break;
 632         }
 633
 634         /* Trying to resize is pointless without a root hub window above 4GB */
 635         if (!res)
 636                 return 0;
 637
 638         /* Disable memory decoding while we change the BAR addresses and size */
 639         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 640         pci_write_config_word(adev->pdev, PCI_COMMAND,
 641                               cmd & ~PCI_COMMAND_MEMORY);
 642
 643         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 644         amdgpu_device_doorbell_fini(adev);
 645         if (adev->asic_type >= CHIP_BONAIRE)
 646                 pci_release_resource(adev->pdev, 2);
 647
 648         pci_release_resource(adev->pdev, 0);
 649
 650         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 651         if (r == -ENOSPC)
 652                 DRM_INFO("Not enough PCI address space for a large BAR.");
 653         else if (r && r != -ENOTSUPP)
 654                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 655
 656         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 657
 658         /* When the doorbell or fb BAR isn't available we have no chance of
 659          * using the device.
 660          */
 661         r = amdgpu_device_doorbell_init(adev);
 662         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 663                 return -ENODEV;
 664
 665         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * GPU helpers function.
 672  */
 673 /**
 674  * amdgpu_device_need_post - check if the hw need post or not
 675  *
 676  * @adev: amdgpu_device pointer
 677  *
 678  * Check if the asic has been initialized (all asics) at driver startup
 679  * or post is needed if  hw reset is performed.
 680  * Returns true if need or false if not.
 681  */
 682 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 683 {
 684         uint32_t reg;
 685
 686         if (amdgpu_sriov_vf(adev))
 687                 return false;
 688
 689         if (amdgpu_passthrough(adev)) {
 690                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 691                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 692                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 693                  * vpost executed for smc version below 22.15
 694                  */
 695                 if (adev->asic_type == CHIP_FIJI) {
 696                         int err;
 697                         uint32_t fw_ver;
 698                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 699                         /* force vPost if error occured */
 700                         if (err)
 701                                 return true;
 702
 703                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 704                         if (fw_ver < 0x00160e00)
 705                                 return true;
 706                 }
 707         }
 708
 709         if (adev->has_hw_reset) {
 710                 adev->has_hw_reset = false;
 711                 return true;
 712         }
 713
 714         /* bios scratch used on CIK+ */
 715         if (adev->asic_type >= CHIP_BONAIRE)
 716                 return amdgpu_atombios_scratch_need_asic_init(adev);
 717
 718         /* check MEM_SIZE for older asics */
 719         reg = amdgpu_asic_get_config_memsize(adev);
 720
 721         if ((reg != 0) && (reg != 0xffffffff))
 722                 return false;
 723
 724         return true;
 725 }
 726
 727 /* if we get transitioned to only one device, take VGA back */
 728 /**
 729  * amdgpu_device_vga_set_decode - enable/disable vga decode
 730  *
 731  * @cookie: amdgpu_device pointer
 732  * @state: enable/disable vga decode
 733  *
 734  * Enable/disable vga decode (all asics).
 735  * Returns VGA resource flags.
 736  */
 737 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 738 {
 739         struct amdgpu_device *adev = cookie;
 740         amdgpu_asic_set_vga_state(adev, state);
 741         if (state)
 742                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 743                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 744         else
 745                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 746 }
 747
 748 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 749 {
 750         /* defines number of bits in page table versus page directory,
 751          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 752          * page table and the remaining bits are in the page directory */
 753         if (amdgpu_vm_block_size == -1)
 754                 return;
 755
 756         if (amdgpu_vm_block_size < 9) {
 757                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 758                          amdgpu_vm_block_size);
 759                 amdgpu_vm_block_size = -1;
 760         }
 761 }
 762
 763 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 764 {
 765         /* no need to check the default value */
 766         if (amdgpu_vm_size == -1)
 767                 return;
 768
 769         if (amdgpu_vm_size < 1) {
 770                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 771                          amdgpu_vm_size);
 772                 amdgpu_vm_size = -1;
 773         }
 774 }
 775
 776 /**
 777  * amdgpu_device_check_arguments - validate module params
 778  *
 779  * @adev: amdgpu_device pointer
 780  *
 781  * Validates certain module parameters and updates
 782  * the associated values used by the driver (all asics).
 783  */
 784 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 785 {
 786         if (amdgpu_sched_jobs < 4) {
 787                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 788                          amdgpu_sched_jobs);
 789                 amdgpu_sched_jobs = 4;
 790         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 791                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 792                          amdgpu_sched_jobs);
 793                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 794         }
 795
 796         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 797                 /* gart size must be greater or equal to 32M */
 798                 dev_warn(adev->dev, "gart size (%d) too small\n",
 799                          amdgpu_gart_size);
 800                 amdgpu_gart_size = -1;
 801         }
 802
 803         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 804                 /* gtt size must be greater or equal to 32M */
 805                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 806                                  amdgpu_gtt_size);
 807                 amdgpu_gtt_size = -1;
 808         }
 809
 810         /* valid range is between 4 and 9 inclusive */
 811         if (amdgpu_vm_fragment_size != -1 &&
 812             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 813                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 814                 amdgpu_vm_fragment_size = -1;
 815         }
 816
 817         amdgpu_device_check_vm_size(adev);
 818
 819         amdgpu_device_check_block_size(adev);
 820
 821         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 822             !is_power_of_2(amdgpu_vram_page_split))) {
 823                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
 824                          amdgpu_vram_page_split);
 825                 amdgpu_vram_page_split = 1024;
 826         }
 827
 828         if (amdgpu_lockup_timeout == 0) {
 829                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
 830                 amdgpu_lockup_timeout = 10000;
 831         }
 832 }
 833
 834 /**
 835  * amdgpu_switcheroo_set_state - set switcheroo state
 836  *
 837  * @pdev: pci dev pointer
 838  * @state: vga_switcheroo state
 839  *
 840  * Callback for the switcheroo driver.  Suspends or resumes the
 841  * the asics before or after it is powered up using ACPI methods.
 842  */
 843 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 844 {
 845         struct drm_device *dev = pci_get_drvdata(pdev);
 846
 847         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 848                 return;
 849
 850         if (state == VGA_SWITCHEROO_ON) {
 851                 pr_info("amdgpu: switched on\n");
 852                 /* don't suspend or resume card normally */
 853                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 854
 855                 amdgpu_device_resume(dev, true, true);
 856
 857                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 858                 drm_kms_helper_poll_enable(dev);
 859         } else {
 860                 pr_info("amdgpu: switched off\n");
 861                 drm_kms_helper_poll_disable(dev);
 862                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 863                 amdgpu_device_suspend(dev, true, true);
 864                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 865         }
 866 }
 867
 868 /**
 869  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
 870  *
 871  * @pdev: pci dev pointer
 872  *
 873  * Callback for the switcheroo driver.  Check of the switcheroo
 874  * state can be changed.
 875  * Returns true if the state can be changed, false if not.
 876  */
 877 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
 878 {
 879         struct drm_device *dev = pci_get_drvdata(pdev);
 880
 881         /*
 882         * FIXME: open_count is protected by drm_global_mutex but that would lead to
 883         * locking inversion with the driver load path. And the access here is
 884         * completely racy anyway. So don't bother with locking for now.
 885         */
 886         return dev->open_count == 0;
 887 }
 888
 889 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
 890         .set_gpu_state = amdgpu_switcheroo_set_state,
 891         .reprobe = NULL,
 892         .can_switch = amdgpu_switcheroo_can_switch,
 893 };
 894
 895 int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
 896                                            enum amd_ip_block_type block_type,
 897                                            enum amd_clockgating_state state)
 898 {
 899         int i, r = 0;
 900
 901         for (i = 0; i < adev->num_ip_blocks; i++) {
 902                 if (!adev->ip_blocks[i].status.valid)
 903                         continue;
 904                 if (adev->ip_blocks[i].version->type != block_type)
 905                         continue;
 906                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
 907                         continue;
 908                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
 909                         (void *)adev, state);
 910                 if (r)
 911                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
 912                                   adev->ip_blocks[i].version->funcs->name, r);
 913         }
 914         return r;
 915 }
 916
 917 int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
 918                                            enum amd_ip_block_type block_type,
 919                                            enum amd_powergating_state state)
 920 {
 921         int i, r = 0;
 922
 923         for (i = 0; i < adev->num_ip_blocks; i++) {
 924                 if (!adev->ip_blocks[i].status.valid)
 925                         continue;
 926                 if (adev->ip_blocks[i].version->type != block_type)
 927                         continue;
 928                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
 929                         continue;
 930                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
 931                         (void *)adev, state);
 932                 if (r)
 933                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
 934                                   adev->ip_blocks[i].version->funcs->name, r);
 935         }
 936         return r;
 937 }
 938
 939 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
 940                                             u32 *flags)
 941 {
 942         int i;
 943
 944         for (i = 0; i < adev->num_ip_blocks; i++) {
 945                 if (!adev->ip_blocks[i].status.valid)
 946                         continue;
 947                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
 948                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
 949         }
 950 }
 951
 952 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
 953                                    enum amd_ip_block_type block_type)
 954 {
 955         int i, r;
 956
 957         for (i = 0; i < adev->num_ip_blocks; i++) {
 958                 if (!adev->ip_blocks[i].status.valid)
 959                         continue;
 960                 if (adev->ip_blocks[i].version->type == block_type) {
 961                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
 962                         if (r)
 963                                 return r;
 964                         break;
 965                 }
 966         }
 967         return 0;
 968
 969 }
 970
 971 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
 972                               enum amd_ip_block_type block_type)
 973 {
 974         int i;
 975
 976         for (i = 0; i < adev->num_ip_blocks; i++) {
 977                 if (!adev->ip_blocks[i].status.valid)
 978                         continue;
 979                 if (adev->ip_blocks[i].version->type == block_type)
 980                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
 981         }
 982         return true;
 983
 984 }
 985
 986 struct amdgpu_ip_block *
 987 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 988                               enum amd_ip_block_type type)
 989 {
 990         int i;
 991
 992         for (i = 0; i < adev->num_ip_blocks; i++)
 993                 if (adev->ip_blocks[i].version->type == type)
 994                         return &adev->ip_blocks[i];
 995
 996         return NULL;
 997 }
 998
 999 /**
1000  * amdgpu_device_ip_block_version_cmp
1001  *
1002  * @adev: amdgpu_device pointer
1003  * @type: enum amd_ip_block_type
1004  * @major: major version
1005  * @minor: minor version
1006  *
1007  * return 0 if equal or greater
1008  * return 1 if smaller or the ip_block doesn't exist
1009  */
1010 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1011                                        enum amd_ip_block_type type,
1012                                        u32 major, u32 minor)
1013 {
1014         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1015
1016         if (ip_block && ((ip_block->version->major > major) ||
1017                         ((ip_block->version->major == major) &&
1018                         (ip_block->version->minor >= minor))))
1019                 return 0;
1020
1021         return 1;
1022 }
1023
1024 /**
1025  * amdgpu_device_ip_block_add
1026  *
1027  * @adev: amdgpu_device pointer
1028  * @ip_block_version: pointer to the IP to add
1029  *
1030  * Adds the IP block driver information to the collection of IPs
1031  * on the asic.
1032  */
1033 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1034                                const struct amdgpu_ip_block_version *ip_block_version)
1035 {
1036         if (!ip_block_version)
1037                 return -EINVAL;
1038
1039         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1040                   ip_block_version->funcs->name);
1041
1042         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1043
1044         return 0;
1045 }
1046
1047 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1048 {
1049         adev->enable_virtual_display = false;
1050
1051         if (amdgpu_virtual_display) {
1052                 struct drm_device *ddev = adev->ddev;
1053                 const char *pci_address_name = pci_name(ddev->pdev);
1054                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1055
1056                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1057                 pciaddstr_tmp = pciaddstr;
1058                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1059                         pciaddname = strsep(&pciaddname_tmp, ",");
1060                         if (!strcmp("all", pciaddname)
1061                             || !strcmp(pci_address_name, pciaddname)) {
1062                                 long num_crtc;
1063                                 int res = -1;
1064
1065                                 adev->enable_virtual_display = true;
1066
1067                                 if (pciaddname_tmp)
1068                                         res = kstrtol(pciaddname_tmp, 10,
1069                                                       &num_crtc);
1070
1071                                 if (!res) {
1072                                         if (num_crtc < 1)
1073                                                 num_crtc = 1;
1074                                         if (num_crtc > 6)
1075                                                 num_crtc = 6;
1076                                         adev->mode_info.num_crtc = num_crtc;
1077                                 } else {
1078                                         adev->mode_info.num_crtc = 1;
1079                                 }
1080                                 break;
1081                         }
1082                 }
1083
1084                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1085                          amdgpu_virtual_display, pci_address_name,
1086                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1087
1088                 kfree(pciaddstr);
1089         }
1090 }
1091
1092 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1093 {
1094         const char *chip_name;
1095         char fw_name[30];
1096         int err;
1097         const struct gpu_info_firmware_header_v1_0 *hdr;
1098
1099         adev->firmware.gpu_info_fw = NULL;
1100
1101         switch (adev->asic_type) {
1102         case CHIP_TOPAZ:
1103         case CHIP_TONGA:
1104         case CHIP_FIJI:
1105         case CHIP_POLARIS11:
1106         case CHIP_POLARIS10:
1107         case CHIP_POLARIS12:
1108         case CHIP_CARRIZO:
1109         case CHIP_STONEY:
1110 #ifdef CONFIG_DRM_AMDGPU_SI
1111         case CHIP_VERDE:
1112         case CHIP_TAHITI:
1113         case CHIP_PITCAIRN:
1114         case CHIP_OLAND:
1115         case CHIP_HAINAN:
1116 #endif
1117 #ifdef CONFIG_DRM_AMDGPU_CIK
1118         case CHIP_BONAIRE:
1119         case CHIP_HAWAII:
1120         case CHIP_KAVERI:
1121         case CHIP_KABINI:
1122         case CHIP_MULLINS:
1123 #endif
1124         default:
1125                 return 0;
1126         case CHIP_VEGA10:
1127                 chip_name = "vega10";
1128                 break;
1129         case CHIP_RAVEN:
1130                 chip_name = "raven";
1131                 break;
1132         }
1133
1134         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1135         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1136         if (err) {
1137                 dev_err(adev->dev,
1138                         "Failed to load gpu_info firmware \"%s\"\n",
1139                         fw_name);
1140                 goto out;
1141         }
1142         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1143         if (err) {
1144                 dev_err(adev->dev,
1145                         "Failed to validate gpu_info firmware \"%s\"\n",
1146                         fw_name);
1147                 goto out;
1148         }
1149
1150         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1151         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1152
1153         switch (hdr->version_major) {
1154         case 1:
1155         {
1156                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1157                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1158                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1159
1160                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1161                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1162                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1163                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1164                 adev->gfx.config.max_texture_channel_caches =
1165                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1166                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1167                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1168                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1169                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1170                 adev->gfx.config.double_offchip_lds_buf =
1171                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1172                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1173                 adev->gfx.cu_info.max_waves_per_simd =
1174                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1175                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1176                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1177                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1178                 break;
1179         }
1180         default:
1181                 dev_err(adev->dev,
1182                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1183                 err = -EINVAL;
1184                 goto out;
1185         }
1186 out:
1187         return err;
1188 }
1189
1190 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1191 {
1192         int i, r;
1193
1194         amdgpu_device_enable_virtual_display(adev);
1195
1196         switch (adev->asic_type) {
1197         case CHIP_TOPAZ:
1198         case CHIP_TONGA:
1199         case CHIP_FIJI:
1200         case CHIP_POLARIS11:
1201         case CHIP_POLARIS10:
1202         case CHIP_POLARIS12:
1203         case CHIP_CARRIZO:
1204         case CHIP_STONEY:
1205                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1206                         adev->family = AMDGPU_FAMILY_CZ;
1207                 else
1208                         adev->family = AMDGPU_FAMILY_VI;
1209
1210                 r = vi_set_ip_blocks(adev);
1211                 if (r)
1212                         return r;
1213                 break;
1214 #ifdef CONFIG_DRM_AMDGPU_SI
1215         case CHIP_VERDE:
1216         case CHIP_TAHITI:
1217         case CHIP_PITCAIRN:
1218         case CHIP_OLAND:
1219         case CHIP_HAINAN:
1220                 adev->family = AMDGPU_FAMILY_SI;
1221                 r = si_set_ip_blocks(adev);
1222                 if (r)
1223                         return r;
1224                 break;
1225 #endif
1226 #ifdef CONFIG_DRM_AMDGPU_CIK
1227         case CHIP_BONAIRE:
1228         case CHIP_HAWAII:
1229         case CHIP_KAVERI:
1230         case CHIP_KABINI:
1231         case CHIP_MULLINS:
1232                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1233                         adev->family = AMDGPU_FAMILY_CI;
1234                 else
1235                         adev->family = AMDGPU_FAMILY_KV;
1236
1237                 r = cik_set_ip_blocks(adev);
1238                 if (r)
1239                         return r;
1240                 break;
1241 #endif
1242         case  CHIP_VEGA10:
1243         case  CHIP_RAVEN:
1244                 if (adev->asic_type == CHIP_RAVEN)
1245                         adev->family = AMDGPU_FAMILY_RV;
1246                 else
1247                         adev->family = AMDGPU_FAMILY_AI;
1248
1249                 r = soc15_set_ip_blocks(adev);
1250                 if (r)
1251                         return r;
1252                 break;
1253         default:
1254                 /* FIXME: not supported yet */
1255                 return -EINVAL;
1256         }
1257
1258         r = amdgpu_device_parse_gpu_info_fw(adev);
1259         if (r)
1260                 return r;
1261
1262         amdgpu_amdkfd_device_probe(adev);
1263
1264         if (amdgpu_sriov_vf(adev)) {
1265                 r = amdgpu_virt_request_full_gpu(adev, true);
1266                 if (r)
1267                         return -EAGAIN;
1268         }
1269
1270         for (i = 0; i < adev->num_ip_blocks; i++) {
1271                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1272                         DRM_ERROR("disabled ip block: %d <%s>\n",
1273                                   i, adev->ip_blocks[i].version->funcs->name);
1274                         adev->ip_blocks[i].status.valid = false;
1275                 } else {
1276                         if (adev->ip_blocks[i].version->funcs->early_init) {
1277                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1278                                 if (r == -ENOENT) {
1279                                         adev->ip_blocks[i].status.valid = false;
1280                                 } else if (r) {
1281                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1282                                                   adev->ip_blocks[i].version->funcs->name, r);
1283                                         return r;
1284                                 } else {
1285                                         adev->ip_blocks[i].status.valid = true;
1286                                 }
1287                         } else {
1288                                 adev->ip_blocks[i].status.valid = true;
1289                         }
1290                 }
1291         }
1292
1293         adev->cg_flags &= amdgpu_cg_mask;
1294         adev->pg_flags &= amdgpu_pg_mask;
1295
1296         return 0;
1297 }
1298
1299 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1300 {
1301         int i, r;
1302
1303         for (i = 0; i < adev->num_ip_blocks; i++) {
1304                 if (!adev->ip_blocks[i].status.valid)
1305                         continue;
1306                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1307                 if (r) {
1308                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1309                                   adev->ip_blocks[i].version->funcs->name, r);
1310                         return r;
1311                 }
1312                 adev->ip_blocks[i].status.sw = true;
1313
1314                 if (amdgpu_emu_mode == 1) {
1315                         /* Need to do common hw init first on emulation  */
1316                         if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1317                                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1318                                 if (r) {
1319                                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1320                                                 adev->ip_blocks[i].version->funcs->name, r);
1321                                         return r;
1322                                 }
1323                                 adev->ip_blocks[i].status.hw = true;
1324                         }
1325                 }
1326
1327                 /* need to do gmc hw init early so we can allocate gpu mem */
1328                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1329                         r = amdgpu_device_vram_scratch_init(adev);
1330                         if (r) {
1331                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1332                                 return r;
1333                         }
1334                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1335                         if (r) {
1336                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1337                                 return r;
1338                         }
1339                         r = amdgpu_device_wb_init(adev);
1340                         if (r) {
1341                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1342                                 return r;
1343                         }
1344                         adev->ip_blocks[i].status.hw = true;
1345
1346                         /* right after GMC hw init, we create CSA */
1347                         if (amdgpu_sriov_vf(adev)) {
1348                                 r = amdgpu_allocate_static_csa(adev);
1349                                 if (r) {
1350                                         DRM_ERROR("allocate CSA failed %d\n", r);
1351                                         return r;
1352                                 }
1353                         }
1354                 }
1355         }
1356
1357         for (i = 0; i < adev->num_ip_blocks; i++) {
1358                 if (!adev->ip_blocks[i].status.sw)
1359                         continue;
1360                 if (adev->ip_blocks[i].status.hw)
1361                         continue;
1362                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1363                 if (r) {
1364                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1365                                   adev->ip_blocks[i].version->funcs->name, r);
1366                         return r;
1367                 }
1368                 adev->ip_blocks[i].status.hw = true;
1369         }
1370
1371         amdgpu_amdkfd_device_init(adev);
1372
1373         if (amdgpu_sriov_vf(adev))
1374                 amdgpu_virt_release_full_gpu(adev, true);
1375
1376         return 0;
1377 }
1378
1379 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1380 {
1381         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1382 }
1383
1384 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1385 {
1386         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1387                         AMDGPU_RESET_MAGIC_NUM);
1388 }
1389
1390 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1391 {
1392         int i = 0, r;
1393
1394         if (amdgpu_emu_mode == 1)
1395                 return 0;
1396
1397         for (i = 0; i < adev->num_ip_blocks; i++) {
1398                 if (!adev->ip_blocks[i].status.valid)
1399                         continue;
1400                 /* skip CG for VCE/UVD, it's handled specially */
1401                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1402                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1403                         /* enable clockgating to save power */
1404                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1405                                                                                      AMD_CG_STATE_GATE);
1406                         if (r) {
1407                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1408                                           adev->ip_blocks[i].version->funcs->name, r);
1409                                 return r;
1410                         }
1411                 }
1412         }
1413         return 0;
1414 }
1415
1416 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1417 {
1418         int i = 0, r;
1419
1420         for (i = 0; i < adev->num_ip_blocks; i++) {
1421                 if (!adev->ip_blocks[i].status.valid)
1422                         continue;
1423                 if (adev->ip_blocks[i].version->funcs->late_init) {
1424                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1425                         if (r) {
1426                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1427                                           adev->ip_blocks[i].version->funcs->name, r);
1428                                 return r;
1429                         }
1430                         adev->ip_blocks[i].status.late_initialized = true;
1431                 }
1432         }
1433
1434         mod_delayed_work(system_wq, &adev->late_init_work,
1435                         msecs_to_jiffies(AMDGPU_RESUME_MS));
1436
1437         amdgpu_device_fill_reset_magic(adev);
1438
1439         return 0;
1440 }
1441
1442 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1443 {
1444         int i, r;
1445
1446         amdgpu_amdkfd_device_fini(adev);
1447         /* need to disable SMC first */
1448         for (i = 0; i < adev->num_ip_blocks; i++) {
1449                 if (!adev->ip_blocks[i].status.hw)
1450                         continue;
1451                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1452                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1453                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1454                                                                                      AMD_CG_STATE_UNGATE);
1455                         if (r) {
1456                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1457                                           adev->ip_blocks[i].version->funcs->name, r);
1458                                 return r;
1459                         }
1460                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1461                         /* XXX handle errors */
1462                         if (r) {
1463                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1464                                           adev->ip_blocks[i].version->funcs->name, r);
1465                         }
1466                         adev->ip_blocks[i].status.hw = false;
1467                         break;
1468                 }
1469         }
1470
1471         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1472                 if (!adev->ip_blocks[i].status.hw)
1473                         continue;
1474                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1475                         amdgpu_free_static_csa(adev);
1476                         amdgpu_device_wb_fini(adev);
1477                         amdgpu_device_vram_scratch_fini(adev);
1478                 }
1479
1480                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1481                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1482                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1483                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1484                                                                                      AMD_CG_STATE_UNGATE);
1485                         if (r) {
1486                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1487                                           adev->ip_blocks[i].version->funcs->name, r);
1488                                 return r;
1489                         }
1490                 }
1491
1492                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1493                 /* XXX handle errors */
1494                 if (r) {
1495                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1496                                   adev->ip_blocks[i].version->funcs->name, r);
1497                 }
1498
1499                 adev->ip_blocks[i].status.hw = false;
1500         }
1501
1502         /* disable all interrupts */
1503         amdgpu_irq_disable_all(adev);
1504
1505         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1506                 if (!adev->ip_blocks[i].status.sw)
1507                         continue;
1508                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1509                 /* XXX handle errors */
1510                 if (r) {
1511                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1512                                   adev->ip_blocks[i].version->funcs->name, r);
1513                 }
1514                 adev->ip_blocks[i].status.sw = false;
1515                 adev->ip_blocks[i].status.valid = false;
1516         }
1517
1518         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1519                 if (!adev->ip_blocks[i].status.late_initialized)
1520                         continue;
1521                 if (adev->ip_blocks[i].version->funcs->late_fini)
1522                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1523                 adev->ip_blocks[i].status.late_initialized = false;
1524         }
1525
1526         if (amdgpu_sriov_vf(adev))
1527                 if (amdgpu_virt_release_full_gpu(adev, false))
1528                         DRM_ERROR("failed to release exclusive mode on fini\n");
1529
1530         return 0;
1531 }
1532
1533 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1534 {
1535         struct amdgpu_device *adev =
1536                 container_of(work, struct amdgpu_device, late_init_work.work);
1537         amdgpu_device_ip_late_set_cg_state(adev);
1538 }
1539
1540 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
1541 {
1542         int i, r;
1543
1544         if (amdgpu_sriov_vf(adev))
1545                 amdgpu_virt_request_full_gpu(adev, false);
1546
1547         /* ungate SMC block first */
1548         r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1549                                                    AMD_CG_STATE_UNGATE);
1550         if (r) {
1551                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
1552         }
1553
1554         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1555                 if (!adev->ip_blocks[i].status.valid)
1556                         continue;
1557                 /* ungate blocks so that suspend can properly shut them down */
1558                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1559                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1560                                                                                      AMD_CG_STATE_UNGATE);
1561                         if (r) {
1562                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1563                                           adev->ip_blocks[i].version->funcs->name, r);
1564                         }
1565                 }
1566                 /* XXX handle errors */
1567                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1568                 /* XXX handle errors */
1569                 if (r) {
1570                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1571                                   adev->ip_blocks[i].version->funcs->name, r);
1572                 }
1573         }
1574
1575         if (amdgpu_sriov_vf(adev))
1576                 amdgpu_virt_release_full_gpu(adev, false);
1577
1578         return 0;
1579 }
1580
1581 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
1582 {
1583         int i, r;
1584
1585         static enum amd_ip_block_type ip_order[] = {
1586                 AMD_IP_BLOCK_TYPE_GMC,
1587                 AMD_IP_BLOCK_TYPE_COMMON,
1588                 AMD_IP_BLOCK_TYPE_IH,
1589         };
1590
1591         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1592                 int j;
1593                 struct amdgpu_ip_block *block;
1594
1595                 for (j = 0; j < adev->num_ip_blocks; j++) {
1596                         block = &adev->ip_blocks[j];
1597
1598                         if (block->version->type != ip_order[i] ||
1599                                 !block->status.valid)
1600                                 continue;
1601
1602                         r = block->version->funcs->hw_init(adev);
1603                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1604                 }
1605         }
1606
1607         return 0;
1608 }
1609
1610 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
1611 {
1612         int i, r;
1613
1614         static enum amd_ip_block_type ip_order[] = {
1615                 AMD_IP_BLOCK_TYPE_SMC,
1616                 AMD_IP_BLOCK_TYPE_PSP,
1617                 AMD_IP_BLOCK_TYPE_DCE,
1618                 AMD_IP_BLOCK_TYPE_GFX,
1619                 AMD_IP_BLOCK_TYPE_SDMA,
1620                 AMD_IP_BLOCK_TYPE_UVD,
1621                 AMD_IP_BLOCK_TYPE_VCE
1622         };
1623
1624         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1625                 int j;
1626                 struct amdgpu_ip_block *block;
1627
1628                 for (j = 0; j < adev->num_ip_blocks; j++) {
1629                         block = &adev->ip_blocks[j];
1630
1631                         if (block->version->type != ip_order[i] ||
1632                                 !block->status.valid)
1633                                 continue;
1634
1635                         r = block->version->funcs->hw_init(adev);
1636                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1637                 }
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
1644 {
1645         int i, r;
1646
1647         for (i = 0; i < adev->num_ip_blocks; i++) {
1648                 if (!adev->ip_blocks[i].status.valid)
1649                         continue;
1650                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1651                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1652                                 adev->ip_blocks[i].version->type ==
1653                                 AMD_IP_BLOCK_TYPE_IH) {
1654                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1655                         if (r) {
1656                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1657                                           adev->ip_blocks[i].version->funcs->name, r);
1658                                 return r;
1659                         }
1660                 }
1661         }
1662
1663         return 0;
1664 }
1665
1666 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
1667 {
1668         int i, r;
1669
1670         for (i = 0; i < adev->num_ip_blocks; i++) {
1671                 if (!adev->ip_blocks[i].status.valid)
1672                         continue;
1673                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1674                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1675                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1676                         continue;
1677                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1678                 if (r) {
1679                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1680                                   adev->ip_blocks[i].version->funcs->name, r);
1681                         return r;
1682                 }
1683         }
1684
1685         return 0;
1686 }
1687
1688 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
1689 {
1690         int r;
1691
1692         r = amdgpu_device_ip_resume_phase1(adev);
1693         if (r)
1694                 return r;
1695         r = amdgpu_device_ip_resume_phase2(adev);
1696
1697         return r;
1698 }
1699
1700 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1701 {
1702         if (amdgpu_sriov_vf(adev)) {
1703                 if (adev->is_atom_fw) {
1704                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1705                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1706                 } else {
1707                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1708                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1709                 }
1710
1711                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
1712                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
1713         }
1714 }
1715
1716 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
1717 {
1718         switch (asic_type) {
1719 #if defined(CONFIG_DRM_AMD_DC)
1720         case CHIP_BONAIRE:
1721         case CHIP_HAWAII:
1722         case CHIP_KAVERI:
1723         case CHIP_KABINI:
1724         case CHIP_MULLINS:
1725         case CHIP_CARRIZO:
1726         case CHIP_STONEY:
1727         case CHIP_POLARIS11:
1728         case CHIP_POLARIS10:
1729         case CHIP_POLARIS12:
1730         case CHIP_TONGA:
1731         case CHIP_FIJI:
1732 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
1733                 return amdgpu_dc != 0;
1734 #endif
1735         case CHIP_VEGA10:
1736 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1737         case CHIP_RAVEN:
1738 #endif
1739                 return amdgpu_dc != 0;
1740 #endif
1741         default:
1742                 return false;
1743         }
1744 }
1745
1746 /**
1747  * amdgpu_device_has_dc_support - check if dc is supported
1748  *
1749  * @adev: amdgpu_device_pointer
1750  *
1751  * Returns true for supported, false for not supported
1752  */
1753 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
1754 {
1755         if (amdgpu_sriov_vf(adev))
1756                 return false;
1757
1758         return amdgpu_device_asic_has_dc_support(adev->asic_type);
1759 }
1760
1761 /**
1762  * amdgpu_device_init - initialize the driver
1763  *
1764  * @adev: amdgpu_device pointer
1765  * @pdev: drm dev pointer
1766  * @pdev: pci dev pointer
1767  * @flags: driver flags
1768  *
1769  * Initializes the driver info and hw (all asics).
1770  * Returns 0 for success or an error on failure.
1771  * Called at driver startup.
1772  */
1773 int amdgpu_device_init(struct amdgpu_device *adev,
1774                        struct drm_device *ddev,
1775                        struct pci_dev *pdev,
1776                        uint32_t flags)
1777 {
1778         int r, i;
1779         bool runtime = false;
1780         u32 max_MBps;
1781
1782         adev->shutdown = false;
1783         adev->dev = &pdev->dev;
1784         adev->ddev = ddev;
1785         adev->pdev = pdev;
1786         adev->flags = flags;
1787         adev->asic_type = flags & AMD_ASIC_MASK;
1788         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1789         if (amdgpu_emu_mode == 1)
1790                 adev->usec_timeout *= 2;
1791         adev->gmc.gart_size = 512 * 1024 * 1024;
1792         adev->accel_working = false;
1793         adev->num_rings = 0;
1794         adev->mman.buffer_funcs = NULL;
1795         adev->mman.buffer_funcs_ring = NULL;
1796         adev->vm_manager.vm_pte_funcs = NULL;
1797         adev->vm_manager.vm_pte_num_rings = 0;
1798         adev->gmc.gmc_funcs = NULL;
1799         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1800         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1801
1802         adev->smc_rreg = &amdgpu_invalid_rreg;
1803         adev->smc_wreg = &amdgpu_invalid_wreg;
1804         adev->pcie_rreg = &amdgpu_invalid_rreg;
1805         adev->pcie_wreg = &amdgpu_invalid_wreg;
1806         adev->pciep_rreg = &amdgpu_invalid_rreg;
1807         adev->pciep_wreg = &amdgpu_invalid_wreg;
1808         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1809         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1810         adev->didt_rreg = &amdgpu_invalid_rreg;
1811         adev->didt_wreg = &amdgpu_invalid_wreg;
1812         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1813         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1814         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1815         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1816
1817         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1818                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1819                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1820
1821         /* mutex initialization are all done here so we
1822          * can recall function without having locking issues */
1823         atomic_set(&adev->irq.ih.lock, 0);
1824         mutex_init(&adev->firmware.mutex);
1825         mutex_init(&adev->pm.mutex);
1826         mutex_init(&adev->gfx.gpu_clock_mutex);
1827         mutex_init(&adev->srbm_mutex);
1828         mutex_init(&adev->gfx.pipe_reserve_mutex);
1829         mutex_init(&adev->grbm_idx_mutex);
1830         mutex_init(&adev->mn_lock);
1831         mutex_init(&adev->virt.vf_errors.lock);
1832         hash_init(adev->mn_hash);
1833         mutex_init(&adev->lock_reset);
1834
1835         amdgpu_device_check_arguments(adev);
1836
1837         spin_lock_init(&adev->mmio_idx_lock);
1838         spin_lock_init(&adev->smc_idx_lock);
1839         spin_lock_init(&adev->pcie_idx_lock);
1840         spin_lock_init(&adev->uvd_ctx_idx_lock);
1841         spin_lock_init(&adev->didt_idx_lock);
1842         spin_lock_init(&adev->gc_cac_idx_lock);
1843         spin_lock_init(&adev->se_cac_idx_lock);
1844         spin_lock_init(&adev->audio_endpt_idx_lock);
1845         spin_lock_init(&adev->mm_stats.lock);
1846
1847         INIT_LIST_HEAD(&adev->shadow_list);
1848         mutex_init(&adev->shadow_list_lock);
1849
1850         INIT_LIST_HEAD(&adev->ring_lru_list);
1851         spin_lock_init(&adev->ring_lru_list_lock);
1852
1853         INIT_DELAYED_WORK(&adev->late_init_work,
1854                           amdgpu_device_ip_late_init_func_handler);
1855
1856         /* Registers mapping */
1857         /* TODO: block userspace mapping of io register */
1858         if (adev->asic_type >= CHIP_BONAIRE) {
1859                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1860                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1861         } else {
1862                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1863                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1864         }
1865
1866         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1867         if (adev->rmmio == NULL) {
1868                 return -ENOMEM;
1869         }
1870         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1871         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1872
1873         /* doorbell bar mapping */
1874         amdgpu_device_doorbell_init(adev);
1875
1876         /* io port mapping */
1877         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1878                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1879                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1880                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1881                         break;
1882                 }
1883         }
1884         if (adev->rio_mem == NULL)
1885                 DRM_INFO("PCI I/O BAR is not found.\n");
1886
1887         /* early init functions */
1888         r = amdgpu_device_ip_early_init(adev);
1889         if (r)
1890                 return r;
1891
1892         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1893         /* this will fail for cards that aren't VGA class devices, just
1894          * ignore it */
1895         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
1896
1897         if (amdgpu_device_is_px(ddev))
1898                 runtime = true;
1899         if (!pci_is_thunderbolt_attached(adev->pdev))
1900                 vga_switcheroo_register_client(adev->pdev,
1901                                                &amdgpu_switcheroo_ops, runtime);
1902         if (runtime)
1903                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1904
1905         if (amdgpu_emu_mode == 1)
1906                 goto fence_driver_init;
1907
1908         /* Read BIOS */
1909         if (!amdgpu_get_bios(adev)) {
1910                 r = -EINVAL;
1911                 goto failed;
1912         }
1913
1914         r = amdgpu_atombios_init(adev);
1915         if (r) {
1916                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1917                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1918                 goto failed;
1919         }
1920
1921         /* detect if we are with an SRIOV vbios */
1922         amdgpu_device_detect_sriov_bios(adev);
1923
1924         /* Post card if necessary */
1925         if (amdgpu_device_need_post(adev)) {
1926                 if (!adev->bios) {
1927                         dev_err(adev->dev, "no vBIOS found\n");
1928                         r = -EINVAL;
1929                         goto failed;
1930                 }
1931                 DRM_INFO("GPU posting now...\n");
1932                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1933                 if (r) {
1934                         dev_err(adev->dev, "gpu post error!\n");
1935                         goto failed;
1936                 }
1937         }
1938
1939         if (adev->is_atom_fw) {
1940                 /* Initialize clocks */
1941                 r = amdgpu_atomfirmware_get_clock_info(adev);
1942                 if (r) {
1943                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
1944                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1945                         goto failed;
1946                 }
1947         } else {
1948                 /* Initialize clocks */
1949                 r = amdgpu_atombios_get_clock_info(adev);
1950                 if (r) {
1951                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1952                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1953                         goto failed;
1954                 }
1955                 /* init i2c buses */
1956                 if (!amdgpu_device_has_dc_support(adev))
1957                         amdgpu_atombios_i2c_init(adev);
1958         }
1959
1960 fence_driver_init:
1961         /* Fence driver */
1962         r = amdgpu_fence_driver_init(adev);
1963         if (r) {
1964                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1965                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
1966                 goto failed;
1967         }
1968
1969         /* init the mode config */
1970         drm_mode_config_init(adev->ddev);
1971
1972         r = amdgpu_device_ip_init(adev);
1973         if (r) {
1974                 /* failed in exclusive mode due to timeout */
1975                 if (amdgpu_sriov_vf(adev) &&
1976                     !amdgpu_sriov_runtime(adev) &&
1977                     amdgpu_virt_mmio_blocked(adev) &&
1978                     !amdgpu_virt_wait_reset(adev)) {
1979                         dev_err(adev->dev, "VF exclusive mode timeout\n");
1980                         /* Don't send request since VF is inactive. */
1981                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
1982                         adev->virt.ops = NULL;
1983                         r = -EAGAIN;
1984                         goto failed;
1985                 }
1986                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
1987                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
1988                 amdgpu_device_ip_fini(adev);
1989                 goto failed;
1990         }
1991
1992         adev->accel_working = true;
1993
1994         amdgpu_vm_check_compute_bug(adev);
1995
1996         /* Initialize the buffer migration limit. */
1997         if (amdgpu_moverate >= 0)
1998                 max_MBps = amdgpu_moverate;
1999         else
2000                 max_MBps = 8; /* Allow 8 MB/s. */
2001         /* Get a log2 for easy divisions. */
2002         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2003
2004         r = amdgpu_ib_pool_init(adev);
2005         if (r) {
2006                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2007                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2008                 goto failed;
2009         }
2010
2011         r = amdgpu_ib_ring_tests(adev);
2012         if (r)
2013                 DRM_ERROR("ib ring test failed (%d).\n", r);
2014
2015         if (amdgpu_sriov_vf(adev))
2016                 amdgpu_virt_init_data_exchange(adev);
2017
2018         amdgpu_fbdev_init(adev);
2019
2020         r = amdgpu_pm_sysfs_init(adev);
2021         if (r)
2022                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2023
2024         r = amdgpu_debugfs_gem_init(adev);
2025         if (r)
2026                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2027
2028         r = amdgpu_debugfs_regs_init(adev);
2029         if (r)
2030                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2031
2032         r = amdgpu_debugfs_firmware_init(adev);
2033         if (r)
2034                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2035
2036         r = amdgpu_debugfs_init(adev);
2037         if (r)
2038                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2039
2040         if ((amdgpu_testing & 1)) {
2041                 if (adev->accel_working)
2042                         amdgpu_test_moves(adev);
2043                 else
2044                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2045         }
2046         if (amdgpu_benchmarking) {
2047                 if (adev->accel_working)
2048                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2049                 else
2050                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2051         }
2052
2053         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2054          * explicit gating rather than handling it automatically.
2055          */
2056         r = amdgpu_device_ip_late_init(adev);
2057         if (r) {
2058                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2059                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2060                 goto failed;
2061         }
2062
2063         return 0;
2064
2065 failed:
2066         amdgpu_vf_error_trans_all(adev);
2067         if (runtime)
2068                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2069
2070         return r;
2071 }
2072
2073 /**
2074  * amdgpu_device_fini - tear down the driver
2075  *
2076  * @adev: amdgpu_device pointer
2077  *
2078  * Tear down the driver info (all asics).
2079  * Called at driver shutdown.
2080  */
2081 void amdgpu_device_fini(struct amdgpu_device *adev)
2082 {
2083         int r;
2084
2085         DRM_INFO("amdgpu: finishing device.\n");
2086         adev->shutdown = true;
2087         if (adev->mode_info.mode_config_initialized)
2088                 drm_crtc_force_disable_all(adev->ddev);
2089
2090         amdgpu_ib_pool_fini(adev);
2091         amdgpu_fence_driver_fini(adev);
2092         amdgpu_fbdev_fini(adev);
2093         r = amdgpu_device_ip_fini(adev);
2094         if (adev->firmware.gpu_info_fw) {
2095                 release_firmware(adev->firmware.gpu_info_fw);
2096                 adev->firmware.gpu_info_fw = NULL;
2097         }
2098         adev->accel_working = false;
2099         cancel_delayed_work_sync(&adev->late_init_work);
2100         /* free i2c buses */
2101         if (!amdgpu_device_has_dc_support(adev))
2102                 amdgpu_i2c_fini(adev);
2103
2104         if (amdgpu_emu_mode != 1)
2105                 amdgpu_atombios_fini(adev);
2106
2107         kfree(adev->bios);
2108         adev->bios = NULL;
2109         if (!pci_is_thunderbolt_attached(adev->pdev))
2110                 vga_switcheroo_unregister_client(adev->pdev);
2111         if (adev->flags & AMD_IS_PX)
2112                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2113         vga_client_register(adev->pdev, NULL, NULL, NULL);
2114         if (adev->rio_mem)
2115                 pci_iounmap(adev->pdev, adev->rio_mem);
2116         adev->rio_mem = NULL;
2117         iounmap(adev->rmmio);
2118         adev->rmmio = NULL;
2119         amdgpu_device_doorbell_fini(adev);
2120         amdgpu_pm_sysfs_fini(adev);
2121         amdgpu_debugfs_regs_cleanup(adev);
2122 }
2123
2124
2125 /*
2126  * Suspend & resume.
2127  */
2128 /**
2129  * amdgpu_device_suspend - initiate device suspend
2130  *
2131  * @pdev: drm dev pointer
2132  * @state: suspend state
2133  *
2134  * Puts the hw in the suspend state (all asics).
2135  * Returns 0 for success or an error on failure.
2136  * Called at driver suspend.
2137  */
2138 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2139 {
2140         struct amdgpu_device *adev;
2141         struct drm_crtc *crtc;
2142         struct drm_connector *connector;
2143         int r;
2144
2145         if (dev == NULL || dev->dev_private == NULL) {
2146                 return -ENODEV;
2147         }
2148
2149         adev = dev->dev_private;
2150
2151         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2152                 return 0;
2153
2154         drm_kms_helper_poll_disable(dev);
2155
2156         if (!amdgpu_device_has_dc_support(adev)) {
2157                 /* turn off display hw */
2158                 drm_modeset_lock_all(dev);
2159                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2160                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2161                 }
2162                 drm_modeset_unlock_all(dev);
2163         }
2164
2165         amdgpu_amdkfd_suspend(adev);
2166
2167         /* unpin the front buffers and cursors */
2168         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2169                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2170                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2171                 struct amdgpu_bo *robj;
2172
2173                 if (amdgpu_crtc->cursor_bo) {
2174                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2175                         r = amdgpu_bo_reserve(aobj, true);
2176                         if (r == 0) {
2177                                 amdgpu_bo_unpin(aobj);
2178                                 amdgpu_bo_unreserve(aobj);
2179                         }
2180                 }
2181
2182                 if (rfb == NULL || rfb->obj == NULL) {
2183                         continue;
2184                 }
2185                 robj = gem_to_amdgpu_bo(rfb->obj);
2186                 /* don't unpin kernel fb objects */
2187                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2188                         r = amdgpu_bo_reserve(robj, true);
2189                         if (r == 0) {
2190                                 amdgpu_bo_unpin(robj);
2191                                 amdgpu_bo_unreserve(robj);
2192                         }
2193                 }
2194         }
2195         /* evict vram memory */
2196         amdgpu_bo_evict_vram(adev);
2197
2198         amdgpu_fence_driver_suspend(adev);
2199
2200         r = amdgpu_device_ip_suspend(adev);
2201
2202         /* evict remaining vram memory
2203          * This second call to evict vram is to evict the gart page table
2204          * using the CPU.
2205          */
2206         amdgpu_bo_evict_vram(adev);
2207
2208         pci_save_state(dev->pdev);
2209         if (suspend) {
2210                 /* Shut down the device */
2211                 pci_disable_device(dev->pdev);
2212                 pci_set_power_state(dev->pdev, PCI_D3hot);
2213         } else {
2214                 r = amdgpu_asic_reset(adev);
2215                 if (r)
2216                         DRM_ERROR("amdgpu asic reset failed\n");
2217         }
2218
2219         if (fbcon) {
2220                 console_lock();
2221                 amdgpu_fbdev_set_suspend(adev, 1);
2222                 console_unlock();
2223         }
2224         return 0;
2225 }
2226
2227 /**
2228  * amdgpu_device_resume - initiate device resume
2229  *
2230  * @pdev: drm dev pointer
2231  *
2232  * Bring the hw back to operating state (all asics).
2233  * Returns 0 for success or an error on failure.
2234  * Called at driver resume.
2235  */
2236 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2237 {
2238         struct drm_connector *connector;
2239         struct amdgpu_device *adev = dev->dev_private;
2240         struct drm_crtc *crtc;
2241         int r = 0;
2242
2243         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2244                 return 0;
2245
2246         if (fbcon)
2247                 console_lock();
2248
2249         if (resume) {
2250                 pci_set_power_state(dev->pdev, PCI_D0);
2251                 pci_restore_state(dev->pdev);
2252                 r = pci_enable_device(dev->pdev);
2253                 if (r)
2254                         goto unlock;
2255         }
2256
2257         /* post card */
2258         if (amdgpu_device_need_post(adev)) {
2259                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2260                 if (r)
2261                         DRM_ERROR("amdgpu asic init failed\n");
2262         }
2263
2264         r = amdgpu_device_ip_resume(adev);
2265         if (r) {
2266                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2267                 goto unlock;
2268         }
2269         amdgpu_fence_driver_resume(adev);
2270
2271         if (resume) {
2272                 r = amdgpu_ib_ring_tests(adev);
2273                 if (r)
2274                         DRM_ERROR("ib ring test failed (%d).\n", r);
2275         }
2276
2277         r = amdgpu_device_ip_late_init(adev);
2278         if (r)
2279                 goto unlock;
2280
2281         /* pin cursors */
2282         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2283                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2284
2285                 if (amdgpu_crtc->cursor_bo) {
2286                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2287                         r = amdgpu_bo_reserve(aobj, true);
2288                         if (r == 0) {
2289                                 r = amdgpu_bo_pin(aobj,
2290                                                   AMDGPU_GEM_DOMAIN_VRAM,
2291                                                   &amdgpu_crtc->cursor_addr);
2292                                 if (r != 0)
2293                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2294                                 amdgpu_bo_unreserve(aobj);
2295                         }
2296                 }
2297         }
2298         r = amdgpu_amdkfd_resume(adev);
2299         if (r)
2300                 return r;
2301
2302         /* blat the mode back in */
2303         if (fbcon) {
2304                 if (!amdgpu_device_has_dc_support(adev)) {
2305                         /* pre DCE11 */
2306                         drm_helper_resume_force_mode(dev);
2307
2308                         /* turn on display hw */
2309                         drm_modeset_lock_all(dev);
2310                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2311                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2312                         }
2313                         drm_modeset_unlock_all(dev);
2314                 } else {
2315                         /*
2316                          * There is no equivalent atomic helper to turn on
2317                          * display, so we defined our own function for this,
2318                          * once suspend resume is supported by the atomic
2319                          * framework this will be reworked
2320                          */
2321                         amdgpu_dm_display_resume(adev);
2322                 }
2323         }
2324
2325         drm_kms_helper_poll_enable(dev);
2326
2327         /*
2328          * Most of the connector probing functions try to acquire runtime pm
2329          * refs to ensure that the GPU is powered on when connector polling is
2330          * performed. Since we're calling this from a runtime PM callback,
2331          * trying to acquire rpm refs will cause us to deadlock.
2332          *
2333          * Since we're guaranteed to be holding the rpm lock, it's safe to
2334          * temporarily disable the rpm helpers so this doesn't deadlock us.
2335          */
2336 #ifdef CONFIG_PM
2337         dev->dev->power.disable_depth++;
2338 #endif
2339         if (!amdgpu_device_has_dc_support(adev))
2340                 drm_helper_hpd_irq_event(dev);
2341         else
2342                 drm_kms_helper_hotplug_event(dev);
2343 #ifdef CONFIG_PM
2344         dev->dev->power.disable_depth--;
2345 #endif
2346
2347         if (fbcon)
2348                 amdgpu_fbdev_set_suspend(adev, 0);
2349
2350 unlock:
2351         if (fbcon)
2352                 console_unlock();
2353
2354         return r;
2355 }
2356
2357 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2358 {
2359         int i;
2360         bool asic_hang = false;
2361
2362         if (amdgpu_sriov_vf(adev))
2363                 return true;
2364
2365         for (i = 0; i < adev->num_ip_blocks; i++) {
2366                 if (!adev->ip_blocks[i].status.valid)
2367                         continue;
2368                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2369                         adev->ip_blocks[i].status.hang =
2370                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2371                 if (adev->ip_blocks[i].status.hang) {
2372                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2373                         asic_hang = true;
2374                 }
2375         }
2376         return asic_hang;
2377 }
2378
2379 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2380 {
2381         int i, r = 0;
2382
2383         for (i = 0; i < adev->num_ip_blocks; i++) {
2384                 if (!adev->ip_blocks[i].status.valid)
2385                         continue;
2386                 if (adev->ip_blocks[i].status.hang &&
2387                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2388                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2389                         if (r)
2390                                 return r;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2398 {
2399         int i;
2400
2401         for (i = 0; i < adev->num_ip_blocks; i++) {
2402                 if (!adev->ip_blocks[i].status.valid)
2403                         continue;
2404                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2405                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2406                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2407                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2408                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2409                         if (adev->ip_blocks[i].status.hang) {
2410                                 DRM_INFO("Some block need full reset!\n");
2411                                 return true;
2412                         }
2413                 }
2414         }
2415         return false;
2416 }
2417
2418 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2419 {
2420         int i, r = 0;
2421
2422         for (i = 0; i < adev->num_ip_blocks; i++) {
2423                 if (!adev->ip_blocks[i].status.valid)
2424                         continue;
2425                 if (adev->ip_blocks[i].status.hang &&
2426                     adev->ip_blocks[i].version->funcs->soft_reset) {
2427                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2428                         if (r)
2429                                 return r;
2430                 }
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
2437 {
2438         int i, r = 0;
2439
2440         for (i = 0; i < adev->num_ip_blocks; i++) {
2441                 if (!adev->ip_blocks[i].status.valid)
2442                         continue;
2443                 if (adev->ip_blocks[i].status.hang &&
2444                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2445                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2446                 if (r)
2447                         return r;
2448         }
2449
2450         return 0;
2451 }
2452
2453 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
2454                                                   struct amdgpu_ring *ring,
2455                                                   struct amdgpu_bo *bo,
2456                                                   struct dma_fence **fence)
2457 {
2458         uint32_t domain;
2459         int r;
2460
2461         if (!bo->shadow)
2462                 return 0;
2463
2464         r = amdgpu_bo_reserve(bo, true);
2465         if (r)
2466                 return r;
2467         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2468         /* if bo has been evicted, then no need to recover */
2469         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2470                 r = amdgpu_bo_validate(bo->shadow);
2471                 if (r) {
2472                         DRM_ERROR("bo validate failed!\n");
2473                         goto err;
2474                 }
2475
2476                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2477                                                  NULL, fence, true);
2478                 if (r) {
2479                         DRM_ERROR("recover page table failed!\n");
2480                         goto err;
2481                 }
2482         }
2483 err:
2484         amdgpu_bo_unreserve(bo);
2485         return r;
2486 }
2487
2488 /*
2489  * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
2490  *
2491  * @adev: amdgpu device pointer
2492  * @reset_flags: output param tells caller the reset result
2493  *
2494  * attempt to do soft-reset or full-reset and reinitialize Asic
2495  * return 0 means successed otherwise failed
2496 */
2497 static int amdgpu_device_reset(struct amdgpu_device *adev,
2498                                uint64_t* reset_flags)
2499 {
2500         bool need_full_reset, vram_lost = 0;
2501         int r;
2502
2503         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
2504
2505         if (!need_full_reset) {
2506                 amdgpu_device_ip_pre_soft_reset(adev);
2507                 r = amdgpu_device_ip_soft_reset(adev);
2508                 amdgpu_device_ip_post_soft_reset(adev);
2509                 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
2510                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2511                         need_full_reset = true;
2512                 }
2513
2514         }
2515
2516         if (need_full_reset) {
2517                 r = amdgpu_device_ip_suspend(adev);
2518
2519 retry:
2520                 r = amdgpu_asic_reset(adev);
2521                 /* post card */
2522                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2523
2524                 if (!r) {
2525                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2526                         r = amdgpu_device_ip_resume_phase1(adev);
2527                         if (r)
2528                                 goto out;
2529
2530                         vram_lost = amdgpu_device_check_vram_lost(adev);
2531                         if (vram_lost) {
2532                                 DRM_ERROR("VRAM is lost!\n");
2533                                 atomic_inc(&adev->vram_lost_counter);
2534                         }
2535
2536                         r = amdgpu_gtt_mgr_recover(
2537                                 &adev->mman.bdev.man[TTM_PL_TT]);
2538                         if (r)
2539                                 goto out;
2540
2541                         r = amdgpu_device_ip_resume_phase2(adev);
2542                         if (r)
2543                                 goto out;
2544
2545                         if (vram_lost)
2546                                 amdgpu_device_fill_reset_magic(adev);
2547                 }
2548         }
2549
2550 out:
2551         if (!r) {
2552                 amdgpu_irq_gpu_reset_resume_helper(adev);
2553                 r = amdgpu_ib_ring_tests(adev);
2554                 if (r) {
2555                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2556                         r = amdgpu_device_ip_suspend(adev);
2557                         need_full_reset = true;
2558                         goto retry;
2559                 }
2560         }
2561
2562         if (reset_flags) {
2563                 if (vram_lost)
2564                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2565
2566                 if (need_full_reset)
2567                         (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2568         }
2569
2570         return r;
2571 }
2572
2573 /*
2574  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
2575  *
2576  * @adev: amdgpu device pointer
2577  * @reset_flags: output param tells caller the reset result
2578  *
2579  * do VF FLR and reinitialize Asic
2580  * return 0 means successed otherwise failed
2581 */
2582 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
2583                                      uint64_t *reset_flags,
2584                                      bool from_hypervisor)
2585 {
2586         int r;
2587
2588         if (from_hypervisor)
2589                 r = amdgpu_virt_request_full_gpu(adev, true);
2590         else
2591                 r = amdgpu_virt_reset_gpu(adev);
2592         if (r)
2593                 return r;
2594
2595         /* Resume IP prior to SMC */
2596         r = amdgpu_device_ip_reinit_early_sriov(adev);
2597         if (r)
2598                 goto error;
2599
2600         /* we need recover gart prior to run SMC/CP/SDMA resume */
2601         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
2602
2603         /* now we are okay to resume SMC/CP/SDMA */
2604         r = amdgpu_device_ip_reinit_late_sriov(adev);
2605         if (r)
2606                 goto error;
2607
2608         amdgpu_irq_gpu_reset_resume_helper(adev);
2609         r = amdgpu_ib_ring_tests(adev);
2610         if (r)
2611                 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2612
2613 error:
2614         /* release full control of GPU after ib test */
2615         amdgpu_virt_release_full_gpu(adev, true);
2616
2617         if (reset_flags) {
2618                 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
2619                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2620                         atomic_inc(&adev->vram_lost_counter);
2621                 }
2622
2623                 /* VF FLR or hotlink reset is always full-reset */
2624                 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2625         }
2626
2627         return r;
2628 }
2629
2630 /**
2631  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
2632  *
2633  * @adev: amdgpu device pointer
2634  * @job: which job trigger hang
2635  * @force forces reset regardless of amdgpu_gpu_recovery
2636  *
2637  * Attempt to reset the GPU if it has hung (all asics).
2638  * Returns 0 for success or an error on failure.
2639  */
2640 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
2641                               struct amdgpu_job *job, bool force)
2642 {
2643         struct drm_atomic_state *state = NULL;
2644         uint64_t reset_flags = 0;
2645         int i, r, resched;
2646
2647         if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
2648                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2649                 return 0;
2650         }
2651
2652         if (!force && (amdgpu_gpu_recovery == 0 ||
2653                         (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))) {
2654                 DRM_INFO("GPU recovery disabled.\n");
2655                 return 0;
2656         }
2657
2658         dev_info(adev->dev, "GPU reset begin!\n");
2659
2660         mutex_lock(&adev->lock_reset);
2661         atomic_inc(&adev->gpu_reset_counter);
2662         adev->in_gpu_reset = 1;
2663
2664         /* block TTM */
2665         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2666         /* store modesetting */
2667         if (amdgpu_device_has_dc_support(adev))
2668                 state = drm_atomic_helper_suspend(adev->ddev);
2669
2670         /* block scheduler */
2671         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2672                 struct amdgpu_ring *ring = adev->rings[i];
2673
2674                 if (!ring || !ring->sched.thread)
2675                         continue;
2676
2677                 /* only focus on the ring hit timeout if &job not NULL */
2678                 if (job && job->ring->idx != i)
2679                         continue;
2680
2681                 kthread_park(ring->sched.thread);
2682                 drm_sched_hw_job_reset(&ring->sched, &job->base);
2683
2684                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2685                 amdgpu_fence_driver_force_completion(ring);
2686         }
2687
2688         if (amdgpu_sriov_vf(adev))
2689                 r = amdgpu_device_reset_sriov(adev, &reset_flags, job ? false : true);
2690         else
2691                 r = amdgpu_device_reset(adev, &reset_flags);
2692
2693         if (!r) {
2694                 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
2695                         (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
2696                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2697                         struct amdgpu_bo *bo, *tmp;
2698                         struct dma_fence *fence = NULL, *next = NULL;
2699
2700                         DRM_INFO("recover vram bo from shadow\n");
2701                         mutex_lock(&adev->shadow_list_lock);
2702                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2703                                 next = NULL;
2704                                 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
2705                                 if (fence) {
2706                                         r = dma_fence_wait(fence, false);
2707                                         if (r) {
2708                                                 WARN(r, "recovery from shadow isn't completed\n");
2709                                                 break;
2710                                         }
2711                                 }
2712
2713                                 dma_fence_put(fence);
2714                                 fence = next;
2715                         }
2716                         mutex_unlock(&adev->shadow_list_lock);
2717                         if (fence) {
2718                                 r = dma_fence_wait(fence, false);
2719                                 if (r)
2720                                         WARN(r, "recovery from shadow isn't completed\n");
2721                         }
2722                         dma_fence_put(fence);
2723                 }
2724
2725                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2726                         struct amdgpu_ring *ring = adev->rings[i];
2727
2728                         if (!ring || !ring->sched.thread)
2729                                 continue;
2730
2731                         /* only focus on the ring hit timeout if &job not NULL */
2732                         if (job && job->ring->idx != i)
2733                                 continue;
2734
2735                         drm_sched_job_recovery(&ring->sched);
2736                         kthread_unpark(ring->sched.thread);
2737                 }
2738         } else {
2739                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2740                         struct amdgpu_ring *ring = adev->rings[i];
2741
2742                         if (!ring || !ring->sched.thread)
2743                                 continue;
2744
2745                         /* only focus on the ring hit timeout if &job not NULL */
2746                         if (job && job->ring->idx != i)
2747                                 continue;
2748
2749                         kthread_unpark(adev->rings[i]->sched.thread);
2750                 }
2751         }
2752
2753         if (amdgpu_device_has_dc_support(adev)) {
2754                 if (drm_atomic_helper_resume(adev->ddev, state))
2755                         dev_info(adev->dev, "drm resume failed:%d\n", r);
2756                 amdgpu_dm_display_resume(adev);
2757         } else {
2758                 drm_helper_resume_force_mode(adev->ddev);
2759         }
2760
2761         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2762
2763         if (r) {
2764                 /* bad news, how to tell it to userspace ? */
2765                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
2766                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
2767         } else {
2768                 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
2769         }
2770
2771         amdgpu_vf_error_trans_all(adev);
2772         adev->in_gpu_reset = 0;
2773         mutex_unlock(&adev->lock_reset);
2774         return r;
2775 }
2776
2777 void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
2778 {
2779         u32 mask;
2780         int ret;
2781
2782         if (amdgpu_pcie_gen_cap)
2783                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2784
2785         if (amdgpu_pcie_lane_cap)
2786                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2787
2788         /* covers APUs as well */
2789         if (pci_is_root_bus(adev->pdev->bus)) {
2790                 if (adev->pm.pcie_gen_mask == 0)
2791                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2792                 if (adev->pm.pcie_mlw_mask == 0)
2793                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2794                 return;
2795         }
2796
2797         if (adev->pm.pcie_gen_mask == 0) {
2798                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2799                 if (!ret) {
2800                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2801                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2802                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2803
2804                         if (mask & DRM_PCIE_SPEED_25)
2805                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2806                         if (mask & DRM_PCIE_SPEED_50)
2807                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2808                         if (mask & DRM_PCIE_SPEED_80)
2809                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2810                 } else {
2811                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2812                 }
2813         }
2814         if (adev->pm.pcie_mlw_mask == 0) {
2815                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2816                 if (!ret) {
2817                         switch (mask) {
2818                         case 32:
2819                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2820                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2821                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2822                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2823                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2824                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2825                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2826                                 break;
2827                         case 16:
2828                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2829                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2830                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2831                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2832                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2833                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2834                                 break;
2835                         case 12:
2836                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2837                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2838                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2839                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2840                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2841                                 break;
2842                         case 8:
2843                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2844                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2845                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2846                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2847                                 break;
2848                         case 4:
2849                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2850                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2851                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2852                                 break;
2853                         case 2:
2854                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2855                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2856                                 break;
2857                         case 1:
2858                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2859                                 break;
2860                         default:
2861                                 break;
2862                         }
2863                 } else {
2864                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2865                 }
2866         }
2867 }
2868