drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  63 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  64
  65 #define AMDGPU_RESUME_MS                2000
  66
  67 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  68 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  69 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
  70 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
  71
  72 static const char *amdgpu_asic_name[] = {
  73         "TAHITI",
  74         "PITCAIRN",
  75         "VERDE",
  76         "OLAND",
  77         "HAINAN",
  78         "BONAIRE",
  79         "KAVERI",
  80         "KABINI",
  81         "HAWAII",
  82         "MULLINS",
  83         "TOPAZ",
  84         "TONGA",
  85         "FIJI",
  86         "CARRIZO",
  87         "STONEY",
  88         "POLARIS10",
  89         "POLARIS11",
  90         "POLARIS12",
  91         "VEGA10",
  92         "RAVEN",
  93         "LAST",
  94 };
  95
  96 bool amdgpu_device_is_px(struct drm_device *dev)
  97 {
  98         struct amdgpu_device *adev = dev->dev_private;
  99
 100         if (adev->flags & AMD_IS_PX)
 101                 return true;
 102         return false;
 103 }
 104
 105 /*
 106  * MMIO register access helper functions.
 107  */
 108 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 109                         uint32_t acc_flags)
 110 {
 111         uint32_t ret;
 112
 113         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 114                 return amdgpu_virt_kiq_rreg(adev, reg);
 115
 116         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 117                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 118         else {
 119                 unsigned long flags;
 120
 121                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 122                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 123                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 124                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 125         }
 126         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 127         return ret;
 128 }
 129
 130 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 131                     uint32_t acc_flags)
 132 {
 133         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 134
 135         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 136                 adev->last_mm_index = v;
 137         }
 138
 139         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 140                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 141
 142         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 143                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 144         else {
 145                 unsigned long flags;
 146
 147                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 148                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 149                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 150                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 151         }
 152
 153         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 154                 udelay(500);
 155         }
 156 }
 157
 158 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 159 {
 160         if ((reg * 4) < adev->rio_mem_size)
 161                 return ioread32(adev->rio_mem + (reg * 4));
 162         else {
 163                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 164                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 165         }
 166 }
 167
 168 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 169 {
 170         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 171                 adev->last_mm_index = v;
 172         }
 173
 174         if ((reg * 4) < adev->rio_mem_size)
 175                 iowrite32(v, adev->rio_mem + (reg * 4));
 176         else {
 177                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 178                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 179         }
 180
 181         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 182                 udelay(500);
 183         }
 184 }
 185
 186 /**
 187  * amdgpu_mm_rdoorbell - read a doorbell dword
 188  *
 189  * @adev: amdgpu_device pointer
 190  * @index: doorbell index
 191  *
 192  * Returns the value in the doorbell aperture at the
 193  * requested doorbell index (CIK).
 194  */
 195 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 196 {
 197         if (index < adev->doorbell.num_doorbells) {
 198                 return readl(adev->doorbell.ptr + index);
 199         } else {
 200                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 201                 return 0;
 202         }
 203 }
 204
 205 /**
 206  * amdgpu_mm_wdoorbell - write a doorbell dword
 207  *
 208  * @adev: amdgpu_device pointer
 209  * @index: doorbell index
 210  * @v: value to write
 211  *
 212  * Writes @v to the doorbell aperture at the
 213  * requested doorbell index (CIK).
 214  */
 215 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 216 {
 217         if (index < adev->doorbell.num_doorbells) {
 218                 writel(v, adev->doorbell.ptr + index);
 219         } else {
 220                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 221         }
 222 }
 223
 224 /**
 225  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 226  *
 227  * @adev: amdgpu_device pointer
 228  * @index: doorbell index
 229  *
 230  * Returns the value in the doorbell aperture at the
 231  * requested doorbell index (VEGA10+).
 232  */
 233 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 234 {
 235         if (index < adev->doorbell.num_doorbells) {
 236                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 237         } else {
 238                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 239                 return 0;
 240         }
 241 }
 242
 243 /**
 244  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 245  *
 246  * @adev: amdgpu_device pointer
 247  * @index: doorbell index
 248  * @v: value to write
 249  *
 250  * Writes @v to the doorbell aperture at the
 251  * requested doorbell index (VEGA10+).
 252  */
 253 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 254 {
 255         if (index < adev->doorbell.num_doorbells) {
 256                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 257         } else {
 258                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 259         }
 260 }
 261
 262 /**
 263  * amdgpu_invalid_rreg - dummy reg read function
 264  *
 265  * @adev: amdgpu device pointer
 266  * @reg: offset of register
 267  *
 268  * Dummy register read function.  Used for register blocks
 269  * that certain asics don't have (all asics).
 270  * Returns the value in the register.
 271  */
 272 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 273 {
 274         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 275         BUG();
 276         return 0;
 277 }
 278
 279 /**
 280  * amdgpu_invalid_wreg - dummy reg write function
 281  *
 282  * @adev: amdgpu device pointer
 283  * @reg: offset of register
 284  * @v: value to write to the register
 285  *
 286  * Dummy register read function.  Used for register blocks
 287  * that certain asics don't have (all asics).
 288  */
 289 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 290 {
 291         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 292                   reg, v);
 293         BUG();
 294 }
 295
 296 /**
 297  * amdgpu_block_invalid_rreg - dummy reg read function
 298  *
 299  * @adev: amdgpu device pointer
 300  * @block: offset of instance
 301  * @reg: offset of register
 302  *
 303  * Dummy register read function.  Used for register blocks
 304  * that certain asics don't have (all asics).
 305  * Returns the value in the register.
 306  */
 307 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 308                                           uint32_t block, uint32_t reg)
 309 {
 310         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 311                   reg, block);
 312         BUG();
 313         return 0;
 314 }
 315
 316 /**
 317  * amdgpu_block_invalid_wreg - dummy reg write function
 318  *
 319  * @adev: amdgpu device pointer
 320  * @block: offset of instance
 321  * @reg: offset of register
 322  * @v: value to write to the register
 323  *
 324  * Dummy register read function.  Used for register blocks
 325  * that certain asics don't have (all asics).
 326  */
 327 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 328                                       uint32_t block,
 329                                       uint32_t reg, uint32_t v)
 330 {
 331         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 332                   reg, block, v);
 333         BUG();
 334 }
 335
 336 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 337 {
 338         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 339                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 340                                        &adev->vram_scratch.robj,
 341                                        &adev->vram_scratch.gpu_addr,
 342                                        (void **)&adev->vram_scratch.ptr);
 343 }
 344
 345 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 346 {
 347         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 348 }
 349
 350 /**
 351  * amdgpu_program_register_sequence - program an array of registers.
 352  *
 353  * @adev: amdgpu_device pointer
 354  * @registers: pointer to the register array
 355  * @array_size: size of the register array
 356  *
 357  * Programs an array or registers with and and or masks.
 358  * This is a helper for setting golden registers.
 359  */
 360 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 361                                       const u32 *registers,
 362                                       const u32 array_size)
 363 {
 364         u32 tmp, reg, and_mask, or_mask;
 365         int i;
 366
 367         if (array_size % 3)
 368                 return;
 369
 370         for (i = 0; i < array_size; i +=3) {
 371                 reg = registers[i + 0];
 372                 and_mask = registers[i + 1];
 373                 or_mask = registers[i + 2];
 374
 375                 if (and_mask == 0xffffffff) {
 376                         tmp = or_mask;
 377                 } else {
 378                         tmp = RREG32(reg);
 379                         tmp &= ~and_mask;
 380                         tmp |= or_mask;
 381                 }
 382                 WREG32(reg, tmp);
 383         }
 384 }
 385
 386 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 387 {
 388         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 389 }
 390
 391 /*
 392  * GPU doorbell aperture helpers function.
 393  */
 394 /**
 395  * amdgpu_doorbell_init - Init doorbell driver information.
 396  *
 397  * @adev: amdgpu_device pointer
 398  *
 399  * Init doorbell driver information (CIK)
 400  * Returns 0 on success, error on failure.
 401  */
 402 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 403 {
 404         /* No doorbell on SI hardware generation */
 405         if (adev->asic_type < CHIP_BONAIRE) {
 406                 adev->doorbell.base = 0;
 407                 adev->doorbell.size = 0;
 408                 adev->doorbell.num_doorbells = 0;
 409                 adev->doorbell.ptr = NULL;
 410                 return 0;
 411         }
 412
 413         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 414                 return -EINVAL;
 415
 416         /* doorbell bar mapping */
 417         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 418         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 419
 420         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 421                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 422         if (adev->doorbell.num_doorbells == 0)
 423                 return -EINVAL;
 424
 425         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 426                                      adev->doorbell.num_doorbells *
 427                                      sizeof(u32));
 428         if (adev->doorbell.ptr == NULL)
 429                 return -ENOMEM;
 430
 431         return 0;
 432 }
 433
 434 /**
 435  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 436  *
 437  * @adev: amdgpu_device pointer
 438  *
 439  * Tear down doorbell driver information (CIK)
 440  */
 441 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 442 {
 443         iounmap(adev->doorbell.ptr);
 444         adev->doorbell.ptr = NULL;
 445 }
 446
 447 /**
 448  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 449  *                                setup amdkfd
 450  *
 451  * @adev: amdgpu_device pointer
 452  * @aperture_base: output returning doorbell aperture base physical address
 453  * @aperture_size: output returning doorbell aperture size in bytes
 454  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 455  *
 456  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 457  * takes doorbells required for its own rings and reports the setup to amdkfd.
 458  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 459  */
 460 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 461                                 phys_addr_t *aperture_base,
 462                                 size_t *aperture_size,
 463                                 size_t *start_offset)
 464 {
 465         /*
 466          * The first num_doorbells are used by amdgpu.
 467          * amdkfd takes whatever's left in the aperture.
 468          */
 469         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 470                 *aperture_base = adev->doorbell.base;
 471                 *aperture_size = adev->doorbell.size;
 472                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 473         } else {
 474                 *aperture_base = 0;
 475                 *aperture_size = 0;
 476                 *start_offset = 0;
 477         }
 478 }
 479
 480 /*
 481  * amdgpu_wb_*()
 482  * Writeback is the method by which the GPU updates special pages in memory
 483  * with the status of certain GPU events (fences, ring pointers,etc.).
 484  */
 485
 486 /**
 487  * amdgpu_wb_fini - Disable Writeback and free memory
 488  *
 489  * @adev: amdgpu_device pointer
 490  *
 491  * Disables Writeback and frees the Writeback memory (all asics).
 492  * Used at driver shutdown.
 493  */
 494 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 495 {
 496         if (adev->wb.wb_obj) {
 497                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 498                                       &adev->wb.gpu_addr,
 499                                       (void **)&adev->wb.wb);
 500                 adev->wb.wb_obj = NULL;
 501         }
 502 }
 503
 504 /**
 505  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 506  *
 507  * @adev: amdgpu_device pointer
 508  *
 509  * Initializes writeback and allocates writeback memory (all asics).
 510  * Used at driver startup.
 511  * Returns 0 on success or an -error on failure.
 512  */
 513 static int amdgpu_wb_init(struct amdgpu_device *adev)
 514 {
 515         int r;
 516
 517         if (adev->wb.wb_obj == NULL) {
 518                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 519                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 520                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 521                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 522                                             (void **)&adev->wb.wb);
 523                 if (r) {
 524                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 525                         return r;
 526                 }
 527
 528                 adev->wb.num_wb = AMDGPU_MAX_WB;
 529                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 530
 531                 /* clear wb memory */
 532                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
 533         }
 534
 535         return 0;
 536 }
 537
 538 /**
 539  * amdgpu_wb_get - Allocate a wb entry
 540  *
 541  * @adev: amdgpu_device pointer
 542  * @wb: wb index
 543  *
 544  * Allocate a wb slot for use by the driver (all asics).
 545  * Returns 0 on success or -EINVAL on failure.
 546  */
 547 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 548 {
 549         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 550
 551         if (offset < adev->wb.num_wb) {
 552                 __set_bit(offset, adev->wb.used);
 553                 *wb = offset << 3; /* convert to dw offset */
 554                 return 0;
 555         } else {
 556                 return -EINVAL;
 557         }
 558 }
 559
 560 /**
 561  * amdgpu_wb_free - Free a wb entry
 562  *
 563  * @adev: amdgpu_device pointer
 564  * @wb: wb index
 565  *
 566  * Free a wb slot allocated for use by the driver (all asics)
 567  */
 568 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 569 {
 570         if (wb < adev->wb.num_wb)
 571                 __clear_bit(wb >> 3, adev->wb.used);
 572 }
 573
 574 /**
 575  * amdgpu_vram_location - try to find VRAM location
 576  * @adev: amdgpu device structure holding all necessary informations
 577  * @mc: memory controller structure holding memory informations
 578  * @base: base address at which to put VRAM
 579  *
 580  * Function will try to place VRAM at base address provided
 581  * as parameter.
 582  */
 583 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 584 {
 585         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 586
 587         mc->vram_start = base;
 588         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 589         if (limit && limit < mc->real_vram_size)
 590                 mc->real_vram_size = limit;
 591         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 592                         mc->mc_vram_size >> 20, mc->vram_start,
 593                         mc->vram_end, mc->real_vram_size >> 20);
 594 }
 595
 596 /**
 597  * amdgpu_gart_location - try to find GTT location
 598  * @adev: amdgpu device structure holding all necessary informations
 599  * @mc: memory controller structure holding memory informations
 600  *
 601  * Function will place try to place GTT before or after VRAM.
 602  *
 603  * If GTT size is bigger than space left then we ajust GTT size.
 604  * Thus function will never fails.
 605  *
 606  * FIXME: when reducing GTT size align new size on power of 2.
 607  */
 608 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 609 {
 610         u64 size_af, size_bf;
 611
 612         size_af = adev->mc.mc_mask - mc->vram_end;
 613         size_bf = mc->vram_start;
 614         if (size_bf > size_af) {
 615                 if (mc->gart_size > size_bf) {
 616                         dev_warn(adev->dev, "limiting GTT\n");
 617                         mc->gart_size = size_bf;
 618                 }
 619                 mc->gart_start = 0;
 620         } else {
 621                 if (mc->gart_size > size_af) {
 622                         dev_warn(adev->dev, "limiting GTT\n");
 623                         mc->gart_size = size_af;
 624                 }
 625                 mc->gart_start = mc->vram_end + 1;
 626         }
 627         mc->gart_end = mc->gart_start + mc->gart_size - 1;
 628         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 629                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 630 }
 631
 632 /*
 633  * Firmware Reservation functions
 634  */
 635 /**
 636  * amdgpu_fw_reserve_vram_fini - free fw reserved vram
 637  *
 638  * @adev: amdgpu_device pointer
 639  *
 640  * free fw reserved vram if it has been reserved.
 641  */
 642 void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
 643 {
 644         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
 645                 NULL, &adev->fw_vram_usage.va);
 646 }
 647
 648 /**
 649  * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
 650  *
 651  * @adev: amdgpu_device pointer
 652  *
 653  * create bo vram reservation from fw.
 654  */
 655 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
 656 {
 657         int r = 0;
 658         int i;
 659         u64 vram_size = adev->mc.visible_vram_size;
 660         u64 offset = adev->fw_vram_usage.start_offset;
 661         u64 size = adev->fw_vram_usage.size;
 662         struct amdgpu_bo *bo;
 663
 664         adev->fw_vram_usage.va = NULL;
 665         adev->fw_vram_usage.reserved_bo = NULL;
 666
 667         if (adev->fw_vram_usage.size > 0 &&
 668                 adev->fw_vram_usage.size <= vram_size) {
 669
 670                 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
 671                         PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 672                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 673                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
 674                         &adev->fw_vram_usage.reserved_bo);
 675                 if (r)
 676                         goto error_create;
 677
 678                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
 679                 if (r)
 680                         goto error_reserve;
 681
 682                 /* remove the original mem node and create a new one at the
 683                  * request position
 684                  */
 685                 bo = adev->fw_vram_usage.reserved_bo;
 686                 offset = ALIGN(offset, PAGE_SIZE);
 687                 for (i = 0; i < bo->placement.num_placement; ++i) {
 688                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
 689                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
 690                 }
 691
 692                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
 693                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem,
 694                                      false, false);
 695                 if (r)
 696                         goto error_pin;
 697
 698                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
 699                         AMDGPU_GEM_DOMAIN_VRAM,
 700                         adev->fw_vram_usage.start_offset,
 701                         (adev->fw_vram_usage.start_offset +
 702                         adev->fw_vram_usage.size), NULL);
 703                 if (r)
 704                         goto error_pin;
 705                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
 706                         &adev->fw_vram_usage.va);
 707                 if (r)
 708                         goto error_kmap;
 709
 710                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
 711         }
 712         return r;
 713
 714 error_kmap:
 715         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
 716 error_pin:
 717         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
 718 error_reserve:
 719         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
 720 error_create:
 721         adev->fw_vram_usage.va = NULL;
 722         adev->fw_vram_usage.reserved_bo = NULL;
 723         return r;
 724 }
 725
 726 /**
 727  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 728  *
 729  * @adev: amdgpu_device pointer
 730  *
 731  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 732  * to fail, but if any of the BARs is not accessible after the size we abort
 733  * driver loading by returning -ENODEV.
 734  */
 735 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 736 {
 737         u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
 738         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 739         struct pci_bus *root;
 740         struct resource *res;
 741         unsigned i;
 742         u16 cmd;
 743         int r;
 744
 745         /* Bypass for VF */
 746         if (amdgpu_sriov_vf(adev))
 747                 return 0;
 748
 749         /* Check if the root BUS has 64bit memory resources */
 750         root = adev->pdev->bus;
 751         while (root->parent)
 752                 root = root->parent;
 753
 754         pci_bus_for_each_resource(root, res, i) {
 755                 if (res && res->flags & IORESOURCE_MEM_64 &&
 756                     res->start > 0x100000000ull)
 757                         break;
 758         }
 759
 760         /* Trying to resize is pointless without a root hub window above 4GB */
 761         if (!res)
 762                 return 0;
 763
 764         /* Disable memory decoding while we change the BAR addresses and size */
 765         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 766         pci_write_config_word(adev->pdev, PCI_COMMAND,
 767                               cmd & ~PCI_COMMAND_MEMORY);
 768
 769         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 770         amdgpu_doorbell_fini(adev);
 771         if (adev->asic_type >= CHIP_BONAIRE)
 772                 pci_release_resource(adev->pdev, 2);
 773
 774         pci_release_resource(adev->pdev, 0);
 775
 776         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 777         if (r == -ENOSPC)
 778                 DRM_INFO("Not enough PCI address space for a large BAR.");
 779         else if (r && r != -ENOTSUPP)
 780                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 781
 782         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 783
 784         /* When the doorbell or fb BAR isn't available we have no chance of
 785          * using the device.
 786          */
 787         r = amdgpu_doorbell_init(adev);
 788         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 789                 return -ENODEV;
 790
 791         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 792
 793         return 0;
 794 }
 795
 796 /*
 797  * GPU helpers function.
 798  */
 799 /**
 800  * amdgpu_need_post - check if the hw need post or not
 801  *
 802  * @adev: amdgpu_device pointer
 803  *
 804  * Check if the asic has been initialized (all asics) at driver startup
 805  * or post is needed if  hw reset is performed.
 806  * Returns true if need or false if not.
 807  */
 808 bool amdgpu_need_post(struct amdgpu_device *adev)
 809 {
 810         uint32_t reg;
 811
 812         if (amdgpu_sriov_vf(adev))
 813                 return false;
 814
 815         if (amdgpu_passthrough(adev)) {
 816                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 817                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 818                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 819                  * vpost executed for smc version below 22.15
 820                  */
 821                 if (adev->asic_type == CHIP_FIJI) {
 822                         int err;
 823                         uint32_t fw_ver;
 824                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 825                         /* force vPost if error occured */
 826                         if (err)
 827                                 return true;
 828
 829                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 830                         if (fw_ver < 0x00160e00)
 831                                 return true;
 832                 }
 833         }
 834
 835         if (adev->has_hw_reset) {
 836                 adev->has_hw_reset = false;
 837                 return true;
 838         }
 839
 840         /* bios scratch used on CIK+ */
 841         if (adev->asic_type >= CHIP_BONAIRE)
 842                 return amdgpu_atombios_scratch_need_asic_init(adev);
 843
 844         /* check MEM_SIZE for older asics */
 845         reg = amdgpu_asic_get_config_memsize(adev);
 846
 847         if ((reg != 0) && (reg != 0xffffffff))
 848                 return false;
 849
 850         return true;
 851 }
 852
 853 /**
 854  * amdgpu_dummy_page_init - init dummy page used by the driver
 855  *
 856  * @adev: amdgpu_device pointer
 857  *
 858  * Allocate the dummy page used by the driver (all asics).
 859  * This dummy page is used by the driver as a filler for gart entries
 860  * when pages are taken out of the GART
 861  * Returns 0 on sucess, -ENOMEM on failure.
 862  */
 863 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 864 {
 865         if (adev->dummy_page.page)
 866                 return 0;
 867         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 868         if (adev->dummy_page.page == NULL)
 869                 return -ENOMEM;
 870         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 871                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 872         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 873                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 874                 __free_page(adev->dummy_page.page);
 875                 adev->dummy_page.page = NULL;
 876                 return -ENOMEM;
 877         }
 878         return 0;
 879 }
 880
 881 /**
 882  * amdgpu_dummy_page_fini - free dummy page used by the driver
 883  *
 884  * @adev: amdgpu_device pointer
 885  *
 886  * Frees the dummy page used by the driver (all asics).
 887  */
 888 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 889 {
 890         if (adev->dummy_page.page == NULL)
 891                 return;
 892         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 893                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 894         __free_page(adev->dummy_page.page);
 895         adev->dummy_page.page = NULL;
 896 }
 897
 898
 899 /* ATOM accessor methods */
 900 /*
 901  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 902  * driver registers callbacks to access registers and the interpreter
 903  * in the driver parses the tables and executes then to program specific
 904  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 905  * atombios.h, and atom.c
 906  */
 907
 908 /**
 909  * cail_pll_read - read PLL register
 910  *
 911  * @info: atom card_info pointer
 912  * @reg: PLL register offset
 913  *
 914  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 915  * Returns the value of the PLL register.
 916  */
 917 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 918 {
 919         return 0;
 920 }
 921
 922 /**
 923  * cail_pll_write - write PLL register
 924  *
 925  * @info: atom card_info pointer
 926  * @reg: PLL register offset
 927  * @val: value to write to the pll register
 928  *
 929  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 930  */
 931 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 932 {
 933
 934 }
 935
 936 /**
 937  * cail_mc_read - read MC (Memory Controller) register
 938  *
 939  * @info: atom card_info pointer
 940  * @reg: MC register offset
 941  *
 942  * Provides an MC register accessor for the atom interpreter (r4xx+).
 943  * Returns the value of the MC register.
 944  */
 945 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 946 {
 947         return 0;
 948 }
 949
 950 /**
 951  * cail_mc_write - write MC (Memory Controller) register
 952  *
 953  * @info: atom card_info pointer
 954  * @reg: MC register offset
 955  * @val: value to write to the pll register
 956  *
 957  * Provides a MC register accessor for the atom interpreter (r4xx+).
 958  */
 959 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 960 {
 961
 962 }
 963
 964 /**
 965  * cail_reg_write - write MMIO register
 966  *
 967  * @info: atom card_info pointer
 968  * @reg: MMIO register offset
 969  * @val: value to write to the pll register
 970  *
 971  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 972  */
 973 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 974 {
 975         struct amdgpu_device *adev = info->dev->dev_private;
 976
 977         WREG32(reg, val);
 978 }
 979
 980 /**
 981  * cail_reg_read - read MMIO register
 982  *
 983  * @info: atom card_info pointer
 984  * @reg: MMIO register offset
 985  *
 986  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 987  * Returns the value of the MMIO register.
 988  */
 989 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 990 {
 991         struct amdgpu_device *adev = info->dev->dev_private;
 992         uint32_t r;
 993
 994         r = RREG32(reg);
 995         return r;
 996 }
 997
 998 /**
 999  * cail_ioreg_write - write IO register
1000  *
1001  * @info: atom card_info pointer
1002  * @reg: IO register offset
1003  * @val: value to write to the pll register
1004  *
1005  * Provides a IO register accessor for the atom interpreter (r4xx+).
1006  */
1007 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1008 {
1009         struct amdgpu_device *adev = info->dev->dev_private;
1010
1011         WREG32_IO(reg, val);
1012 }
1013
1014 /**
1015  * cail_ioreg_read - read IO register
1016  *
1017  * @info: atom card_info pointer
1018  * @reg: IO register offset
1019  *
1020  * Provides an IO register accessor for the atom interpreter (r4xx+).
1021  * Returns the value of the IO register.
1022  */
1023 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1024 {
1025         struct amdgpu_device *adev = info->dev->dev_private;
1026         uint32_t r;
1027
1028         r = RREG32_IO(reg);
1029         return r;
1030 }
1031
1032 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1033                                                  struct device_attribute *attr,
1034                                                  char *buf)
1035 {
1036         struct drm_device *ddev = dev_get_drvdata(dev);
1037         struct amdgpu_device *adev = ddev->dev_private;
1038         struct atom_context *ctx = adev->mode_info.atom_context;
1039
1040         return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1041 }
1042
1043 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1044                    NULL);
1045
1046 /**
1047  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1048  *
1049  * @adev: amdgpu_device pointer
1050  *
1051  * Frees the driver info and register access callbacks for the ATOM
1052  * interpreter (r4xx+).
1053  * Called at driver shutdown.
1054  */
1055 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
1056 {
1057         if (adev->mode_info.atom_context) {
1058                 kfree(adev->mode_info.atom_context->scratch);
1059                 kfree(adev->mode_info.atom_context->iio);
1060         }
1061         kfree(adev->mode_info.atom_context);
1062         adev->mode_info.atom_context = NULL;
1063         kfree(adev->mode_info.atom_card_info);
1064         adev->mode_info.atom_card_info = NULL;
1065         device_remove_file(adev->dev, &dev_attr_vbios_version);
1066 }
1067
1068 /**
1069  * amdgpu_atombios_init - init the driver info and callbacks for atombios
1070  *
1071  * @adev: amdgpu_device pointer
1072  *
1073  * Initializes the driver info and register access callbacks for the
1074  * ATOM interpreter (r4xx+).
1075  * Returns 0 on sucess, -ENOMEM on failure.
1076  * Called at driver startup.
1077  */
1078 static int amdgpu_atombios_init(struct amdgpu_device *adev)
1079 {
1080         struct card_info *atom_card_info =
1081             kzalloc(sizeof(struct card_info), GFP_KERNEL);
1082         int ret;
1083
1084         if (!atom_card_info)
1085                 return -ENOMEM;
1086
1087         adev->mode_info.atom_card_info = atom_card_info;
1088         atom_card_info->dev = adev->ddev;
1089         atom_card_info->reg_read = cail_reg_read;
1090         atom_card_info->reg_write = cail_reg_write;
1091         /* needed for iio ops */
1092         if (adev->rio_mem) {
1093                 atom_card_info->ioreg_read = cail_ioreg_read;
1094                 atom_card_info->ioreg_write = cail_ioreg_write;
1095         } else {
1096                 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1097                 atom_card_info->ioreg_read = cail_reg_read;
1098                 atom_card_info->ioreg_write = cail_reg_write;
1099         }
1100         atom_card_info->mc_read = cail_mc_read;
1101         atom_card_info->mc_write = cail_mc_write;
1102         atom_card_info->pll_read = cail_pll_read;
1103         atom_card_info->pll_write = cail_pll_write;
1104
1105         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1106         if (!adev->mode_info.atom_context) {
1107                 amdgpu_atombios_fini(adev);
1108                 return -ENOMEM;
1109         }
1110
1111         mutex_init(&adev->mode_info.atom_context->mutex);
1112         if (adev->is_atom_fw) {
1113                 amdgpu_atomfirmware_scratch_regs_init(adev);
1114                 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1115         } else {
1116                 amdgpu_atombios_scratch_regs_init(adev);
1117                 amdgpu_atombios_allocate_fb_scratch(adev);
1118         }
1119
1120         ret = device_create_file(adev->dev, &dev_attr_vbios_version);
1121         if (ret) {
1122                 DRM_ERROR("Failed to create device file for VBIOS version\n");
1123                 return ret;
1124         }
1125
1126         return 0;
1127 }
1128
1129 /* if we get transitioned to only one device, take VGA back */
1130 /**
1131  * amdgpu_vga_set_decode - enable/disable vga decode
1132  *
1133  * @cookie: amdgpu_device pointer
1134  * @state: enable/disable vga decode
1135  *
1136  * Enable/disable vga decode (all asics).
1137  * Returns VGA resource flags.
1138  */
1139 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1140 {
1141         struct amdgpu_device *adev = cookie;
1142         amdgpu_asic_set_vga_state(adev, state);
1143         if (state)
1144                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1145                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1146         else
1147                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1148 }
1149
1150 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1151 {
1152         /* defines number of bits in page table versus page directory,
1153          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1154          * page table and the remaining bits are in the page directory */
1155         if (amdgpu_vm_block_size == -1)
1156                 return;
1157
1158         if (amdgpu_vm_block_size < 9) {
1159                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1160                          amdgpu_vm_block_size);
1161                 goto def_value;
1162         }
1163
1164         if (amdgpu_vm_block_size > 24 ||
1165             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1166                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1167                          amdgpu_vm_block_size);
1168                 goto def_value;
1169         }
1170
1171         return;
1172
1173 def_value:
1174         amdgpu_vm_block_size = -1;
1175 }
1176
1177 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1178 {
1179         /* no need to check the default value */
1180         if (amdgpu_vm_size == -1)
1181                 return;
1182
1183         if (!is_power_of_2(amdgpu_vm_size)) {
1184                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1185                          amdgpu_vm_size);
1186                 goto def_value;
1187         }
1188
1189         if (amdgpu_vm_size < 1) {
1190                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1191                          amdgpu_vm_size);
1192                 goto def_value;
1193         }
1194
1195         /*
1196          * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1197          */
1198         if (amdgpu_vm_size > 1024) {
1199                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1200                          amdgpu_vm_size);
1201                 goto def_value;
1202         }
1203
1204         return;
1205
1206 def_value:
1207         amdgpu_vm_size = -1;
1208 }
1209
1210 /**
1211  * amdgpu_check_arguments - validate module params
1212  *
1213  * @adev: amdgpu_device pointer
1214  *
1215  * Validates certain module parameters and updates
1216  * the associated values used by the driver (all asics).
1217  */
1218 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1219 {
1220         if (amdgpu_sched_jobs < 4) {
1221                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1222                          amdgpu_sched_jobs);
1223                 amdgpu_sched_jobs = 4;
1224         } else if (!is_power_of_2(amdgpu_sched_jobs)){
1225                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1226                          amdgpu_sched_jobs);
1227                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1228         }
1229
1230         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1231                 /* gart size must be greater or equal to 32M */
1232                 dev_warn(adev->dev, "gart size (%d) too small\n",
1233                          amdgpu_gart_size);
1234                 amdgpu_gart_size = -1;
1235         }
1236
1237         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1238                 /* gtt size must be greater or equal to 32M */
1239                 dev_warn(adev->dev, "gtt size (%d) too small\n",
1240                                  amdgpu_gtt_size);
1241                 amdgpu_gtt_size = -1;
1242         }
1243
1244         /* valid range is between 4 and 9 inclusive */
1245         if (amdgpu_vm_fragment_size != -1 &&
1246             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1247                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1248                 amdgpu_vm_fragment_size = -1;
1249         }
1250
1251         amdgpu_check_vm_size(adev);
1252
1253         amdgpu_check_block_size(adev);
1254
1255         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1256             !is_power_of_2(amdgpu_vram_page_split))) {
1257                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1258                          amdgpu_vram_page_split);
1259                 amdgpu_vram_page_split = 1024;
1260         }
1261 }
1262
1263 /**
1264  * amdgpu_switcheroo_set_state - set switcheroo state
1265  *
1266  * @pdev: pci dev pointer
1267  * @state: vga_switcheroo state
1268  *
1269  * Callback for the switcheroo driver.  Suspends or resumes the
1270  * the asics before or after it is powered up using ACPI methods.
1271  */
1272 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1273 {
1274         struct drm_device *dev = pci_get_drvdata(pdev);
1275
1276         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1277                 return;
1278
1279         if (state == VGA_SWITCHEROO_ON) {
1280                 pr_info("amdgpu: switched on\n");
1281                 /* don't suspend or resume card normally */
1282                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1283
1284                 amdgpu_device_resume(dev, true, true);
1285
1286                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1287                 drm_kms_helper_poll_enable(dev);
1288         } else {
1289                 pr_info("amdgpu: switched off\n");
1290                 drm_kms_helper_poll_disable(dev);
1291                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1292                 amdgpu_device_suspend(dev, true, true);
1293                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1294         }
1295 }
1296
1297 /**
1298  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1299  *
1300  * @pdev: pci dev pointer
1301  *
1302  * Callback for the switcheroo driver.  Check of the switcheroo
1303  * state can be changed.
1304  * Returns true if the state can be changed, false if not.
1305  */
1306 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1307 {
1308         struct drm_device *dev = pci_get_drvdata(pdev);
1309
1310         /*
1311         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1312         * locking inversion with the driver load path. And the access here is
1313         * completely racy anyway. So don't bother with locking for now.
1314         */
1315         return dev->open_count == 0;
1316 }
1317
1318 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1319         .set_gpu_state = amdgpu_switcheroo_set_state,
1320         .reprobe = NULL,
1321         .can_switch = amdgpu_switcheroo_can_switch,
1322 };
1323
1324 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1325                                   enum amd_ip_block_type block_type,
1326                                   enum amd_clockgating_state state)
1327 {
1328         int i, r = 0;
1329
1330         for (i = 0; i < adev->num_ip_blocks; i++) {
1331                 if (!adev->ip_blocks[i].status.valid)
1332                         continue;
1333                 if (adev->ip_blocks[i].version->type != block_type)
1334                         continue;
1335                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1336                         continue;
1337                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1338                         (void *)adev, state);
1339                 if (r)
1340                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1341                                   adev->ip_blocks[i].version->funcs->name, r);
1342         }
1343         return r;
1344 }
1345
1346 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1347                                   enum amd_ip_block_type block_type,
1348                                   enum amd_powergating_state state)
1349 {
1350         int i, r = 0;
1351
1352         for (i = 0; i < adev->num_ip_blocks; i++) {
1353                 if (!adev->ip_blocks[i].status.valid)
1354                         continue;
1355                 if (adev->ip_blocks[i].version->type != block_type)
1356                         continue;
1357                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1358                         continue;
1359                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1360                         (void *)adev, state);
1361                 if (r)
1362                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1363                                   adev->ip_blocks[i].version->funcs->name, r);
1364         }
1365         return r;
1366 }
1367
1368 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1369 {
1370         int i;
1371
1372         for (i = 0; i < adev->num_ip_blocks; i++) {
1373                 if (!adev->ip_blocks[i].status.valid)
1374                         continue;
1375                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1376                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1377         }
1378 }
1379
1380 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1381                          enum amd_ip_block_type block_type)
1382 {
1383         int i, r;
1384
1385         for (i = 0; i < adev->num_ip_blocks; i++) {
1386                 if (!adev->ip_blocks[i].status.valid)
1387                         continue;
1388                 if (adev->ip_blocks[i].version->type == block_type) {
1389                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1390                         if (r)
1391                                 return r;
1392                         break;
1393                 }
1394         }
1395         return 0;
1396
1397 }
1398
1399 bool amdgpu_is_idle(struct amdgpu_device *adev,
1400                     enum amd_ip_block_type block_type)
1401 {
1402         int i;
1403
1404         for (i = 0; i < adev->num_ip_blocks; i++) {
1405                 if (!adev->ip_blocks[i].status.valid)
1406                         continue;
1407                 if (adev->ip_blocks[i].version->type == block_type)
1408                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1409         }
1410         return true;
1411
1412 }
1413
1414 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1415                                              enum amd_ip_block_type type)
1416 {
1417         int i;
1418
1419         for (i = 0; i < adev->num_ip_blocks; i++)
1420                 if (adev->ip_blocks[i].version->type == type)
1421                         return &adev->ip_blocks[i];
1422
1423         return NULL;
1424 }
1425
1426 /**
1427  * amdgpu_ip_block_version_cmp
1428  *
1429  * @adev: amdgpu_device pointer
1430  * @type: enum amd_ip_block_type
1431  * @major: major version
1432  * @minor: minor version
1433  *
1434  * return 0 if equal or greater
1435  * return 1 if smaller or the ip_block doesn't exist
1436  */
1437 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1438                                 enum amd_ip_block_type type,
1439                                 u32 major, u32 minor)
1440 {
1441         struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1442
1443         if (ip_block && ((ip_block->version->major > major) ||
1444                         ((ip_block->version->major == major) &&
1445                         (ip_block->version->minor >= minor))))
1446                 return 0;
1447
1448         return 1;
1449 }
1450
1451 /**
1452  * amdgpu_ip_block_add
1453  *
1454  * @adev: amdgpu_device pointer
1455  * @ip_block_version: pointer to the IP to add
1456  *
1457  * Adds the IP block driver information to the collection of IPs
1458  * on the asic.
1459  */
1460 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1461                         const struct amdgpu_ip_block_version *ip_block_version)
1462 {
1463         if (!ip_block_version)
1464                 return -EINVAL;
1465
1466         DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1467                   ip_block_version->funcs->name);
1468
1469         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1470
1471         return 0;
1472 }
1473
1474 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1475 {
1476         adev->enable_virtual_display = false;
1477
1478         if (amdgpu_virtual_display) {
1479                 struct drm_device *ddev = adev->ddev;
1480                 const char *pci_address_name = pci_name(ddev->pdev);
1481                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1482
1483                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1484                 pciaddstr_tmp = pciaddstr;
1485                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1486                         pciaddname = strsep(&pciaddname_tmp, ",");
1487                         if (!strcmp("all", pciaddname)
1488                             || !strcmp(pci_address_name, pciaddname)) {
1489                                 long num_crtc;
1490                                 int res = -1;
1491
1492                                 adev->enable_virtual_display = true;
1493
1494                                 if (pciaddname_tmp)
1495                                         res = kstrtol(pciaddname_tmp, 10,
1496                                                       &num_crtc);
1497
1498                                 if (!res) {
1499                                         if (num_crtc < 1)
1500                                                 num_crtc = 1;
1501                                         if (num_crtc > 6)
1502                                                 num_crtc = 6;
1503                                         adev->mode_info.num_crtc = num_crtc;
1504                                 } else {
1505                                         adev->mode_info.num_crtc = 1;
1506                                 }
1507                                 break;
1508                         }
1509                 }
1510
1511                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1512                          amdgpu_virtual_display, pci_address_name,
1513                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1514
1515                 kfree(pciaddstr);
1516         }
1517 }
1518
1519 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1520 {
1521         const char *chip_name;
1522         char fw_name[30];
1523         int err;
1524         const struct gpu_info_firmware_header_v1_0 *hdr;
1525
1526         adev->firmware.gpu_info_fw = NULL;
1527
1528         switch (adev->asic_type) {
1529         case CHIP_TOPAZ:
1530         case CHIP_TONGA:
1531         case CHIP_FIJI:
1532         case CHIP_POLARIS11:
1533         case CHIP_POLARIS10:
1534         case CHIP_POLARIS12:
1535         case CHIP_CARRIZO:
1536         case CHIP_STONEY:
1537 #ifdef CONFIG_DRM_AMDGPU_SI
1538         case CHIP_VERDE:
1539         case CHIP_TAHITI:
1540         case CHIP_PITCAIRN:
1541         case CHIP_OLAND:
1542         case CHIP_HAINAN:
1543 #endif
1544 #ifdef CONFIG_DRM_AMDGPU_CIK
1545         case CHIP_BONAIRE:
1546         case CHIP_HAWAII:
1547         case CHIP_KAVERI:
1548         case CHIP_KABINI:
1549         case CHIP_MULLINS:
1550 #endif
1551         default:
1552                 return 0;
1553         case CHIP_VEGA10:
1554                 chip_name = "vega10";
1555                 break;
1556         case CHIP_RAVEN:
1557                 chip_name = "raven";
1558                 break;
1559         }
1560
1561         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1562         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1563         if (err) {
1564                 dev_err(adev->dev,
1565                         "Failed to load gpu_info firmware \"%s\"\n",
1566                         fw_name);
1567                 goto out;
1568         }
1569         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1570         if (err) {
1571                 dev_err(adev->dev,
1572                         "Failed to validate gpu_info firmware \"%s\"\n",
1573                         fw_name);
1574                 goto out;
1575         }
1576
1577         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1578         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1579
1580         switch (hdr->version_major) {
1581         case 1:
1582         {
1583                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1584                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1585                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1586
1587                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1588                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1589                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1590                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1591                 adev->gfx.config.max_texture_channel_caches =
1592                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1593                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1594                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1595                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1596                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1597                 adev->gfx.config.double_offchip_lds_buf =
1598                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1599                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1600                 adev->gfx.cu_info.max_waves_per_simd =
1601                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1602                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1603                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1604                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1605                 break;
1606         }
1607         default:
1608                 dev_err(adev->dev,
1609                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1610                 err = -EINVAL;
1611                 goto out;
1612         }
1613 out:
1614         return err;
1615 }
1616
1617 static int amdgpu_early_init(struct amdgpu_device *adev)
1618 {
1619         int i, r;
1620
1621         amdgpu_device_enable_virtual_display(adev);
1622
1623         switch (adev->asic_type) {
1624         case CHIP_TOPAZ:
1625         case CHIP_TONGA:
1626         case CHIP_FIJI:
1627         case CHIP_POLARIS11:
1628         case CHIP_POLARIS10:
1629         case CHIP_POLARIS12:
1630         case CHIP_CARRIZO:
1631         case CHIP_STONEY:
1632                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1633                         adev->family = AMDGPU_FAMILY_CZ;
1634                 else
1635                         adev->family = AMDGPU_FAMILY_VI;
1636
1637                 r = vi_set_ip_blocks(adev);
1638                 if (r)
1639                         return r;
1640                 break;
1641 #ifdef CONFIG_DRM_AMDGPU_SI
1642         case CHIP_VERDE:
1643         case CHIP_TAHITI:
1644         case CHIP_PITCAIRN:
1645         case CHIP_OLAND:
1646         case CHIP_HAINAN:
1647                 adev->family = AMDGPU_FAMILY_SI;
1648                 r = si_set_ip_blocks(adev);
1649                 if (r)
1650                         return r;
1651                 break;
1652 #endif
1653 #ifdef CONFIG_DRM_AMDGPU_CIK
1654         case CHIP_BONAIRE:
1655         case CHIP_HAWAII:
1656         case CHIP_KAVERI:
1657         case CHIP_KABINI:
1658         case CHIP_MULLINS:
1659                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1660                         adev->family = AMDGPU_FAMILY_CI;
1661                 else
1662                         adev->family = AMDGPU_FAMILY_KV;
1663
1664                 r = cik_set_ip_blocks(adev);
1665                 if (r)
1666                         return r;
1667                 break;
1668 #endif
1669         case  CHIP_VEGA10:
1670         case  CHIP_RAVEN:
1671                 if (adev->asic_type == CHIP_RAVEN)
1672                         adev->family = AMDGPU_FAMILY_RV;
1673                 else
1674                         adev->family = AMDGPU_FAMILY_AI;
1675
1676                 r = soc15_set_ip_blocks(adev);
1677                 if (r)
1678                         return r;
1679                 break;
1680         default:
1681                 /* FIXME: not supported yet */
1682                 return -EINVAL;
1683         }
1684
1685         r = amdgpu_device_parse_gpu_info_fw(adev);
1686         if (r)
1687                 return r;
1688
1689         amdgpu_amdkfd_device_probe(adev);
1690
1691         if (amdgpu_sriov_vf(adev)) {
1692                 r = amdgpu_virt_request_full_gpu(adev, true);
1693                 if (r)
1694                         return -EAGAIN;
1695         }
1696
1697         for (i = 0; i < adev->num_ip_blocks; i++) {
1698                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1699                         DRM_ERROR("disabled ip block: %d <%s>\n",
1700                                   i, adev->ip_blocks[i].version->funcs->name);
1701                         adev->ip_blocks[i].status.valid = false;
1702                 } else {
1703                         if (adev->ip_blocks[i].version->funcs->early_init) {
1704                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1705                                 if (r == -ENOENT) {
1706                                         adev->ip_blocks[i].status.valid = false;
1707                                 } else if (r) {
1708                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1709                                                   adev->ip_blocks[i].version->funcs->name, r);
1710                                         return r;
1711                                 } else {
1712                                         adev->ip_blocks[i].status.valid = true;
1713                                 }
1714                         } else {
1715                                 adev->ip_blocks[i].status.valid = true;
1716                         }
1717                 }
1718         }
1719
1720         adev->cg_flags &= amdgpu_cg_mask;
1721         adev->pg_flags &= amdgpu_pg_mask;
1722
1723         return 0;
1724 }
1725
1726 static int amdgpu_init(struct amdgpu_device *adev)
1727 {
1728         int i, r;
1729
1730         for (i = 0; i < adev->num_ip_blocks; i++) {
1731                 if (!adev->ip_blocks[i].status.valid)
1732                         continue;
1733                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1734                 if (r) {
1735                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1736                                   adev->ip_blocks[i].version->funcs->name, r);
1737                         return r;
1738                 }
1739                 adev->ip_blocks[i].status.sw = true;
1740                 /* need to do gmc hw init early so we can allocate gpu mem */
1741                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1742                         r = amdgpu_vram_scratch_init(adev);
1743                         if (r) {
1744                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1745                                 return r;
1746                         }
1747                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1748                         if (r) {
1749                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1750                                 return r;
1751                         }
1752                         r = amdgpu_wb_init(adev);
1753                         if (r) {
1754                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1755                                 return r;
1756                         }
1757                         adev->ip_blocks[i].status.hw = true;
1758
1759                         /* right after GMC hw init, we create CSA */
1760                         if (amdgpu_sriov_vf(adev)) {
1761                                 r = amdgpu_allocate_static_csa(adev);
1762                                 if (r) {
1763                                         DRM_ERROR("allocate CSA failed %d\n", r);
1764                                         return r;
1765                                 }
1766                         }
1767                 }
1768         }
1769
1770         for (i = 0; i < adev->num_ip_blocks; i++) {
1771                 if (!adev->ip_blocks[i].status.sw)
1772                         continue;
1773                 /* gmc hw init is done early */
1774                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1775                         continue;
1776                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1777                 if (r) {
1778                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1779                                   adev->ip_blocks[i].version->funcs->name, r);
1780                         return r;
1781                 }
1782                 adev->ip_blocks[i].status.hw = true;
1783         }
1784
1785         amdgpu_amdkfd_device_init(adev);
1786
1787         if (amdgpu_sriov_vf(adev))
1788                 amdgpu_virt_release_full_gpu(adev, true);
1789
1790         return 0;
1791 }
1792
1793 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1794 {
1795         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1796 }
1797
1798 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1799 {
1800         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1801                         AMDGPU_RESET_MAGIC_NUM);
1802 }
1803
1804 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1805 {
1806         int i = 0, r;
1807
1808         for (i = 0; i < adev->num_ip_blocks; i++) {
1809                 if (!adev->ip_blocks[i].status.valid)
1810                         continue;
1811                 /* skip CG for VCE/UVD, it's handled specially */
1812                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1813                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1814                         /* enable clockgating to save power */
1815                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1816                                                                                      AMD_CG_STATE_GATE);
1817                         if (r) {
1818                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1819                                           adev->ip_blocks[i].version->funcs->name, r);
1820                                 return r;
1821                         }
1822                 }
1823         }
1824         return 0;
1825 }
1826
1827 static int amdgpu_late_init(struct amdgpu_device *adev)
1828 {
1829         int i = 0, r;
1830
1831         for (i = 0; i < adev->num_ip_blocks; i++) {
1832                 if (!adev->ip_blocks[i].status.valid)
1833                         continue;
1834                 if (adev->ip_blocks[i].version->funcs->late_init) {
1835                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1836                         if (r) {
1837                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1838                                           adev->ip_blocks[i].version->funcs->name, r);
1839                                 return r;
1840                         }
1841                         adev->ip_blocks[i].status.late_initialized = true;
1842                 }
1843         }
1844
1845         mod_delayed_work(system_wq, &adev->late_init_work,
1846                         msecs_to_jiffies(AMDGPU_RESUME_MS));
1847
1848         amdgpu_fill_reset_magic(adev);
1849
1850         return 0;
1851 }
1852
1853 static int amdgpu_fini(struct amdgpu_device *adev)
1854 {
1855         int i, r;
1856
1857         amdgpu_amdkfd_device_fini(adev);
1858         /* need to disable SMC first */
1859         for (i = 0; i < adev->num_ip_blocks; i++) {
1860                 if (!adev->ip_blocks[i].status.hw)
1861                         continue;
1862                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1863                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1864                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1865                                                                                      AMD_CG_STATE_UNGATE);
1866                         if (r) {
1867                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1868                                           adev->ip_blocks[i].version->funcs->name, r);
1869                                 return r;
1870                         }
1871                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1872                         /* XXX handle errors */
1873                         if (r) {
1874                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1875                                           adev->ip_blocks[i].version->funcs->name, r);
1876                         }
1877                         adev->ip_blocks[i].status.hw = false;
1878                         break;
1879                 }
1880         }
1881
1882         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1883                 if (!adev->ip_blocks[i].status.hw)
1884                         continue;
1885                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1886                         amdgpu_free_static_csa(adev);
1887                         amdgpu_wb_fini(adev);
1888                         amdgpu_vram_scratch_fini(adev);
1889                 }
1890
1891                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1892                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1893                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1894                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1895                                                                                      AMD_CG_STATE_UNGATE);
1896                         if (r) {
1897                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1898                                           adev->ip_blocks[i].version->funcs->name, r);
1899                                 return r;
1900                         }
1901                 }
1902
1903                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1904                 /* XXX handle errors */
1905                 if (r) {
1906                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1907                                   adev->ip_blocks[i].version->funcs->name, r);
1908                 }
1909
1910                 adev->ip_blocks[i].status.hw = false;
1911         }
1912
1913         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1914                 if (!adev->ip_blocks[i].status.sw)
1915                         continue;
1916                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1917                 /* XXX handle errors */
1918                 if (r) {
1919                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1920                                   adev->ip_blocks[i].version->funcs->name, r);
1921                 }
1922                 adev->ip_blocks[i].status.sw = false;
1923                 adev->ip_blocks[i].status.valid = false;
1924         }
1925
1926         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1927                 if (!adev->ip_blocks[i].status.late_initialized)
1928                         continue;
1929                 if (adev->ip_blocks[i].version->funcs->late_fini)
1930                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1931                 adev->ip_blocks[i].status.late_initialized = false;
1932         }
1933
1934         if (amdgpu_sriov_vf(adev))
1935                 if (amdgpu_virt_release_full_gpu(adev, false))
1936                         DRM_ERROR("failed to release exclusive mode on fini\n");
1937
1938         return 0;
1939 }
1940
1941 static void amdgpu_late_init_func_handler(struct work_struct *work)
1942 {
1943         struct amdgpu_device *adev =
1944                 container_of(work, struct amdgpu_device, late_init_work.work);
1945         amdgpu_late_set_cg_state(adev);
1946 }
1947
1948 int amdgpu_suspend(struct amdgpu_device *adev)
1949 {
1950         int i, r;
1951
1952         if (amdgpu_sriov_vf(adev))
1953                 amdgpu_virt_request_full_gpu(adev, false);
1954
1955         /* ungate SMC block first */
1956         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1957                                          AMD_CG_STATE_UNGATE);
1958         if (r) {
1959                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1960         }
1961
1962         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1963                 if (!adev->ip_blocks[i].status.valid)
1964                         continue;
1965                 /* ungate blocks so that suspend can properly shut them down */
1966                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1967                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1968                                                                                      AMD_CG_STATE_UNGATE);
1969                         if (r) {
1970                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1971                                           adev->ip_blocks[i].version->funcs->name, r);
1972                         }
1973                 }
1974                 /* XXX handle errors */
1975                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1976                 /* XXX handle errors */
1977                 if (r) {
1978                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1979                                   adev->ip_blocks[i].version->funcs->name, r);
1980                 }
1981         }
1982
1983         if (amdgpu_sriov_vf(adev))
1984                 amdgpu_virt_release_full_gpu(adev, false);
1985
1986         return 0;
1987 }
1988
1989 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1990 {
1991         int i, r;
1992
1993         static enum amd_ip_block_type ip_order[] = {
1994                 AMD_IP_BLOCK_TYPE_GMC,
1995                 AMD_IP_BLOCK_TYPE_COMMON,
1996                 AMD_IP_BLOCK_TYPE_IH,
1997         };
1998
1999         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2000                 int j;
2001                 struct amdgpu_ip_block *block;
2002
2003                 for (j = 0; j < adev->num_ip_blocks; j++) {
2004                         block = &adev->ip_blocks[j];
2005
2006                         if (block->version->type != ip_order[i] ||
2007                                 !block->status.valid)
2008                                 continue;
2009
2010                         r = block->version->funcs->hw_init(adev);
2011                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2012                 }
2013         }
2014
2015         return 0;
2016 }
2017
2018 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
2019 {
2020         int i, r;
2021
2022         static enum amd_ip_block_type ip_order[] = {
2023                 AMD_IP_BLOCK_TYPE_SMC,
2024                 AMD_IP_BLOCK_TYPE_PSP,
2025                 AMD_IP_BLOCK_TYPE_DCE,
2026                 AMD_IP_BLOCK_TYPE_GFX,
2027                 AMD_IP_BLOCK_TYPE_SDMA,
2028                 AMD_IP_BLOCK_TYPE_UVD,
2029                 AMD_IP_BLOCK_TYPE_VCE
2030         };
2031
2032         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2033                 int j;
2034                 struct amdgpu_ip_block *block;
2035
2036                 for (j = 0; j < adev->num_ip_blocks; j++) {
2037                         block = &adev->ip_blocks[j];
2038
2039                         if (block->version->type != ip_order[i] ||
2040                                 !block->status.valid)
2041                                 continue;
2042
2043                         r = block->version->funcs->hw_init(adev);
2044                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2045                 }
2046         }
2047
2048         return 0;
2049 }
2050
2051 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
2052 {
2053         int i, r;
2054
2055         for (i = 0; i < adev->num_ip_blocks; i++) {
2056                 if (!adev->ip_blocks[i].status.valid)
2057                         continue;
2058                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2059                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2060                                 adev->ip_blocks[i].version->type ==
2061                                 AMD_IP_BLOCK_TYPE_IH) {
2062                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2063                         if (r) {
2064                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2065                                           adev->ip_blocks[i].version->funcs->name, r);
2066                                 return r;
2067                         }
2068                 }
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
2075 {
2076         int i, r;
2077
2078         for (i = 0; i < adev->num_ip_blocks; i++) {
2079                 if (!adev->ip_blocks[i].status.valid)
2080                         continue;
2081                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2082                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2083                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
2084                         continue;
2085                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2086                 if (r) {
2087                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2088                                   adev->ip_blocks[i].version->funcs->name, r);
2089                         return r;
2090                 }
2091         }
2092
2093         return 0;
2094 }
2095
2096 static int amdgpu_resume(struct amdgpu_device *adev)
2097 {
2098         int r;
2099
2100         r = amdgpu_resume_phase1(adev);
2101         if (r)
2102                 return r;
2103         r = amdgpu_resume_phase2(adev);
2104
2105         return r;
2106 }
2107
2108 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2109 {
2110         if (amdgpu_sriov_vf(adev)) {
2111                 if (adev->is_atom_fw) {
2112                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2113                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2114                 } else {
2115                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2116                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2117                 }
2118
2119                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2120                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2121         }
2122 }
2123
2124 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2125 {
2126         switch (asic_type) {
2127 #if defined(CONFIG_DRM_AMD_DC)
2128         case CHIP_BONAIRE:
2129         case CHIP_HAWAII:
2130         case CHIP_KAVERI:
2131         case CHIP_CARRIZO:
2132         case CHIP_STONEY:
2133         case CHIP_POLARIS11:
2134         case CHIP_POLARIS10:
2135         case CHIP_POLARIS12:
2136         case CHIP_TONGA:
2137         case CHIP_FIJI:
2138 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
2139                 return amdgpu_dc != 0;
2140 #endif
2141         case CHIP_KABINI:
2142         case CHIP_MULLINS:
2143                 return amdgpu_dc > 0;
2144         case CHIP_VEGA10:
2145 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2146         case CHIP_RAVEN:
2147 #endif
2148                 return amdgpu_dc != 0;
2149 #endif
2150         default:
2151                 return false;
2152         }
2153 }
2154
2155 /**
2156  * amdgpu_device_has_dc_support - check if dc is supported
2157  *
2158  * @adev: amdgpu_device_pointer
2159  *
2160  * Returns true for supported, false for not supported
2161  */
2162 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2163 {
2164         if (amdgpu_sriov_vf(adev))
2165                 return false;
2166
2167         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2168 }
2169
2170 /**
2171  * amdgpu_device_init - initialize the driver
2172  *
2173  * @adev: amdgpu_device pointer
2174  * @pdev: drm dev pointer
2175  * @pdev: pci dev pointer
2176  * @flags: driver flags
2177  *
2178  * Initializes the driver info and hw (all asics).
2179  * Returns 0 for success or an error on failure.
2180  * Called at driver startup.
2181  */
2182 int amdgpu_device_init(struct amdgpu_device *adev,
2183                        struct drm_device *ddev,
2184                        struct pci_dev *pdev,
2185                        uint32_t flags)
2186 {
2187         int r, i;
2188         bool runtime = false;
2189         u32 max_MBps;
2190
2191         adev->shutdown = false;
2192         adev->dev = &pdev->dev;
2193         adev->ddev = ddev;
2194         adev->pdev = pdev;
2195         adev->flags = flags;
2196         adev->asic_type = flags & AMD_ASIC_MASK;
2197         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2198         adev->mc.gart_size = 512 * 1024 * 1024;
2199         adev->accel_working = false;
2200         adev->num_rings = 0;
2201         adev->mman.buffer_funcs = NULL;
2202         adev->mman.buffer_funcs_ring = NULL;
2203         adev->vm_manager.vm_pte_funcs = NULL;
2204         adev->vm_manager.vm_pte_num_rings = 0;
2205         adev->gart.gart_funcs = NULL;
2206         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2207         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2208
2209         adev->smc_rreg = &amdgpu_invalid_rreg;
2210         adev->smc_wreg = &amdgpu_invalid_wreg;
2211         adev->pcie_rreg = &amdgpu_invalid_rreg;
2212         adev->pcie_wreg = &amdgpu_invalid_wreg;
2213         adev->pciep_rreg = &amdgpu_invalid_rreg;
2214         adev->pciep_wreg = &amdgpu_invalid_wreg;
2215         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2216         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2217         adev->didt_rreg = &amdgpu_invalid_rreg;
2218         adev->didt_wreg = &amdgpu_invalid_wreg;
2219         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2220         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2221         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2222         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2223
2224         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2225                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2226                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2227
2228         /* mutex initialization are all done here so we
2229          * can recall function without having locking issues */
2230         atomic_set(&adev->irq.ih.lock, 0);
2231         mutex_init(&adev->firmware.mutex);
2232         mutex_init(&adev->pm.mutex);
2233         mutex_init(&adev->gfx.gpu_clock_mutex);
2234         mutex_init(&adev->srbm_mutex);
2235         mutex_init(&adev->gfx.pipe_reserve_mutex);
2236         mutex_init(&adev->grbm_idx_mutex);
2237         mutex_init(&adev->mn_lock);
2238         mutex_init(&adev->virt.vf_errors.lock);
2239         hash_init(adev->mn_hash);
2240         mutex_init(&adev->lock_reset);
2241
2242         amdgpu_check_arguments(adev);
2243
2244         spin_lock_init(&adev->mmio_idx_lock);
2245         spin_lock_init(&adev->smc_idx_lock);
2246         spin_lock_init(&adev->pcie_idx_lock);
2247         spin_lock_init(&adev->uvd_ctx_idx_lock);
2248         spin_lock_init(&adev->didt_idx_lock);
2249         spin_lock_init(&adev->gc_cac_idx_lock);
2250         spin_lock_init(&adev->se_cac_idx_lock);
2251         spin_lock_init(&adev->audio_endpt_idx_lock);
2252         spin_lock_init(&adev->mm_stats.lock);
2253
2254         INIT_LIST_HEAD(&adev->shadow_list);
2255         mutex_init(&adev->shadow_list_lock);
2256
2257         INIT_LIST_HEAD(&adev->ring_lru_list);
2258         spin_lock_init(&adev->ring_lru_list_lock);
2259
2260         INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2261
2262         /* Registers mapping */
2263         /* TODO: block userspace mapping of io register */
2264         if (adev->asic_type >= CHIP_BONAIRE) {
2265                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2266                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2267         } else {
2268                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2269                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2270         }
2271
2272         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2273         if (adev->rmmio == NULL) {
2274                 return -ENOMEM;
2275         }
2276         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2277         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2278
2279         /* doorbell bar mapping */
2280         amdgpu_doorbell_init(adev);
2281
2282         /* io port mapping */
2283         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2284                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2285                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2286                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2287                         break;
2288                 }
2289         }
2290         if (adev->rio_mem == NULL)
2291                 DRM_INFO("PCI I/O BAR is not found.\n");
2292
2293         /* early init functions */
2294         r = amdgpu_early_init(adev);
2295         if (r)
2296                 return r;
2297
2298         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2299         /* this will fail for cards that aren't VGA class devices, just
2300          * ignore it */
2301         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2302
2303         if (amdgpu_runtime_pm == 1)
2304                 runtime = true;
2305         if (amdgpu_device_is_px(ddev))
2306                 runtime = true;
2307         if (!pci_is_thunderbolt_attached(adev->pdev))
2308                 vga_switcheroo_register_client(adev->pdev,
2309                                                &amdgpu_switcheroo_ops, runtime);
2310         if (runtime)
2311                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2312
2313         /* Read BIOS */
2314         if (!amdgpu_get_bios(adev)) {
2315                 r = -EINVAL;
2316                 goto failed;
2317         }
2318
2319         r = amdgpu_atombios_init(adev);
2320         if (r) {
2321                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2322                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2323                 goto failed;
2324         }
2325
2326         /* detect if we are with an SRIOV vbios */
2327         amdgpu_device_detect_sriov_bios(adev);
2328
2329         /* Post card if necessary */
2330         if (amdgpu_need_post(adev)) {
2331                 if (!adev->bios) {
2332                         dev_err(adev->dev, "no vBIOS found\n");
2333                         r = -EINVAL;
2334                         goto failed;
2335                 }
2336                 DRM_INFO("GPU posting now...\n");
2337                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2338                 if (r) {
2339                         dev_err(adev->dev, "gpu post error!\n");
2340                         goto failed;
2341                 }
2342         }
2343
2344         if (adev->is_atom_fw) {
2345                 /* Initialize clocks */
2346                 r = amdgpu_atomfirmware_get_clock_info(adev);
2347                 if (r) {
2348                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2349                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2350                         goto failed;
2351                 }
2352         } else {
2353                 /* Initialize clocks */
2354                 r = amdgpu_atombios_get_clock_info(adev);
2355                 if (r) {
2356                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2357                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2358                         goto failed;
2359                 }
2360                 /* init i2c buses */
2361                 if (!amdgpu_device_has_dc_support(adev))
2362                         amdgpu_atombios_i2c_init(adev);
2363         }
2364
2365         /* Fence driver */
2366         r = amdgpu_fence_driver_init(adev);
2367         if (r) {
2368                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2369                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2370                 goto failed;
2371         }
2372
2373         /* init the mode config */
2374         drm_mode_config_init(adev->ddev);
2375
2376         r = amdgpu_init(adev);
2377         if (r) {
2378                 /* failed in exclusive mode due to timeout */
2379                 if (amdgpu_sriov_vf(adev) &&
2380                     !amdgpu_sriov_runtime(adev) &&
2381                     amdgpu_virt_mmio_blocked(adev) &&
2382                     !amdgpu_virt_wait_reset(adev)) {
2383                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2384                         /* Don't send request since VF is inactive. */
2385                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2386                         adev->virt.ops = NULL;
2387                         r = -EAGAIN;
2388                         goto failed;
2389                 }
2390                 dev_err(adev->dev, "amdgpu_init failed\n");
2391                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2392                 amdgpu_fini(adev);
2393                 goto failed;
2394         }
2395
2396         adev->accel_working = true;
2397
2398         amdgpu_vm_check_compute_bug(adev);
2399
2400         /* Initialize the buffer migration limit. */
2401         if (amdgpu_moverate >= 0)
2402                 max_MBps = amdgpu_moverate;
2403         else
2404                 max_MBps = 8; /* Allow 8 MB/s. */
2405         /* Get a log2 for easy divisions. */
2406         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2407
2408         r = amdgpu_ib_pool_init(adev);
2409         if (r) {
2410                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2411                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2412                 goto failed;
2413         }
2414
2415         r = amdgpu_ib_ring_tests(adev);
2416         if (r)
2417                 DRM_ERROR("ib ring test failed (%d).\n", r);
2418
2419         if (amdgpu_sriov_vf(adev))
2420                 amdgpu_virt_init_data_exchange(adev);
2421
2422         amdgpu_fbdev_init(adev);
2423
2424         r = amdgpu_pm_sysfs_init(adev);
2425         if (r)
2426                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2427
2428         r = amdgpu_gem_debugfs_init(adev);
2429         if (r)
2430                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2431
2432         r = amdgpu_debugfs_regs_init(adev);
2433         if (r)
2434                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2435
2436         r = amdgpu_debugfs_test_ib_ring_init(adev);
2437         if (r)
2438                 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2439
2440         r = amdgpu_debugfs_firmware_init(adev);
2441         if (r)
2442                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2443
2444         r = amdgpu_debugfs_vbios_dump_init(adev);
2445         if (r)
2446                 DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
2447
2448         if ((amdgpu_testing & 1)) {
2449                 if (adev->accel_working)
2450                         amdgpu_test_moves(adev);
2451                 else
2452                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2453         }
2454         if (amdgpu_benchmarking) {
2455                 if (adev->accel_working)
2456                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2457                 else
2458                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2459         }
2460
2461         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2462          * explicit gating rather than handling it automatically.
2463          */
2464         r = amdgpu_late_init(adev);
2465         if (r) {
2466                 dev_err(adev->dev, "amdgpu_late_init failed\n");
2467                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2468                 goto failed;
2469         }
2470
2471         return 0;
2472
2473 failed:
2474         amdgpu_vf_error_trans_all(adev);
2475         if (runtime)
2476                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2477
2478         return r;
2479 }
2480
2481 /**
2482  * amdgpu_device_fini - tear down the driver
2483  *
2484  * @adev: amdgpu_device pointer
2485  *
2486  * Tear down the driver info (all asics).
2487  * Called at driver shutdown.
2488  */
2489 void amdgpu_device_fini(struct amdgpu_device *adev)
2490 {
2491         int r;
2492
2493         DRM_INFO("amdgpu: finishing device.\n");
2494         adev->shutdown = true;
2495         if (adev->mode_info.mode_config_initialized)
2496                 drm_crtc_force_disable_all(adev->ddev);
2497         /* evict vram memory */
2498         amdgpu_bo_evict_vram(adev);
2499         amdgpu_ib_pool_fini(adev);
2500         amdgpu_fence_driver_fini(adev);
2501         amdgpu_fbdev_fini(adev);
2502         r = amdgpu_fini(adev);
2503         if (adev->firmware.gpu_info_fw) {
2504                 release_firmware(adev->firmware.gpu_info_fw);
2505                 adev->firmware.gpu_info_fw = NULL;
2506         }
2507         adev->accel_working = false;
2508         cancel_delayed_work_sync(&adev->late_init_work);
2509         /* free i2c buses */
2510         if (!amdgpu_device_has_dc_support(adev))
2511                 amdgpu_i2c_fini(adev);
2512         amdgpu_atombios_fini(adev);
2513         kfree(adev->bios);
2514         adev->bios = NULL;
2515         if (!pci_is_thunderbolt_attached(adev->pdev))
2516                 vga_switcheroo_unregister_client(adev->pdev);
2517         if (adev->flags & AMD_IS_PX)
2518                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2519         vga_client_register(adev->pdev, NULL, NULL, NULL);
2520         if (adev->rio_mem)
2521                 pci_iounmap(adev->pdev, adev->rio_mem);
2522         adev->rio_mem = NULL;
2523         iounmap(adev->rmmio);
2524         adev->rmmio = NULL;
2525         amdgpu_doorbell_fini(adev);
2526         amdgpu_pm_sysfs_fini(adev);
2527         amdgpu_debugfs_regs_cleanup(adev);
2528 }
2529
2530
2531 /*
2532  * Suspend & resume.
2533  */
2534 /**
2535  * amdgpu_device_suspend - initiate device suspend
2536  *
2537  * @pdev: drm dev pointer
2538  * @state: suspend state
2539  *
2540  * Puts the hw in the suspend state (all asics).
2541  * Returns 0 for success or an error on failure.
2542  * Called at driver suspend.
2543  */
2544 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2545 {
2546         struct amdgpu_device *adev;
2547         struct drm_crtc *crtc;
2548         struct drm_connector *connector;
2549         int r;
2550
2551         if (dev == NULL || dev->dev_private == NULL) {
2552                 return -ENODEV;
2553         }
2554
2555         adev = dev->dev_private;
2556
2557         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2558                 return 0;
2559
2560         drm_kms_helper_poll_disable(dev);
2561
2562         if (!amdgpu_device_has_dc_support(adev)) {
2563                 /* turn off display hw */
2564                 drm_modeset_lock_all(dev);
2565                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2566                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2567                 }
2568                 drm_modeset_unlock_all(dev);
2569         }
2570
2571         amdgpu_amdkfd_suspend(adev);
2572
2573         /* unpin the front buffers and cursors */
2574         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2575                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2576                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2577                 struct amdgpu_bo *robj;
2578
2579                 if (amdgpu_crtc->cursor_bo) {
2580                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2581                         r = amdgpu_bo_reserve(aobj, true);
2582                         if (r == 0) {
2583                                 amdgpu_bo_unpin(aobj);
2584                                 amdgpu_bo_unreserve(aobj);
2585                         }
2586                 }
2587
2588                 if (rfb == NULL || rfb->obj == NULL) {
2589                         continue;
2590                 }
2591                 robj = gem_to_amdgpu_bo(rfb->obj);
2592                 /* don't unpin kernel fb objects */
2593                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2594                         r = amdgpu_bo_reserve(robj, true);
2595                         if (r == 0) {
2596                                 amdgpu_bo_unpin(robj);
2597                                 amdgpu_bo_unreserve(robj);
2598                         }
2599                 }
2600         }
2601         /* evict vram memory */
2602         amdgpu_bo_evict_vram(adev);
2603
2604         amdgpu_fence_driver_suspend(adev);
2605
2606         r = amdgpu_suspend(adev);
2607
2608         /* evict remaining vram memory
2609          * This second call to evict vram is to evict the gart page table
2610          * using the CPU.
2611          */
2612         amdgpu_bo_evict_vram(adev);
2613
2614         amdgpu_atombios_scratch_regs_save(adev);
2615         pci_save_state(dev->pdev);
2616         if (suspend) {
2617                 /* Shut down the device */
2618                 pci_disable_device(dev->pdev);
2619                 pci_set_power_state(dev->pdev, PCI_D3hot);
2620         } else {
2621                 r = amdgpu_asic_reset(adev);
2622                 if (r)
2623                         DRM_ERROR("amdgpu asic reset failed\n");
2624         }
2625
2626         if (fbcon) {
2627                 console_lock();
2628                 amdgpu_fbdev_set_suspend(adev, 1);
2629                 console_unlock();
2630         }
2631         return 0;
2632 }
2633
2634 /**
2635  * amdgpu_device_resume - initiate device resume
2636  *
2637  * @pdev: drm dev pointer
2638  *
2639  * Bring the hw back to operating state (all asics).
2640  * Returns 0 for success or an error on failure.
2641  * Called at driver resume.
2642  */
2643 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2644 {
2645         struct drm_connector *connector;
2646         struct amdgpu_device *adev = dev->dev_private;
2647         struct drm_crtc *crtc;
2648         int r = 0;
2649
2650         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2651                 return 0;
2652
2653         if (fbcon)
2654                 console_lock();
2655
2656         if (resume) {
2657                 pci_set_power_state(dev->pdev, PCI_D0);
2658                 pci_restore_state(dev->pdev);
2659                 r = pci_enable_device(dev->pdev);
2660                 if (r)
2661                         goto unlock;
2662         }
2663         amdgpu_atombios_scratch_regs_restore(adev);
2664
2665         /* post card */
2666         if (amdgpu_need_post(adev)) {
2667                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2668                 if (r)
2669                         DRM_ERROR("amdgpu asic init failed\n");
2670         }
2671
2672         r = amdgpu_resume(adev);
2673         if (r) {
2674                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2675                 goto unlock;
2676         }
2677         amdgpu_fence_driver_resume(adev);
2678
2679         if (resume) {
2680                 r = amdgpu_ib_ring_tests(adev);
2681                 if (r)
2682                         DRM_ERROR("ib ring test failed (%d).\n", r);
2683         }
2684
2685         r = amdgpu_late_init(adev);
2686         if (r)
2687                 goto unlock;
2688
2689         /* pin cursors */
2690         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2691                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2692
2693                 if (amdgpu_crtc->cursor_bo) {
2694                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2695                         r = amdgpu_bo_reserve(aobj, true);
2696                         if (r == 0) {
2697                                 r = amdgpu_bo_pin(aobj,
2698                                                   AMDGPU_GEM_DOMAIN_VRAM,
2699                                                   &amdgpu_crtc->cursor_addr);
2700                                 if (r != 0)
2701                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2702                                 amdgpu_bo_unreserve(aobj);
2703                         }
2704                 }
2705         }
2706         r = amdgpu_amdkfd_resume(adev);
2707         if (r)
2708                 return r;
2709
2710         /* blat the mode back in */
2711         if (fbcon) {
2712                 if (!amdgpu_device_has_dc_support(adev)) {
2713                         /* pre DCE11 */
2714                         drm_helper_resume_force_mode(dev);
2715
2716                         /* turn on display hw */
2717                         drm_modeset_lock_all(dev);
2718                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2719                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2720                         }
2721                         drm_modeset_unlock_all(dev);
2722                 } else {
2723                         /*
2724                          * There is no equivalent atomic helper to turn on
2725                          * display, so we defined our own function for this,
2726                          * once suspend resume is supported by the atomic
2727                          * framework this will be reworked
2728                          */
2729                         amdgpu_dm_display_resume(adev);
2730                 }
2731         }
2732
2733         drm_kms_helper_poll_enable(dev);
2734
2735         /*
2736          * Most of the connector probing functions try to acquire runtime pm
2737          * refs to ensure that the GPU is powered on when connector polling is
2738          * performed. Since we're calling this from a runtime PM callback,
2739          * trying to acquire rpm refs will cause us to deadlock.
2740          *
2741          * Since we're guaranteed to be holding the rpm lock, it's safe to
2742          * temporarily disable the rpm helpers so this doesn't deadlock us.
2743          */
2744 #ifdef CONFIG_PM
2745         dev->dev->power.disable_depth++;
2746 #endif
2747         if (!amdgpu_device_has_dc_support(adev))
2748                 drm_helper_hpd_irq_event(dev);
2749         else
2750                 drm_kms_helper_hotplug_event(dev);
2751 #ifdef CONFIG_PM
2752         dev->dev->power.disable_depth--;
2753 #endif
2754
2755         if (fbcon)
2756                 amdgpu_fbdev_set_suspend(adev, 0);
2757
2758 unlock:
2759         if (fbcon)
2760                 console_unlock();
2761
2762         return r;
2763 }
2764
2765 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2766 {
2767         int i;
2768         bool asic_hang = false;
2769
2770         if (amdgpu_sriov_vf(adev))
2771                 return true;
2772
2773         for (i = 0; i < adev->num_ip_blocks; i++) {
2774                 if (!adev->ip_blocks[i].status.valid)
2775                         continue;
2776                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2777                         adev->ip_blocks[i].status.hang =
2778                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2779                 if (adev->ip_blocks[i].status.hang) {
2780                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2781                         asic_hang = true;
2782                 }
2783         }
2784         return asic_hang;
2785 }
2786
2787 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2788 {
2789         int i, r = 0;
2790
2791         for (i = 0; i < adev->num_ip_blocks; i++) {
2792                 if (!adev->ip_blocks[i].status.valid)
2793                         continue;
2794                 if (adev->ip_blocks[i].status.hang &&
2795                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2796                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2797                         if (r)
2798                                 return r;
2799                 }
2800         }
2801
2802         return 0;
2803 }
2804
2805 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2806 {
2807         int i;
2808
2809         for (i = 0; i < adev->num_ip_blocks; i++) {
2810                 if (!adev->ip_blocks[i].status.valid)
2811                         continue;
2812                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2813                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2814                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2815                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2816                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2817                         if (adev->ip_blocks[i].status.hang) {
2818                                 DRM_INFO("Some block need full reset!\n");
2819                                 return true;
2820                         }
2821                 }
2822         }
2823         return false;
2824 }
2825
2826 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2827 {
2828         int i, r = 0;
2829
2830         for (i = 0; i < adev->num_ip_blocks; i++) {
2831                 if (!adev->ip_blocks[i].status.valid)
2832                         continue;
2833                 if (adev->ip_blocks[i].status.hang &&
2834                     adev->ip_blocks[i].version->funcs->soft_reset) {
2835                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2836                         if (r)
2837                                 return r;
2838                 }
2839         }
2840
2841         return 0;
2842 }
2843
2844 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2845 {
2846         int i, r = 0;
2847
2848         for (i = 0; i < adev->num_ip_blocks; i++) {
2849                 if (!adev->ip_blocks[i].status.valid)
2850                         continue;
2851                 if (adev->ip_blocks[i].status.hang &&
2852                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2853                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2854                 if (r)
2855                         return r;
2856         }
2857
2858         return 0;
2859 }
2860
2861 bool amdgpu_need_backup(struct amdgpu_device *adev)
2862 {
2863         if (adev->flags & AMD_IS_APU)
2864                 return false;
2865
2866         return amdgpu_lockup_timeout > 0 ? true : false;
2867 }
2868
2869 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2870                                            struct amdgpu_ring *ring,
2871                                            struct amdgpu_bo *bo,
2872                                            struct dma_fence **fence)
2873 {
2874         uint32_t domain;
2875         int r;
2876
2877         if (!bo->shadow)
2878                 return 0;
2879
2880         r = amdgpu_bo_reserve(bo, true);
2881         if (r)
2882                 return r;
2883         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2884         /* if bo has been evicted, then no need to recover */
2885         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2886                 r = amdgpu_bo_validate(bo->shadow);
2887                 if (r) {
2888                         DRM_ERROR("bo validate failed!\n");
2889                         goto err;
2890                 }
2891
2892                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2893                                                  NULL, fence, true);
2894                 if (r) {
2895                         DRM_ERROR("recover page table failed!\n");
2896                         goto err;
2897                 }
2898         }
2899 err:
2900         amdgpu_bo_unreserve(bo);
2901         return r;
2902 }
2903
2904 /*
2905  * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
2906  *
2907  * @adev: amdgpu device pointer
2908  * @reset_flags: output param tells caller the reset result
2909  *
2910  * attempt to do soft-reset or full-reset and reinitialize Asic
2911  * return 0 means successed otherwise failed
2912 */
2913 static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
2914 {
2915         bool need_full_reset, vram_lost = 0;
2916         int r;
2917
2918         need_full_reset = amdgpu_need_full_reset(adev);
2919
2920         if (!need_full_reset) {
2921                 amdgpu_pre_soft_reset(adev);
2922                 r = amdgpu_soft_reset(adev);
2923                 amdgpu_post_soft_reset(adev);
2924                 if (r || amdgpu_check_soft_reset(adev)) {
2925                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2926                         need_full_reset = true;
2927                 }
2928
2929         }
2930
2931         if (need_full_reset) {
2932                 r = amdgpu_suspend(adev);
2933
2934 retry:
2935                 amdgpu_atombios_scratch_regs_save(adev);
2936                 r = amdgpu_asic_reset(adev);
2937                 amdgpu_atombios_scratch_regs_restore(adev);
2938                 /* post card */
2939                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2940
2941                 if (!r) {
2942                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2943                         r = amdgpu_resume_phase1(adev);
2944                         if (r)
2945                                 goto out;
2946
2947                         vram_lost = amdgpu_check_vram_lost(adev);
2948                         if (vram_lost) {
2949                                 DRM_ERROR("VRAM is lost!\n");
2950                                 atomic_inc(&adev->vram_lost_counter);
2951                         }
2952
2953                         r = amdgpu_gtt_mgr_recover(
2954                                 &adev->mman.bdev.man[TTM_PL_TT]);
2955                         if (r)
2956                                 goto out;
2957
2958                         r = amdgpu_resume_phase2(adev);
2959                         if (r)
2960                                 goto out;
2961
2962                         if (vram_lost)
2963                                 amdgpu_fill_reset_magic(adev);
2964                 }
2965         }
2966
2967 out:
2968         if (!r) {
2969                 amdgpu_irq_gpu_reset_resume_helper(adev);
2970                 r = amdgpu_ib_ring_tests(adev);
2971                 if (r) {
2972                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2973                         r = amdgpu_suspend(adev);
2974                         need_full_reset = true;
2975                         goto retry;
2976                 }
2977         }
2978
2979         if (reset_flags) {
2980                 if (vram_lost)
2981                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2982
2983                 if (need_full_reset)
2984                         (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2985         }
2986
2987         return r;
2988 }
2989
2990 /*
2991  * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
2992  *
2993  * @adev: amdgpu device pointer
2994  * @reset_flags: output param tells caller the reset result
2995  *
2996  * do VF FLR and reinitialize Asic
2997  * return 0 means successed otherwise failed
2998 */
2999 static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
3000 {
3001         int r;
3002
3003         if (from_hypervisor)
3004                 r = amdgpu_virt_request_full_gpu(adev, true);
3005         else
3006                 r = amdgpu_virt_reset_gpu(adev);
3007         if (r)
3008                 return r;
3009
3010         /* Resume IP prior to SMC */
3011         r = amdgpu_sriov_reinit_early(adev);
3012         if (r)
3013                 goto error;
3014
3015         /* we need recover gart prior to run SMC/CP/SDMA resume */
3016         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3017
3018         /* now we are okay to resume SMC/CP/SDMA */
3019         r = amdgpu_sriov_reinit_late(adev);
3020         if (r)
3021                 goto error;
3022
3023         amdgpu_irq_gpu_reset_resume_helper(adev);
3024         r = amdgpu_ib_ring_tests(adev);
3025         if (r)
3026                 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
3027
3028 error:
3029         /* release full control of GPU after ib test */
3030         amdgpu_virt_release_full_gpu(adev, true);
3031
3032         if (reset_flags) {
3033                 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3034                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
3035                         atomic_inc(&adev->vram_lost_counter);
3036                 }
3037
3038                 /* VF FLR or hotlink reset is always full-reset */
3039                 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
3040         }
3041
3042         return r;
3043 }
3044
3045 /**
3046  * amdgpu_gpu_recover - reset the asic and recover scheduler
3047  *
3048  * @adev: amdgpu device pointer
3049  * @job: which job trigger hang
3050  *
3051  * Attempt to reset the GPU if it has hung (all asics).
3052  * Returns 0 for success or an error on failure.
3053  */
3054 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
3055 {
3056         struct drm_atomic_state *state = NULL;
3057         uint64_t reset_flags = 0;
3058         int i, r, resched;
3059
3060         if (!amdgpu_check_soft_reset(adev)) {
3061                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
3062                 return 0;
3063         }
3064
3065         dev_info(adev->dev, "GPU reset begin!\n");
3066
3067         mutex_lock(&adev->lock_reset);
3068         atomic_inc(&adev->gpu_reset_counter);
3069         adev->in_gpu_reset = 1;
3070
3071         /* block TTM */
3072         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3073         /* store modesetting */
3074         if (amdgpu_device_has_dc_support(adev))
3075                 state = drm_atomic_helper_suspend(adev->ddev);
3076
3077         /* block scheduler */
3078         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3079                 struct amdgpu_ring *ring = adev->rings[i];
3080
3081                 if (!ring || !ring->sched.thread)
3082                         continue;
3083
3084                 /* only focus on the ring hit timeout if &job not NULL */
3085                 if (job && job->ring->idx != i)
3086                         continue;
3087
3088                 kthread_park(ring->sched.thread);
3089                 amd_sched_hw_job_reset(&ring->sched, &job->base);
3090
3091                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3092                 amdgpu_fence_driver_force_completion(ring);
3093         }
3094
3095         if (amdgpu_sriov_vf(adev))
3096                 r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
3097         else
3098                 r = amdgpu_reset(adev, &reset_flags);
3099
3100         if (!r) {
3101                 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
3102                         (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
3103                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3104                         struct amdgpu_bo *bo, *tmp;
3105                         struct dma_fence *fence = NULL, *next = NULL;
3106
3107                         DRM_INFO("recover vram bo from shadow\n");
3108                         mutex_lock(&adev->shadow_list_lock);
3109                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3110                                 next = NULL;
3111                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
3112                                 if (fence) {
3113                                         r = dma_fence_wait(fence, false);
3114                                         if (r) {
3115                                                 WARN(r, "recovery from shadow isn't completed\n");
3116                                                 break;
3117                                         }
3118                                 }
3119
3120                                 dma_fence_put(fence);
3121                                 fence = next;
3122                         }
3123                         mutex_unlock(&adev->shadow_list_lock);
3124                         if (fence) {
3125                                 r = dma_fence_wait(fence, false);
3126                                 if (r)
3127                                         WARN(r, "recovery from shadow isn't completed\n");
3128                         }
3129                         dma_fence_put(fence);
3130                 }
3131
3132                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3133                         struct amdgpu_ring *ring = adev->rings[i];
3134
3135                         if (!ring || !ring->sched.thread)
3136                                 continue;
3137
3138                         /* only focus on the ring hit timeout if &job not NULL */
3139                         if (job && job->ring->idx != i)
3140                                 continue;
3141
3142                         amd_sched_job_recovery(&ring->sched);
3143                         kthread_unpark(ring->sched.thread);
3144                 }
3145         } else {
3146                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3147                         struct amdgpu_ring *ring = adev->rings[i];
3148
3149                         if (!ring || !ring->sched.thread)
3150                                 continue;
3151
3152                         /* only focus on the ring hit timeout if &job not NULL */
3153                         if (job && job->ring->idx != i)
3154                                 continue;
3155
3156                         kthread_unpark(adev->rings[i]->sched.thread);
3157                 }
3158         }
3159
3160         if (amdgpu_device_has_dc_support(adev)) {
3161                 if (drm_atomic_helper_resume(adev->ddev, state))
3162                         dev_info(adev->dev, "drm resume failed:%d\n", r);
3163                 amdgpu_dm_display_resume(adev);
3164         } else {
3165                 drm_helper_resume_force_mode(adev->ddev);
3166         }
3167
3168         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3169
3170         if (r) {
3171                 /* bad news, how to tell it to userspace ? */
3172                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3173                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3174         } else {
3175                 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
3176         }
3177
3178         amdgpu_vf_error_trans_all(adev);
3179         adev->in_gpu_reset = 0;
3180         mutex_unlock(&adev->lock_reset);
3181         return r;
3182 }
3183
3184 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
3185 {
3186         u32 mask;
3187         int ret;
3188
3189         if (amdgpu_pcie_gen_cap)
3190                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3191
3192         if (amdgpu_pcie_lane_cap)
3193                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3194
3195         /* covers APUs as well */
3196         if (pci_is_root_bus(adev->pdev->bus)) {
3197                 if (adev->pm.pcie_gen_mask == 0)
3198                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3199                 if (adev->pm.pcie_mlw_mask == 0)
3200                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3201                 return;
3202         }
3203
3204         if (adev->pm.pcie_gen_mask == 0) {
3205                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
3206                 if (!ret) {
3207                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3208                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3209                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3210
3211                         if (mask & DRM_PCIE_SPEED_25)
3212                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3213                         if (mask & DRM_PCIE_SPEED_50)
3214                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
3215                         if (mask & DRM_PCIE_SPEED_80)
3216                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
3217                 } else {
3218                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3219                 }
3220         }
3221         if (adev->pm.pcie_mlw_mask == 0) {
3222                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3223                 if (!ret) {
3224                         switch (mask) {
3225                         case 32:
3226                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3227                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3228                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3229                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3230                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3231                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3232                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3233                                 break;
3234                         case 16:
3235                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3236                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3237                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3238                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3239                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3240                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3241                                 break;
3242                         case 12:
3243                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3244                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3245                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3246                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3247                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3248                                 break;
3249                         case 8:
3250                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3251                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3252                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3253                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3254                                 break;
3255                         case 4:
3256                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3257                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3258                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3259                                 break;
3260                         case 2:
3261                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3262                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3263                                 break;
3264                         case 1:
3265                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3266                                 break;
3267                         default:
3268                                 break;
3269                         }
3270                 } else {
3271                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3272                 }
3273         }
3274 }
3275
3276 /*
3277  * Debugfs
3278  */
3279 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3280                              const struct drm_info_list *files,
3281                              unsigned nfiles)
3282 {
3283         unsigned i;
3284
3285         for (i = 0; i < adev->debugfs_count; i++) {
3286                 if (adev->debugfs[i].files == files) {
3287                         /* Already registered */
3288                         return 0;
3289                 }
3290         }
3291
3292         i = adev->debugfs_count + 1;
3293         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3294                 DRM_ERROR("Reached maximum number of debugfs components.\n");
3295                 DRM_ERROR("Report so we increase "
3296                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3297                 return -EINVAL;
3298         }
3299         adev->debugfs[adev->debugfs_count].files = files;
3300         adev->debugfs[adev->debugfs_count].num_files = nfiles;
3301         adev->debugfs_count = i;
3302 #if defined(CONFIG_DEBUG_FS)
3303         drm_debugfs_create_files(files, nfiles,
3304                                  adev->ddev->primary->debugfs_root,
3305                                  adev->ddev->primary);
3306 #endif
3307         return 0;
3308 }
3309
3310 #if defined(CONFIG_DEBUG_FS)
3311
3312 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3313                                         size_t size, loff_t *pos)
3314 {
3315         struct amdgpu_device *adev = file_inode(f)->i_private;
3316         ssize_t result = 0;
3317         int r;
3318         bool pm_pg_lock, use_bank;
3319         unsigned instance_bank, sh_bank, se_bank;
3320
3321         if (size & 0x3 || *pos & 0x3)
3322                 return -EINVAL;
3323
3324         /* are we reading registers for which a PG lock is necessary? */
3325         pm_pg_lock = (*pos >> 23) & 1;
3326
3327         if (*pos & (1ULL << 62)) {
3328                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3329                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3330                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3331
3332                 if (se_bank == 0x3FF)
3333                         se_bank = 0xFFFFFFFF;
3334                 if (sh_bank == 0x3FF)
3335                         sh_bank = 0xFFFFFFFF;
3336                 if (instance_bank == 0x3FF)
3337                         instance_bank = 0xFFFFFFFF;
3338                 use_bank = 1;
3339         } else {
3340                 use_bank = 0;
3341         }
3342
3343         *pos &= (1UL << 22) - 1;
3344
3345         if (use_bank) {
3346                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3347                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3348                         return -EINVAL;
3349                 mutex_lock(&adev->grbm_idx_mutex);
3350                 amdgpu_gfx_select_se_sh(adev, se_bank,
3351                                         sh_bank, instance_bank);
3352         }
3353
3354         if (pm_pg_lock)
3355                 mutex_lock(&adev->pm.mutex);
3356
3357         while (size) {
3358                 uint32_t value;
3359
3360                 if (*pos > adev->rmmio_size)
3361                         goto end;
3362
3363                 value = RREG32(*pos >> 2);
3364                 r = put_user(value, (uint32_t *)buf);
3365                 if (r) {
3366                         result = r;
3367                         goto end;
3368                 }
3369
3370                 result += 4;
3371                 buf += 4;
3372                 *pos += 4;
3373                 size -= 4;
3374         }
3375
3376 end:
3377         if (use_bank) {
3378                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3379                 mutex_unlock(&adev->grbm_idx_mutex);
3380         }
3381
3382         if (pm_pg_lock)
3383                 mutex_unlock(&adev->pm.mutex);
3384
3385         return result;
3386 }
3387
3388 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3389                                          size_t size, loff_t *pos)
3390 {
3391         struct amdgpu_device *adev = file_inode(f)->i_private;
3392         ssize_t result = 0;
3393         int r;
3394         bool pm_pg_lock, use_bank;
3395         unsigned instance_bank, sh_bank, se_bank;
3396
3397         if (size & 0x3 || *pos & 0x3)
3398                 return -EINVAL;
3399
3400         /* are we reading registers for which a PG lock is necessary? */
3401         pm_pg_lock = (*pos >> 23) & 1;
3402
3403         if (*pos & (1ULL << 62)) {
3404                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3405                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3406                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3407
3408                 if (se_bank == 0x3FF)
3409                         se_bank = 0xFFFFFFFF;
3410                 if (sh_bank == 0x3FF)
3411                         sh_bank = 0xFFFFFFFF;
3412                 if (instance_bank == 0x3FF)
3413                         instance_bank = 0xFFFFFFFF;
3414                 use_bank = 1;
3415         } else {
3416                 use_bank = 0;
3417         }
3418
3419         *pos &= (1UL << 22) - 1;
3420
3421         if (use_bank) {
3422                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3423                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3424                         return -EINVAL;
3425                 mutex_lock(&adev->grbm_idx_mutex);
3426                 amdgpu_gfx_select_se_sh(adev, se_bank,
3427                                         sh_bank, instance_bank);
3428         }
3429
3430         if (pm_pg_lock)
3431                 mutex_lock(&adev->pm.mutex);
3432
3433         while (size) {
3434                 uint32_t value;
3435
3436                 if (*pos > adev->rmmio_size)
3437                         return result;
3438
3439                 r = get_user(value, (uint32_t *)buf);
3440                 if (r)
3441                         return r;
3442
3443                 WREG32(*pos >> 2, value);
3444
3445                 result += 4;
3446                 buf += 4;
3447                 *pos += 4;
3448                 size -= 4;
3449         }
3450
3451         if (use_bank) {
3452                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3453                 mutex_unlock(&adev->grbm_idx_mutex);
3454         }
3455
3456         if (pm_pg_lock)
3457                 mutex_unlock(&adev->pm.mutex);
3458
3459         return result;
3460 }
3461
3462 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3463                                         size_t size, loff_t *pos)
3464 {
3465         struct amdgpu_device *adev = file_inode(f)->i_private;
3466         ssize_t result = 0;
3467         int r;
3468
3469         if (size & 0x3 || *pos & 0x3)
3470                 return -EINVAL;
3471
3472         while (size) {
3473                 uint32_t value;
3474
3475                 value = RREG32_PCIE(*pos >> 2);
3476                 r = put_user(value, (uint32_t *)buf);
3477                 if (r)
3478                         return r;
3479
3480                 result += 4;
3481                 buf += 4;
3482                 *pos += 4;
3483                 size -= 4;
3484         }
3485
3486         return result;
3487 }
3488
3489 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3490                                          size_t size, loff_t *pos)
3491 {
3492         struct amdgpu_device *adev = file_inode(f)->i_private;
3493         ssize_t result = 0;
3494         int r;
3495
3496         if (size & 0x3 || *pos & 0x3)
3497                 return -EINVAL;
3498
3499         while (size) {
3500                 uint32_t value;
3501
3502                 r = get_user(value, (uint32_t *)buf);
3503                 if (r)
3504                         return r;
3505
3506                 WREG32_PCIE(*pos >> 2, value);
3507
3508                 result += 4;
3509                 buf += 4;
3510                 *pos += 4;
3511                 size -= 4;
3512         }
3513
3514         return result;
3515 }
3516
3517 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3518                                         size_t size, loff_t *pos)
3519 {
3520         struct amdgpu_device *adev = file_inode(f)->i_private;
3521         ssize_t result = 0;
3522         int r;
3523
3524         if (size & 0x3 || *pos & 0x3)
3525                 return -EINVAL;
3526
3527         while (size) {
3528                 uint32_t value;
3529
3530                 value = RREG32_DIDT(*pos >> 2);
3531                 r = put_user(value, (uint32_t *)buf);
3532                 if (r)
3533                         return r;
3534
3535                 result += 4;
3536                 buf += 4;
3537                 *pos += 4;
3538                 size -= 4;
3539         }
3540
3541         return result;
3542 }
3543
3544 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3545                                          size_t size, loff_t *pos)
3546 {
3547         struct amdgpu_device *adev = file_inode(f)->i_private;
3548         ssize_t result = 0;
3549         int r;
3550
3551         if (size & 0x3 || *pos & 0x3)
3552                 return -EINVAL;
3553
3554         while (size) {
3555                 uint32_t value;
3556
3557                 r = get_user(value, (uint32_t *)buf);
3558                 if (r)
3559                         return r;
3560
3561                 WREG32_DIDT(*pos >> 2, value);
3562
3563                 result += 4;
3564                 buf += 4;
3565                 *pos += 4;
3566                 size -= 4;
3567         }
3568
3569         return result;
3570 }
3571
3572 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3573                                         size_t size, loff_t *pos)
3574 {
3575         struct amdgpu_device *adev = file_inode(f)->i_private;
3576         ssize_t result = 0;
3577         int r;
3578
3579         if (size & 0x3 || *pos & 0x3)
3580                 return -EINVAL;
3581
3582         while (size) {
3583                 uint32_t value;
3584
3585                 value = RREG32_SMC(*pos);
3586                 r = put_user(value, (uint32_t *)buf);
3587                 if (r)
3588                         return r;
3589
3590                 result += 4;
3591                 buf += 4;
3592                 *pos += 4;
3593                 size -= 4;
3594         }
3595
3596         return result;
3597 }
3598
3599 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3600                                          size_t size, loff_t *pos)
3601 {
3602         struct amdgpu_device *adev = file_inode(f)->i_private;
3603         ssize_t result = 0;
3604         int r;
3605
3606         if (size & 0x3 || *pos & 0x3)
3607                 return -EINVAL;
3608
3609         while (size) {
3610                 uint32_t value;
3611
3612                 r = get_user(value, (uint32_t *)buf);
3613                 if (r)
3614                         return r;
3615
3616                 WREG32_SMC(*pos, value);
3617
3618                 result += 4;
3619                 buf += 4;
3620                 *pos += 4;
3621                 size -= 4;
3622         }
3623
3624         return result;
3625 }
3626
3627 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3628                                         size_t size, loff_t *pos)
3629 {
3630         struct amdgpu_device *adev = file_inode(f)->i_private;
3631         ssize_t result = 0;
3632         int r;
3633         uint32_t *config, no_regs = 0;
3634
3635         if (size & 0x3 || *pos & 0x3)
3636                 return -EINVAL;
3637
3638         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3639         if (!config)
3640                 return -ENOMEM;
3641
3642         /* version, increment each time something is added */
3643         config[no_regs++] = 3;
3644         config[no_regs++] = adev->gfx.config.max_shader_engines;
3645         config[no_regs++] = adev->gfx.config.max_tile_pipes;
3646         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3647         config[no_regs++] = adev->gfx.config.max_sh_per_se;
3648         config[no_regs++] = adev->gfx.config.max_backends_per_se;
3649         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3650         config[no_regs++] = adev->gfx.config.max_gprs;
3651         config[no_regs++] = adev->gfx.config.max_gs_threads;
3652         config[no_regs++] = adev->gfx.config.max_hw_contexts;
3653         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3654         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3655         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3656         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3657         config[no_regs++] = adev->gfx.config.num_tile_pipes;
3658         config[no_regs++] = adev->gfx.config.backend_enable_mask;
3659         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3660         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3661         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3662         config[no_regs++] = adev->gfx.config.num_gpus;
3663         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3664         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3665         config[no_regs++] = adev->gfx.config.gb_addr_config;
3666         config[no_regs++] = adev->gfx.config.num_rbs;
3667
3668         /* rev==1 */
3669         config[no_regs++] = adev->rev_id;
3670         config[no_regs++] = adev->pg_flags;
3671         config[no_regs++] = adev->cg_flags;
3672
3673         /* rev==2 */
3674         config[no_regs++] = adev->family;
3675         config[no_regs++] = adev->external_rev_id;
3676
3677         /* rev==3 */
3678         config[no_regs++] = adev->pdev->device;
3679         config[no_regs++] = adev->pdev->revision;
3680         config[no_regs++] = adev->pdev->subsystem_device;
3681         config[no_regs++] = adev->pdev->subsystem_vendor;
3682
3683         while (size && (*pos < no_regs * 4)) {
3684                 uint32_t value;
3685
3686                 value = config[*pos >> 2];
3687                 r = put_user(value, (uint32_t *)buf);
3688                 if (r) {
3689                         kfree(config);
3690                         return r;
3691                 }
3692
3693                 result += 4;
3694                 buf += 4;
3695                 *pos += 4;
3696                 size -= 4;
3697         }
3698
3699         kfree(config);
3700         return result;
3701 }
3702
3703 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3704                                         size_t size, loff_t *pos)
3705 {
3706         struct amdgpu_device *adev = file_inode(f)->i_private;
3707         int idx, x, outsize, r, valuesize;
3708         uint32_t values[16];
3709
3710         if (size & 3 || *pos & 0x3)
3711                 return -EINVAL;
3712
3713         if (amdgpu_dpm == 0)
3714                 return -EINVAL;
3715
3716         /* convert offset to sensor number */
3717         idx = *pos >> 2;
3718
3719         valuesize = sizeof(values);
3720         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3721                 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
3722         else
3723                 return -EINVAL;
3724
3725         if (size > valuesize)
3726                 return -EINVAL;
3727
3728         outsize = 0;
3729         x = 0;
3730         if (!r) {
3731                 while (size) {
3732                         r = put_user(values[x++], (int32_t *)buf);
3733                         buf += 4;
3734                         size -= 4;
3735                         outsize += 4;
3736                 }
3737         }
3738
3739         return !r ? outsize : r;
3740 }
3741
3742 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3743                                         size_t size, loff_t *pos)
3744 {
3745         struct amdgpu_device *adev = f->f_inode->i_private;
3746         int r, x;
3747         ssize_t result=0;
3748         uint32_t offset, se, sh, cu, wave, simd, data[32];
3749
3750         if (size & 3 || *pos & 3)
3751                 return -EINVAL;
3752
3753         /* decode offset */
3754         offset = (*pos & GENMASK_ULL(6, 0));
3755         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
3756         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
3757         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
3758         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
3759         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3760
3761         /* switch to the specific se/sh/cu */
3762         mutex_lock(&adev->grbm_idx_mutex);
3763         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3764
3765         x = 0;
3766         if (adev->gfx.funcs->read_wave_data)
3767                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3768
3769         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3770         mutex_unlock(&adev->grbm_idx_mutex);
3771
3772         if (!x)
3773                 return -EINVAL;
3774
3775         while (size && (offset < x * 4)) {
3776                 uint32_t value;
3777
3778                 value = data[offset >> 2];
3779                 r = put_user(value, (uint32_t *)buf);
3780                 if (r)
3781                         return r;
3782
3783                 result += 4;
3784                 buf += 4;
3785                 offset += 4;
3786                 size -= 4;
3787         }
3788
3789         return result;
3790 }
3791
3792 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3793                                         size_t size, loff_t *pos)
3794 {
3795         struct amdgpu_device *adev = f->f_inode->i_private;
3796         int r;
3797         ssize_t result = 0;
3798         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3799
3800         if (size & 3 || *pos & 3)
3801                 return -EINVAL;
3802
3803         /* decode offset */
3804         offset = *pos & GENMASK_ULL(11, 0);
3805         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3806         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3807         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3808         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3809         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3810         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3811         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3812
3813         data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3814         if (!data)
3815                 return -ENOMEM;
3816
3817         /* switch to the specific se/sh/cu */
3818         mutex_lock(&adev->grbm_idx_mutex);
3819         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3820
3821         if (bank == 0) {
3822                 if (adev->gfx.funcs->read_wave_vgprs)
3823                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3824         } else {
3825                 if (adev->gfx.funcs->read_wave_sgprs)
3826                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3827         }
3828
3829         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3830         mutex_unlock(&adev->grbm_idx_mutex);
3831
3832         while (size) {
3833                 uint32_t value;
3834
3835                 value = data[offset++];
3836                 r = put_user(value, (uint32_t *)buf);
3837                 if (r) {
3838                         result = r;
3839                         goto err;
3840                 }
3841
3842                 result += 4;
3843                 buf += 4;
3844                 size -= 4;
3845         }
3846
3847 err:
3848         kfree(data);
3849         return result;
3850 }
3851
3852 static const struct file_operations amdgpu_debugfs_regs_fops = {
3853         .owner = THIS_MODULE,
3854         .read = amdgpu_debugfs_regs_read,
3855         .write = amdgpu_debugfs_regs_write,
3856         .llseek = default_llseek
3857 };
3858 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3859         .owner = THIS_MODULE,
3860         .read = amdgpu_debugfs_regs_didt_read,
3861         .write = amdgpu_debugfs_regs_didt_write,
3862         .llseek = default_llseek
3863 };
3864 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3865         .owner = THIS_MODULE,
3866         .read = amdgpu_debugfs_regs_pcie_read,
3867         .write = amdgpu_debugfs_regs_pcie_write,
3868         .llseek = default_llseek
3869 };
3870 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3871         .owner = THIS_MODULE,
3872         .read = amdgpu_debugfs_regs_smc_read,
3873         .write = amdgpu_debugfs_regs_smc_write,
3874         .llseek = default_llseek
3875 };
3876
3877 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3878         .owner = THIS_MODULE,
3879         .read = amdgpu_debugfs_gca_config_read,
3880         .llseek = default_llseek
3881 };
3882
3883 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3884         .owner = THIS_MODULE,
3885         .read = amdgpu_debugfs_sensor_read,
3886         .llseek = default_llseek
3887 };
3888
3889 static const struct file_operations amdgpu_debugfs_wave_fops = {
3890         .owner = THIS_MODULE,
3891         .read = amdgpu_debugfs_wave_read,
3892         .llseek = default_llseek
3893 };
3894 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3895         .owner = THIS_MODULE,
3896         .read = amdgpu_debugfs_gpr_read,
3897         .llseek = default_llseek
3898 };
3899
3900 static const struct file_operations *debugfs_regs[] = {
3901         &amdgpu_debugfs_regs_fops,
3902         &amdgpu_debugfs_regs_didt_fops,
3903         &amdgpu_debugfs_regs_pcie_fops,
3904         &amdgpu_debugfs_regs_smc_fops,
3905         &amdgpu_debugfs_gca_config_fops,
3906         &amdgpu_debugfs_sensors_fops,
3907         &amdgpu_debugfs_wave_fops,
3908         &amdgpu_debugfs_gpr_fops,
3909 };
3910
3911 static const char *debugfs_regs_names[] = {
3912         "amdgpu_regs",
3913         "amdgpu_regs_didt",
3914         "amdgpu_regs_pcie",
3915         "amdgpu_regs_smc",
3916         "amdgpu_gca_config",
3917         "amdgpu_sensors",
3918         "amdgpu_wave",
3919         "amdgpu_gpr",
3920 };
3921
3922 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3923 {
3924         struct drm_minor *minor = adev->ddev->primary;
3925         struct dentry *ent, *root = minor->debugfs_root;
3926         unsigned i, j;
3927
3928         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3929                 ent = debugfs_create_file(debugfs_regs_names[i],
3930                                           S_IFREG | S_IRUGO, root,
3931                                           adev, debugfs_regs[i]);
3932                 if (IS_ERR(ent)) {
3933                         for (j = 0; j < i; j++) {
3934                                 debugfs_remove(adev->debugfs_regs[i]);
3935                                 adev->debugfs_regs[i] = NULL;
3936                         }
3937                         return PTR_ERR(ent);
3938                 }
3939
3940                 if (!i)
3941                         i_size_write(ent->d_inode, adev->rmmio_size);
3942                 adev->debugfs_regs[i] = ent;
3943         }
3944
3945         return 0;
3946 }
3947
3948 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3949 {
3950         unsigned i;
3951
3952         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3953                 if (adev->debugfs_regs[i]) {
3954                         debugfs_remove(adev->debugfs_regs[i]);
3955                         adev->debugfs_regs[i] = NULL;
3956                 }
3957         }
3958 }
3959
3960 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3961 {
3962         struct drm_info_node *node = (struct drm_info_node *) m->private;
3963         struct drm_device *dev = node->minor->dev;
3964         struct amdgpu_device *adev = dev->dev_private;
3965         int r = 0, i;
3966
3967         /* hold on the scheduler */
3968         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3969                 struct amdgpu_ring *ring = adev->rings[i];
3970
3971                 if (!ring || !ring->sched.thread)
3972                         continue;
3973                 kthread_park(ring->sched.thread);
3974         }
3975
3976         seq_printf(m, "run ib test:\n");
3977         r = amdgpu_ib_ring_tests(adev);
3978         if (r)
3979                 seq_printf(m, "ib ring tests failed (%d).\n", r);
3980         else
3981                 seq_printf(m, "ib ring tests passed.\n");
3982
3983         /* go on the scheduler */
3984         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3985                 struct amdgpu_ring *ring = adev->rings[i];
3986
3987                 if (!ring || !ring->sched.thread)
3988                         continue;
3989                 kthread_unpark(ring->sched.thread);
3990         }
3991
3992         return 0;
3993 }
3994
3995 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
3996         {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
3997 };
3998
3999 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
4000 {
4001         return amdgpu_debugfs_add_files(adev,
4002                                         amdgpu_debugfs_test_ib_ring_list, 1);
4003 }
4004
4005 int amdgpu_debugfs_init(struct drm_minor *minor)
4006 {
4007         return 0;
4008 }
4009
4010 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
4011 {
4012         struct drm_info_node *node = (struct drm_info_node *) m->private;
4013         struct drm_device *dev = node->minor->dev;
4014         struct amdgpu_device *adev = dev->dev_private;
4015
4016         seq_write(m, adev->bios, adev->bios_size);
4017         return 0;
4018 }
4019
4020 static const struct drm_info_list amdgpu_vbios_dump_list[] = {
4021                 {"amdgpu_vbios",
4022                  amdgpu_debugfs_get_vbios_dump,
4023                  0, NULL},
4024 };
4025
4026 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4027 {
4028         return amdgpu_debugfs_add_files(adev,
4029                                         amdgpu_vbios_dump_list, 1);
4030 }
4031 #else
4032 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
4033 {
4034         return 0;
4035 }
4036 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
4037 {
4038         return 0;
4039 }
4040 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4041 {
4042         return 0;
4043 }
4044 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
4045 #endif