2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/devcoredump.h>
36 #include <generated/utsrelease.h>
37 #include <linux/pci-p2pdma.h>
39 #include <drm/drm_aperture.h>
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_fb_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/amdgpu_drm.h>
45 #include <linux/vgaarb.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/efi.h>
49 #include "amdgpu_trace.h"
50 #include "amdgpu_i2c.h"
52 #include "amdgpu_atombios.h"
53 #include "amdgpu_atomfirmware.h"
55 #ifdef CONFIG_DRM_AMDGPU_SI
58 #ifdef CONFIG_DRM_AMDGPU_CIK
64 #include "bif/bif_4_1_d.h"
65 #include <linux/firmware.h>
66 #include "amdgpu_vf_error.h"
68 #include "amdgpu_amdkfd.h"
69 #include "amdgpu_pm.h"
71 #include "amdgpu_xgmi.h"
72 #include "amdgpu_ras.h"
73 #include "amdgpu_pmu.h"
74 #include "amdgpu_fru_eeprom.h"
75 #include "amdgpu_reset.h"
77 #include <linux/suspend.h>
78 #include <drm/task_barrier.h>
79 #include <linux/pm_runtime.h>
81 #include <drm/drm_drv.h>
83 #if IS_ENABLED(CONFIG_X86)
84 #include <asm/intel-family.h>
87 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
88 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
95 #define AMDGPU_RESUME_MS 2000
96 #define AMDGPU_MAX_RETRY_LIMIT 2
97 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
99 static const struct drm_driver amdgpu_kms_driver;
101 const char *amdgpu_asic_name[] = {
143 * DOC: pcie_replay_count
145 * The amdgpu driver provides a sysfs API for reporting the total number
146 * of PCIe replays (NAKs)
147 * The file pcie_replay_count is used for this and returns the total
148 * number of replays as a sum of the NAKs generated and NAKs received
151 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
152 struct device_attribute *attr, char *buf)
154 struct drm_device *ddev = dev_get_drvdata(dev);
155 struct amdgpu_device *adev = drm_to_adev(ddev);
156 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
158 return sysfs_emit(buf, "%llu\n", cnt);
161 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
162 amdgpu_device_get_pcie_replay_count, NULL);
164 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
169 * The amdgpu driver provides a sysfs API for reporting the product name
171 * The file product_name is used for this and returns the product name
172 * as returned from the FRU.
173 * NOTE: This is only available for certain server cards
176 static ssize_t amdgpu_device_get_product_name(struct device *dev,
177 struct device_attribute *attr, char *buf)
179 struct drm_device *ddev = dev_get_drvdata(dev);
180 struct amdgpu_device *adev = drm_to_adev(ddev);
182 return sysfs_emit(buf, "%s\n", adev->product_name);
185 static DEVICE_ATTR(product_name, S_IRUGO,
186 amdgpu_device_get_product_name, NULL);
189 * DOC: product_number
191 * The amdgpu driver provides a sysfs API for reporting the part number
193 * The file product_number is used for this and returns the part number
194 * as returned from the FRU.
195 * NOTE: This is only available for certain server cards
198 static ssize_t amdgpu_device_get_product_number(struct device *dev,
199 struct device_attribute *attr, char *buf)
201 struct drm_device *ddev = dev_get_drvdata(dev);
202 struct amdgpu_device *adev = drm_to_adev(ddev);
204 return sysfs_emit(buf, "%s\n", adev->product_number);
207 static DEVICE_ATTR(product_number, S_IRUGO,
208 amdgpu_device_get_product_number, NULL);
213 * The amdgpu driver provides a sysfs API for reporting the serial number
215 * The file serial_number is used for this and returns the serial number
216 * as returned from the FRU.
217 * NOTE: This is only available for certain server cards
220 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
221 struct device_attribute *attr, char *buf)
223 struct drm_device *ddev = dev_get_drvdata(dev);
224 struct amdgpu_device *adev = drm_to_adev(ddev);
226 return sysfs_emit(buf, "%s\n", adev->serial);
229 static DEVICE_ATTR(serial_number, S_IRUGO,
230 amdgpu_device_get_serial_number, NULL);
233 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
235 * @dev: drm_device pointer
237 * Returns true if the device is a dGPU with ATPX power control,
238 * otherwise return false.
240 bool amdgpu_device_supports_px(struct drm_device *dev)
242 struct amdgpu_device *adev = drm_to_adev(dev);
244 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
250 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
252 * @dev: drm_device pointer
254 * Returns true if the device is a dGPU with ACPI power control,
255 * otherwise return false.
257 bool amdgpu_device_supports_boco(struct drm_device *dev)
259 struct amdgpu_device *adev = drm_to_adev(dev);
262 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
268 * amdgpu_device_supports_baco - Does the device support BACO
270 * @dev: drm_device pointer
272 * Returns true if the device supporte BACO,
273 * otherwise return false.
275 bool amdgpu_device_supports_baco(struct drm_device *dev)
277 struct amdgpu_device *adev = drm_to_adev(dev);
279 return amdgpu_asic_supports_baco(adev);
283 * amdgpu_device_supports_smart_shift - Is the device dGPU with
284 * smart shift support
286 * @dev: drm_device pointer
288 * Returns true if the device is a dGPU with Smart Shift support,
289 * otherwise returns false.
291 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
293 return (amdgpu_device_supports_boco(dev) &&
294 amdgpu_acpi_is_power_shift_control_supported());
298 * VRAM access helper functions
302 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
304 * @adev: amdgpu_device pointer
305 * @pos: offset of the buffer in vram
306 * @buf: virtual address of the buffer in system memory
307 * @size: read/write size, sizeof(@buf) must > @size
308 * @write: true - write to vram, otherwise - read from vram
310 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
311 void *buf, size_t size, bool write)
314 uint32_t hi = ~0, tmp = 0;
315 uint32_t *data = buf;
319 if (!drm_dev_enter(adev_to_drm(adev), &idx))
322 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
324 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
325 for (last = pos + size; pos < last; pos += 4) {
328 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
330 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
334 WREG32_NO_KIQ(mmMM_DATA, *data++);
336 *data++ = RREG32_NO_KIQ(mmMM_DATA);
339 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
344 * amdgpu_device_aper_access - access vram by vram aperature
346 * @adev: amdgpu_device pointer
347 * @pos: offset of the buffer in vram
348 * @buf: virtual address of the buffer in system memory
349 * @size: read/write size, sizeof(@buf) must > @size
350 * @write: true - write to vram, otherwise - read from vram
352 * The return value means how many bytes have been transferred.
354 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
355 void *buf, size_t size, bool write)
362 if (!adev->mman.aper_base_kaddr)
365 last = min(pos + size, adev->gmc.visible_vram_size);
367 addr = adev->mman.aper_base_kaddr + pos;
371 memcpy_toio(addr, buf, count);
373 amdgpu_device_flush_hdp(adev, NULL);
375 amdgpu_device_invalidate_hdp(adev, NULL);
377 memcpy_fromio(buf, addr, count);
389 * amdgpu_device_vram_access - read/write a buffer in vram
391 * @adev: amdgpu_device pointer
392 * @pos: offset of the buffer in vram
393 * @buf: virtual address of the buffer in system memory
394 * @size: read/write size, sizeof(@buf) must > @size
395 * @write: true - write to vram, otherwise - read from vram
397 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
398 void *buf, size_t size, bool write)
402 /* try to using vram apreature to access vram first */
403 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
406 /* using MM to access rest vram */
409 amdgpu_device_mm_access(adev, pos, buf, size, write);
414 * register access helper functions.
417 /* Check if hw access should be skipped because of hotplug or device error */
418 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
420 if (adev->no_hw_access)
423 #ifdef CONFIG_LOCKDEP
425 * This is a bit complicated to understand, so worth a comment. What we assert
426 * here is that the GPU reset is not running on another thread in parallel.
428 * For this we trylock the read side of the reset semaphore, if that succeeds
429 * we know that the reset is not running in paralell.
431 * If the trylock fails we assert that we are either already holding the read
432 * side of the lock or are the reset thread itself and hold the write side of
436 if (down_read_trylock(&adev->reset_domain->sem))
437 up_read(&adev->reset_domain->sem);
439 lockdep_assert_held(&adev->reset_domain->sem);
446 * amdgpu_device_rreg - read a memory mapped IO or indirect register
448 * @adev: amdgpu_device pointer
449 * @reg: dword aligned register offset
450 * @acc_flags: access flags which require special behavior
452 * Returns the 32 bit value from the offset specified.
454 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
455 uint32_t reg, uint32_t acc_flags)
459 if (amdgpu_device_skip_hw_access(adev))
462 if ((reg * 4) < adev->rmmio_size) {
463 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
464 amdgpu_sriov_runtime(adev) &&
465 down_read_trylock(&adev->reset_domain->sem)) {
466 ret = amdgpu_kiq_rreg(adev, reg);
467 up_read(&adev->reset_domain->sem);
469 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
472 ret = adev->pcie_rreg(adev, reg * 4);
475 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
481 * MMIO register read with bytes helper functions
482 * @offset:bytes offset from MMIO start
487 * amdgpu_mm_rreg8 - read a memory mapped IO register
489 * @adev: amdgpu_device pointer
490 * @offset: byte aligned register offset
492 * Returns the 8 bit value from the offset specified.
494 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
496 if (amdgpu_device_skip_hw_access(adev))
499 if (offset < adev->rmmio_size)
500 return (readb(adev->rmmio + offset));
505 * MMIO register write with bytes helper functions
506 * @offset:bytes offset from MMIO start
507 * @value: the value want to be written to the register
511 * amdgpu_mm_wreg8 - read a memory mapped IO register
513 * @adev: amdgpu_device pointer
514 * @offset: byte aligned register offset
515 * @value: 8 bit value to write
517 * Writes the value specified to the offset specified.
519 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
521 if (amdgpu_device_skip_hw_access(adev))
524 if (offset < adev->rmmio_size)
525 writeb(value, adev->rmmio + offset);
531 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
533 * @adev: amdgpu_device pointer
534 * @reg: dword aligned register offset
535 * @v: 32 bit value to write to the register
536 * @acc_flags: access flags which require special behavior
538 * Writes the value specified to the offset specified.
540 void amdgpu_device_wreg(struct amdgpu_device *adev,
541 uint32_t reg, uint32_t v,
544 if (amdgpu_device_skip_hw_access(adev))
547 if ((reg * 4) < adev->rmmio_size) {
548 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
549 amdgpu_sriov_runtime(adev) &&
550 down_read_trylock(&adev->reset_domain->sem)) {
551 amdgpu_kiq_wreg(adev, reg, v);
552 up_read(&adev->reset_domain->sem);
554 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
557 adev->pcie_wreg(adev, reg * 4, v);
560 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
564 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
566 * @adev: amdgpu_device pointer
567 * @reg: mmio/rlc register
570 * this function is invoked only for the debugfs register access
572 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
573 uint32_t reg, uint32_t v)
575 if (amdgpu_device_skip_hw_access(adev))
578 if (amdgpu_sriov_fullaccess(adev) &&
579 adev->gfx.rlc.funcs &&
580 adev->gfx.rlc.funcs->is_rlcg_access_range) {
581 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
582 return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
583 } else if ((reg * 4) >= adev->rmmio_size) {
584 adev->pcie_wreg(adev, reg * 4, v);
586 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
591 * amdgpu_mm_rdoorbell - read a doorbell dword
593 * @adev: amdgpu_device pointer
594 * @index: doorbell index
596 * Returns the value in the doorbell aperture at the
597 * requested doorbell index (CIK).
599 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
601 if (amdgpu_device_skip_hw_access(adev))
604 if (index < adev->doorbell.num_doorbells) {
605 return readl(adev->doorbell.ptr + index);
607 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
613 * amdgpu_mm_wdoorbell - write a doorbell dword
615 * @adev: amdgpu_device pointer
616 * @index: doorbell index
619 * Writes @v to the doorbell aperture at the
620 * requested doorbell index (CIK).
622 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
624 if (amdgpu_device_skip_hw_access(adev))
627 if (index < adev->doorbell.num_doorbells) {
628 writel(v, adev->doorbell.ptr + index);
630 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
635 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
637 * @adev: amdgpu_device pointer
638 * @index: doorbell index
640 * Returns the value in the doorbell aperture at the
641 * requested doorbell index (VEGA10+).
643 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
645 if (amdgpu_device_skip_hw_access(adev))
648 if (index < adev->doorbell.num_doorbells) {
649 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
651 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
657 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
659 * @adev: amdgpu_device pointer
660 * @index: doorbell index
663 * Writes @v to the doorbell aperture at the
664 * requested doorbell index (VEGA10+).
666 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
668 if (amdgpu_device_skip_hw_access(adev))
671 if (index < adev->doorbell.num_doorbells) {
672 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
674 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
679 * amdgpu_device_indirect_rreg - read an indirect register
681 * @adev: amdgpu_device pointer
682 * @pcie_index: mmio register offset
683 * @pcie_data: mmio register offset
684 * @reg_addr: indirect register address to read from
686 * Returns the value of indirect register @reg_addr
688 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
689 u32 pcie_index, u32 pcie_data,
694 void __iomem *pcie_index_offset;
695 void __iomem *pcie_data_offset;
697 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
698 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
699 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
701 writel(reg_addr, pcie_index_offset);
702 readl(pcie_index_offset);
703 r = readl(pcie_data_offset);
704 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
710 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
712 * @adev: amdgpu_device pointer
713 * @pcie_index: mmio register offset
714 * @pcie_data: mmio register offset
715 * @reg_addr: indirect register address to read from
717 * Returns the value of indirect register @reg_addr
719 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
720 u32 pcie_index, u32 pcie_data,
725 void __iomem *pcie_index_offset;
726 void __iomem *pcie_data_offset;
728 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
729 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
730 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
732 /* read low 32 bits */
733 writel(reg_addr, pcie_index_offset);
734 readl(pcie_index_offset);
735 r = readl(pcie_data_offset);
736 /* read high 32 bits */
737 writel(reg_addr + 4, pcie_index_offset);
738 readl(pcie_index_offset);
739 r |= ((u64)readl(pcie_data_offset) << 32);
740 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
746 * amdgpu_device_indirect_wreg - write an indirect register address
748 * @adev: amdgpu_device pointer
749 * @pcie_index: mmio register offset
750 * @pcie_data: mmio register offset
751 * @reg_addr: indirect register offset
752 * @reg_data: indirect register data
755 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
756 u32 pcie_index, u32 pcie_data,
757 u32 reg_addr, u32 reg_data)
760 void __iomem *pcie_index_offset;
761 void __iomem *pcie_data_offset;
763 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
764 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
765 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
767 writel(reg_addr, pcie_index_offset);
768 readl(pcie_index_offset);
769 writel(reg_data, pcie_data_offset);
770 readl(pcie_data_offset);
771 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
775 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
777 * @adev: amdgpu_device pointer
778 * @pcie_index: mmio register offset
779 * @pcie_data: mmio register offset
780 * @reg_addr: indirect register offset
781 * @reg_data: indirect register data
784 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
785 u32 pcie_index, u32 pcie_data,
786 u32 reg_addr, u64 reg_data)
789 void __iomem *pcie_index_offset;
790 void __iomem *pcie_data_offset;
792 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
793 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
794 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
796 /* write low 32 bits */
797 writel(reg_addr, pcie_index_offset);
798 readl(pcie_index_offset);
799 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
800 readl(pcie_data_offset);
801 /* write high 32 bits */
802 writel(reg_addr + 4, pcie_index_offset);
803 readl(pcie_index_offset);
804 writel((u32)(reg_data >> 32), pcie_data_offset);
805 readl(pcie_data_offset);
806 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
810 * amdgpu_invalid_rreg - dummy reg read function
812 * @adev: amdgpu_device pointer
813 * @reg: offset of register
815 * Dummy register read function. Used for register blocks
816 * that certain asics don't have (all asics).
817 * Returns the value in the register.
819 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
821 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
827 * amdgpu_invalid_wreg - dummy reg write function
829 * @adev: amdgpu_device pointer
830 * @reg: offset of register
831 * @v: value to write to the register
833 * Dummy register read function. Used for register blocks
834 * that certain asics don't have (all asics).
836 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
838 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
844 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
846 * @adev: amdgpu_device pointer
847 * @reg: offset of register
849 * Dummy register read function. Used for register blocks
850 * that certain asics don't have (all asics).
851 * Returns the value in the register.
853 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
855 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
861 * amdgpu_invalid_wreg64 - dummy reg write function
863 * @adev: amdgpu_device pointer
864 * @reg: offset of register
865 * @v: value to write to the register
867 * Dummy register read function. Used for register blocks
868 * that certain asics don't have (all asics).
870 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
872 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
878 * amdgpu_block_invalid_rreg - dummy reg read function
880 * @adev: amdgpu_device pointer
881 * @block: offset of instance
882 * @reg: offset of register
884 * Dummy register read function. Used for register blocks
885 * that certain asics don't have (all asics).
886 * Returns the value in the register.
888 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
889 uint32_t block, uint32_t reg)
891 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
898 * amdgpu_block_invalid_wreg - dummy reg write function
900 * @adev: amdgpu_device pointer
901 * @block: offset of instance
902 * @reg: offset of register
903 * @v: value to write to the register
905 * Dummy register read function. Used for register blocks
906 * that certain asics don't have (all asics).
908 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
910 uint32_t reg, uint32_t v)
912 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
918 * amdgpu_device_asic_init - Wrapper for atom asic_init
920 * @adev: amdgpu_device pointer
922 * Does any asic specific work and then calls atom asic init.
924 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
926 amdgpu_asic_pre_asic_init(adev);
928 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
929 return amdgpu_atomfirmware_asic_init(adev, true);
931 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
935 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
937 * @adev: amdgpu_device pointer
939 * Allocates a scratch page of VRAM for use by various things in the
942 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
944 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
945 AMDGPU_GEM_DOMAIN_VRAM |
946 AMDGPU_GEM_DOMAIN_GTT,
947 &adev->mem_scratch.robj,
948 &adev->mem_scratch.gpu_addr,
949 (void **)&adev->mem_scratch.ptr);
953 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
955 * @adev: amdgpu_device pointer
957 * Frees the VRAM scratch page.
959 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
961 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
965 * amdgpu_device_program_register_sequence - program an array of registers.
967 * @adev: amdgpu_device pointer
968 * @registers: pointer to the register array
969 * @array_size: size of the register array
971 * Programs an array or registers with and and or masks.
972 * This is a helper for setting golden registers.
974 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
975 const u32 *registers,
976 const u32 array_size)
978 u32 tmp, reg, and_mask, or_mask;
984 for (i = 0; i < array_size; i +=3) {
985 reg = registers[i + 0];
986 and_mask = registers[i + 1];
987 or_mask = registers[i + 2];
989 if (and_mask == 0xffffffff) {
994 if (adev->family >= AMDGPU_FAMILY_AI)
995 tmp |= (or_mask & and_mask);
1004 * amdgpu_device_pci_config_reset - reset the GPU
1006 * @adev: amdgpu_device pointer
1008 * Resets the GPU using the pci config reset sequence.
1009 * Only applicable to asics prior to vega10.
1011 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1013 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1017 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1019 * @adev: amdgpu_device pointer
1021 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1023 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1025 return pci_reset_function(adev->pdev);
1029 * GPU doorbell aperture helpers function.
1032 * amdgpu_device_doorbell_init - Init doorbell driver information.
1034 * @adev: amdgpu_device pointer
1036 * Init doorbell driver information (CIK)
1037 * Returns 0 on success, error on failure.
1039 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
1042 /* No doorbell on SI hardware generation */
1043 if (adev->asic_type < CHIP_BONAIRE) {
1044 adev->doorbell.base = 0;
1045 adev->doorbell.size = 0;
1046 adev->doorbell.num_doorbells = 0;
1047 adev->doorbell.ptr = NULL;
1051 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
1054 amdgpu_asic_init_doorbell_index(adev);
1056 /* doorbell bar mapping */
1057 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
1058 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
1060 if (adev->enable_mes) {
1061 adev->doorbell.num_doorbells =
1062 adev->doorbell.size / sizeof(u32);
1064 adev->doorbell.num_doorbells =
1065 min_t(u32, adev->doorbell.size / sizeof(u32),
1066 adev->doorbell_index.max_assignment+1);
1067 if (adev->doorbell.num_doorbells == 0)
1070 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
1071 * paging queue doorbell use the second page. The
1072 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
1073 * doorbells are in the first page. So with paging queue enabled,
1074 * the max num_doorbells should + 1 page (0x400 in dword)
1076 if (adev->asic_type >= CHIP_VEGA10)
1077 adev->doorbell.num_doorbells += 0x400;
1080 adev->doorbell.ptr = ioremap(adev->doorbell.base,
1081 adev->doorbell.num_doorbells *
1083 if (adev->doorbell.ptr == NULL)
1090 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1092 * @adev: amdgpu_device pointer
1094 * Tear down doorbell driver information (CIK)
1096 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1098 iounmap(adev->doorbell.ptr);
1099 adev->doorbell.ptr = NULL;
1105 * amdgpu_device_wb_*()
1106 * Writeback is the method by which the GPU updates special pages in memory
1107 * with the status of certain GPU events (fences, ring pointers,etc.).
1111 * amdgpu_device_wb_fini - Disable Writeback and free memory
1113 * @adev: amdgpu_device pointer
1115 * Disables Writeback and frees the Writeback memory (all asics).
1116 * Used at driver shutdown.
1118 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1120 if (adev->wb.wb_obj) {
1121 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1123 (void **)&adev->wb.wb);
1124 adev->wb.wb_obj = NULL;
1129 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1131 * @adev: amdgpu_device pointer
1133 * Initializes writeback and allocates writeback memory (all asics).
1134 * Used at driver startup.
1135 * Returns 0 on success or an -error on failure.
1137 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1141 if (adev->wb.wb_obj == NULL) {
1142 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1143 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1144 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1145 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1146 (void **)&adev->wb.wb);
1148 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1152 adev->wb.num_wb = AMDGPU_MAX_WB;
1153 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1155 /* clear wb memory */
1156 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1163 * amdgpu_device_wb_get - Allocate a wb entry
1165 * @adev: amdgpu_device pointer
1168 * Allocate a wb slot for use by the driver (all asics).
1169 * Returns 0 on success or -EINVAL on failure.
1171 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1173 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1175 if (offset < adev->wb.num_wb) {
1176 __set_bit(offset, adev->wb.used);
1177 *wb = offset << 3; /* convert to dw offset */
1185 * amdgpu_device_wb_free - Free a wb entry
1187 * @adev: amdgpu_device pointer
1190 * Free a wb slot allocated for use by the driver (all asics)
1192 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1195 if (wb < adev->wb.num_wb)
1196 __clear_bit(wb, adev->wb.used);
1200 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1202 * @adev: amdgpu_device pointer
1204 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1205 * to fail, but if any of the BARs is not accessible after the size we abort
1206 * driver loading by returning -ENODEV.
1208 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1210 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1211 struct pci_bus *root;
1212 struct resource *res;
1218 if (amdgpu_sriov_vf(adev))
1221 /* skip if the bios has already enabled large BAR */
1222 if (adev->gmc.real_vram_size &&
1223 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1226 /* Check if the root BUS has 64bit memory resources */
1227 root = adev->pdev->bus;
1228 while (root->parent)
1229 root = root->parent;
1231 pci_bus_for_each_resource(root, res, i) {
1232 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1233 res->start > 0x100000000ull)
1237 /* Trying to resize is pointless without a root hub window above 4GB */
1241 /* Limit the BAR size to what is available */
1242 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1245 /* Disable memory decoding while we change the BAR addresses and size */
1246 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1247 pci_write_config_word(adev->pdev, PCI_COMMAND,
1248 cmd & ~PCI_COMMAND_MEMORY);
1250 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1251 amdgpu_device_doorbell_fini(adev);
1252 if (adev->asic_type >= CHIP_BONAIRE)
1253 pci_release_resource(adev->pdev, 2);
1255 pci_release_resource(adev->pdev, 0);
1257 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1259 DRM_INFO("Not enough PCI address space for a large BAR.");
1260 else if (r && r != -ENOTSUPP)
1261 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1263 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1265 /* When the doorbell or fb BAR isn't available we have no chance of
1268 r = amdgpu_device_doorbell_init(adev);
1269 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1272 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1278 * GPU helpers function.
1281 * amdgpu_device_need_post - check if the hw need post or not
1283 * @adev: amdgpu_device pointer
1285 * Check if the asic has been initialized (all asics) at driver startup
1286 * or post is needed if hw reset is performed.
1287 * Returns true if need or false if not.
1289 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1293 if (amdgpu_sriov_vf(adev))
1296 if (amdgpu_passthrough(adev)) {
1297 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1298 * some old smc fw still need driver do vPost otherwise gpu hang, while
1299 * those smc fw version above 22.15 doesn't have this flaw, so we force
1300 * vpost executed for smc version below 22.15
1302 if (adev->asic_type == CHIP_FIJI) {
1305 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1306 /* force vPost if error occured */
1310 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1311 if (fw_ver < 0x00160e00)
1316 /* Don't post if we need to reset whole hive on init */
1317 if (adev->gmc.xgmi.pending_reset)
1320 if (adev->has_hw_reset) {
1321 adev->has_hw_reset = false;
1325 /* bios scratch used on CIK+ */
1326 if (adev->asic_type >= CHIP_BONAIRE)
1327 return amdgpu_atombios_scratch_need_asic_init(adev);
1329 /* check MEM_SIZE for older asics */
1330 reg = amdgpu_asic_get_config_memsize(adev);
1332 if ((reg != 0) && (reg != 0xffffffff))
1339 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1341 * @adev: amdgpu_device pointer
1343 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1344 * be set for this device.
1346 * Returns true if it should be used or false if not.
1348 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1350 switch (amdgpu_aspm) {
1360 return pcie_aspm_enabled(adev->pdev);
1363 bool amdgpu_device_aspm_support_quirk(void)
1365 #if IS_ENABLED(CONFIG_X86)
1366 struct cpuinfo_x86 *c = &cpu_data(0);
1368 return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
1374 /* if we get transitioned to only one device, take VGA back */
1376 * amdgpu_device_vga_set_decode - enable/disable vga decode
1378 * @pdev: PCI device pointer
1379 * @state: enable/disable vga decode
1381 * Enable/disable vga decode (all asics).
1382 * Returns VGA resource flags.
1384 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1387 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1388 amdgpu_asic_set_vga_state(adev, state);
1390 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1391 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1393 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1397 * amdgpu_device_check_block_size - validate the vm block size
1399 * @adev: amdgpu_device pointer
1401 * Validates the vm block size specified via module parameter.
1402 * The vm block size defines number of bits in page table versus page directory,
1403 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1404 * page table and the remaining bits are in the page directory.
1406 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1408 /* defines number of bits in page table versus page directory,
1409 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1410 * page table and the remaining bits are in the page directory */
1411 if (amdgpu_vm_block_size == -1)
1414 if (amdgpu_vm_block_size < 9) {
1415 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1416 amdgpu_vm_block_size);
1417 amdgpu_vm_block_size = -1;
1422 * amdgpu_device_check_vm_size - validate the vm size
1424 * @adev: amdgpu_device pointer
1426 * Validates the vm size in GB specified via module parameter.
1427 * The VM size is the size of the GPU virtual memory space in GB.
1429 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1431 /* no need to check the default value */
1432 if (amdgpu_vm_size == -1)
1435 if (amdgpu_vm_size < 1) {
1436 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1438 amdgpu_vm_size = -1;
1442 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1445 bool is_os_64 = (sizeof(void *) == 8);
1446 uint64_t total_memory;
1447 uint64_t dram_size_seven_GB = 0x1B8000000;
1448 uint64_t dram_size_three_GB = 0xB8000000;
1450 if (amdgpu_smu_memory_pool_size == 0)
1454 DRM_WARN("Not 64-bit OS, feature not supported\n");
1458 total_memory = (uint64_t)si.totalram * si.mem_unit;
1460 if ((amdgpu_smu_memory_pool_size == 1) ||
1461 (amdgpu_smu_memory_pool_size == 2)) {
1462 if (total_memory < dram_size_three_GB)
1464 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1465 (amdgpu_smu_memory_pool_size == 8)) {
1466 if (total_memory < dram_size_seven_GB)
1469 DRM_WARN("Smu memory pool size not supported\n");
1472 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1477 DRM_WARN("No enough system memory\n");
1479 adev->pm.smu_prv_buffer_size = 0;
1482 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1484 if (!(adev->flags & AMD_IS_APU) ||
1485 adev->asic_type < CHIP_RAVEN)
1488 switch (adev->asic_type) {
1490 if (adev->pdev->device == 0x15dd)
1491 adev->apu_flags |= AMD_APU_IS_RAVEN;
1492 if (adev->pdev->device == 0x15d8)
1493 adev->apu_flags |= AMD_APU_IS_PICASSO;
1496 if ((adev->pdev->device == 0x1636) ||
1497 (adev->pdev->device == 0x164c))
1498 adev->apu_flags |= AMD_APU_IS_RENOIR;
1500 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1503 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1505 case CHIP_YELLOW_CARP:
1507 case CHIP_CYAN_SKILLFISH:
1508 if ((adev->pdev->device == 0x13FE) ||
1509 (adev->pdev->device == 0x143F))
1510 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1520 * amdgpu_device_check_arguments - validate module params
1522 * @adev: amdgpu_device pointer
1524 * Validates certain module parameters and updates
1525 * the associated values used by the driver (all asics).
1527 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1529 if (amdgpu_sched_jobs < 4) {
1530 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1532 amdgpu_sched_jobs = 4;
1533 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1534 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1536 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1539 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1540 /* gart size must be greater or equal to 32M */
1541 dev_warn(adev->dev, "gart size (%d) too small\n",
1543 amdgpu_gart_size = -1;
1546 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1547 /* gtt size must be greater or equal to 32M */
1548 dev_warn(adev->dev, "gtt size (%d) too small\n",
1550 amdgpu_gtt_size = -1;
1553 /* valid range is between 4 and 9 inclusive */
1554 if (amdgpu_vm_fragment_size != -1 &&
1555 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1556 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1557 amdgpu_vm_fragment_size = -1;
1560 if (amdgpu_sched_hw_submission < 2) {
1561 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1562 amdgpu_sched_hw_submission);
1563 amdgpu_sched_hw_submission = 2;
1564 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1565 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1566 amdgpu_sched_hw_submission);
1567 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1570 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1571 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1572 amdgpu_reset_method = -1;
1575 amdgpu_device_check_smu_prv_buffer_size(adev);
1577 amdgpu_device_check_vm_size(adev);
1579 amdgpu_device_check_block_size(adev);
1581 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1587 * amdgpu_switcheroo_set_state - set switcheroo state
1589 * @pdev: pci dev pointer
1590 * @state: vga_switcheroo state
1592 * Callback for the switcheroo driver. Suspends or resumes
1593 * the asics before or after it is powered up using ACPI methods.
1595 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1596 enum vga_switcheroo_state state)
1598 struct drm_device *dev = pci_get_drvdata(pdev);
1601 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1604 if (state == VGA_SWITCHEROO_ON) {
1605 pr_info("switched on\n");
1606 /* don't suspend or resume card normally */
1607 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1609 pci_set_power_state(pdev, PCI_D0);
1610 amdgpu_device_load_pci_state(pdev);
1611 r = pci_enable_device(pdev);
1613 DRM_WARN("pci_enable_device failed (%d)\n", r);
1614 amdgpu_device_resume(dev, true);
1616 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1618 pr_info("switched off\n");
1619 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1620 amdgpu_device_suspend(dev, true);
1621 amdgpu_device_cache_pci_state(pdev);
1622 /* Shut down the device */
1623 pci_disable_device(pdev);
1624 pci_set_power_state(pdev, PCI_D3cold);
1625 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1630 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1632 * @pdev: pci dev pointer
1634 * Callback for the switcheroo driver. Check of the switcheroo
1635 * state can be changed.
1636 * Returns true if the state can be changed, false if not.
1638 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1640 struct drm_device *dev = pci_get_drvdata(pdev);
1643 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1644 * locking inversion with the driver load path. And the access here is
1645 * completely racy anyway. So don't bother with locking for now.
1647 return atomic_read(&dev->open_count) == 0;
1650 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1651 .set_gpu_state = amdgpu_switcheroo_set_state,
1653 .can_switch = amdgpu_switcheroo_can_switch,
1657 * amdgpu_device_ip_set_clockgating_state - set the CG state
1659 * @dev: amdgpu_device pointer
1660 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1661 * @state: clockgating state (gate or ungate)
1663 * Sets the requested clockgating state for all instances of
1664 * the hardware IP specified.
1665 * Returns the error code from the last instance.
1667 int amdgpu_device_ip_set_clockgating_state(void *dev,
1668 enum amd_ip_block_type block_type,
1669 enum amd_clockgating_state state)
1671 struct amdgpu_device *adev = dev;
1674 for (i = 0; i < adev->num_ip_blocks; i++) {
1675 if (!adev->ip_blocks[i].status.valid)
1677 if (adev->ip_blocks[i].version->type != block_type)
1679 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1681 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1682 (void *)adev, state);
1684 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1685 adev->ip_blocks[i].version->funcs->name, r);
1691 * amdgpu_device_ip_set_powergating_state - set the PG state
1693 * @dev: amdgpu_device pointer
1694 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1695 * @state: powergating state (gate or ungate)
1697 * Sets the requested powergating state for all instances of
1698 * the hardware IP specified.
1699 * Returns the error code from the last instance.
1701 int amdgpu_device_ip_set_powergating_state(void *dev,
1702 enum amd_ip_block_type block_type,
1703 enum amd_powergating_state state)
1705 struct amdgpu_device *adev = dev;
1708 for (i = 0; i < adev->num_ip_blocks; i++) {
1709 if (!adev->ip_blocks[i].status.valid)
1711 if (adev->ip_blocks[i].version->type != block_type)
1713 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1715 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1716 (void *)adev, state);
1718 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1719 adev->ip_blocks[i].version->funcs->name, r);
1725 * amdgpu_device_ip_get_clockgating_state - get the CG state
1727 * @adev: amdgpu_device pointer
1728 * @flags: clockgating feature flags
1730 * Walks the list of IPs on the device and updates the clockgating
1731 * flags for each IP.
1732 * Updates @flags with the feature flags for each hardware IP where
1733 * clockgating is enabled.
1735 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1740 for (i = 0; i < adev->num_ip_blocks; i++) {
1741 if (!adev->ip_blocks[i].status.valid)
1743 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1744 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1749 * amdgpu_device_ip_wait_for_idle - wait for idle
1751 * @adev: amdgpu_device pointer
1752 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1754 * Waits for the request hardware IP to be idle.
1755 * Returns 0 for success or a negative error code on failure.
1757 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1758 enum amd_ip_block_type block_type)
1762 for (i = 0; i < adev->num_ip_blocks; i++) {
1763 if (!adev->ip_blocks[i].status.valid)
1765 if (adev->ip_blocks[i].version->type == block_type) {
1766 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1777 * amdgpu_device_ip_is_idle - is the hardware IP idle
1779 * @adev: amdgpu_device pointer
1780 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1782 * Check if the hardware IP is idle or not.
1783 * Returns true if it the IP is idle, false if not.
1785 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1786 enum amd_ip_block_type block_type)
1790 for (i = 0; i < adev->num_ip_blocks; i++) {
1791 if (!adev->ip_blocks[i].status.valid)
1793 if (adev->ip_blocks[i].version->type == block_type)
1794 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1801 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1803 * @adev: amdgpu_device pointer
1804 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1806 * Returns a pointer to the hardware IP block structure
1807 * if it exists for the asic, otherwise NULL.
1809 struct amdgpu_ip_block *
1810 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1811 enum amd_ip_block_type type)
1815 for (i = 0; i < adev->num_ip_blocks; i++)
1816 if (adev->ip_blocks[i].version->type == type)
1817 return &adev->ip_blocks[i];
1823 * amdgpu_device_ip_block_version_cmp
1825 * @adev: amdgpu_device pointer
1826 * @type: enum amd_ip_block_type
1827 * @major: major version
1828 * @minor: minor version
1830 * return 0 if equal or greater
1831 * return 1 if smaller or the ip_block doesn't exist
1833 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1834 enum amd_ip_block_type type,
1835 u32 major, u32 minor)
1837 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1839 if (ip_block && ((ip_block->version->major > major) ||
1840 ((ip_block->version->major == major) &&
1841 (ip_block->version->minor >= minor))))
1848 * amdgpu_device_ip_block_add
1850 * @adev: amdgpu_device pointer
1851 * @ip_block_version: pointer to the IP to add
1853 * Adds the IP block driver information to the collection of IPs
1856 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1857 const struct amdgpu_ip_block_version *ip_block_version)
1859 if (!ip_block_version)
1862 switch (ip_block_version->type) {
1863 case AMD_IP_BLOCK_TYPE_VCN:
1864 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1867 case AMD_IP_BLOCK_TYPE_JPEG:
1868 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1875 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1876 ip_block_version->funcs->name);
1878 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1884 * amdgpu_device_enable_virtual_display - enable virtual display feature
1886 * @adev: amdgpu_device pointer
1888 * Enabled the virtual display feature if the user has enabled it via
1889 * the module parameter virtual_display. This feature provides a virtual
1890 * display hardware on headless boards or in virtualized environments.
1891 * This function parses and validates the configuration string specified by
1892 * the user and configues the virtual display configuration (number of
1893 * virtual connectors, crtcs, etc.) specified.
1895 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1897 adev->enable_virtual_display = false;
1899 if (amdgpu_virtual_display) {
1900 const char *pci_address_name = pci_name(adev->pdev);
1901 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1903 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1904 pciaddstr_tmp = pciaddstr;
1905 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1906 pciaddname = strsep(&pciaddname_tmp, ",");
1907 if (!strcmp("all", pciaddname)
1908 || !strcmp(pci_address_name, pciaddname)) {
1912 adev->enable_virtual_display = true;
1915 res = kstrtol(pciaddname_tmp, 10,
1923 adev->mode_info.num_crtc = num_crtc;
1925 adev->mode_info.num_crtc = 1;
1931 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1932 amdgpu_virtual_display, pci_address_name,
1933 adev->enable_virtual_display, adev->mode_info.num_crtc);
1939 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1941 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1942 adev->mode_info.num_crtc = 1;
1943 adev->enable_virtual_display = true;
1944 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1945 adev->enable_virtual_display, adev->mode_info.num_crtc);
1950 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1952 * @adev: amdgpu_device pointer
1954 * Parses the asic configuration parameters specified in the gpu info
1955 * firmware and makes them availale to the driver for use in configuring
1957 * Returns 0 on success, -EINVAL on failure.
1959 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1961 const char *chip_name;
1964 const struct gpu_info_firmware_header_v1_0 *hdr;
1966 adev->firmware.gpu_info_fw = NULL;
1968 if (adev->mman.discovery_bin) {
1970 * FIXME: The bounding box is still needed by Navi12, so
1971 * temporarily read it from gpu_info firmware. Should be dropped
1972 * when DAL no longer needs it.
1974 if (adev->asic_type != CHIP_NAVI12)
1978 switch (adev->asic_type) {
1982 chip_name = "vega10";
1985 chip_name = "vega12";
1988 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1989 chip_name = "raven2";
1990 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1991 chip_name = "picasso";
1993 chip_name = "raven";
1996 chip_name = "arcturus";
1999 chip_name = "navi12";
2003 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2004 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2007 "Failed to get gpu_info firmware \"%s\"\n",
2012 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2013 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2015 switch (hdr->version_major) {
2018 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2019 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2020 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2023 * Should be droped when DAL no longer needs it.
2025 if (adev->asic_type == CHIP_NAVI12)
2026 goto parse_soc_bounding_box;
2028 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2029 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2030 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2031 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2032 adev->gfx.config.max_texture_channel_caches =
2033 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2034 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2035 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2036 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2037 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2038 adev->gfx.config.double_offchip_lds_buf =
2039 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2040 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2041 adev->gfx.cu_info.max_waves_per_simd =
2042 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2043 adev->gfx.cu_info.max_scratch_slots_per_cu =
2044 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2045 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2046 if (hdr->version_minor >= 1) {
2047 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2048 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2049 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2050 adev->gfx.config.num_sc_per_sh =
2051 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2052 adev->gfx.config.num_packer_per_sc =
2053 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2056 parse_soc_bounding_box:
2058 * soc bounding box info is not integrated in disocovery table,
2059 * we always need to parse it from gpu info firmware if needed.
2061 if (hdr->version_minor == 2) {
2062 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2063 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2064 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2065 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2071 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2080 * amdgpu_device_ip_early_init - run early init for hardware IPs
2082 * @adev: amdgpu_device pointer
2084 * Early initialization pass for hardware IPs. The hardware IPs that make
2085 * up each asic are discovered each IP's early_init callback is run. This
2086 * is the first stage in initializing the asic.
2087 * Returns 0 on success, negative error code on failure.
2089 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2091 struct drm_device *dev = adev_to_drm(adev);
2092 struct pci_dev *parent;
2096 amdgpu_device_enable_virtual_display(adev);
2098 if (amdgpu_sriov_vf(adev)) {
2099 r = amdgpu_virt_request_full_gpu(adev, true);
2104 switch (adev->asic_type) {
2105 #ifdef CONFIG_DRM_AMDGPU_SI
2111 adev->family = AMDGPU_FAMILY_SI;
2112 r = si_set_ip_blocks(adev);
2117 #ifdef CONFIG_DRM_AMDGPU_CIK
2123 if (adev->flags & AMD_IS_APU)
2124 adev->family = AMDGPU_FAMILY_KV;
2126 adev->family = AMDGPU_FAMILY_CI;
2128 r = cik_set_ip_blocks(adev);
2136 case CHIP_POLARIS10:
2137 case CHIP_POLARIS11:
2138 case CHIP_POLARIS12:
2142 if (adev->flags & AMD_IS_APU)
2143 adev->family = AMDGPU_FAMILY_CZ;
2145 adev->family = AMDGPU_FAMILY_VI;
2147 r = vi_set_ip_blocks(adev);
2152 r = amdgpu_discovery_set_ip_blocks(adev);
2158 if (amdgpu_has_atpx() &&
2159 (amdgpu_is_atpx_hybrid() ||
2160 amdgpu_has_atpx_dgpu_power_cntl()) &&
2161 ((adev->flags & AMD_IS_APU) == 0) &&
2162 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2163 adev->flags |= AMD_IS_PX;
2165 if (!(adev->flags & AMD_IS_APU)) {
2166 parent = pci_upstream_bridge(adev->pdev);
2167 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2170 amdgpu_amdkfd_device_probe(adev);
2172 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2173 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2174 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2175 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2176 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2179 for (i = 0; i < adev->num_ip_blocks; i++) {
2180 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2181 DRM_ERROR("disabled ip block: %d <%s>\n",
2182 i, adev->ip_blocks[i].version->funcs->name);
2183 adev->ip_blocks[i].status.valid = false;
2185 if (adev->ip_blocks[i].version->funcs->early_init) {
2186 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2188 adev->ip_blocks[i].status.valid = false;
2190 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2191 adev->ip_blocks[i].version->funcs->name, r);
2194 adev->ip_blocks[i].status.valid = true;
2197 adev->ip_blocks[i].status.valid = true;
2200 /* get the vbios after the asic_funcs are set up */
2201 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2202 r = amdgpu_device_parse_gpu_info_fw(adev);
2207 if (!amdgpu_get_bios(adev))
2210 r = amdgpu_atombios_init(adev);
2212 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2213 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2217 /*get pf2vf msg info at it's earliest time*/
2218 if (amdgpu_sriov_vf(adev))
2219 amdgpu_virt_init_data_exchange(adev);
2226 adev->cg_flags &= amdgpu_cg_mask;
2227 adev->pg_flags &= amdgpu_pg_mask;
2232 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2236 for (i = 0; i < adev->num_ip_blocks; i++) {
2237 if (!adev->ip_blocks[i].status.sw)
2239 if (adev->ip_blocks[i].status.hw)
2241 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2242 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2243 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2244 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2246 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2247 adev->ip_blocks[i].version->funcs->name, r);
2250 adev->ip_blocks[i].status.hw = true;
2257 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2261 for (i = 0; i < adev->num_ip_blocks; i++) {
2262 if (!adev->ip_blocks[i].status.sw)
2264 if (adev->ip_blocks[i].status.hw)
2266 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2268 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2269 adev->ip_blocks[i].version->funcs->name, r);
2272 adev->ip_blocks[i].status.hw = true;
2278 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2282 uint32_t smu_version;
2284 if (adev->asic_type >= CHIP_VEGA10) {
2285 for (i = 0; i < adev->num_ip_blocks; i++) {
2286 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2289 if (!adev->ip_blocks[i].status.sw)
2292 /* no need to do the fw loading again if already done*/
2293 if (adev->ip_blocks[i].status.hw == true)
2296 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2297 r = adev->ip_blocks[i].version->funcs->resume(adev);
2299 DRM_ERROR("resume of IP block <%s> failed %d\n",
2300 adev->ip_blocks[i].version->funcs->name, r);
2304 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2306 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2307 adev->ip_blocks[i].version->funcs->name, r);
2312 adev->ip_blocks[i].status.hw = true;
2317 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2318 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2323 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2328 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2329 struct amdgpu_ring *ring = adev->rings[i];
2331 /* No need to setup the GPU scheduler for rings that don't need it */
2332 if (!ring || ring->no_scheduler)
2335 switch (ring->funcs->type) {
2336 case AMDGPU_RING_TYPE_GFX:
2337 timeout = adev->gfx_timeout;
2339 case AMDGPU_RING_TYPE_COMPUTE:
2340 timeout = adev->compute_timeout;
2342 case AMDGPU_RING_TYPE_SDMA:
2343 timeout = adev->sdma_timeout;
2346 timeout = adev->video_timeout;
2350 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2351 ring->num_hw_submission, amdgpu_job_hang_limit,
2352 timeout, adev->reset_domain->wq,
2353 ring->sched_score, ring->name,
2356 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2367 * amdgpu_device_ip_init - run init for hardware IPs
2369 * @adev: amdgpu_device pointer
2371 * Main initialization pass for hardware IPs. The list of all the hardware
2372 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2373 * are run. sw_init initializes the software state associated with each IP
2374 * and hw_init initializes the hardware associated with each IP.
2375 * Returns 0 on success, negative error code on failure.
2377 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2381 r = amdgpu_ras_init(adev);
2385 for (i = 0; i < adev->num_ip_blocks; i++) {
2386 if (!adev->ip_blocks[i].status.valid)
2388 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2390 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2391 adev->ip_blocks[i].version->funcs->name, r);
2394 adev->ip_blocks[i].status.sw = true;
2396 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2397 /* need to do common hw init early so everything is set up for gmc */
2398 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2400 DRM_ERROR("hw_init %d failed %d\n", i, r);
2403 adev->ip_blocks[i].status.hw = true;
2404 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2405 /* need to do gmc hw init early so we can allocate gpu mem */
2406 /* Try to reserve bad pages early */
2407 if (amdgpu_sriov_vf(adev))
2408 amdgpu_virt_exchange_data(adev);
2410 r = amdgpu_device_mem_scratch_init(adev);
2412 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2415 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2417 DRM_ERROR("hw_init %d failed %d\n", i, r);
2420 r = amdgpu_device_wb_init(adev);
2422 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2425 adev->ip_blocks[i].status.hw = true;
2427 /* right after GMC hw init, we create CSA */
2429 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2430 AMDGPU_GEM_DOMAIN_VRAM |
2431 AMDGPU_GEM_DOMAIN_GTT,
2434 DRM_ERROR("allocate CSA failed %d\n", r);
2441 if (amdgpu_sriov_vf(adev))
2442 amdgpu_virt_init_data_exchange(adev);
2444 r = amdgpu_ib_pool_init(adev);
2446 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2447 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2451 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2455 r = amdgpu_device_ip_hw_init_phase1(adev);
2459 r = amdgpu_device_fw_loading(adev);
2463 r = amdgpu_device_ip_hw_init_phase2(adev);
2468 * retired pages will be loaded from eeprom and reserved here,
2469 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2470 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2471 * for I2C communication which only true at this point.
2473 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2474 * failure from bad gpu situation and stop amdgpu init process
2475 * accordingly. For other failed cases, it will still release all
2476 * the resource and print error message, rather than returning one
2477 * negative value to upper level.
2479 * Note: theoretically, this should be called before all vram allocations
2480 * to protect retired page from abusing
2482 r = amdgpu_ras_recovery_init(adev);
2487 * In case of XGMI grab extra reference for reset domain for this device
2489 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2490 if (amdgpu_xgmi_add_device(adev) == 0) {
2491 if (!amdgpu_sriov_vf(adev)) {
2492 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2494 if (WARN_ON(!hive)) {
2499 if (!hive->reset_domain ||
2500 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2502 amdgpu_put_xgmi_hive(hive);
2506 /* Drop the early temporary reset domain we created for device */
2507 amdgpu_reset_put_reset_domain(adev->reset_domain);
2508 adev->reset_domain = hive->reset_domain;
2509 amdgpu_put_xgmi_hive(hive);
2514 r = amdgpu_device_init_schedulers(adev);
2518 /* Don't init kfd if whole hive need to be reset during init */
2519 if (!adev->gmc.xgmi.pending_reset)
2520 amdgpu_amdkfd_device_init(adev);
2522 amdgpu_fru_get_product_info(adev);
2525 if (amdgpu_sriov_vf(adev))
2526 amdgpu_virt_release_full_gpu(adev, true);
2532 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2534 * @adev: amdgpu_device pointer
2536 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2537 * this function before a GPU reset. If the value is retained after a
2538 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2540 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2542 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2546 * amdgpu_device_check_vram_lost - check if vram is valid
2548 * @adev: amdgpu_device pointer
2550 * Checks the reset magic value written to the gart pointer in VRAM.
2551 * The driver calls this after a GPU reset to see if the contents of
2552 * VRAM is lost or now.
2553 * returns true if vram is lost, false if not.
2555 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2557 if (memcmp(adev->gart.ptr, adev->reset_magic,
2558 AMDGPU_RESET_MAGIC_NUM))
2561 if (!amdgpu_in_reset(adev))
2565 * For all ASICs with baco/mode1 reset, the VRAM is
2566 * always assumed to be lost.
2568 switch (amdgpu_asic_reset_method(adev)) {
2569 case AMD_RESET_METHOD_BACO:
2570 case AMD_RESET_METHOD_MODE1:
2578 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2580 * @adev: amdgpu_device pointer
2581 * @state: clockgating state (gate or ungate)
2583 * The list of all the hardware IPs that make up the asic is walked and the
2584 * set_clockgating_state callbacks are run.
2585 * Late initialization pass enabling clockgating for hardware IPs.
2586 * Fini or suspend, pass disabling clockgating for hardware IPs.
2587 * Returns 0 on success, negative error code on failure.
2590 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2591 enum amd_clockgating_state state)
2595 if (amdgpu_emu_mode == 1)
2598 for (j = 0; j < adev->num_ip_blocks; j++) {
2599 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2600 if (!adev->ip_blocks[i].status.late_initialized)
2602 /* skip CG for GFX, SDMA on S0ix */
2603 if (adev->in_s0ix &&
2604 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2605 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2607 /* skip CG for VCE/UVD, it's handled specially */
2608 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2609 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2610 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2611 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2612 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2613 /* enable clockgating to save power */
2614 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2617 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2618 adev->ip_blocks[i].version->funcs->name, r);
2627 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2628 enum amd_powergating_state state)
2632 if (amdgpu_emu_mode == 1)
2635 for (j = 0; j < adev->num_ip_blocks; j++) {
2636 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2637 if (!adev->ip_blocks[i].status.late_initialized)
2639 /* skip PG for GFX, SDMA on S0ix */
2640 if (adev->in_s0ix &&
2641 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2642 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2644 /* skip CG for VCE/UVD, it's handled specially */
2645 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2646 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2647 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2648 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2649 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2650 /* enable powergating to save power */
2651 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2654 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2655 adev->ip_blocks[i].version->funcs->name, r);
2663 static int amdgpu_device_enable_mgpu_fan_boost(void)
2665 struct amdgpu_gpu_instance *gpu_ins;
2666 struct amdgpu_device *adev;
2669 mutex_lock(&mgpu_info.mutex);
2672 * MGPU fan boost feature should be enabled
2673 * only when there are two or more dGPUs in
2676 if (mgpu_info.num_dgpu < 2)
2679 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2680 gpu_ins = &(mgpu_info.gpu_ins[i]);
2681 adev = gpu_ins->adev;
2682 if (!(adev->flags & AMD_IS_APU) &&
2683 !gpu_ins->mgpu_fan_enabled) {
2684 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2688 gpu_ins->mgpu_fan_enabled = 1;
2693 mutex_unlock(&mgpu_info.mutex);
2699 * amdgpu_device_ip_late_init - run late init for hardware IPs
2701 * @adev: amdgpu_device pointer
2703 * Late initialization pass for hardware IPs. The list of all the hardware
2704 * IPs that make up the asic is walked and the late_init callbacks are run.
2705 * late_init covers any special initialization that an IP requires
2706 * after all of the have been initialized or something that needs to happen
2707 * late in the init process.
2708 * Returns 0 on success, negative error code on failure.
2710 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2712 struct amdgpu_gpu_instance *gpu_instance;
2715 for (i = 0; i < adev->num_ip_blocks; i++) {
2716 if (!adev->ip_blocks[i].status.hw)
2718 if (adev->ip_blocks[i].version->funcs->late_init) {
2719 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2721 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2722 adev->ip_blocks[i].version->funcs->name, r);
2726 adev->ip_blocks[i].status.late_initialized = true;
2729 r = amdgpu_ras_late_init(adev);
2731 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2735 amdgpu_ras_set_error_query_ready(adev, true);
2737 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2738 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2740 amdgpu_device_fill_reset_magic(adev);
2742 r = amdgpu_device_enable_mgpu_fan_boost();
2744 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2746 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2747 if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
2748 adev->asic_type == CHIP_ALDEBARAN ))
2749 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2751 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2752 mutex_lock(&mgpu_info.mutex);
2755 * Reset device p-state to low as this was booted with high.
2757 * This should be performed only after all devices from the same
2758 * hive get initialized.
2760 * However, it's unknown how many device in the hive in advance.
2761 * As this is counted one by one during devices initializations.
2763 * So, we wait for all XGMI interlinked devices initialized.
2764 * This may bring some delays as those devices may come from
2765 * different hives. But that should be OK.
2767 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2768 for (i = 0; i < mgpu_info.num_gpu; i++) {
2769 gpu_instance = &(mgpu_info.gpu_ins[i]);
2770 if (gpu_instance->adev->flags & AMD_IS_APU)
2773 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2774 AMDGPU_XGMI_PSTATE_MIN);
2776 DRM_ERROR("pstate setting failed (%d).\n", r);
2782 mutex_unlock(&mgpu_info.mutex);
2789 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2791 * @adev: amdgpu_device pointer
2793 * For ASICs need to disable SMC first
2795 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2799 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2802 for (i = 0; i < adev->num_ip_blocks; i++) {
2803 if (!adev->ip_blocks[i].status.hw)
2805 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2806 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2807 /* XXX handle errors */
2809 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2810 adev->ip_blocks[i].version->funcs->name, r);
2812 adev->ip_blocks[i].status.hw = false;
2818 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2822 for (i = 0; i < adev->num_ip_blocks; i++) {
2823 if (!adev->ip_blocks[i].version->funcs->early_fini)
2826 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2828 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2829 adev->ip_blocks[i].version->funcs->name, r);
2833 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2834 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2836 amdgpu_amdkfd_suspend(adev, false);
2838 /* Workaroud for ASICs need to disable SMC first */
2839 amdgpu_device_smu_fini_early(adev);
2841 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2842 if (!adev->ip_blocks[i].status.hw)
2845 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2846 /* XXX handle errors */
2848 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2849 adev->ip_blocks[i].version->funcs->name, r);
2852 adev->ip_blocks[i].status.hw = false;
2855 if (amdgpu_sriov_vf(adev)) {
2856 if (amdgpu_virt_release_full_gpu(adev, false))
2857 DRM_ERROR("failed to release exclusive mode on fini\n");
2864 * amdgpu_device_ip_fini - run fini for hardware IPs
2866 * @adev: amdgpu_device pointer
2868 * Main teardown pass for hardware IPs. The list of all the hardware
2869 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2870 * are run. hw_fini tears down the hardware associated with each IP
2871 * and sw_fini tears down any software state associated with each IP.
2872 * Returns 0 on success, negative error code on failure.
2874 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2878 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2879 amdgpu_virt_release_ras_err_handler_data(adev);
2881 if (adev->gmc.xgmi.num_physical_nodes > 1)
2882 amdgpu_xgmi_remove_device(adev);
2884 amdgpu_amdkfd_device_fini_sw(adev);
2886 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2887 if (!adev->ip_blocks[i].status.sw)
2890 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2891 amdgpu_ucode_free_bo(adev);
2892 amdgpu_free_static_csa(&adev->virt.csa_obj);
2893 amdgpu_device_wb_fini(adev);
2894 amdgpu_device_mem_scratch_fini(adev);
2895 amdgpu_ib_pool_fini(adev);
2898 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2899 /* XXX handle errors */
2901 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2902 adev->ip_blocks[i].version->funcs->name, r);
2904 adev->ip_blocks[i].status.sw = false;
2905 adev->ip_blocks[i].status.valid = false;
2908 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2909 if (!adev->ip_blocks[i].status.late_initialized)
2911 if (adev->ip_blocks[i].version->funcs->late_fini)
2912 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2913 adev->ip_blocks[i].status.late_initialized = false;
2916 amdgpu_ras_fini(adev);
2922 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2924 * @work: work_struct.
2926 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2928 struct amdgpu_device *adev =
2929 container_of(work, struct amdgpu_device, delayed_init_work.work);
2932 r = amdgpu_ib_ring_tests(adev);
2934 DRM_ERROR("ib ring test failed (%d).\n", r);
2937 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2939 struct amdgpu_device *adev =
2940 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2942 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2943 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2945 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2946 adev->gfx.gfx_off_state = true;
2950 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2952 * @adev: amdgpu_device pointer
2954 * Main suspend function for hardware IPs. The list of all the hardware
2955 * IPs that make up the asic is walked, clockgating is disabled and the
2956 * suspend callbacks are run. suspend puts the hardware and software state
2957 * in each IP into a state suitable for suspend.
2958 * Returns 0 on success, negative error code on failure.
2960 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2964 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2965 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2968 * Per PMFW team's suggestion, driver needs to handle gfxoff
2969 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2970 * scenario. Add the missing df cstate disablement here.
2972 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2973 dev_warn(adev->dev, "Failed to disallow df cstate");
2975 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2976 if (!adev->ip_blocks[i].status.valid)
2979 /* displays are handled separately */
2980 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2983 /* XXX handle errors */
2984 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2985 /* XXX handle errors */
2987 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2988 adev->ip_blocks[i].version->funcs->name, r);
2992 adev->ip_blocks[i].status.hw = false;
2999 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3001 * @adev: amdgpu_device pointer
3003 * Main suspend function for hardware IPs. The list of all the hardware
3004 * IPs that make up the asic is walked, clockgating is disabled and the
3005 * suspend callbacks are run. suspend puts the hardware and software state
3006 * in each IP into a state suitable for suspend.
3007 * Returns 0 on success, negative error code on failure.
3009 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3014 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3016 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3017 if (!adev->ip_blocks[i].status.valid)
3019 /* displays are handled in phase1 */
3020 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3022 /* PSP lost connection when err_event_athub occurs */
3023 if (amdgpu_ras_intr_triggered() &&
3024 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3025 adev->ip_blocks[i].status.hw = false;
3029 /* skip unnecessary suspend if we do not initialize them yet */
3030 if (adev->gmc.xgmi.pending_reset &&
3031 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3032 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3033 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3034 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3035 adev->ip_blocks[i].status.hw = false;
3039 /* skip suspend of gfx/mes and psp for S0ix
3040 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3041 * like at runtime. PSP is also part of the always on hardware
3042 * so no need to suspend it.
3044 if (adev->in_s0ix &&
3045 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3046 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3047 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3050 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3051 if (adev->in_s0ix &&
3052 (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) &&
3053 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3056 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3057 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3058 * from this location and RLC Autoload automatically also gets loaded
3059 * from here based on PMFW -> PSP message during re-init sequence.
3060 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3061 * the TMR and reload FWs again for IMU enabled APU ASICs.
3063 if (amdgpu_in_reset(adev) &&
3064 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3065 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3068 /* XXX handle errors */
3069 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3070 /* XXX handle errors */
3072 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3073 adev->ip_blocks[i].version->funcs->name, r);
3075 adev->ip_blocks[i].status.hw = false;
3076 /* handle putting the SMC in the appropriate state */
3077 if(!amdgpu_sriov_vf(adev)){
3078 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3079 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3081 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3082 adev->mp1_state, r);
3093 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3095 * @adev: amdgpu_device pointer
3097 * Main suspend function for hardware IPs. The list of all the hardware
3098 * IPs that make up the asic is walked, clockgating is disabled and the
3099 * suspend callbacks are run. suspend puts the hardware and software state
3100 * in each IP into a state suitable for suspend.
3101 * Returns 0 on success, negative error code on failure.
3103 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3107 if (amdgpu_sriov_vf(adev)) {
3108 amdgpu_virt_fini_data_exchange(adev);
3109 amdgpu_virt_request_full_gpu(adev, false);
3112 r = amdgpu_device_ip_suspend_phase1(adev);
3115 r = amdgpu_device_ip_suspend_phase2(adev);
3117 if (amdgpu_sriov_vf(adev))
3118 amdgpu_virt_release_full_gpu(adev, false);
3123 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3127 static enum amd_ip_block_type ip_order[] = {
3128 AMD_IP_BLOCK_TYPE_COMMON,
3129 AMD_IP_BLOCK_TYPE_GMC,
3130 AMD_IP_BLOCK_TYPE_PSP,
3131 AMD_IP_BLOCK_TYPE_IH,
3134 for (i = 0; i < adev->num_ip_blocks; i++) {
3136 struct amdgpu_ip_block *block;
3138 block = &adev->ip_blocks[i];
3139 block->status.hw = false;
3141 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3143 if (block->version->type != ip_order[j] ||
3144 !block->status.valid)
3147 r = block->version->funcs->hw_init(adev);
3148 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3151 block->status.hw = true;
3158 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3162 static enum amd_ip_block_type ip_order[] = {
3163 AMD_IP_BLOCK_TYPE_SMC,
3164 AMD_IP_BLOCK_TYPE_DCE,
3165 AMD_IP_BLOCK_TYPE_GFX,
3166 AMD_IP_BLOCK_TYPE_SDMA,
3167 AMD_IP_BLOCK_TYPE_UVD,
3168 AMD_IP_BLOCK_TYPE_VCE,
3169 AMD_IP_BLOCK_TYPE_VCN
3172 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3174 struct amdgpu_ip_block *block;
3176 for (j = 0; j < adev->num_ip_blocks; j++) {
3177 block = &adev->ip_blocks[j];
3179 if (block->version->type != ip_order[i] ||
3180 !block->status.valid ||
3184 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3185 r = block->version->funcs->resume(adev);
3187 r = block->version->funcs->hw_init(adev);
3189 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3192 block->status.hw = true;
3200 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3202 * @adev: amdgpu_device pointer
3204 * First resume function for hardware IPs. The list of all the hardware
3205 * IPs that make up the asic is walked and the resume callbacks are run for
3206 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3207 * after a suspend and updates the software state as necessary. This
3208 * function is also used for restoring the GPU after a GPU reset.
3209 * Returns 0 on success, negative error code on failure.
3211 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3215 for (i = 0; i < adev->num_ip_blocks; i++) {
3216 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3218 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3219 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3220 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3221 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3223 r = adev->ip_blocks[i].version->funcs->resume(adev);
3225 DRM_ERROR("resume of IP block <%s> failed %d\n",
3226 adev->ip_blocks[i].version->funcs->name, r);
3229 adev->ip_blocks[i].status.hw = true;
3237 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3239 * @adev: amdgpu_device pointer
3241 * First resume function for hardware IPs. The list of all the hardware
3242 * IPs that make up the asic is walked and the resume callbacks are run for
3243 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3244 * functional state after a suspend and updates the software state as
3245 * necessary. This function is also used for restoring the GPU after a GPU
3247 * Returns 0 on success, negative error code on failure.
3249 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3253 for (i = 0; i < adev->num_ip_blocks; i++) {
3254 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3256 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3257 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3258 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3259 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3261 r = adev->ip_blocks[i].version->funcs->resume(adev);
3263 DRM_ERROR("resume of IP block <%s> failed %d\n",
3264 adev->ip_blocks[i].version->funcs->name, r);
3267 adev->ip_blocks[i].status.hw = true;
3274 * amdgpu_device_ip_resume - run resume for hardware IPs
3276 * @adev: amdgpu_device pointer
3278 * Main resume function for hardware IPs. The hardware IPs
3279 * are split into two resume functions because they are
3280 * are also used in in recovering from a GPU reset and some additional
3281 * steps need to be take between them. In this case (S3/S4) they are
3283 * Returns 0 on success, negative error code on failure.
3285 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3289 r = amdgpu_amdkfd_resume_iommu(adev);
3293 r = amdgpu_device_ip_resume_phase1(adev);
3297 r = amdgpu_device_fw_loading(adev);
3301 r = amdgpu_device_ip_resume_phase2(adev);
3307 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3309 * @adev: amdgpu_device pointer
3311 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3313 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3315 if (amdgpu_sriov_vf(adev)) {
3316 if (adev->is_atom_fw) {
3317 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3318 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3320 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3321 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3324 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3325 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3330 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3332 * @asic_type: AMD asic type
3334 * Check if there is DC (new modesetting infrastructre) support for an asic.
3335 * returns true if DC has support, false if not.
3337 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3339 switch (asic_type) {
3340 #ifdef CONFIG_DRM_AMDGPU_SI
3344 /* chips with no display hardware */
3346 #if defined(CONFIG_DRM_AMD_DC)
3352 * We have systems in the wild with these ASICs that require
3353 * LVDS and VGA support which is not supported with DC.
3355 * Fallback to the non-DC driver here by default so as not to
3356 * cause regressions.
3358 #if defined(CONFIG_DRM_AMD_DC_SI)
3359 return amdgpu_dc > 0;
3368 * We have systems in the wild with these ASICs that require
3369 * VGA support which is not supported with DC.
3371 * Fallback to the non-DC driver here by default so as not to
3372 * cause regressions.
3374 return amdgpu_dc > 0;
3376 return amdgpu_dc != 0;
3380 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3381 "but isn't supported by ASIC, ignoring\n");
3388 * amdgpu_device_has_dc_support - check if dc is supported
3390 * @adev: amdgpu_device pointer
3392 * Returns true for supported, false for not supported
3394 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3396 if (adev->enable_virtual_display ||
3397 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3400 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3403 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3405 struct amdgpu_device *adev =
3406 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3407 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3409 /* It's a bug to not have a hive within this function */
3414 * Use task barrier to synchronize all xgmi reset works across the
3415 * hive. task_barrier_enter and task_barrier_exit will block
3416 * until all the threads running the xgmi reset works reach
3417 * those points. task_barrier_full will do both blocks.
3419 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3421 task_barrier_enter(&hive->tb);
3422 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3424 if (adev->asic_reset_res)
3427 task_barrier_exit(&hive->tb);
3428 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3430 if (adev->asic_reset_res)
3433 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3434 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3435 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3438 task_barrier_full(&hive->tb);
3439 adev->asic_reset_res = amdgpu_asic_reset(adev);
3443 if (adev->asic_reset_res)
3444 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3445 adev->asic_reset_res, adev_to_drm(adev)->unique);
3446 amdgpu_put_xgmi_hive(hive);
3449 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3451 char *input = amdgpu_lockup_timeout;
3452 char *timeout_setting = NULL;
3458 * By default timeout for non compute jobs is 10000
3459 * and 60000 for compute jobs.
3460 * In SR-IOV or passthrough mode, timeout for compute
3461 * jobs are 60000 by default.
3463 adev->gfx_timeout = msecs_to_jiffies(10000);
3464 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3465 if (amdgpu_sriov_vf(adev))
3466 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3467 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3469 adev->compute_timeout = msecs_to_jiffies(60000);
3471 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3472 while ((timeout_setting = strsep(&input, ",")) &&
3473 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3474 ret = kstrtol(timeout_setting, 0, &timeout);
3481 } else if (timeout < 0) {
3482 timeout = MAX_SCHEDULE_TIMEOUT;
3483 dev_warn(adev->dev, "lockup timeout disabled");
3484 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3486 timeout = msecs_to_jiffies(timeout);
3491 adev->gfx_timeout = timeout;
3494 adev->compute_timeout = timeout;
3497 adev->sdma_timeout = timeout;
3500 adev->video_timeout = timeout;
3507 * There is only one value specified and
3508 * it should apply to all non-compute jobs.
3511 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3512 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3513 adev->compute_timeout = adev->gfx_timeout;
3521 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3523 * @adev: amdgpu_device pointer
3525 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3527 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3529 struct iommu_domain *domain;
3531 domain = iommu_get_domain_for_dev(adev->dev);
3532 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3533 adev->ram_is_direct_mapped = true;
3536 static const struct attribute *amdgpu_dev_attributes[] = {
3537 &dev_attr_product_name.attr,
3538 &dev_attr_product_number.attr,
3539 &dev_attr_serial_number.attr,
3540 &dev_attr_pcie_replay_count.attr,
3545 * amdgpu_device_init - initialize the driver
3547 * @adev: amdgpu_device pointer
3548 * @flags: driver flags
3550 * Initializes the driver info and hw (all asics).
3551 * Returns 0 for success or an error on failure.
3552 * Called at driver startup.
3554 int amdgpu_device_init(struct amdgpu_device *adev,
3557 struct drm_device *ddev = adev_to_drm(adev);
3558 struct pci_dev *pdev = adev->pdev;
3563 adev->shutdown = false;
3564 adev->flags = flags;
3566 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3567 adev->asic_type = amdgpu_force_asic_type;
3569 adev->asic_type = flags & AMD_ASIC_MASK;
3571 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3572 if (amdgpu_emu_mode == 1)
3573 adev->usec_timeout *= 10;
3574 adev->gmc.gart_size = 512 * 1024 * 1024;
3575 adev->accel_working = false;
3576 adev->num_rings = 0;
3577 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3578 adev->mman.buffer_funcs = NULL;
3579 adev->mman.buffer_funcs_ring = NULL;
3580 adev->vm_manager.vm_pte_funcs = NULL;
3581 adev->vm_manager.vm_pte_num_scheds = 0;
3582 adev->gmc.gmc_funcs = NULL;
3583 adev->harvest_ip_mask = 0x0;
3584 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3585 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3587 adev->smc_rreg = &amdgpu_invalid_rreg;
3588 adev->smc_wreg = &amdgpu_invalid_wreg;
3589 adev->pcie_rreg = &amdgpu_invalid_rreg;
3590 adev->pcie_wreg = &amdgpu_invalid_wreg;
3591 adev->pciep_rreg = &amdgpu_invalid_rreg;
3592 adev->pciep_wreg = &amdgpu_invalid_wreg;
3593 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3594 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3595 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3596 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3597 adev->didt_rreg = &amdgpu_invalid_rreg;
3598 adev->didt_wreg = &amdgpu_invalid_wreg;
3599 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3600 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3601 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3602 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3604 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3605 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3606 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3608 /* mutex initialization are all done here so we
3609 * can recall function without having locking issues */
3610 mutex_init(&adev->firmware.mutex);
3611 mutex_init(&adev->pm.mutex);
3612 mutex_init(&adev->gfx.gpu_clock_mutex);
3613 mutex_init(&adev->srbm_mutex);
3614 mutex_init(&adev->gfx.pipe_reserve_mutex);
3615 mutex_init(&adev->gfx.gfx_off_mutex);
3616 mutex_init(&adev->grbm_idx_mutex);
3617 mutex_init(&adev->mn_lock);
3618 mutex_init(&adev->virt.vf_errors.lock);
3619 hash_init(adev->mn_hash);
3620 mutex_init(&adev->psp.mutex);
3621 mutex_init(&adev->notifier_lock);
3622 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3623 mutex_init(&adev->benchmark_mutex);
3625 amdgpu_device_init_apu_flags(adev);
3627 r = amdgpu_device_check_arguments(adev);
3631 spin_lock_init(&adev->mmio_idx_lock);
3632 spin_lock_init(&adev->smc_idx_lock);
3633 spin_lock_init(&adev->pcie_idx_lock);
3634 spin_lock_init(&adev->uvd_ctx_idx_lock);
3635 spin_lock_init(&adev->didt_idx_lock);
3636 spin_lock_init(&adev->gc_cac_idx_lock);
3637 spin_lock_init(&adev->se_cac_idx_lock);
3638 spin_lock_init(&adev->audio_endpt_idx_lock);
3639 spin_lock_init(&adev->mm_stats.lock);
3641 INIT_LIST_HEAD(&adev->shadow_list);
3642 mutex_init(&adev->shadow_list_lock);
3644 INIT_LIST_HEAD(&adev->reset_list);
3646 INIT_LIST_HEAD(&adev->ras_list);
3648 INIT_DELAYED_WORK(&adev->delayed_init_work,
3649 amdgpu_device_delayed_init_work_handler);
3650 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3651 amdgpu_device_delay_enable_gfx_off);
3653 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3655 adev->gfx.gfx_off_req_count = 1;
3656 adev->gfx.gfx_off_residency = 0;
3657 adev->gfx.gfx_off_entrycount = 0;
3658 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3660 atomic_set(&adev->throttling_logging_enabled, 1);
3662 * If throttling continues, logging will be performed every minute
3663 * to avoid log flooding. "-1" is subtracted since the thermal
3664 * throttling interrupt comes every second. Thus, the total logging
3665 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3666 * for throttling interrupt) = 60 seconds.
3668 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3669 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3671 /* Registers mapping */
3672 /* TODO: block userspace mapping of io register */
3673 if (adev->asic_type >= CHIP_BONAIRE) {
3674 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3675 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3677 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3678 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3681 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3682 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3684 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3685 if (adev->rmmio == NULL) {
3688 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3689 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3691 amdgpu_device_get_pcie_info(adev);
3694 DRM_INFO("MCBP is enabled\n");
3697 * Reset domain needs to be present early, before XGMI hive discovered
3698 * (if any) and intitialized to use reset sem and in_gpu reset flag
3699 * early on during init and before calling to RREG32.
3701 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3702 if (!adev->reset_domain)
3705 /* detect hw virtualization here */
3706 amdgpu_detect_virtualization(adev);
3708 r = amdgpu_device_get_job_timeout_settings(adev);
3710 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3714 /* early init functions */
3715 r = amdgpu_device_ip_early_init(adev);
3719 /* Get rid of things like offb */
3720 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3724 /* Enable TMZ based on IP_VERSION */
3725 amdgpu_gmc_tmz_set(adev);
3727 amdgpu_gmc_noretry_set(adev);
3728 /* Need to get xgmi info early to decide the reset behavior*/
3729 if (adev->gmc.xgmi.supported) {
3730 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3735 /* enable PCIE atomic ops */
3736 if (amdgpu_sriov_vf(adev))
3737 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3738 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3739 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3741 adev->have_atomics_support =
3742 !pci_enable_atomic_ops_to_root(adev->pdev,
3743 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3744 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3745 if (!adev->have_atomics_support)
3746 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3748 /* doorbell bar mapping and doorbell index init*/
3749 amdgpu_device_doorbell_init(adev);
3751 if (amdgpu_emu_mode == 1) {
3752 /* post the asic on emulation mode */
3753 emu_soc_asic_init(adev);
3754 goto fence_driver_init;
3757 amdgpu_reset_init(adev);
3759 /* detect if we are with an SRIOV vbios */
3760 amdgpu_device_detect_sriov_bios(adev);
3762 /* check if we need to reset the asic
3763 * E.g., driver was not cleanly unloaded previously, etc.
3765 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3766 if (adev->gmc.xgmi.num_physical_nodes) {
3767 dev_info(adev->dev, "Pending hive reset.\n");
3768 adev->gmc.xgmi.pending_reset = true;
3769 /* Only need to init necessary block for SMU to handle the reset */
3770 for (i = 0; i < adev->num_ip_blocks; i++) {
3771 if (!adev->ip_blocks[i].status.valid)
3773 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3774 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3775 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3776 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3777 DRM_DEBUG("IP %s disabled for hw_init.\n",
3778 adev->ip_blocks[i].version->funcs->name);
3779 adev->ip_blocks[i].status.hw = true;
3783 r = amdgpu_asic_reset(adev);
3785 dev_err(adev->dev, "asic reset on init failed\n");
3791 pci_enable_pcie_error_reporting(adev->pdev);
3793 /* Post card if necessary */
3794 if (amdgpu_device_need_post(adev)) {
3796 dev_err(adev->dev, "no vBIOS found\n");
3800 DRM_INFO("GPU posting now...\n");
3801 r = amdgpu_device_asic_init(adev);
3803 dev_err(adev->dev, "gpu post error!\n");
3808 if (adev->is_atom_fw) {
3809 /* Initialize clocks */
3810 r = amdgpu_atomfirmware_get_clock_info(adev);
3812 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3813 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3817 /* Initialize clocks */
3818 r = amdgpu_atombios_get_clock_info(adev);
3820 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3821 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3824 /* init i2c buses */
3825 if (!amdgpu_device_has_dc_support(adev))
3826 amdgpu_atombios_i2c_init(adev);
3831 r = amdgpu_fence_driver_sw_init(adev);
3833 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3834 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3838 /* init the mode config */
3839 drm_mode_config_init(adev_to_drm(adev));
3841 r = amdgpu_device_ip_init(adev);
3843 /* failed in exclusive mode due to timeout */
3844 if (amdgpu_sriov_vf(adev) &&
3845 !amdgpu_sriov_runtime(adev) &&
3846 amdgpu_virt_mmio_blocked(adev) &&
3847 !amdgpu_virt_wait_reset(adev)) {
3848 dev_err(adev->dev, "VF exclusive mode timeout\n");
3849 /* Don't send request since VF is inactive. */
3850 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3851 adev->virt.ops = NULL;
3853 goto release_ras_con;
3855 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3856 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3857 goto release_ras_con;
3860 amdgpu_fence_driver_hw_init(adev);
3863 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3864 adev->gfx.config.max_shader_engines,
3865 adev->gfx.config.max_sh_per_se,
3866 adev->gfx.config.max_cu_per_sh,
3867 adev->gfx.cu_info.number);
3869 adev->accel_working = true;
3871 amdgpu_vm_check_compute_bug(adev);
3873 /* Initialize the buffer migration limit. */
3874 if (amdgpu_moverate >= 0)
3875 max_MBps = amdgpu_moverate;
3877 max_MBps = 8; /* Allow 8 MB/s. */
3878 /* Get a log2 for easy divisions. */
3879 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3881 r = amdgpu_pm_sysfs_init(adev);
3883 adev->pm_sysfs_en = false;
3884 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3886 adev->pm_sysfs_en = true;
3888 r = amdgpu_ucode_sysfs_init(adev);
3890 adev->ucode_sysfs_en = false;
3891 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3893 adev->ucode_sysfs_en = true;
3895 r = amdgpu_psp_sysfs_init(adev);
3897 adev->psp_sysfs_en = false;
3898 if (!amdgpu_sriov_vf(adev))
3899 DRM_ERROR("Creating psp sysfs failed\n");
3901 adev->psp_sysfs_en = true;
3904 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3905 * Otherwise the mgpu fan boost feature will be skipped due to the
3906 * gpu instance is counted less.
3908 amdgpu_register_gpu_instance(adev);
3910 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3911 * explicit gating rather than handling it automatically.
3913 if (!adev->gmc.xgmi.pending_reset) {
3914 r = amdgpu_device_ip_late_init(adev);
3916 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3917 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3918 goto release_ras_con;
3921 amdgpu_ras_resume(adev);
3922 queue_delayed_work(system_wq, &adev->delayed_init_work,
3923 msecs_to_jiffies(AMDGPU_RESUME_MS));
3926 if (amdgpu_sriov_vf(adev))
3927 flush_delayed_work(&adev->delayed_init_work);
3929 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3931 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3933 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3934 r = amdgpu_pmu_init(adev);
3936 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3938 /* Have stored pci confspace at hand for restore in sudden PCI error */
3939 if (amdgpu_device_cache_pci_state(adev->pdev))
3940 pci_restore_state(pdev);
3942 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3943 /* this will fail for cards that aren't VGA class devices, just
3945 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3946 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3948 if (amdgpu_device_supports_px(ddev)) {
3950 vga_switcheroo_register_client(adev->pdev,
3951 &amdgpu_switcheroo_ops, px);
3952 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3955 if (adev->gmc.xgmi.pending_reset)
3956 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3957 msecs_to_jiffies(AMDGPU_RESUME_MS));
3959 amdgpu_device_check_iommu_direct_map(adev);
3964 amdgpu_release_ras_context(adev);
3967 amdgpu_vf_error_trans_all(adev);
3972 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
3975 /* Clear all CPU mappings pointing to this device */
3976 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
3978 /* Unmap all mapped bars - Doorbell, registers and VRAM */
3979 amdgpu_device_doorbell_fini(adev);
3981 iounmap(adev->rmmio);
3983 if (adev->mman.aper_base_kaddr)
3984 iounmap(adev->mman.aper_base_kaddr);
3985 adev->mman.aper_base_kaddr = NULL;
3987 /* Memory manager related */
3988 if (!adev->gmc.xgmi.connected_to_cpu) {
3989 arch_phys_wc_del(adev->gmc.vram_mtrr);
3990 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
3995 * amdgpu_device_fini_hw - tear down the driver
3997 * @adev: amdgpu_device pointer
3999 * Tear down the driver info (all asics).
4000 * Called at driver shutdown.
4002 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4004 dev_info(adev->dev, "amdgpu: finishing device.\n");
4005 flush_delayed_work(&adev->delayed_init_work);
4006 adev->shutdown = true;
4008 /* make sure IB test finished before entering exclusive mode
4009 * to avoid preemption on IB test
4011 if (amdgpu_sriov_vf(adev)) {
4012 amdgpu_virt_request_full_gpu(adev, false);
4013 amdgpu_virt_fini_data_exchange(adev);
4016 /* disable all interrupts */
4017 amdgpu_irq_disable_all(adev);
4018 if (adev->mode_info.mode_config_initialized){
4019 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4020 drm_helper_force_disable_all(adev_to_drm(adev));
4022 drm_atomic_helper_shutdown(adev_to_drm(adev));
4024 amdgpu_fence_driver_hw_fini(adev);
4026 if (adev->mman.initialized)
4027 drain_workqueue(adev->mman.bdev.wq);
4029 if (adev->pm_sysfs_en)
4030 amdgpu_pm_sysfs_fini(adev);
4031 if (adev->ucode_sysfs_en)
4032 amdgpu_ucode_sysfs_fini(adev);
4033 if (adev->psp_sysfs_en)
4034 amdgpu_psp_sysfs_fini(adev);
4035 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4037 /* disable ras feature must before hw fini */
4038 amdgpu_ras_pre_fini(adev);
4040 amdgpu_device_ip_fini_early(adev);
4042 amdgpu_irq_fini_hw(adev);
4044 if (adev->mman.initialized)
4045 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4047 amdgpu_gart_dummy_page_fini(adev);
4049 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4050 amdgpu_device_unmap_mmio(adev);
4054 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4058 amdgpu_fence_driver_sw_fini(adev);
4059 amdgpu_device_ip_fini(adev);
4060 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4061 adev->accel_working = false;
4062 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4064 amdgpu_reset_fini(adev);
4066 /* free i2c buses */
4067 if (!amdgpu_device_has_dc_support(adev))
4068 amdgpu_i2c_fini(adev);
4070 if (amdgpu_emu_mode != 1)
4071 amdgpu_atombios_fini(adev);
4075 if (amdgpu_device_supports_px(adev_to_drm(adev))) {
4076 vga_switcheroo_unregister_client(adev->pdev);
4077 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4079 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4080 vga_client_unregister(adev->pdev);
4082 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4084 iounmap(adev->rmmio);
4086 amdgpu_device_doorbell_fini(adev);
4090 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4091 amdgpu_pmu_fini(adev);
4092 if (adev->mman.discovery_bin)
4093 amdgpu_discovery_fini(adev);
4095 amdgpu_reset_put_reset_domain(adev->reset_domain);
4096 adev->reset_domain = NULL;
4098 kfree(adev->pci_state);
4103 * amdgpu_device_evict_resources - evict device resources
4104 * @adev: amdgpu device object
4106 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4107 * of the vram memory type. Mainly used for evicting device resources
4111 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4115 /* No need to evict vram on APUs for suspend to ram or s2idle */
4116 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4119 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4121 DRM_WARN("evicting device resources failed\n");
4129 * amdgpu_device_suspend - initiate device suspend
4131 * @dev: drm dev pointer
4132 * @fbcon : notify the fbdev of suspend
4134 * Puts the hw in the suspend state (all asics).
4135 * Returns 0 for success or an error on failure.
4136 * Called at driver suspend.
4138 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4140 struct amdgpu_device *adev = drm_to_adev(dev);
4143 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4146 adev->in_suspend = true;
4148 /* Evict the majority of BOs before grabbing the full access */
4149 r = amdgpu_device_evict_resources(adev);
4153 if (amdgpu_sriov_vf(adev)) {
4154 amdgpu_virt_fini_data_exchange(adev);
4155 r = amdgpu_virt_request_full_gpu(adev, false);
4160 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4161 DRM_WARN("smart shift update failed\n");
4164 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4166 cancel_delayed_work_sync(&adev->delayed_init_work);
4168 amdgpu_ras_suspend(adev);
4170 amdgpu_device_ip_suspend_phase1(adev);
4173 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4175 r = amdgpu_device_evict_resources(adev);
4179 amdgpu_fence_driver_hw_fini(adev);
4181 amdgpu_device_ip_suspend_phase2(adev);
4183 if (amdgpu_sriov_vf(adev))
4184 amdgpu_virt_release_full_gpu(adev, false);
4190 * amdgpu_device_resume - initiate device resume
4192 * @dev: drm dev pointer
4193 * @fbcon : notify the fbdev of resume
4195 * Bring the hw back to operating state (all asics).
4196 * Returns 0 for success or an error on failure.
4197 * Called at driver resume.
4199 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4201 struct amdgpu_device *adev = drm_to_adev(dev);
4204 if (amdgpu_sriov_vf(adev)) {
4205 r = amdgpu_virt_request_full_gpu(adev, true);
4210 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4214 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4217 if (amdgpu_device_need_post(adev)) {
4218 r = amdgpu_device_asic_init(adev);
4220 dev_err(adev->dev, "amdgpu asic init failed\n");
4223 r = amdgpu_device_ip_resume(adev);
4226 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4229 amdgpu_fence_driver_hw_init(adev);
4231 r = amdgpu_device_ip_late_init(adev);
4235 queue_delayed_work(system_wq, &adev->delayed_init_work,
4236 msecs_to_jiffies(AMDGPU_RESUME_MS));
4238 if (!adev->in_s0ix) {
4239 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4245 if (amdgpu_sriov_vf(adev)) {
4246 amdgpu_virt_init_data_exchange(adev);
4247 amdgpu_virt_release_full_gpu(adev, true);
4253 /* Make sure IB tests flushed */
4254 flush_delayed_work(&adev->delayed_init_work);
4257 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4259 amdgpu_ras_resume(adev);
4261 if (adev->mode_info.num_crtc) {
4263 * Most of the connector probing functions try to acquire runtime pm
4264 * refs to ensure that the GPU is powered on when connector polling is
4265 * performed. Since we're calling this from a runtime PM callback,
4266 * trying to acquire rpm refs will cause us to deadlock.
4268 * Since we're guaranteed to be holding the rpm lock, it's safe to
4269 * temporarily disable the rpm helpers so this doesn't deadlock us.
4272 dev->dev->power.disable_depth++;
4274 if (!adev->dc_enabled)
4275 drm_helper_hpd_irq_event(dev);
4277 drm_kms_helper_hotplug_event(dev);
4279 dev->dev->power.disable_depth--;
4282 adev->in_suspend = false;
4284 if (adev->enable_mes)
4285 amdgpu_mes_self_test(adev);
4287 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4288 DRM_WARN("smart shift update failed\n");
4294 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4296 * @adev: amdgpu_device pointer
4298 * The list of all the hardware IPs that make up the asic is walked and
4299 * the check_soft_reset callbacks are run. check_soft_reset determines
4300 * if the asic is still hung or not.
4301 * Returns true if any of the IPs are still in a hung state, false if not.
4303 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4306 bool asic_hang = false;
4308 if (amdgpu_sriov_vf(adev))
4311 if (amdgpu_asic_need_full_reset(adev))
4314 for (i = 0; i < adev->num_ip_blocks; i++) {
4315 if (!adev->ip_blocks[i].status.valid)
4317 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4318 adev->ip_blocks[i].status.hang =
4319 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4320 if (adev->ip_blocks[i].status.hang) {
4321 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4329 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4331 * @adev: amdgpu_device pointer
4333 * The list of all the hardware IPs that make up the asic is walked and the
4334 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4335 * handles any IP specific hardware or software state changes that are
4336 * necessary for a soft reset to succeed.
4337 * Returns 0 on success, negative error code on failure.
4339 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4343 for (i = 0; i < adev->num_ip_blocks; i++) {
4344 if (!adev->ip_blocks[i].status.valid)
4346 if (adev->ip_blocks[i].status.hang &&
4347 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4348 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4358 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4360 * @adev: amdgpu_device pointer
4362 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4363 * reset is necessary to recover.
4364 * Returns true if a full asic reset is required, false if not.
4366 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4370 if (amdgpu_asic_need_full_reset(adev))
4373 for (i = 0; i < adev->num_ip_blocks; i++) {
4374 if (!adev->ip_blocks[i].status.valid)
4376 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4377 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4378 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4379 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4380 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4381 if (adev->ip_blocks[i].status.hang) {
4382 dev_info(adev->dev, "Some block need full reset!\n");
4391 * amdgpu_device_ip_soft_reset - do a soft reset
4393 * @adev: amdgpu_device pointer
4395 * The list of all the hardware IPs that make up the asic is walked and the
4396 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4397 * IP specific hardware or software state changes that are necessary to soft
4399 * Returns 0 on success, negative error code on failure.
4401 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4405 for (i = 0; i < adev->num_ip_blocks; i++) {
4406 if (!adev->ip_blocks[i].status.valid)
4408 if (adev->ip_blocks[i].status.hang &&
4409 adev->ip_blocks[i].version->funcs->soft_reset) {
4410 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4420 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4422 * @adev: amdgpu_device pointer
4424 * The list of all the hardware IPs that make up the asic is walked and the
4425 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4426 * handles any IP specific hardware or software state changes that are
4427 * necessary after the IP has been soft reset.
4428 * Returns 0 on success, negative error code on failure.
4430 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4434 for (i = 0; i < adev->num_ip_blocks; i++) {
4435 if (!adev->ip_blocks[i].status.valid)
4437 if (adev->ip_blocks[i].status.hang &&
4438 adev->ip_blocks[i].version->funcs->post_soft_reset)
4439 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4448 * amdgpu_device_recover_vram - Recover some VRAM contents
4450 * @adev: amdgpu_device pointer
4452 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4453 * restore things like GPUVM page tables after a GPU reset where
4454 * the contents of VRAM might be lost.
4457 * 0 on success, negative error code on failure.
4459 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4461 struct dma_fence *fence = NULL, *next = NULL;
4462 struct amdgpu_bo *shadow;
4463 struct amdgpu_bo_vm *vmbo;
4466 if (amdgpu_sriov_runtime(adev))
4467 tmo = msecs_to_jiffies(8000);
4469 tmo = msecs_to_jiffies(100);
4471 dev_info(adev->dev, "recover vram bo from shadow start\n");
4472 mutex_lock(&adev->shadow_list_lock);
4473 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4475 /* No need to recover an evicted BO */
4476 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4477 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4478 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4481 r = amdgpu_bo_restore_shadow(shadow, &next);
4486 tmo = dma_fence_wait_timeout(fence, false, tmo);
4487 dma_fence_put(fence);
4492 } else if (tmo < 0) {
4500 mutex_unlock(&adev->shadow_list_lock);
4503 tmo = dma_fence_wait_timeout(fence, false, tmo);
4504 dma_fence_put(fence);
4506 if (r < 0 || tmo <= 0) {
4507 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4511 dev_info(adev->dev, "recover vram bo from shadow done\n");
4517 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4519 * @adev: amdgpu_device pointer
4520 * @from_hypervisor: request from hypervisor
4522 * do VF FLR and reinitialize Asic
4523 * return 0 means succeeded otherwise failed
4525 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4526 bool from_hypervisor)
4529 struct amdgpu_hive_info *hive = NULL;
4530 int retry_limit = 0;
4533 amdgpu_amdkfd_pre_reset(adev);
4535 if (from_hypervisor)
4536 r = amdgpu_virt_request_full_gpu(adev, true);
4538 r = amdgpu_virt_reset_gpu(adev);
4542 /* Resume IP prior to SMC */
4543 r = amdgpu_device_ip_reinit_early_sriov(adev);
4547 amdgpu_virt_init_data_exchange(adev);
4549 r = amdgpu_device_fw_loading(adev);
4553 /* now we are okay to resume SMC/CP/SDMA */
4554 r = amdgpu_device_ip_reinit_late_sriov(adev);
4558 hive = amdgpu_get_xgmi_hive(adev);
4559 /* Update PSP FW topology after reset */
4560 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4561 r = amdgpu_xgmi_update_topology(hive, adev);
4564 amdgpu_put_xgmi_hive(hive);
4567 amdgpu_irq_gpu_reset_resume_helper(adev);
4568 r = amdgpu_ib_ring_tests(adev);
4570 amdgpu_amdkfd_post_reset(adev);
4574 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4575 amdgpu_inc_vram_lost(adev);
4576 r = amdgpu_device_recover_vram(adev);
4578 amdgpu_virt_release_full_gpu(adev, true);
4580 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4581 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4585 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4592 * amdgpu_device_has_job_running - check if there is any job in mirror list
4594 * @adev: amdgpu_device pointer
4596 * check if there is any job in mirror list
4598 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4601 struct drm_sched_job *job;
4603 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4604 struct amdgpu_ring *ring = adev->rings[i];
4606 if (!ring || !ring->sched.thread)
4609 spin_lock(&ring->sched.job_list_lock);
4610 job = list_first_entry_or_null(&ring->sched.pending_list,
4611 struct drm_sched_job, list);
4612 spin_unlock(&ring->sched.job_list_lock);
4620 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4622 * @adev: amdgpu_device pointer
4624 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4627 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4630 if (amdgpu_gpu_recovery == 0)
4633 /* Skip soft reset check in fatal error mode */
4634 if (!amdgpu_ras_is_poison_mode_supported(adev))
4637 if (amdgpu_sriov_vf(adev))
4640 if (amdgpu_gpu_recovery == -1) {
4641 switch (adev->asic_type) {
4642 #ifdef CONFIG_DRM_AMDGPU_SI
4649 #ifdef CONFIG_DRM_AMDGPU_CIK
4656 case CHIP_CYAN_SKILLFISH:
4666 dev_info(adev->dev, "GPU recovery disabled.\n");
4670 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4675 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4677 dev_info(adev->dev, "GPU mode1 reset\n");
4680 pci_clear_master(adev->pdev);
4682 amdgpu_device_cache_pci_state(adev->pdev);
4684 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4685 dev_info(adev->dev, "GPU smu mode1 reset\n");
4686 ret = amdgpu_dpm_mode1_reset(adev);
4688 dev_info(adev->dev, "GPU psp mode1 reset\n");
4689 ret = psp_gpu_reset(adev);
4693 dev_err(adev->dev, "GPU mode1 reset failed\n");
4695 amdgpu_device_load_pci_state(adev->pdev);
4697 /* wait for asic to come out of reset */
4698 for (i = 0; i < adev->usec_timeout; i++) {
4699 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4701 if (memsize != 0xffffffff)
4706 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4710 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4711 struct amdgpu_reset_context *reset_context)
4714 struct amdgpu_job *job = NULL;
4715 bool need_full_reset =
4716 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4718 if (reset_context->reset_req_dev == adev)
4719 job = reset_context->job;
4721 if (amdgpu_sriov_vf(adev)) {
4722 /* stop the data exchange thread */
4723 amdgpu_virt_fini_data_exchange(adev);
4726 amdgpu_fence_driver_isr_toggle(adev, true);
4728 /* block all schedulers and reset given job's ring */
4729 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4730 struct amdgpu_ring *ring = adev->rings[i];
4732 if (!ring || !ring->sched.thread)
4735 /*clear job fence from fence drv to avoid force_completion
4736 *leave NULL and vm flush fence in fence drv */
4737 amdgpu_fence_driver_clear_job_fences(ring);
4739 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4740 amdgpu_fence_driver_force_completion(ring);
4743 amdgpu_fence_driver_isr_toggle(adev, false);
4746 drm_sched_increase_karma(&job->base);
4748 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4749 /* If reset handler not implemented, continue; otherwise return */
4755 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4756 if (!amdgpu_sriov_vf(adev)) {
4758 if (!need_full_reset)
4759 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4761 if (!need_full_reset && amdgpu_gpu_recovery &&
4762 amdgpu_device_ip_check_soft_reset(adev)) {
4763 amdgpu_device_ip_pre_soft_reset(adev);
4764 r = amdgpu_device_ip_soft_reset(adev);
4765 amdgpu_device_ip_post_soft_reset(adev);
4766 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4767 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4768 need_full_reset = true;
4772 if (need_full_reset)
4773 r = amdgpu_device_ip_suspend(adev);
4774 if (need_full_reset)
4775 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4777 clear_bit(AMDGPU_NEED_FULL_RESET,
4778 &reset_context->flags);
4784 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4788 lockdep_assert_held(&adev->reset_domain->sem);
4790 for (i = 0; i < adev->num_regs; i++) {
4791 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4792 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4793 adev->reset_dump_reg_value[i]);
4799 #ifdef CONFIG_DEV_COREDUMP
4800 static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4801 size_t count, void *data, size_t datalen)
4803 struct drm_printer p;
4804 struct amdgpu_device *adev = data;
4805 struct drm_print_iterator iter;
4810 iter.start = offset;
4811 iter.remain = count;
4813 p = drm_coredump_printer(&iter);
4815 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4816 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4817 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4818 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4819 if (adev->reset_task_info.pid)
4820 drm_printf(&p, "process_name: %s PID: %d\n",
4821 adev->reset_task_info.process_name,
4822 adev->reset_task_info.pid);
4824 if (adev->reset_vram_lost)
4825 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4826 if (adev->num_regs) {
4827 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4829 for (i = 0; i < adev->num_regs; i++)
4830 drm_printf(&p, "0x%08x: 0x%08x\n",
4831 adev->reset_dump_reg_list[i],
4832 adev->reset_dump_reg_value[i]);
4835 return count - iter.remain;
4838 static void amdgpu_devcoredump_free(void *data)
4842 static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4844 struct drm_device *dev = adev_to_drm(adev);
4846 ktime_get_ts64(&adev->reset_time);
4847 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
4848 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4852 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4853 struct amdgpu_reset_context *reset_context)
4855 struct amdgpu_device *tmp_adev = NULL;
4856 bool need_full_reset, skip_hw_reset, vram_lost = false;
4858 bool gpu_reset_for_dev_remove = 0;
4860 /* Try reset handler method first */
4861 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4863 amdgpu_reset_reg_dumps(tmp_adev);
4865 reset_context->reset_device_list = device_list_handle;
4866 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4867 /* If reset handler not implemented, continue; otherwise return */
4873 /* Reset handler not implemented, use the default method */
4875 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4876 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4878 gpu_reset_for_dev_remove =
4879 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4880 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4883 * ASIC reset has to be done on all XGMI hive nodes ASAP
4884 * to allow proper links negotiation in FW (within 1 sec)
4886 if (!skip_hw_reset && need_full_reset) {
4887 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4888 /* For XGMI run all resets in parallel to speed up the process */
4889 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4890 tmp_adev->gmc.xgmi.pending_reset = false;
4891 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4894 r = amdgpu_asic_reset(tmp_adev);
4897 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4898 r, adev_to_drm(tmp_adev)->unique);
4903 /* For XGMI wait for all resets to complete before proceed */
4905 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4906 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4907 flush_work(&tmp_adev->xgmi_reset_work);
4908 r = tmp_adev->asic_reset_res;
4916 if (!r && amdgpu_ras_intr_triggered()) {
4917 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4918 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4919 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4920 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4923 amdgpu_ras_intr_cleared();
4926 /* Since the mode1 reset affects base ip blocks, the
4927 * phase1 ip blocks need to be resumed. Otherwise there
4928 * will be a BIOS signature error and the psp bootloader
4929 * can't load kdb on the next amdgpu install.
4931 if (gpu_reset_for_dev_remove) {
4932 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
4933 amdgpu_device_ip_resume_phase1(tmp_adev);
4938 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4939 if (need_full_reset) {
4941 r = amdgpu_device_asic_init(tmp_adev);
4943 dev_warn(tmp_adev->dev, "asic atom init failed!");
4945 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4946 r = amdgpu_amdkfd_resume_iommu(tmp_adev);
4950 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4954 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4955 #ifdef CONFIG_DEV_COREDUMP
4956 tmp_adev->reset_vram_lost = vram_lost;
4957 memset(&tmp_adev->reset_task_info, 0,
4958 sizeof(tmp_adev->reset_task_info));
4959 if (reset_context->job && reset_context->job->vm)
4960 tmp_adev->reset_task_info =
4961 reset_context->job->vm->task_info;
4962 amdgpu_reset_capture_coredumpm(tmp_adev);
4965 DRM_INFO("VRAM is lost due to GPU reset!\n");
4966 amdgpu_inc_vram_lost(tmp_adev);
4969 r = amdgpu_device_fw_loading(tmp_adev);
4973 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4978 amdgpu_device_fill_reset_magic(tmp_adev);
4981 * Add this ASIC as tracked as reset was already
4982 * complete successfully.
4984 amdgpu_register_gpu_instance(tmp_adev);
4986 if (!reset_context->hive &&
4987 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4988 amdgpu_xgmi_add_device(tmp_adev);
4990 r = amdgpu_device_ip_late_init(tmp_adev);
4994 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
4997 * The GPU enters bad state once faulty pages
4998 * by ECC has reached the threshold, and ras
4999 * recovery is scheduled next. So add one check
5000 * here to break recovery if it indeed exceeds
5001 * bad page threshold, and remind user to
5002 * retire this GPU or setting one bigger
5003 * bad_page_threshold value to fix this once
5004 * probing driver again.
5006 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5008 amdgpu_ras_resume(tmp_adev);
5014 /* Update PSP FW topology after reset */
5015 if (reset_context->hive &&
5016 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5017 r = amdgpu_xgmi_update_topology(
5018 reset_context->hive, tmp_adev);
5024 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5025 r = amdgpu_ib_ring_tests(tmp_adev);
5027 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5028 need_full_reset = true;
5035 r = amdgpu_device_recover_vram(tmp_adev);
5037 tmp_adev->asic_reset_res = r;
5041 if (need_full_reset)
5042 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5044 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5048 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5051 switch (amdgpu_asic_reset_method(adev)) {
5052 case AMD_RESET_METHOD_MODE1:
5053 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5055 case AMD_RESET_METHOD_MODE2:
5056 adev->mp1_state = PP_MP1_STATE_RESET;
5059 adev->mp1_state = PP_MP1_STATE_NONE;
5064 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5066 amdgpu_vf_error_trans_all(adev);
5067 adev->mp1_state = PP_MP1_STATE_NONE;
5070 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5072 struct pci_dev *p = NULL;
5074 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5075 adev->pdev->bus->number, 1);
5077 pm_runtime_enable(&(p->dev));
5078 pm_runtime_resume(&(p->dev));
5084 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5086 enum amd_reset_method reset_method;
5087 struct pci_dev *p = NULL;
5091 * For now, only BACO and mode1 reset are confirmed
5092 * to suffer the audio issue without proper suspended.
5094 reset_method = amdgpu_asic_reset_method(adev);
5095 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5096 (reset_method != AMD_RESET_METHOD_MODE1))
5099 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5100 adev->pdev->bus->number, 1);
5104 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5107 * If we cannot get the audio device autosuspend delay,
5108 * a fixed 4S interval will be used. Considering 3S is
5109 * the audio controller default autosuspend delay setting.
5110 * 4S used here is guaranteed to cover that.
5112 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5114 while (!pm_runtime_status_suspended(&(p->dev))) {
5115 if (!pm_runtime_suspend(&(p->dev)))
5118 if (expires < ktime_get_mono_fast_ns()) {
5119 dev_warn(adev->dev, "failed to suspend display audio\n");
5121 /* TODO: abort the succeeding gpu reset? */
5126 pm_runtime_disable(&(p->dev));
5132 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5134 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5136 #if defined(CONFIG_DEBUG_FS)
5137 if (!amdgpu_sriov_vf(adev))
5138 cancel_work(&adev->reset_work);
5142 cancel_work(&adev->kfd.reset_work);
5144 if (amdgpu_sriov_vf(adev))
5145 cancel_work(&adev->virt.flr_work);
5147 if (con && adev->ras_enabled)
5148 cancel_work(&con->recovery_work);
5153 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5155 * @adev: amdgpu_device pointer
5156 * @job: which job trigger hang
5158 * Attempt to reset the GPU if it has hung (all asics).
5159 * Attempt to do soft-reset or full-reset and reinitialize Asic
5160 * Returns 0 for success or an error on failure.
5163 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5164 struct amdgpu_job *job,
5165 struct amdgpu_reset_context *reset_context)
5167 struct list_head device_list, *device_list_handle = NULL;
5168 bool job_signaled = false;
5169 struct amdgpu_hive_info *hive = NULL;
5170 struct amdgpu_device *tmp_adev = NULL;
5172 bool need_emergency_restart = false;
5173 bool audio_suspended = false;
5174 bool gpu_reset_for_dev_remove = false;
5176 gpu_reset_for_dev_remove =
5177 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5178 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5181 * Special case: RAS triggered and full reset isn't supported
5183 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5186 * Flush RAM to disk so that after reboot
5187 * the user can read log and see why the system rebooted.
5189 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5190 DRM_WARN("Emergency reboot.");
5193 emergency_restart();
5196 dev_info(adev->dev, "GPU %s begin!\n",
5197 need_emergency_restart ? "jobs stop":"reset");
5199 if (!amdgpu_sriov_vf(adev))
5200 hive = amdgpu_get_xgmi_hive(adev);
5202 mutex_lock(&hive->hive_lock);
5204 reset_context->job = job;
5205 reset_context->hive = hive;
5207 * Build list of devices to reset.
5208 * In case we are in XGMI hive mode, resort the device list
5209 * to put adev in the 1st position.
5211 INIT_LIST_HEAD(&device_list);
5212 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5213 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5214 list_add_tail(&tmp_adev->reset_list, &device_list);
5215 if (gpu_reset_for_dev_remove && adev->shutdown)
5216 tmp_adev->shutdown = true;
5218 if (!list_is_first(&adev->reset_list, &device_list))
5219 list_rotate_to_front(&adev->reset_list, &device_list);
5220 device_list_handle = &device_list;
5222 list_add_tail(&adev->reset_list, &device_list);
5223 device_list_handle = &device_list;
5226 /* We need to lock reset domain only once both for XGMI and single device */
5227 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5229 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5231 /* block all schedulers and reset given job's ring */
5232 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5234 amdgpu_device_set_mp1_state(tmp_adev);
5237 * Try to put the audio codec into suspend state
5238 * before gpu reset started.
5240 * Due to the power domain of the graphics device
5241 * is shared with AZ power domain. Without this,
5242 * we may change the audio hardware from behind
5243 * the audio driver's back. That will trigger
5244 * some audio codec errors.
5246 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5247 audio_suspended = true;
5249 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5251 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5253 if (!amdgpu_sriov_vf(tmp_adev))
5254 amdgpu_amdkfd_pre_reset(tmp_adev);
5257 * Mark these ASICs to be reseted as untracked first
5258 * And add them back after reset completed
5260 amdgpu_unregister_gpu_instance(tmp_adev);
5262 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5264 /* disable ras on ALL IPs */
5265 if (!need_emergency_restart &&
5266 amdgpu_device_ip_need_full_reset(tmp_adev))
5267 amdgpu_ras_suspend(tmp_adev);
5269 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5270 struct amdgpu_ring *ring = tmp_adev->rings[i];
5272 if (!ring || !ring->sched.thread)
5275 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5277 if (need_emergency_restart)
5278 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5280 atomic_inc(&tmp_adev->gpu_reset_counter);
5283 if (need_emergency_restart)
5284 goto skip_sched_resume;
5287 * Must check guilty signal here since after this point all old
5288 * HW fences are force signaled.
5290 * job->base holds a reference to parent fence
5292 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5293 job_signaled = true;
5294 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5298 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5299 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5300 if (gpu_reset_for_dev_remove) {
5301 /* Workaroud for ASICs need to disable SMC first */
5302 amdgpu_device_smu_fini_early(tmp_adev);
5304 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5305 /*TODO Should we stop ?*/
5307 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5308 r, adev_to_drm(tmp_adev)->unique);
5309 tmp_adev->asic_reset_res = r;
5313 * Drop all pending non scheduler resets. Scheduler resets
5314 * were already dropped during drm_sched_stop
5316 amdgpu_device_stop_pending_resets(tmp_adev);
5319 /* Actual ASIC resets if needed.*/
5320 /* Host driver will handle XGMI hive reset for SRIOV */
5321 if (amdgpu_sriov_vf(adev)) {
5322 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5324 adev->asic_reset_res = r;
5326 /* Aldebaran supports ras in SRIOV, so need resume ras during reset */
5327 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
5328 amdgpu_ras_resume(adev);
5330 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5331 if (r && r == -EAGAIN)
5334 if (!r && gpu_reset_for_dev_remove)
5340 /* Post ASIC reset for all devs .*/
5341 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5343 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5344 struct amdgpu_ring *ring = tmp_adev->rings[i];
5346 if (!ring || !ring->sched.thread)
5349 drm_sched_start(&ring->sched, true);
5352 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5353 amdgpu_mes_self_test(tmp_adev);
5355 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
5356 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5359 if (tmp_adev->asic_reset_res)
5360 r = tmp_adev->asic_reset_res;
5362 tmp_adev->asic_reset_res = 0;
5365 /* bad news, how to tell it to userspace ? */
5366 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5367 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5369 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5370 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5371 DRM_WARN("smart shift update failed\n");
5376 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5377 /* unlock kfd: SRIOV would do it separately */
5378 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5379 amdgpu_amdkfd_post_reset(tmp_adev);
5381 /* kfd_post_reset will do nothing if kfd device is not initialized,
5382 * need to bring up kfd here if it's not be initialized before
5384 if (!adev->kfd.init_complete)
5385 amdgpu_amdkfd_device_init(adev);
5387 if (audio_suspended)
5388 amdgpu_device_resume_display_audio(tmp_adev);
5390 amdgpu_device_unset_mp1_state(tmp_adev);
5392 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5396 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5398 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5401 mutex_unlock(&hive->hive_lock);
5402 amdgpu_put_xgmi_hive(hive);
5406 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5408 atomic_set(&adev->reset_domain->reset_res, r);
5413 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5415 * @adev: amdgpu_device pointer
5417 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5418 * and lanes) of the slot the device is in. Handles APUs and
5419 * virtualized environments where PCIE config space may not be available.
5421 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5423 struct pci_dev *pdev;
5424 enum pci_bus_speed speed_cap, platform_speed_cap;
5425 enum pcie_link_width platform_link_width;
5427 if (amdgpu_pcie_gen_cap)
5428 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5430 if (amdgpu_pcie_lane_cap)
5431 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5433 /* covers APUs as well */
5434 if (pci_is_root_bus(adev->pdev->bus)) {
5435 if (adev->pm.pcie_gen_mask == 0)
5436 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5437 if (adev->pm.pcie_mlw_mask == 0)
5438 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5442 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5445 pcie_bandwidth_available(adev->pdev, NULL,
5446 &platform_speed_cap, &platform_link_width);
5448 if (adev->pm.pcie_gen_mask == 0) {
5451 speed_cap = pcie_get_speed_cap(pdev);
5452 if (speed_cap == PCI_SPEED_UNKNOWN) {
5453 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5454 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5455 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5457 if (speed_cap == PCIE_SPEED_32_0GT)
5458 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5459 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5460 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5461 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5462 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5463 else if (speed_cap == PCIE_SPEED_16_0GT)
5464 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5465 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5466 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5467 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5468 else if (speed_cap == PCIE_SPEED_8_0GT)
5469 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5470 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5471 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5472 else if (speed_cap == PCIE_SPEED_5_0GT)
5473 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5474 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5476 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5479 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5480 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5481 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5483 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5484 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5485 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5486 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5487 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5488 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5489 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5490 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5491 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5492 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5493 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5494 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5495 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5496 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5497 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5498 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5499 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5500 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5502 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5506 if (adev->pm.pcie_mlw_mask == 0) {
5507 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5508 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5510 switch (platform_link_width) {
5512 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5513 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5514 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5515 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5516 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5517 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5518 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5521 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5522 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5523 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5524 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5525 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5526 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5529 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5530 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5531 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5532 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5533 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5536 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5537 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5538 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5539 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5542 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5543 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5544 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5547 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5548 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5551 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5561 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5563 * @adev: amdgpu_device pointer
5564 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5566 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5567 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5570 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5571 struct amdgpu_device *peer_adev)
5573 #ifdef CONFIG_HSA_AMD_P2P
5574 uint64_t address_mask = peer_adev->dev->dma_mask ?
5575 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5576 resource_size_t aper_limit =
5577 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5579 !adev->gmc.xgmi.connected_to_cpu &&
5580 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5582 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5583 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5584 !(adev->gmc.aper_base & address_mask ||
5585 aper_limit & address_mask));
5591 int amdgpu_device_baco_enter(struct drm_device *dev)
5593 struct amdgpu_device *adev = drm_to_adev(dev);
5594 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5596 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5599 if (ras && adev->ras_enabled &&
5600 adev->nbio.funcs->enable_doorbell_interrupt)
5601 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5603 return amdgpu_dpm_baco_enter(adev);
5606 int amdgpu_device_baco_exit(struct drm_device *dev)
5608 struct amdgpu_device *adev = drm_to_adev(dev);
5609 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5612 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5615 ret = amdgpu_dpm_baco_exit(adev);
5619 if (ras && adev->ras_enabled &&
5620 adev->nbio.funcs->enable_doorbell_interrupt)
5621 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5623 if (amdgpu_passthrough(adev) &&
5624 adev->nbio.funcs->clear_doorbell_interrupt)
5625 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5631 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5632 * @pdev: PCI device struct
5633 * @state: PCI channel state
5635 * Description: Called when a PCI error is detected.
5637 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5639 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5641 struct drm_device *dev = pci_get_drvdata(pdev);
5642 struct amdgpu_device *adev = drm_to_adev(dev);
5645 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5647 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5648 DRM_WARN("No support for XGMI hive yet...");
5649 return PCI_ERS_RESULT_DISCONNECT;
5652 adev->pci_channel_state = state;
5655 case pci_channel_io_normal:
5656 return PCI_ERS_RESULT_CAN_RECOVER;
5657 /* Fatal error, prepare for slot reset */
5658 case pci_channel_io_frozen:
5660 * Locking adev->reset_domain->sem will prevent any external access
5661 * to GPU during PCI error recovery
5663 amdgpu_device_lock_reset_domain(adev->reset_domain);
5664 amdgpu_device_set_mp1_state(adev);
5667 * Block any work scheduling as we do for regular GPU reset
5668 * for the duration of the recovery
5670 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5671 struct amdgpu_ring *ring = adev->rings[i];
5673 if (!ring || !ring->sched.thread)
5676 drm_sched_stop(&ring->sched, NULL);
5678 atomic_inc(&adev->gpu_reset_counter);
5679 return PCI_ERS_RESULT_NEED_RESET;
5680 case pci_channel_io_perm_failure:
5681 /* Permanent error, prepare for device removal */
5682 return PCI_ERS_RESULT_DISCONNECT;
5685 return PCI_ERS_RESULT_NEED_RESET;
5689 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5690 * @pdev: pointer to PCI device
5692 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5695 DRM_INFO("PCI error: mmio enabled callback!!\n");
5697 /* TODO - dump whatever for debugging purposes */
5699 /* This called only if amdgpu_pci_error_detected returns
5700 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5701 * works, no need to reset slot.
5704 return PCI_ERS_RESULT_RECOVERED;
5708 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5709 * @pdev: PCI device struct
5711 * Description: This routine is called by the pci error recovery
5712 * code after the PCI slot has been reset, just before we
5713 * should resume normal operations.
5715 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5717 struct drm_device *dev = pci_get_drvdata(pdev);
5718 struct amdgpu_device *adev = drm_to_adev(dev);
5720 struct amdgpu_reset_context reset_context;
5722 struct list_head device_list;
5724 DRM_INFO("PCI error: slot reset callback!!\n");
5726 memset(&reset_context, 0, sizeof(reset_context));
5728 INIT_LIST_HEAD(&device_list);
5729 list_add_tail(&adev->reset_list, &device_list);
5731 /* wait for asic to come out of reset */
5734 /* Restore PCI confspace */
5735 amdgpu_device_load_pci_state(pdev);
5737 /* confirm ASIC came out of reset */
5738 for (i = 0; i < adev->usec_timeout; i++) {
5739 memsize = amdgpu_asic_get_config_memsize(adev);
5741 if (memsize != 0xffffffff)
5745 if (memsize == 0xffffffff) {
5750 reset_context.method = AMD_RESET_METHOD_NONE;
5751 reset_context.reset_req_dev = adev;
5752 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5753 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5755 adev->no_hw_access = true;
5756 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5757 adev->no_hw_access = false;
5761 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5765 if (amdgpu_device_cache_pci_state(adev->pdev))
5766 pci_restore_state(adev->pdev);
5768 DRM_INFO("PCIe error recovery succeeded\n");
5770 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5771 amdgpu_device_unset_mp1_state(adev);
5772 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5775 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5779 * amdgpu_pci_resume() - resume normal ops after PCI reset
5780 * @pdev: pointer to PCI device
5782 * Called when the error recovery driver tells us that its
5783 * OK to resume normal operation.
5785 void amdgpu_pci_resume(struct pci_dev *pdev)
5787 struct drm_device *dev = pci_get_drvdata(pdev);
5788 struct amdgpu_device *adev = drm_to_adev(dev);
5792 DRM_INFO("PCI error: resume callback!!\n");
5794 /* Only continue execution for the case of pci_channel_io_frozen */
5795 if (adev->pci_channel_state != pci_channel_io_frozen)
5798 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5799 struct amdgpu_ring *ring = adev->rings[i];
5801 if (!ring || !ring->sched.thread)
5804 drm_sched_start(&ring->sched, true);
5807 amdgpu_device_unset_mp1_state(adev);
5808 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5811 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5813 struct drm_device *dev = pci_get_drvdata(pdev);
5814 struct amdgpu_device *adev = drm_to_adev(dev);
5817 r = pci_save_state(pdev);
5819 kfree(adev->pci_state);
5821 adev->pci_state = pci_store_saved_state(pdev);
5823 if (!adev->pci_state) {
5824 DRM_ERROR("Failed to store PCI saved state");
5828 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5835 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5837 struct drm_device *dev = pci_get_drvdata(pdev);
5838 struct amdgpu_device *adev = drm_to_adev(dev);
5841 if (!adev->pci_state)
5844 r = pci_load_saved_state(pdev, adev->pci_state);
5847 pci_restore_state(pdev);
5849 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5856 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5857 struct amdgpu_ring *ring)
5859 #ifdef CONFIG_X86_64
5860 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5863 if (adev->gmc.xgmi.connected_to_cpu)
5866 if (ring && ring->funcs->emit_hdp_flush)
5867 amdgpu_ring_emit_hdp_flush(ring);
5869 amdgpu_asic_flush_hdp(adev, ring);
5872 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5873 struct amdgpu_ring *ring)
5875 #ifdef CONFIG_X86_64
5876 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5879 if (adev->gmc.xgmi.connected_to_cpu)
5882 amdgpu_asic_invalidate_hdp(adev, ring);
5885 int amdgpu_in_reset(struct amdgpu_device *adev)
5887 return atomic_read(&adev->reset_domain->in_gpu_reset);
5891 * amdgpu_device_halt() - bring hardware to some kind of halt state
5893 * @adev: amdgpu_device pointer
5895 * Bring hardware to some kind of halt state so that no one can touch it
5896 * any more. It will help to maintain error context when error occurred.
5897 * Compare to a simple hang, the system will keep stable at least for SSH
5898 * access. Then it should be trivial to inspect the hardware state and
5899 * see what's going on. Implemented as following:
5901 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5902 * clears all CPU mappings to device, disallows remappings through page faults
5903 * 2. amdgpu_irq_disable_all() disables all interrupts
5904 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5905 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5906 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5907 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5908 * flush any in flight DMA operations
5910 void amdgpu_device_halt(struct amdgpu_device *adev)
5912 struct pci_dev *pdev = adev->pdev;
5913 struct drm_device *ddev = adev_to_drm(adev);
5915 drm_dev_unplug(ddev);
5917 amdgpu_irq_disable_all(adev);
5919 amdgpu_fence_driver_hw_fini(adev);
5921 adev->no_hw_access = true;
5923 amdgpu_device_unmap_mmio(adev);
5925 pci_disable_device(pdev);
5926 pci_wait_for_pending_transaction(pdev);
5929 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5932 unsigned long flags, address, data;
5935 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5936 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5938 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5939 WREG32(address, reg * 4);
5940 (void)RREG32(address);
5942 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5946 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5949 unsigned long flags, address, data;
5951 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5952 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5954 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5955 WREG32(address, reg * 4);
5956 (void)RREG32(address);
5959 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5963 * amdgpu_device_switch_gang - switch to a new gang
5964 * @adev: amdgpu_device pointer
5965 * @gang: the gang to switch to
5967 * Try to switch to a new gang.
5968 * Returns: NULL if we switched to the new gang or a reference to the current
5971 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
5972 struct dma_fence *gang)
5974 struct dma_fence *old = NULL;
5979 old = dma_fence_get_rcu_safe(&adev->gang_submit);
5985 if (!dma_fence_is_signaled(old))
5988 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
5995 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
5997 switch (adev->asic_type) {
5998 #ifdef CONFIG_DRM_AMDGPU_SI
6002 /* chips with no display hardware */
6004 #ifdef CONFIG_DRM_AMDGPU_SI
6010 #ifdef CONFIG_DRM_AMDGPU_CIK
6019 case CHIP_POLARIS10:
6020 case CHIP_POLARIS11:
6021 case CHIP_POLARIS12:
6025 /* chips with display hardware */
6029 if (!adev->ip_versions[DCE_HWIP][0] ||
6030 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))