2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_vf_error.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_pm.h"
61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
64 #define AMDGPU_RESUME_MS 2000
66 static const char *amdgpu_asic_name[] = {
90 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
92 bool amdgpu_device_is_px(struct drm_device *dev)
94 struct amdgpu_device *adev = dev->dev_private;
96 if (adev->flags & AMD_IS_PX)
102 * MMIO register access helper functions.
104 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
109 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
110 return amdgpu_virt_kiq_rreg(adev, reg);
112 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
113 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
117 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
118 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
119 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
120 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
122 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
127 * MMIO register read with bytes helper functions
128 * @offset:bytes offset from MMIO start
132 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
133 if (offset < adev->rmmio_size)
134 return (readb(adev->rmmio + offset));
139 * MMIO register write with bytes helper functions
140 * @offset:bytes offset from MMIO start
141 * @value: the value want to be written to the register
144 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
145 if (offset < adev->rmmio_size)
146 writeb(value, adev->rmmio + offset);
152 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
155 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
157 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
158 adev->last_mm_index = v;
161 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
162 return amdgpu_virt_kiq_wreg(adev, reg, v);
164 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
165 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
169 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
170 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
171 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
172 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
175 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
180 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
182 if ((reg * 4) < adev->rio_mem_size)
183 return ioread32(adev->rio_mem + (reg * 4));
185 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
186 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
190 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
193 adev->last_mm_index = v;
196 if ((reg * 4) < adev->rio_mem_size)
197 iowrite32(v, adev->rio_mem + (reg * 4));
199 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
200 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
203 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
209 * amdgpu_mm_rdoorbell - read a doorbell dword
211 * @adev: amdgpu_device pointer
212 * @index: doorbell index
214 * Returns the value in the doorbell aperture at the
215 * requested doorbell index (CIK).
217 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
219 if (index < adev->doorbell.num_doorbells) {
220 return readl(adev->doorbell.ptr + index);
222 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
228 * amdgpu_mm_wdoorbell - write a doorbell dword
230 * @adev: amdgpu_device pointer
231 * @index: doorbell index
234 * Writes @v to the doorbell aperture at the
235 * requested doorbell index (CIK).
237 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
239 if (index < adev->doorbell.num_doorbells) {
240 writel(v, adev->doorbell.ptr + index);
242 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
247 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
249 * @adev: amdgpu_device pointer
250 * @index: doorbell index
252 * Returns the value in the doorbell aperture at the
253 * requested doorbell index (VEGA10+).
255 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
257 if (index < adev->doorbell.num_doorbells) {
258 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
260 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
266 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
268 * @adev: amdgpu_device pointer
269 * @index: doorbell index
272 * Writes @v to the doorbell aperture at the
273 * requested doorbell index (VEGA10+).
275 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
277 if (index < adev->doorbell.num_doorbells) {
278 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
280 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
285 * amdgpu_invalid_rreg - dummy reg read function
287 * @adev: amdgpu device pointer
288 * @reg: offset of register
290 * Dummy register read function. Used for register blocks
291 * that certain asics don't have (all asics).
292 * Returns the value in the register.
294 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
296 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
302 * amdgpu_invalid_wreg - dummy reg write function
304 * @adev: amdgpu device pointer
305 * @reg: offset of register
306 * @v: value to write to the register
308 * Dummy register read function. Used for register blocks
309 * that certain asics don't have (all asics).
311 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
313 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
319 * amdgpu_block_invalid_rreg - dummy reg read function
321 * @adev: amdgpu device pointer
322 * @block: offset of instance
323 * @reg: offset of register
325 * Dummy register read function. Used for register blocks
326 * that certain asics don't have (all asics).
327 * Returns the value in the register.
329 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
330 uint32_t block, uint32_t reg)
332 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
339 * amdgpu_block_invalid_wreg - dummy reg write function
341 * @adev: amdgpu device pointer
342 * @block: offset of instance
343 * @reg: offset of register
344 * @v: value to write to the register
346 * Dummy register read function. Used for register blocks
347 * that certain asics don't have (all asics).
349 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
351 uint32_t reg, uint32_t v)
353 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
358 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
360 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
361 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
362 &adev->vram_scratch.robj,
363 &adev->vram_scratch.gpu_addr,
364 (void **)&adev->vram_scratch.ptr);
367 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
369 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
373 * amdgpu_device_program_register_sequence - program an array of registers.
375 * @adev: amdgpu_device pointer
376 * @registers: pointer to the register array
377 * @array_size: size of the register array
379 * Programs an array or registers with and and or masks.
380 * This is a helper for setting golden registers.
382 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
383 const u32 *registers,
384 const u32 array_size)
386 u32 tmp, reg, and_mask, or_mask;
392 for (i = 0; i < array_size; i +=3) {
393 reg = registers[i + 0];
394 and_mask = registers[i + 1];
395 or_mask = registers[i + 2];
397 if (and_mask == 0xffffffff) {
408 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
410 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
414 * GPU doorbell aperture helpers function.
417 * amdgpu_device_doorbell_init - Init doorbell driver information.
419 * @adev: amdgpu_device pointer
421 * Init doorbell driver information (CIK)
422 * Returns 0 on success, error on failure.
424 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
426 /* No doorbell on SI hardware generation */
427 if (adev->asic_type < CHIP_BONAIRE) {
428 adev->doorbell.base = 0;
429 adev->doorbell.size = 0;
430 adev->doorbell.num_doorbells = 0;
431 adev->doorbell.ptr = NULL;
435 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
438 /* doorbell bar mapping */
439 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
440 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
442 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
443 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
444 if (adev->doorbell.num_doorbells == 0)
447 adev->doorbell.ptr = ioremap(adev->doorbell.base,
448 adev->doorbell.num_doorbells *
450 if (adev->doorbell.ptr == NULL)
457 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
459 * @adev: amdgpu_device pointer
461 * Tear down doorbell driver information (CIK)
463 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
465 iounmap(adev->doorbell.ptr);
466 adev->doorbell.ptr = NULL;
472 * amdgpu_device_wb_*()
473 * Writeback is the method by which the GPU updates special pages in memory
474 * with the status of certain GPU events (fences, ring pointers,etc.).
478 * amdgpu_device_wb_fini - Disable Writeback and free memory
480 * @adev: amdgpu_device pointer
482 * Disables Writeback and frees the Writeback memory (all asics).
483 * Used at driver shutdown.
485 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
487 if (adev->wb.wb_obj) {
488 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
490 (void **)&adev->wb.wb);
491 adev->wb.wb_obj = NULL;
496 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
498 * @adev: amdgpu_device pointer
500 * Initializes writeback and allocates writeback memory (all asics).
501 * Used at driver startup.
502 * Returns 0 on success or an -error on failure.
504 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
508 if (adev->wb.wb_obj == NULL) {
509 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
510 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
512 &adev->wb.wb_obj, &adev->wb.gpu_addr,
513 (void **)&adev->wb.wb);
515 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
519 adev->wb.num_wb = AMDGPU_MAX_WB;
520 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
522 /* clear wb memory */
523 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
530 * amdgpu_device_wb_get - Allocate a wb entry
532 * @adev: amdgpu_device pointer
535 * Allocate a wb slot for use by the driver (all asics).
536 * Returns 0 on success or -EINVAL on failure.
538 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
540 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
542 if (offset < adev->wb.num_wb) {
543 __set_bit(offset, adev->wb.used);
544 *wb = offset << 3; /* convert to dw offset */
552 * amdgpu_device_wb_free - Free a wb entry
554 * @adev: amdgpu_device pointer
557 * Free a wb slot allocated for use by the driver (all asics)
559 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
562 if (wb < adev->wb.num_wb)
563 __clear_bit(wb, adev->wb.used);
567 * amdgpu_device_vram_location - try to find VRAM location
568 * @adev: amdgpu device structure holding all necessary informations
569 * @mc: memory controller structure holding memory informations
570 * @base: base address at which to put VRAM
572 * Function will try to place VRAM at base address provided
575 void amdgpu_device_vram_location(struct amdgpu_device *adev,
576 struct amdgpu_gmc *mc, u64 base)
578 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
580 mc->vram_start = base;
581 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
582 if (limit && limit < mc->real_vram_size)
583 mc->real_vram_size = limit;
584 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
585 mc->mc_vram_size >> 20, mc->vram_start,
586 mc->vram_end, mc->real_vram_size >> 20);
590 * amdgpu_device_gart_location - try to find GTT location
591 * @adev: amdgpu device structure holding all necessary informations
592 * @mc: memory controller structure holding memory informations
594 * Function will place try to place GTT before or after VRAM.
596 * If GTT size is bigger than space left then we ajust GTT size.
597 * Thus function will never fails.
599 * FIXME: when reducing GTT size align new size on power of 2.
601 void amdgpu_device_gart_location(struct amdgpu_device *adev,
602 struct amdgpu_gmc *mc)
604 u64 size_af, size_bf;
606 size_af = adev->gmc.mc_mask - mc->vram_end;
607 size_bf = mc->vram_start;
608 if (size_bf > size_af) {
609 if (mc->gart_size > size_bf) {
610 dev_warn(adev->dev, "limiting GTT\n");
611 mc->gart_size = size_bf;
615 if (mc->gart_size > size_af) {
616 dev_warn(adev->dev, "limiting GTT\n");
617 mc->gart_size = size_af;
619 /* VCE doesn't like it when BOs cross a 4GB segment, so align
620 * the GART base on a 4GB boundary as well.
622 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
624 mc->gart_end = mc->gart_start + mc->gart_size - 1;
625 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
626 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
630 * amdgpu_device_resize_fb_bar - try to resize FB BAR
632 * @adev: amdgpu_device pointer
634 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
635 * to fail, but if any of the BARs is not accessible after the size we abort
636 * driver loading by returning -ENODEV.
638 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
640 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
641 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
642 struct pci_bus *root;
643 struct resource *res;
649 if (amdgpu_sriov_vf(adev))
652 /* Check if the root BUS has 64bit memory resources */
653 root = adev->pdev->bus;
657 pci_bus_for_each_resource(root, res, i) {
658 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
659 res->start > 0x100000000ull)
663 /* Trying to resize is pointless without a root hub window above 4GB */
667 /* Disable memory decoding while we change the BAR addresses and size */
668 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
669 pci_write_config_word(adev->pdev, PCI_COMMAND,
670 cmd & ~PCI_COMMAND_MEMORY);
672 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
673 amdgpu_device_doorbell_fini(adev);
674 if (adev->asic_type >= CHIP_BONAIRE)
675 pci_release_resource(adev->pdev, 2);
677 pci_release_resource(adev->pdev, 0);
679 r = pci_resize_resource(adev->pdev, 0, rbar_size);
681 DRM_INFO("Not enough PCI address space for a large BAR.");
682 else if (r && r != -ENOTSUPP)
683 DRM_ERROR("Problem resizing BAR0 (%d).", r);
685 pci_assign_unassigned_bus_resources(adev->pdev->bus);
687 /* When the doorbell or fb BAR isn't available we have no chance of
690 r = amdgpu_device_doorbell_init(adev);
691 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
694 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
700 * GPU helpers function.
703 * amdgpu_device_need_post - check if the hw need post or not
705 * @adev: amdgpu_device pointer
707 * Check if the asic has been initialized (all asics) at driver startup
708 * or post is needed if hw reset is performed.
709 * Returns true if need or false if not.
711 bool amdgpu_device_need_post(struct amdgpu_device *adev)
715 if (amdgpu_sriov_vf(adev))
718 if (amdgpu_passthrough(adev)) {
719 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
720 * some old smc fw still need driver do vPost otherwise gpu hang, while
721 * those smc fw version above 22.15 doesn't have this flaw, so we force
722 * vpost executed for smc version below 22.15
724 if (adev->asic_type == CHIP_FIJI) {
727 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
728 /* force vPost if error occured */
732 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
733 if (fw_ver < 0x00160e00)
738 if (adev->has_hw_reset) {
739 adev->has_hw_reset = false;
743 /* bios scratch used on CIK+ */
744 if (adev->asic_type >= CHIP_BONAIRE)
745 return amdgpu_atombios_scratch_need_asic_init(adev);
747 /* check MEM_SIZE for older asics */
748 reg = amdgpu_asic_get_config_memsize(adev);
750 if ((reg != 0) && (reg != 0xffffffff))
756 /* if we get transitioned to only one device, take VGA back */
758 * amdgpu_device_vga_set_decode - enable/disable vga decode
760 * @cookie: amdgpu_device pointer
761 * @state: enable/disable vga decode
763 * Enable/disable vga decode (all asics).
764 * Returns VGA resource flags.
766 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
768 struct amdgpu_device *adev = cookie;
769 amdgpu_asic_set_vga_state(adev, state);
771 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
772 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
774 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
777 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
779 /* defines number of bits in page table versus page directory,
780 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
781 * page table and the remaining bits are in the page directory */
782 if (amdgpu_vm_block_size == -1)
785 if (amdgpu_vm_block_size < 9) {
786 dev_warn(adev->dev, "VM page table size (%d) too small\n",
787 amdgpu_vm_block_size);
788 amdgpu_vm_block_size = -1;
792 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
794 /* no need to check the default value */
795 if (amdgpu_vm_size == -1)
798 if (amdgpu_vm_size < 1) {
799 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
806 * amdgpu_device_check_arguments - validate module params
808 * @adev: amdgpu_device pointer
810 * Validates certain module parameters and updates
811 * the associated values used by the driver (all asics).
813 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
815 if (amdgpu_sched_jobs < 4) {
816 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
818 amdgpu_sched_jobs = 4;
819 } else if (!is_power_of_2(amdgpu_sched_jobs)){
820 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
822 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
825 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
826 /* gart size must be greater or equal to 32M */
827 dev_warn(adev->dev, "gart size (%d) too small\n",
829 amdgpu_gart_size = -1;
832 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
833 /* gtt size must be greater or equal to 32M */
834 dev_warn(adev->dev, "gtt size (%d) too small\n",
836 amdgpu_gtt_size = -1;
839 /* valid range is between 4 and 9 inclusive */
840 if (amdgpu_vm_fragment_size != -1 &&
841 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
842 dev_warn(adev->dev, "valid range is between 4 and 9\n");
843 amdgpu_vm_fragment_size = -1;
846 amdgpu_device_check_vm_size(adev);
848 amdgpu_device_check_block_size(adev);
850 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
851 !is_power_of_2(amdgpu_vram_page_split))) {
852 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
853 amdgpu_vram_page_split);
854 amdgpu_vram_page_split = 1024;
857 if (amdgpu_lockup_timeout == 0) {
858 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
859 amdgpu_lockup_timeout = 10000;
862 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
866 * amdgpu_switcheroo_set_state - set switcheroo state
868 * @pdev: pci dev pointer
869 * @state: vga_switcheroo state
871 * Callback for the switcheroo driver. Suspends or resumes the
872 * the asics before or after it is powered up using ACPI methods.
874 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
876 struct drm_device *dev = pci_get_drvdata(pdev);
878 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
881 if (state == VGA_SWITCHEROO_ON) {
882 pr_info("amdgpu: switched on\n");
883 /* don't suspend or resume card normally */
884 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
886 amdgpu_device_resume(dev, true, true);
888 dev->switch_power_state = DRM_SWITCH_POWER_ON;
889 drm_kms_helper_poll_enable(dev);
891 pr_info("amdgpu: switched off\n");
892 drm_kms_helper_poll_disable(dev);
893 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
894 amdgpu_device_suspend(dev, true, true);
895 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
900 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
902 * @pdev: pci dev pointer
904 * Callback for the switcheroo driver. Check of the switcheroo
905 * state can be changed.
906 * Returns true if the state can be changed, false if not.
908 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
910 struct drm_device *dev = pci_get_drvdata(pdev);
913 * FIXME: open_count is protected by drm_global_mutex but that would lead to
914 * locking inversion with the driver load path. And the access here is
915 * completely racy anyway. So don't bother with locking for now.
917 return dev->open_count == 0;
920 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
921 .set_gpu_state = amdgpu_switcheroo_set_state,
923 .can_switch = amdgpu_switcheroo_can_switch,
926 int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
927 enum amd_ip_block_type block_type,
928 enum amd_clockgating_state state)
932 for (i = 0; i < adev->num_ip_blocks; i++) {
933 if (!adev->ip_blocks[i].status.valid)
935 if (adev->ip_blocks[i].version->type != block_type)
937 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
939 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
940 (void *)adev, state);
942 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
943 adev->ip_blocks[i].version->funcs->name, r);
948 int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
949 enum amd_ip_block_type block_type,
950 enum amd_powergating_state state)
954 for (i = 0; i < adev->num_ip_blocks; i++) {
955 if (!adev->ip_blocks[i].status.valid)
957 if (adev->ip_blocks[i].version->type != block_type)
959 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
961 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
962 (void *)adev, state);
964 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
965 adev->ip_blocks[i].version->funcs->name, r);
970 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
975 for (i = 0; i < adev->num_ip_blocks; i++) {
976 if (!adev->ip_blocks[i].status.valid)
978 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
979 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
983 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
984 enum amd_ip_block_type block_type)
988 for (i = 0; i < adev->num_ip_blocks; i++) {
989 if (!adev->ip_blocks[i].status.valid)
991 if (adev->ip_blocks[i].version->type == block_type) {
992 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1002 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1003 enum amd_ip_block_type block_type)
1007 for (i = 0; i < adev->num_ip_blocks; i++) {
1008 if (!adev->ip_blocks[i].status.valid)
1010 if (adev->ip_blocks[i].version->type == block_type)
1011 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1017 struct amdgpu_ip_block *
1018 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1019 enum amd_ip_block_type type)
1023 for (i = 0; i < adev->num_ip_blocks; i++)
1024 if (adev->ip_blocks[i].version->type == type)
1025 return &adev->ip_blocks[i];
1031 * amdgpu_device_ip_block_version_cmp
1033 * @adev: amdgpu_device pointer
1034 * @type: enum amd_ip_block_type
1035 * @major: major version
1036 * @minor: minor version
1038 * return 0 if equal or greater
1039 * return 1 if smaller or the ip_block doesn't exist
1041 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1042 enum amd_ip_block_type type,
1043 u32 major, u32 minor)
1045 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1047 if (ip_block && ((ip_block->version->major > major) ||
1048 ((ip_block->version->major == major) &&
1049 (ip_block->version->minor >= minor))))
1056 * amdgpu_device_ip_block_add
1058 * @adev: amdgpu_device pointer
1059 * @ip_block_version: pointer to the IP to add
1061 * Adds the IP block driver information to the collection of IPs
1064 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1065 const struct amdgpu_ip_block_version *ip_block_version)
1067 if (!ip_block_version)
1070 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1071 ip_block_version->funcs->name);
1073 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1078 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1080 adev->enable_virtual_display = false;
1082 if (amdgpu_virtual_display) {
1083 struct drm_device *ddev = adev->ddev;
1084 const char *pci_address_name = pci_name(ddev->pdev);
1085 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1087 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1088 pciaddstr_tmp = pciaddstr;
1089 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1090 pciaddname = strsep(&pciaddname_tmp, ",");
1091 if (!strcmp("all", pciaddname)
1092 || !strcmp(pci_address_name, pciaddname)) {
1096 adev->enable_virtual_display = true;
1099 res = kstrtol(pciaddname_tmp, 10,
1107 adev->mode_info.num_crtc = num_crtc;
1109 adev->mode_info.num_crtc = 1;
1115 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1116 amdgpu_virtual_display, pci_address_name,
1117 adev->enable_virtual_display, adev->mode_info.num_crtc);
1123 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1125 const char *chip_name;
1128 const struct gpu_info_firmware_header_v1_0 *hdr;
1130 adev->firmware.gpu_info_fw = NULL;
1132 switch (adev->asic_type) {
1136 case CHIP_POLARIS11:
1137 case CHIP_POLARIS10:
1138 case CHIP_POLARIS12:
1141 #ifdef CONFIG_DRM_AMDGPU_SI
1148 #ifdef CONFIG_DRM_AMDGPU_CIK
1158 chip_name = "vega10";
1161 chip_name = "raven";
1165 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1166 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1169 "Failed to load gpu_info firmware \"%s\"\n",
1173 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1176 "Failed to validate gpu_info firmware \"%s\"\n",
1181 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1182 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1184 switch (hdr->version_major) {
1187 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1188 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1189 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1191 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1192 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1193 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1194 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1195 adev->gfx.config.max_texture_channel_caches =
1196 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1197 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1198 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1199 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1200 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1201 adev->gfx.config.double_offchip_lds_buf =
1202 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1203 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1204 adev->gfx.cu_info.max_waves_per_simd =
1205 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1206 adev->gfx.cu_info.max_scratch_slots_per_cu =
1207 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1208 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1213 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1221 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1225 amdgpu_device_enable_virtual_display(adev);
1227 switch (adev->asic_type) {
1231 case CHIP_POLARIS11:
1232 case CHIP_POLARIS10:
1233 case CHIP_POLARIS12:
1236 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1237 adev->family = AMDGPU_FAMILY_CZ;
1239 adev->family = AMDGPU_FAMILY_VI;
1241 r = vi_set_ip_blocks(adev);
1245 #ifdef CONFIG_DRM_AMDGPU_SI
1251 adev->family = AMDGPU_FAMILY_SI;
1252 r = si_set_ip_blocks(adev);
1257 #ifdef CONFIG_DRM_AMDGPU_CIK
1263 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1264 adev->family = AMDGPU_FAMILY_CI;
1266 adev->family = AMDGPU_FAMILY_KV;
1268 r = cik_set_ip_blocks(adev);
1275 if (adev->asic_type == CHIP_RAVEN)
1276 adev->family = AMDGPU_FAMILY_RV;
1278 adev->family = AMDGPU_FAMILY_AI;
1280 r = soc15_set_ip_blocks(adev);
1285 /* FIXME: not supported yet */
1289 r = amdgpu_device_parse_gpu_info_fw(adev);
1293 amdgpu_amdkfd_device_probe(adev);
1295 if (amdgpu_sriov_vf(adev)) {
1296 r = amdgpu_virt_request_full_gpu(adev, true);
1301 for (i = 0; i < adev->num_ip_blocks; i++) {
1302 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1303 DRM_ERROR("disabled ip block: %d <%s>\n",
1304 i, adev->ip_blocks[i].version->funcs->name);
1305 adev->ip_blocks[i].status.valid = false;
1307 if (adev->ip_blocks[i].version->funcs->early_init) {
1308 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1310 adev->ip_blocks[i].status.valid = false;
1312 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1313 adev->ip_blocks[i].version->funcs->name, r);
1316 adev->ip_blocks[i].status.valid = true;
1319 adev->ip_blocks[i].status.valid = true;
1324 adev->cg_flags &= amdgpu_cg_mask;
1325 adev->pg_flags &= amdgpu_pg_mask;
1330 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1334 for (i = 0; i < adev->num_ip_blocks; i++) {
1335 if (!adev->ip_blocks[i].status.valid)
1337 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1339 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1340 adev->ip_blocks[i].version->funcs->name, r);
1343 adev->ip_blocks[i].status.sw = true;
1345 /* need to do gmc hw init early so we can allocate gpu mem */
1346 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1347 r = amdgpu_device_vram_scratch_init(adev);
1349 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1352 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1354 DRM_ERROR("hw_init %d failed %d\n", i, r);
1357 r = amdgpu_device_wb_init(adev);
1359 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1362 adev->ip_blocks[i].status.hw = true;
1364 /* right after GMC hw init, we create CSA */
1365 if (amdgpu_sriov_vf(adev)) {
1366 r = amdgpu_allocate_static_csa(adev);
1368 DRM_ERROR("allocate CSA failed %d\n", r);
1375 for (i = 0; i < adev->num_ip_blocks; i++) {
1376 if (!adev->ip_blocks[i].status.sw)
1378 if (adev->ip_blocks[i].status.hw)
1380 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1382 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1383 adev->ip_blocks[i].version->funcs->name, r);
1386 adev->ip_blocks[i].status.hw = true;
1389 amdgpu_amdkfd_device_init(adev);
1391 if (amdgpu_sriov_vf(adev))
1392 amdgpu_virt_release_full_gpu(adev, true);
1397 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1399 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1402 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1404 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1405 AMDGPU_RESET_MAGIC_NUM);
1408 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1412 if (amdgpu_emu_mode == 1)
1415 for (i = 0; i < adev->num_ip_blocks; i++) {
1416 if (!adev->ip_blocks[i].status.valid)
1418 /* skip CG for VCE/UVD, it's handled specially */
1419 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1420 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1421 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1422 /* enable clockgating to save power */
1423 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1426 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1427 adev->ip_blocks[i].version->funcs->name, r);
1435 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1439 for (i = 0; i < adev->num_ip_blocks; i++) {
1440 if (!adev->ip_blocks[i].status.valid)
1442 if (adev->ip_blocks[i].version->funcs->late_init) {
1443 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1445 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1446 adev->ip_blocks[i].version->funcs->name, r);
1449 adev->ip_blocks[i].status.late_initialized = true;
1453 mod_delayed_work(system_wq, &adev->late_init_work,
1454 msecs_to_jiffies(AMDGPU_RESUME_MS));
1456 amdgpu_device_fill_reset_magic(adev);
1461 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1465 amdgpu_amdkfd_device_fini(adev);
1466 /* need to disable SMC first */
1467 for (i = 0; i < adev->num_ip_blocks; i++) {
1468 if (!adev->ip_blocks[i].status.hw)
1470 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
1471 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1472 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1473 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1474 AMD_CG_STATE_UNGATE);
1476 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1477 adev->ip_blocks[i].version->funcs->name, r);
1480 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1481 /* XXX handle errors */
1483 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1484 adev->ip_blocks[i].version->funcs->name, r);
1486 adev->ip_blocks[i].status.hw = false;
1491 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1492 if (!adev->ip_blocks[i].status.hw)
1495 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1496 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1497 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1498 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1499 AMD_CG_STATE_UNGATE);
1501 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1502 adev->ip_blocks[i].version->funcs->name, r);
1507 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1508 /* XXX handle errors */
1510 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1511 adev->ip_blocks[i].version->funcs->name, r);
1514 adev->ip_blocks[i].status.hw = false;
1517 /* disable all interrupts */
1518 amdgpu_irq_disable_all(adev);
1520 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1521 if (!adev->ip_blocks[i].status.sw)
1524 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1525 amdgpu_free_static_csa(adev);
1526 amdgpu_device_wb_fini(adev);
1527 amdgpu_device_vram_scratch_fini(adev);
1530 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1531 /* XXX handle errors */
1533 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1534 adev->ip_blocks[i].version->funcs->name, r);
1536 adev->ip_blocks[i].status.sw = false;
1537 adev->ip_blocks[i].status.valid = false;
1540 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1541 if (!adev->ip_blocks[i].status.late_initialized)
1543 if (adev->ip_blocks[i].version->funcs->late_fini)
1544 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1545 adev->ip_blocks[i].status.late_initialized = false;
1548 if (amdgpu_sriov_vf(adev))
1549 if (amdgpu_virt_release_full_gpu(adev, false))
1550 DRM_ERROR("failed to release exclusive mode on fini\n");
1555 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1557 struct amdgpu_device *adev =
1558 container_of(work, struct amdgpu_device, late_init_work.work);
1559 amdgpu_device_ip_late_set_cg_state(adev);
1562 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
1566 if (amdgpu_sriov_vf(adev))
1567 amdgpu_virt_request_full_gpu(adev, false);
1569 /* ungate SMC block first */
1570 r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1571 AMD_CG_STATE_UNGATE);
1573 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
1576 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1577 if (!adev->ip_blocks[i].status.valid)
1579 /* ungate blocks so that suspend can properly shut them down */
1580 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC &&
1581 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1582 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1583 AMD_CG_STATE_UNGATE);
1585 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1586 adev->ip_blocks[i].version->funcs->name, r);
1589 /* XXX handle errors */
1590 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1591 /* XXX handle errors */
1593 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1594 adev->ip_blocks[i].version->funcs->name, r);
1598 if (amdgpu_sriov_vf(adev))
1599 amdgpu_virt_release_full_gpu(adev, false);
1604 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
1608 static enum amd_ip_block_type ip_order[] = {
1609 AMD_IP_BLOCK_TYPE_GMC,
1610 AMD_IP_BLOCK_TYPE_COMMON,
1611 AMD_IP_BLOCK_TYPE_IH,
1614 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1616 struct amdgpu_ip_block *block;
1618 for (j = 0; j < adev->num_ip_blocks; j++) {
1619 block = &adev->ip_blocks[j];
1621 if (block->version->type != ip_order[i] ||
1622 !block->status.valid)
1625 r = block->version->funcs->hw_init(adev);
1626 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1635 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
1639 static enum amd_ip_block_type ip_order[] = {
1640 AMD_IP_BLOCK_TYPE_SMC,
1641 AMD_IP_BLOCK_TYPE_PSP,
1642 AMD_IP_BLOCK_TYPE_DCE,
1643 AMD_IP_BLOCK_TYPE_GFX,
1644 AMD_IP_BLOCK_TYPE_SDMA,
1645 AMD_IP_BLOCK_TYPE_UVD,
1646 AMD_IP_BLOCK_TYPE_VCE
1649 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1651 struct amdgpu_ip_block *block;
1653 for (j = 0; j < adev->num_ip_blocks; j++) {
1654 block = &adev->ip_blocks[j];
1656 if (block->version->type != ip_order[i] ||
1657 !block->status.valid)
1660 r = block->version->funcs->hw_init(adev);
1661 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1670 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
1674 for (i = 0; i < adev->num_ip_blocks; i++) {
1675 if (!adev->ip_blocks[i].status.valid)
1677 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1678 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1679 adev->ip_blocks[i].version->type ==
1680 AMD_IP_BLOCK_TYPE_IH) {
1681 r = adev->ip_blocks[i].version->funcs->resume(adev);
1683 DRM_ERROR("resume of IP block <%s> failed %d\n",
1684 adev->ip_blocks[i].version->funcs->name, r);
1693 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
1697 for (i = 0; i < adev->num_ip_blocks; i++) {
1698 if (!adev->ip_blocks[i].status.valid)
1700 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1701 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1702 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1704 r = adev->ip_blocks[i].version->funcs->resume(adev);
1706 DRM_ERROR("resume of IP block <%s> failed %d\n",
1707 adev->ip_blocks[i].version->funcs->name, r);
1715 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
1719 r = amdgpu_device_ip_resume_phase1(adev);
1722 r = amdgpu_device_ip_resume_phase2(adev);
1727 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1729 if (amdgpu_sriov_vf(adev)) {
1730 if (adev->is_atom_fw) {
1731 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1732 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1734 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1735 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1738 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
1739 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
1743 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
1745 switch (asic_type) {
1746 #if defined(CONFIG_DRM_AMD_DC)
1754 case CHIP_POLARIS11:
1755 case CHIP_POLARIS10:
1756 case CHIP_POLARIS12:
1759 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
1760 return amdgpu_dc != 0;
1763 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1766 return amdgpu_dc != 0;
1774 * amdgpu_device_has_dc_support - check if dc is supported
1776 * @adev: amdgpu_device_pointer
1778 * Returns true for supported, false for not supported
1780 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
1782 if (amdgpu_sriov_vf(adev))
1785 return amdgpu_device_asic_has_dc_support(adev->asic_type);
1789 * amdgpu_device_init - initialize the driver
1791 * @adev: amdgpu_device pointer
1792 * @pdev: drm dev pointer
1793 * @pdev: pci dev pointer
1794 * @flags: driver flags
1796 * Initializes the driver info and hw (all asics).
1797 * Returns 0 for success or an error on failure.
1798 * Called at driver startup.
1800 int amdgpu_device_init(struct amdgpu_device *adev,
1801 struct drm_device *ddev,
1802 struct pci_dev *pdev,
1806 bool runtime = false;
1809 adev->shutdown = false;
1810 adev->dev = &pdev->dev;
1813 adev->flags = flags;
1814 adev->asic_type = flags & AMD_ASIC_MASK;
1815 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1816 if (amdgpu_emu_mode == 1)
1817 adev->usec_timeout *= 2;
1818 adev->gmc.gart_size = 512 * 1024 * 1024;
1819 adev->accel_working = false;
1820 adev->num_rings = 0;
1821 adev->mman.buffer_funcs = NULL;
1822 adev->mman.buffer_funcs_ring = NULL;
1823 adev->vm_manager.vm_pte_funcs = NULL;
1824 adev->vm_manager.vm_pte_num_rings = 0;
1825 adev->gmc.gmc_funcs = NULL;
1826 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1827 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1829 adev->smc_rreg = &amdgpu_invalid_rreg;
1830 adev->smc_wreg = &amdgpu_invalid_wreg;
1831 adev->pcie_rreg = &amdgpu_invalid_rreg;
1832 adev->pcie_wreg = &amdgpu_invalid_wreg;
1833 adev->pciep_rreg = &amdgpu_invalid_rreg;
1834 adev->pciep_wreg = &amdgpu_invalid_wreg;
1835 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1836 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1837 adev->didt_rreg = &amdgpu_invalid_rreg;
1838 adev->didt_wreg = &amdgpu_invalid_wreg;
1839 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1840 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1841 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1842 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1844 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1845 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1846 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1848 /* mutex initialization are all done here so we
1849 * can recall function without having locking issues */
1850 atomic_set(&adev->irq.ih.lock, 0);
1851 mutex_init(&adev->firmware.mutex);
1852 mutex_init(&adev->pm.mutex);
1853 mutex_init(&adev->gfx.gpu_clock_mutex);
1854 mutex_init(&adev->srbm_mutex);
1855 mutex_init(&adev->gfx.pipe_reserve_mutex);
1856 mutex_init(&adev->grbm_idx_mutex);
1857 mutex_init(&adev->mn_lock);
1858 mutex_init(&adev->virt.vf_errors.lock);
1859 hash_init(adev->mn_hash);
1860 mutex_init(&adev->lock_reset);
1862 amdgpu_device_check_arguments(adev);
1864 spin_lock_init(&adev->mmio_idx_lock);
1865 spin_lock_init(&adev->smc_idx_lock);
1866 spin_lock_init(&adev->pcie_idx_lock);
1867 spin_lock_init(&adev->uvd_ctx_idx_lock);
1868 spin_lock_init(&adev->didt_idx_lock);
1869 spin_lock_init(&adev->gc_cac_idx_lock);
1870 spin_lock_init(&adev->se_cac_idx_lock);
1871 spin_lock_init(&adev->audio_endpt_idx_lock);
1872 spin_lock_init(&adev->mm_stats.lock);
1874 INIT_LIST_HEAD(&adev->shadow_list);
1875 mutex_init(&adev->shadow_list_lock);
1877 INIT_LIST_HEAD(&adev->ring_lru_list);
1878 spin_lock_init(&adev->ring_lru_list_lock);
1880 INIT_DELAYED_WORK(&adev->late_init_work,
1881 amdgpu_device_ip_late_init_func_handler);
1883 /* Registers mapping */
1884 /* TODO: block userspace mapping of io register */
1885 if (adev->asic_type >= CHIP_BONAIRE) {
1886 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1887 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1889 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1890 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1893 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1894 if (adev->rmmio == NULL) {
1897 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1898 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1900 /* doorbell bar mapping */
1901 amdgpu_device_doorbell_init(adev);
1903 /* io port mapping */
1904 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1905 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1906 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1907 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1911 if (adev->rio_mem == NULL)
1912 DRM_INFO("PCI I/O BAR is not found.\n");
1914 amdgpu_device_get_pcie_info(adev);
1916 /* early init functions */
1917 r = amdgpu_device_ip_early_init(adev);
1921 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1922 /* this will fail for cards that aren't VGA class devices, just
1924 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
1926 if (amdgpu_device_is_px(ddev))
1928 if (!pci_is_thunderbolt_attached(adev->pdev))
1929 vga_switcheroo_register_client(adev->pdev,
1930 &amdgpu_switcheroo_ops, runtime);
1932 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1934 if (amdgpu_emu_mode == 1) {
1935 /* post the asic on emulation mode */
1936 emu_soc_asic_init(adev);
1937 goto fence_driver_init;
1941 if (!amdgpu_get_bios(adev)) {
1946 r = amdgpu_atombios_init(adev);
1948 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1949 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1953 /* detect if we are with an SRIOV vbios */
1954 amdgpu_device_detect_sriov_bios(adev);
1956 /* Post card if necessary */
1957 if (amdgpu_device_need_post(adev)) {
1959 dev_err(adev->dev, "no vBIOS found\n");
1963 DRM_INFO("GPU posting now...\n");
1964 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1966 dev_err(adev->dev, "gpu post error!\n");
1971 if (adev->is_atom_fw) {
1972 /* Initialize clocks */
1973 r = amdgpu_atomfirmware_get_clock_info(adev);
1975 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
1976 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1980 /* Initialize clocks */
1981 r = amdgpu_atombios_get_clock_info(adev);
1983 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1984 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
1987 /* init i2c buses */
1988 if (!amdgpu_device_has_dc_support(adev))
1989 amdgpu_atombios_i2c_init(adev);
1994 r = amdgpu_fence_driver_init(adev);
1996 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1997 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2001 /* init the mode config */
2002 drm_mode_config_init(adev->ddev);
2004 r = amdgpu_device_ip_init(adev);
2006 /* failed in exclusive mode due to timeout */
2007 if (amdgpu_sriov_vf(adev) &&
2008 !amdgpu_sriov_runtime(adev) &&
2009 amdgpu_virt_mmio_blocked(adev) &&
2010 !amdgpu_virt_wait_reset(adev)) {
2011 dev_err(adev->dev, "VF exclusive mode timeout\n");
2012 /* Don't send request since VF is inactive. */
2013 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2014 adev->virt.ops = NULL;
2018 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2019 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2020 amdgpu_device_ip_fini(adev);
2024 adev->accel_working = true;
2026 amdgpu_vm_check_compute_bug(adev);
2028 /* Initialize the buffer migration limit. */
2029 if (amdgpu_moverate >= 0)
2030 max_MBps = amdgpu_moverate;
2032 max_MBps = 8; /* Allow 8 MB/s. */
2033 /* Get a log2 for easy divisions. */
2034 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2036 r = amdgpu_ib_pool_init(adev);
2038 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2039 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2043 r = amdgpu_ib_ring_tests(adev);
2045 DRM_ERROR("ib ring test failed (%d).\n", r);
2047 if (amdgpu_sriov_vf(adev))
2048 amdgpu_virt_init_data_exchange(adev);
2050 amdgpu_fbdev_init(adev);
2052 r = amdgpu_pm_sysfs_init(adev);
2054 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2056 r = amdgpu_debugfs_gem_init(adev);
2058 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2060 r = amdgpu_debugfs_regs_init(adev);
2062 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2064 r = amdgpu_debugfs_firmware_init(adev);
2066 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2068 r = amdgpu_debugfs_init(adev);
2070 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2072 if ((amdgpu_testing & 1)) {
2073 if (adev->accel_working)
2074 amdgpu_test_moves(adev);
2076 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2078 if (amdgpu_benchmarking) {
2079 if (adev->accel_working)
2080 amdgpu_benchmark(adev, amdgpu_benchmarking);
2082 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2085 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2086 * explicit gating rather than handling it automatically.
2088 r = amdgpu_device_ip_late_init(adev);
2090 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2091 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2098 amdgpu_vf_error_trans_all(adev);
2100 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2106 * amdgpu_device_fini - tear down the driver
2108 * @adev: amdgpu_device pointer
2110 * Tear down the driver info (all asics).
2111 * Called at driver shutdown.
2113 void amdgpu_device_fini(struct amdgpu_device *adev)
2117 DRM_INFO("amdgpu: finishing device.\n");
2118 adev->shutdown = true;
2119 if (adev->mode_info.mode_config_initialized)
2120 drm_crtc_force_disable_all(adev->ddev);
2122 amdgpu_ib_pool_fini(adev);
2123 amdgpu_fence_driver_fini(adev);
2124 amdgpu_pm_sysfs_fini(adev);
2125 amdgpu_fbdev_fini(adev);
2126 r = amdgpu_device_ip_fini(adev);
2127 if (adev->firmware.gpu_info_fw) {
2128 release_firmware(adev->firmware.gpu_info_fw);
2129 adev->firmware.gpu_info_fw = NULL;
2131 adev->accel_working = false;
2132 cancel_delayed_work_sync(&adev->late_init_work);
2133 /* free i2c buses */
2134 if (!amdgpu_device_has_dc_support(adev))
2135 amdgpu_i2c_fini(adev);
2137 if (amdgpu_emu_mode != 1)
2138 amdgpu_atombios_fini(adev);
2142 if (!pci_is_thunderbolt_attached(adev->pdev))
2143 vga_switcheroo_unregister_client(adev->pdev);
2144 if (adev->flags & AMD_IS_PX)
2145 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2146 vga_client_register(adev->pdev, NULL, NULL, NULL);
2148 pci_iounmap(adev->pdev, adev->rio_mem);
2149 adev->rio_mem = NULL;
2150 iounmap(adev->rmmio);
2152 amdgpu_device_doorbell_fini(adev);
2153 amdgpu_debugfs_regs_cleanup(adev);
2161 * amdgpu_device_suspend - initiate device suspend
2163 * @pdev: drm dev pointer
2164 * @state: suspend state
2166 * Puts the hw in the suspend state (all asics).
2167 * Returns 0 for success or an error on failure.
2168 * Called at driver suspend.
2170 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2172 struct amdgpu_device *adev;
2173 struct drm_crtc *crtc;
2174 struct drm_connector *connector;
2177 if (dev == NULL || dev->dev_private == NULL) {
2181 adev = dev->dev_private;
2183 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2186 drm_kms_helper_poll_disable(dev);
2188 if (!amdgpu_device_has_dc_support(adev)) {
2189 /* turn off display hw */
2190 drm_modeset_lock_all(dev);
2191 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2192 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2194 drm_modeset_unlock_all(dev);
2197 amdgpu_amdkfd_suspend(adev);
2199 /* unpin the front buffers and cursors */
2200 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2201 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2202 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2203 struct amdgpu_bo *robj;
2205 if (amdgpu_crtc->cursor_bo) {
2206 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2207 r = amdgpu_bo_reserve(aobj, true);
2209 amdgpu_bo_unpin(aobj);
2210 amdgpu_bo_unreserve(aobj);
2214 if (rfb == NULL || rfb->obj == NULL) {
2217 robj = gem_to_amdgpu_bo(rfb->obj);
2218 /* don't unpin kernel fb objects */
2219 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2220 r = amdgpu_bo_reserve(robj, true);
2222 amdgpu_bo_unpin(robj);
2223 amdgpu_bo_unreserve(robj);
2227 /* evict vram memory */
2228 amdgpu_bo_evict_vram(adev);
2230 amdgpu_fence_driver_suspend(adev);
2232 r = amdgpu_device_ip_suspend(adev);
2234 /* evict remaining vram memory
2235 * This second call to evict vram is to evict the gart page table
2238 amdgpu_bo_evict_vram(adev);
2240 pci_save_state(dev->pdev);
2242 /* Shut down the device */
2243 pci_disable_device(dev->pdev);
2244 pci_set_power_state(dev->pdev, PCI_D3hot);
2246 r = amdgpu_asic_reset(adev);
2248 DRM_ERROR("amdgpu asic reset failed\n");
2253 amdgpu_fbdev_set_suspend(adev, 1);
2260 * amdgpu_device_resume - initiate device resume
2262 * @pdev: drm dev pointer
2264 * Bring the hw back to operating state (all asics).
2265 * Returns 0 for success or an error on failure.
2266 * Called at driver resume.
2268 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2270 struct drm_connector *connector;
2271 struct amdgpu_device *adev = dev->dev_private;
2272 struct drm_crtc *crtc;
2275 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2282 pci_set_power_state(dev->pdev, PCI_D0);
2283 pci_restore_state(dev->pdev);
2284 r = pci_enable_device(dev->pdev);
2290 if (amdgpu_device_need_post(adev)) {
2291 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2293 DRM_ERROR("amdgpu asic init failed\n");
2296 r = amdgpu_device_ip_resume(adev);
2298 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2301 amdgpu_fence_driver_resume(adev);
2304 r = amdgpu_ib_ring_tests(adev);
2306 DRM_ERROR("ib ring test failed (%d).\n", r);
2309 r = amdgpu_device_ip_late_init(adev);
2314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2315 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2317 if (amdgpu_crtc->cursor_bo) {
2318 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2319 r = amdgpu_bo_reserve(aobj, true);
2321 r = amdgpu_bo_pin(aobj,
2322 AMDGPU_GEM_DOMAIN_VRAM,
2323 &amdgpu_crtc->cursor_addr);
2325 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2326 amdgpu_bo_unreserve(aobj);
2330 r = amdgpu_amdkfd_resume(adev);
2334 /* blat the mode back in */
2336 if (!amdgpu_device_has_dc_support(adev)) {
2338 drm_helper_resume_force_mode(dev);
2340 /* turn on display hw */
2341 drm_modeset_lock_all(dev);
2342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2343 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2345 drm_modeset_unlock_all(dev);
2349 drm_kms_helper_poll_enable(dev);
2352 * Most of the connector probing functions try to acquire runtime pm
2353 * refs to ensure that the GPU is powered on when connector polling is
2354 * performed. Since we're calling this from a runtime PM callback,
2355 * trying to acquire rpm refs will cause us to deadlock.
2357 * Since we're guaranteed to be holding the rpm lock, it's safe to
2358 * temporarily disable the rpm helpers so this doesn't deadlock us.
2361 dev->dev->power.disable_depth++;
2363 if (!amdgpu_device_has_dc_support(adev))
2364 drm_helper_hpd_irq_event(dev);
2366 drm_kms_helper_hotplug_event(dev);
2368 dev->dev->power.disable_depth--;
2372 amdgpu_fbdev_set_suspend(adev, 0);
2381 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2384 bool asic_hang = false;
2386 if (amdgpu_sriov_vf(adev))
2389 for (i = 0; i < adev->num_ip_blocks; i++) {
2390 if (!adev->ip_blocks[i].status.valid)
2392 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2393 adev->ip_blocks[i].status.hang =
2394 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2395 if (adev->ip_blocks[i].status.hang) {
2396 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2403 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2407 for (i = 0; i < adev->num_ip_blocks; i++) {
2408 if (!adev->ip_blocks[i].status.valid)
2410 if (adev->ip_blocks[i].status.hang &&
2411 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2412 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2421 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2425 for (i = 0; i < adev->num_ip_blocks; i++) {
2426 if (!adev->ip_blocks[i].status.valid)
2428 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2429 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2430 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2431 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2432 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2433 if (adev->ip_blocks[i].status.hang) {
2434 DRM_INFO("Some block need full reset!\n");
2442 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2446 for (i = 0; i < adev->num_ip_blocks; i++) {
2447 if (!adev->ip_blocks[i].status.valid)
2449 if (adev->ip_blocks[i].status.hang &&
2450 adev->ip_blocks[i].version->funcs->soft_reset) {
2451 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2460 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
2464 for (i = 0; i < adev->num_ip_blocks; i++) {
2465 if (!adev->ip_blocks[i].status.valid)
2467 if (adev->ip_blocks[i].status.hang &&
2468 adev->ip_blocks[i].version->funcs->post_soft_reset)
2469 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2477 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
2478 struct amdgpu_ring *ring,
2479 struct amdgpu_bo *bo,
2480 struct dma_fence **fence)
2488 r = amdgpu_bo_reserve(bo, true);
2491 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2492 /* if bo has been evicted, then no need to recover */
2493 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2494 r = amdgpu_bo_validate(bo->shadow);
2496 DRM_ERROR("bo validate failed!\n");
2500 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2503 DRM_ERROR("recover page table failed!\n");
2508 amdgpu_bo_unreserve(bo);
2512 static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev)
2514 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2515 struct amdgpu_bo *bo, *tmp;
2516 struct dma_fence *fence = NULL, *next = NULL;
2521 if (amdgpu_sriov_runtime(adev))
2522 tmo = msecs_to_jiffies(amdgpu_lockup_timeout);
2524 tmo = msecs_to_jiffies(100);
2526 DRM_INFO("recover vram bo from shadow start\n");
2527 mutex_lock(&adev->shadow_list_lock);
2528 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2530 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
2532 r = dma_fence_wait_timeout(fence, false, tmo);
2534 pr_err("wait fence %p[%d] timeout\n", fence, i);
2536 pr_err("wait fence %p[%d] interrupted\n", fence, i);
2538 dma_fence_put(fence);
2545 dma_fence_put(fence);
2548 mutex_unlock(&adev->shadow_list_lock);
2551 r = dma_fence_wait_timeout(fence, false, tmo);
2553 pr_err("wait fence %p[%d] timeout\n", fence, i);
2555 pr_err("wait fence %p[%d] interrupted\n", fence, i);
2558 dma_fence_put(fence);
2561 DRM_INFO("recover vram bo from shadow done\n");
2563 DRM_ERROR("recover vram bo from shadow failed\n");
2569 * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
2571 * @adev: amdgpu device pointer
2573 * attempt to do soft-reset or full-reset and reinitialize Asic
2574 * return 0 means successed otherwise failed
2576 static int amdgpu_device_reset(struct amdgpu_device *adev)
2578 bool need_full_reset, vram_lost = 0;
2581 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
2583 if (!need_full_reset) {
2584 amdgpu_device_ip_pre_soft_reset(adev);
2585 r = amdgpu_device_ip_soft_reset(adev);
2586 amdgpu_device_ip_post_soft_reset(adev);
2587 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
2588 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2589 need_full_reset = true;
2593 if (need_full_reset) {
2594 r = amdgpu_device_ip_suspend(adev);
2597 r = amdgpu_asic_reset(adev);
2599 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2602 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2603 r = amdgpu_device_ip_resume_phase1(adev);
2607 vram_lost = amdgpu_device_check_vram_lost(adev);
2609 DRM_ERROR("VRAM is lost!\n");
2610 atomic_inc(&adev->vram_lost_counter);
2613 r = amdgpu_gtt_mgr_recover(
2614 &adev->mman.bdev.man[TTM_PL_TT]);
2618 r = amdgpu_device_ip_resume_phase2(adev);
2623 amdgpu_device_fill_reset_magic(adev);
2629 amdgpu_irq_gpu_reset_resume_helper(adev);
2630 r = amdgpu_ib_ring_tests(adev);
2632 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2633 r = amdgpu_device_ip_suspend(adev);
2634 need_full_reset = true;
2639 if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost))
2640 r = amdgpu_device_handle_vram_lost(adev);
2646 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
2648 * @adev: amdgpu device pointer
2650 * do VF FLR and reinitialize Asic
2651 * return 0 means successed otherwise failed
2653 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, bool from_hypervisor)
2657 if (from_hypervisor)
2658 r = amdgpu_virt_request_full_gpu(adev, true);
2660 r = amdgpu_virt_reset_gpu(adev);
2664 /* Resume IP prior to SMC */
2665 r = amdgpu_device_ip_reinit_early_sriov(adev);
2669 /* we need recover gart prior to run SMC/CP/SDMA resume */
2670 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
2672 /* now we are okay to resume SMC/CP/SDMA */
2673 r = amdgpu_device_ip_reinit_late_sriov(adev);
2674 amdgpu_virt_release_full_gpu(adev, true);
2678 amdgpu_irq_gpu_reset_resume_helper(adev);
2679 r = amdgpu_ib_ring_tests(adev);
2681 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
2682 atomic_inc(&adev->vram_lost_counter);
2683 r = amdgpu_device_handle_vram_lost(adev);
2692 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
2694 * @adev: amdgpu device pointer
2695 * @job: which job trigger hang
2696 * @force forces reset regardless of amdgpu_gpu_recovery
2698 * Attempt to reset the GPU if it has hung (all asics).
2699 * Returns 0 for success or an error on failure.
2701 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
2702 struct amdgpu_job *job, bool force)
2704 struct drm_atomic_state *state = NULL;
2707 if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
2708 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2712 if (!force && (amdgpu_gpu_recovery == 0 ||
2713 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) {
2714 DRM_INFO("GPU recovery disabled.\n");
2718 dev_info(adev->dev, "GPU reset begin!\n");
2720 mutex_lock(&adev->lock_reset);
2721 atomic_inc(&adev->gpu_reset_counter);
2722 adev->in_gpu_reset = 1;
2725 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2727 /* store modesetting */
2728 if (amdgpu_device_has_dc_support(adev))
2729 state = drm_atomic_helper_suspend(adev->ddev);
2731 /* block all schedulers and reset given job's ring */
2732 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2733 struct amdgpu_ring *ring = adev->rings[i];
2735 if (!ring || !ring->sched.thread)
2738 kthread_park(ring->sched.thread);
2740 if (job && job->ring->idx != i)
2743 drm_sched_hw_job_reset(&ring->sched, &job->base);
2745 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2746 amdgpu_fence_driver_force_completion(ring);
2749 if (amdgpu_sriov_vf(adev))
2750 r = amdgpu_device_reset_sriov(adev, job ? false : true);
2752 r = amdgpu_device_reset(adev);
2754 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2755 struct amdgpu_ring *ring = adev->rings[i];
2757 if (!ring || !ring->sched.thread)
2760 /* only need recovery sched of the given job's ring
2761 * or all rings (in the case @job is NULL)
2762 * after above amdgpu_reset accomplished
2764 if ((!job || job->ring->idx == i) && !r)
2765 drm_sched_job_recovery(&ring->sched);
2767 kthread_unpark(ring->sched.thread);
2770 if (amdgpu_device_has_dc_support(adev)) {
2771 if (drm_atomic_helper_resume(adev->ddev, state))
2772 dev_info(adev->dev, "drm resume failed:%d\n", r);
2774 drm_helper_resume_force_mode(adev->ddev);
2777 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2780 /* bad news, how to tell it to userspace ? */
2781 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
2782 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
2784 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
2787 amdgpu_vf_error_trans_all(adev);
2788 adev->in_gpu_reset = 0;
2789 mutex_unlock(&adev->lock_reset);
2793 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
2798 if (amdgpu_pcie_gen_cap)
2799 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2801 if (amdgpu_pcie_lane_cap)
2802 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2804 /* covers APUs as well */
2805 if (pci_is_root_bus(adev->pdev->bus)) {
2806 if (adev->pm.pcie_gen_mask == 0)
2807 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2808 if (adev->pm.pcie_mlw_mask == 0)
2809 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2813 if (adev->pm.pcie_gen_mask == 0) {
2814 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2816 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2817 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2818 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2820 if (mask & DRM_PCIE_SPEED_25)
2821 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2822 if (mask & DRM_PCIE_SPEED_50)
2823 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2824 if (mask & DRM_PCIE_SPEED_80)
2825 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2827 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2830 if (adev->pm.pcie_mlw_mask == 0) {
2831 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2835 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2836 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2837 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2838 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2839 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2844 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2846 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2847 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2848 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2852 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2854 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2855 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2856 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2859 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2861 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2862 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2865 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2866 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2867 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2870 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2874 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2880 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;