2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
68 #include "amdgpu_reset.h"
70 #include <linux/suspend.h>
71 #include <drm/task_barrier.h>
72 #include <linux/pm_runtime.h>
74 #include <drm/drm_drv.h>
76 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
84 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
85 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
86 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
88 #define AMDGPU_RESUME_MS 2000
90 const char *amdgpu_asic_name[] = {
129 * DOC: pcie_replay_count
131 * The amdgpu driver provides a sysfs API for reporting the total number
132 * of PCIe replays (NAKs)
133 * The file pcie_replay_count is used for this and returns the total
134 * number of replays as a sum of the NAKs generated and NAKs received
137 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
138 struct device_attribute *attr, char *buf)
140 struct drm_device *ddev = dev_get_drvdata(dev);
141 struct amdgpu_device *adev = drm_to_adev(ddev);
142 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
144 return sysfs_emit(buf, "%llu\n", cnt);
147 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
148 amdgpu_device_get_pcie_replay_count, NULL);
150 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
155 * The amdgpu driver provides a sysfs API for reporting the product name
157 * The file serial_number is used for this and returns the product name
158 * as returned from the FRU.
159 * NOTE: This is only available for certain server cards
162 static ssize_t amdgpu_device_get_product_name(struct device *dev,
163 struct device_attribute *attr, char *buf)
165 struct drm_device *ddev = dev_get_drvdata(dev);
166 struct amdgpu_device *adev = drm_to_adev(ddev);
168 return sysfs_emit(buf, "%s\n", adev->product_name);
171 static DEVICE_ATTR(product_name, S_IRUGO,
172 amdgpu_device_get_product_name, NULL);
175 * DOC: product_number
177 * The amdgpu driver provides a sysfs API for reporting the part number
179 * The file serial_number is used for this and returns the part number
180 * as returned from the FRU.
181 * NOTE: This is only available for certain server cards
184 static ssize_t amdgpu_device_get_product_number(struct device *dev,
185 struct device_attribute *attr, char *buf)
187 struct drm_device *ddev = dev_get_drvdata(dev);
188 struct amdgpu_device *adev = drm_to_adev(ddev);
190 return sysfs_emit(buf, "%s\n", adev->product_number);
193 static DEVICE_ATTR(product_number, S_IRUGO,
194 amdgpu_device_get_product_number, NULL);
199 * The amdgpu driver provides a sysfs API for reporting the serial number
201 * The file serial_number is used for this and returns the serial number
202 * as returned from the FRU.
203 * NOTE: This is only available for certain server cards
206 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
207 struct device_attribute *attr, char *buf)
209 struct drm_device *ddev = dev_get_drvdata(dev);
210 struct amdgpu_device *adev = drm_to_adev(ddev);
212 return sysfs_emit(buf, "%s\n", adev->serial);
215 static DEVICE_ATTR(serial_number, S_IRUGO,
216 amdgpu_device_get_serial_number, NULL);
219 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
221 * @dev: drm_device pointer
223 * Returns true if the device is a dGPU with ATPX power control,
224 * otherwise return false.
226 bool amdgpu_device_supports_px(struct drm_device *dev)
228 struct amdgpu_device *adev = drm_to_adev(dev);
230 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
236 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
238 * @dev: drm_device pointer
240 * Returns true if the device is a dGPU with ACPI power control,
241 * otherwise return false.
243 bool amdgpu_device_supports_boco(struct drm_device *dev)
245 struct amdgpu_device *adev = drm_to_adev(dev);
248 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
254 * amdgpu_device_supports_baco - Does the device support BACO
256 * @dev: drm_device pointer
258 * Returns true if the device supporte BACO,
259 * otherwise return false.
261 bool amdgpu_device_supports_baco(struct drm_device *dev)
263 struct amdgpu_device *adev = drm_to_adev(dev);
265 return amdgpu_asic_supports_baco(adev);
269 * amdgpu_device_supports_smart_shift - Is the device dGPU with
270 * smart shift support
272 * @dev: drm_device pointer
274 * Returns true if the device is a dGPU with Smart Shift support,
275 * otherwise returns false.
277 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
279 return (amdgpu_device_supports_boco(dev) &&
280 amdgpu_acpi_is_power_shift_control_supported());
284 * VRAM access helper functions
288 * amdgpu_device_vram_access - read/write a buffer in vram
290 * @adev: amdgpu_device pointer
291 * @pos: offset of the buffer in vram
292 * @buf: virtual address of the buffer in system memory
293 * @size: read/write size, sizeof(@buf) must > @size
294 * @write: true - write to vram, otherwise - read from vram
296 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
297 uint32_t *buf, size_t size, bool write)
304 if (!drm_dev_enter(&adev->ddev, &idx))
308 last = min(pos + size, adev->gmc.visible_vram_size);
310 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
311 size_t count = last - pos;
314 memcpy_toio(addr, buf, count);
316 amdgpu_asic_flush_hdp(adev, NULL);
318 amdgpu_asic_invalidate_hdp(adev, NULL);
320 memcpy_fromio(buf, addr, count);
332 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
333 for (last = pos + size; pos < last; pos += 4) {
334 uint32_t tmp = pos >> 31;
336 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
338 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
342 WREG32_NO_KIQ(mmMM_DATA, *buf++);
344 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
346 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
355 * register access helper functions.
358 /* Check if hw access should be skipped because of hotplug or device error */
359 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
361 if (adev->no_hw_access)
364 #ifdef CONFIG_LOCKDEP
366 * This is a bit complicated to understand, so worth a comment. What we assert
367 * here is that the GPU reset is not running on another thread in parallel.
369 * For this we trylock the read side of the reset semaphore, if that succeeds
370 * we know that the reset is not running in paralell.
372 * If the trylock fails we assert that we are either already holding the read
373 * side of the lock or are the reset thread itself and hold the write side of
377 if (down_read_trylock(&adev->reset_sem))
378 up_read(&adev->reset_sem);
380 lockdep_assert_held(&adev->reset_sem);
387 * amdgpu_device_rreg - read a memory mapped IO or indirect register
389 * @adev: amdgpu_device pointer
390 * @reg: dword aligned register offset
391 * @acc_flags: access flags which require special behavior
393 * Returns the 32 bit value from the offset specified.
395 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
396 uint32_t reg, uint32_t acc_flags)
400 if (amdgpu_device_skip_hw_access(adev))
403 if ((reg * 4) < adev->rmmio_size) {
404 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
405 amdgpu_sriov_runtime(adev) &&
406 down_read_trylock(&adev->reset_sem)) {
407 ret = amdgpu_kiq_rreg(adev, reg);
408 up_read(&adev->reset_sem);
410 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
413 ret = adev->pcie_rreg(adev, reg * 4);
416 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
422 * MMIO register read with bytes helper functions
423 * @offset:bytes offset from MMIO start
428 * amdgpu_mm_rreg8 - read a memory mapped IO register
430 * @adev: amdgpu_device pointer
431 * @offset: byte aligned register offset
433 * Returns the 8 bit value from the offset specified.
435 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
437 if (amdgpu_device_skip_hw_access(adev))
440 if (offset < adev->rmmio_size)
441 return (readb(adev->rmmio + offset));
446 * MMIO register write with bytes helper functions
447 * @offset:bytes offset from MMIO start
448 * @value: the value want to be written to the register
452 * amdgpu_mm_wreg8 - read a memory mapped IO register
454 * @adev: amdgpu_device pointer
455 * @offset: byte aligned register offset
456 * @value: 8 bit value to write
458 * Writes the value specified to the offset specified.
460 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
462 if (amdgpu_device_skip_hw_access(adev))
465 if (offset < adev->rmmio_size)
466 writeb(value, adev->rmmio + offset);
472 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
474 * @adev: amdgpu_device pointer
475 * @reg: dword aligned register offset
476 * @v: 32 bit value to write to the register
477 * @acc_flags: access flags which require special behavior
479 * Writes the value specified to the offset specified.
481 void amdgpu_device_wreg(struct amdgpu_device *adev,
482 uint32_t reg, uint32_t v,
485 if (amdgpu_device_skip_hw_access(adev))
488 if ((reg * 4) < adev->rmmio_size) {
489 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
490 amdgpu_sriov_runtime(adev) &&
491 down_read_trylock(&adev->reset_sem)) {
492 amdgpu_kiq_wreg(adev, reg, v);
493 up_read(&adev->reset_sem);
495 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
498 adev->pcie_wreg(adev, reg * 4, v);
501 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
505 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
507 * this function is invoked only the debugfs register access
509 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
510 uint32_t reg, uint32_t v)
512 if (amdgpu_device_skip_hw_access(adev))
515 if (amdgpu_sriov_fullaccess(adev) &&
516 adev->gfx.rlc.funcs &&
517 adev->gfx.rlc.funcs->is_rlcg_access_range) {
518 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
519 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0);
521 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
526 * amdgpu_mm_rdoorbell - read a doorbell dword
528 * @adev: amdgpu_device pointer
529 * @index: doorbell index
531 * Returns the value in the doorbell aperture at the
532 * requested doorbell index (CIK).
534 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
536 if (amdgpu_device_skip_hw_access(adev))
539 if (index < adev->doorbell.num_doorbells) {
540 return readl(adev->doorbell.ptr + index);
542 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
548 * amdgpu_mm_wdoorbell - write a doorbell dword
550 * @adev: amdgpu_device pointer
551 * @index: doorbell index
554 * Writes @v to the doorbell aperture at the
555 * requested doorbell index (CIK).
557 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
559 if (amdgpu_device_skip_hw_access(adev))
562 if (index < adev->doorbell.num_doorbells) {
563 writel(v, adev->doorbell.ptr + index);
565 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
570 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
572 * @adev: amdgpu_device pointer
573 * @index: doorbell index
575 * Returns the value in the doorbell aperture at the
576 * requested doorbell index (VEGA10+).
578 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
580 if (amdgpu_device_skip_hw_access(adev))
583 if (index < adev->doorbell.num_doorbells) {
584 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
586 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
592 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
594 * @adev: amdgpu_device pointer
595 * @index: doorbell index
598 * Writes @v to the doorbell aperture at the
599 * requested doorbell index (VEGA10+).
601 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
603 if (amdgpu_device_skip_hw_access(adev))
606 if (index < adev->doorbell.num_doorbells) {
607 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
609 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
614 * amdgpu_device_indirect_rreg - read an indirect register
616 * @adev: amdgpu_device pointer
617 * @pcie_index: mmio register offset
618 * @pcie_data: mmio register offset
619 * @reg_addr: indirect register address to read from
621 * Returns the value of indirect register @reg_addr
623 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
624 u32 pcie_index, u32 pcie_data,
629 void __iomem *pcie_index_offset;
630 void __iomem *pcie_data_offset;
632 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
633 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
634 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
636 writel(reg_addr, pcie_index_offset);
637 readl(pcie_index_offset);
638 r = readl(pcie_data_offset);
639 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
645 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
647 * @adev: amdgpu_device pointer
648 * @pcie_index: mmio register offset
649 * @pcie_data: mmio register offset
650 * @reg_addr: indirect register address to read from
652 * Returns the value of indirect register @reg_addr
654 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
655 u32 pcie_index, u32 pcie_data,
660 void __iomem *pcie_index_offset;
661 void __iomem *pcie_data_offset;
663 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
664 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
665 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
667 /* read low 32 bits */
668 writel(reg_addr, pcie_index_offset);
669 readl(pcie_index_offset);
670 r = readl(pcie_data_offset);
671 /* read high 32 bits */
672 writel(reg_addr + 4, pcie_index_offset);
673 readl(pcie_index_offset);
674 r |= ((u64)readl(pcie_data_offset) << 32);
675 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
681 * amdgpu_device_indirect_wreg - write an indirect register address
683 * @adev: amdgpu_device pointer
684 * @pcie_index: mmio register offset
685 * @pcie_data: mmio register offset
686 * @reg_addr: indirect register offset
687 * @reg_data: indirect register data
690 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
691 u32 pcie_index, u32 pcie_data,
692 u32 reg_addr, u32 reg_data)
695 void __iomem *pcie_index_offset;
696 void __iomem *pcie_data_offset;
698 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
699 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
700 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
702 writel(reg_addr, pcie_index_offset);
703 readl(pcie_index_offset);
704 writel(reg_data, pcie_data_offset);
705 readl(pcie_data_offset);
706 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
710 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
712 * @adev: amdgpu_device pointer
713 * @pcie_index: mmio register offset
714 * @pcie_data: mmio register offset
715 * @reg_addr: indirect register offset
716 * @reg_data: indirect register data
719 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
720 u32 pcie_index, u32 pcie_data,
721 u32 reg_addr, u64 reg_data)
724 void __iomem *pcie_index_offset;
725 void __iomem *pcie_data_offset;
727 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
728 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
729 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
731 /* write low 32 bits */
732 writel(reg_addr, pcie_index_offset);
733 readl(pcie_index_offset);
734 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
735 readl(pcie_data_offset);
736 /* write high 32 bits */
737 writel(reg_addr + 4, pcie_index_offset);
738 readl(pcie_index_offset);
739 writel((u32)(reg_data >> 32), pcie_data_offset);
740 readl(pcie_data_offset);
741 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
745 * amdgpu_invalid_rreg - dummy reg read function
747 * @adev: amdgpu_device pointer
748 * @reg: offset of register
750 * Dummy register read function. Used for register blocks
751 * that certain asics don't have (all asics).
752 * Returns the value in the register.
754 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
756 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
762 * amdgpu_invalid_wreg - dummy reg write function
764 * @adev: amdgpu_device pointer
765 * @reg: offset of register
766 * @v: value to write to the register
768 * Dummy register read function. Used for register blocks
769 * that certain asics don't have (all asics).
771 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
773 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
779 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
781 * @adev: amdgpu_device pointer
782 * @reg: offset of register
784 * Dummy register read function. Used for register blocks
785 * that certain asics don't have (all asics).
786 * Returns the value in the register.
788 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
790 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
796 * amdgpu_invalid_wreg64 - dummy reg write function
798 * @adev: amdgpu_device pointer
799 * @reg: offset of register
800 * @v: value to write to the register
802 * Dummy register read function. Used for register blocks
803 * that certain asics don't have (all asics).
805 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
807 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
813 * amdgpu_block_invalid_rreg - dummy reg read function
815 * @adev: amdgpu_device pointer
816 * @block: offset of instance
817 * @reg: offset of register
819 * Dummy register read function. Used for register blocks
820 * that certain asics don't have (all asics).
821 * Returns the value in the register.
823 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
824 uint32_t block, uint32_t reg)
826 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
833 * amdgpu_block_invalid_wreg - dummy reg write function
835 * @adev: amdgpu_device pointer
836 * @block: offset of instance
837 * @reg: offset of register
838 * @v: value to write to the register
840 * Dummy register read function. Used for register blocks
841 * that certain asics don't have (all asics).
843 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
845 uint32_t reg, uint32_t v)
847 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
853 * amdgpu_device_asic_init - Wrapper for atom asic_init
855 * @adev: amdgpu_device pointer
857 * Does any asic specific work and then calls atom asic init.
859 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
861 amdgpu_asic_pre_asic_init(adev);
863 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
867 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
869 * @adev: amdgpu_device pointer
871 * Allocates a scratch page of VRAM for use by various things in the
874 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
876 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
877 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
878 &adev->vram_scratch.robj,
879 &adev->vram_scratch.gpu_addr,
880 (void **)&adev->vram_scratch.ptr);
884 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
886 * @adev: amdgpu_device pointer
888 * Frees the VRAM scratch page.
890 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
892 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
896 * amdgpu_device_program_register_sequence - program an array of registers.
898 * @adev: amdgpu_device pointer
899 * @registers: pointer to the register array
900 * @array_size: size of the register array
902 * Programs an array or registers with and and or masks.
903 * This is a helper for setting golden registers.
905 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
906 const u32 *registers,
907 const u32 array_size)
909 u32 tmp, reg, and_mask, or_mask;
915 for (i = 0; i < array_size; i +=3) {
916 reg = registers[i + 0];
917 and_mask = registers[i + 1];
918 or_mask = registers[i + 2];
920 if (and_mask == 0xffffffff) {
925 if (adev->family >= AMDGPU_FAMILY_AI)
926 tmp |= (or_mask & and_mask);
935 * amdgpu_device_pci_config_reset - reset the GPU
937 * @adev: amdgpu_device pointer
939 * Resets the GPU using the pci config reset sequence.
940 * Only applicable to asics prior to vega10.
942 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
944 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
948 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
950 * @adev: amdgpu_device pointer
952 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
954 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
956 return pci_reset_function(adev->pdev);
960 * GPU doorbell aperture helpers function.
963 * amdgpu_device_doorbell_init - Init doorbell driver information.
965 * @adev: amdgpu_device pointer
967 * Init doorbell driver information (CIK)
968 * Returns 0 on success, error on failure.
970 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
973 /* No doorbell on SI hardware generation */
974 if (adev->asic_type < CHIP_BONAIRE) {
975 adev->doorbell.base = 0;
976 adev->doorbell.size = 0;
977 adev->doorbell.num_doorbells = 0;
978 adev->doorbell.ptr = NULL;
982 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
985 amdgpu_asic_init_doorbell_index(adev);
987 /* doorbell bar mapping */
988 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
989 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
991 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
992 adev->doorbell_index.max_assignment+1);
993 if (adev->doorbell.num_doorbells == 0)
996 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
997 * paging queue doorbell use the second page. The
998 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
999 * doorbells are in the first page. So with paging queue enabled,
1000 * the max num_doorbells should + 1 page (0x400 in dword)
1002 if (adev->asic_type >= CHIP_VEGA10)
1003 adev->doorbell.num_doorbells += 0x400;
1005 adev->doorbell.ptr = ioremap(adev->doorbell.base,
1006 adev->doorbell.num_doorbells *
1008 if (adev->doorbell.ptr == NULL)
1015 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1017 * @adev: amdgpu_device pointer
1019 * Tear down doorbell driver information (CIK)
1021 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1023 iounmap(adev->doorbell.ptr);
1024 adev->doorbell.ptr = NULL;
1030 * amdgpu_device_wb_*()
1031 * Writeback is the method by which the GPU updates special pages in memory
1032 * with the status of certain GPU events (fences, ring pointers,etc.).
1036 * amdgpu_device_wb_fini - Disable Writeback and free memory
1038 * @adev: amdgpu_device pointer
1040 * Disables Writeback and frees the Writeback memory (all asics).
1041 * Used at driver shutdown.
1043 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1045 if (adev->wb.wb_obj) {
1046 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1048 (void **)&adev->wb.wb);
1049 adev->wb.wb_obj = NULL;
1054 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1056 * @adev: amdgpu_device pointer
1058 * Initializes writeback and allocates writeback memory (all asics).
1059 * Used at driver startup.
1060 * Returns 0 on success or an -error on failure.
1062 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1066 if (adev->wb.wb_obj == NULL) {
1067 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1068 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1069 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1070 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1071 (void **)&adev->wb.wb);
1073 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1077 adev->wb.num_wb = AMDGPU_MAX_WB;
1078 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1080 /* clear wb memory */
1081 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1088 * amdgpu_device_wb_get - Allocate a wb entry
1090 * @adev: amdgpu_device pointer
1093 * Allocate a wb slot for use by the driver (all asics).
1094 * Returns 0 on success or -EINVAL on failure.
1096 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1098 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1100 if (offset < adev->wb.num_wb) {
1101 __set_bit(offset, adev->wb.used);
1102 *wb = offset << 3; /* convert to dw offset */
1110 * amdgpu_device_wb_free - Free a wb entry
1112 * @adev: amdgpu_device pointer
1115 * Free a wb slot allocated for use by the driver (all asics)
1117 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1120 if (wb < adev->wb.num_wb)
1121 __clear_bit(wb, adev->wb.used);
1125 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1127 * @adev: amdgpu_device pointer
1129 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1130 * to fail, but if any of the BARs is not accessible after the size we abort
1131 * driver loading by returning -ENODEV.
1133 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1135 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1136 struct pci_bus *root;
1137 struct resource *res;
1143 if (amdgpu_sriov_vf(adev))
1146 /* skip if the bios has already enabled large BAR */
1147 if (adev->gmc.real_vram_size &&
1148 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1151 /* Check if the root BUS has 64bit memory resources */
1152 root = adev->pdev->bus;
1153 while (root->parent)
1154 root = root->parent;
1156 pci_bus_for_each_resource(root, res, i) {
1157 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1158 res->start > 0x100000000ull)
1162 /* Trying to resize is pointless without a root hub window above 4GB */
1166 /* Limit the BAR size to what is available */
1167 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1170 /* Disable memory decoding while we change the BAR addresses and size */
1171 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1172 pci_write_config_word(adev->pdev, PCI_COMMAND,
1173 cmd & ~PCI_COMMAND_MEMORY);
1175 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1176 amdgpu_device_doorbell_fini(adev);
1177 if (adev->asic_type >= CHIP_BONAIRE)
1178 pci_release_resource(adev->pdev, 2);
1180 pci_release_resource(adev->pdev, 0);
1182 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1184 DRM_INFO("Not enough PCI address space for a large BAR.");
1185 else if (r && r != -ENOTSUPP)
1186 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1188 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1190 /* When the doorbell or fb BAR isn't available we have no chance of
1193 r = amdgpu_device_doorbell_init(adev);
1194 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1197 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1203 * GPU helpers function.
1206 * amdgpu_device_need_post - check if the hw need post or not
1208 * @adev: amdgpu_device pointer
1210 * Check if the asic has been initialized (all asics) at driver startup
1211 * or post is needed if hw reset is performed.
1212 * Returns true if need or false if not.
1214 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1218 if (amdgpu_sriov_vf(adev))
1221 if (amdgpu_passthrough(adev)) {
1222 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1223 * some old smc fw still need driver do vPost otherwise gpu hang, while
1224 * those smc fw version above 22.15 doesn't have this flaw, so we force
1225 * vpost executed for smc version below 22.15
1227 if (adev->asic_type == CHIP_FIJI) {
1230 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1231 /* force vPost if error occured */
1235 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1236 if (fw_ver < 0x00160e00)
1241 /* Don't post if we need to reset whole hive on init */
1242 if (adev->gmc.xgmi.pending_reset)
1245 if (adev->has_hw_reset) {
1246 adev->has_hw_reset = false;
1250 /* bios scratch used on CIK+ */
1251 if (adev->asic_type >= CHIP_BONAIRE)
1252 return amdgpu_atombios_scratch_need_asic_init(adev);
1254 /* check MEM_SIZE for older asics */
1255 reg = amdgpu_asic_get_config_memsize(adev);
1257 if ((reg != 0) && (reg != 0xffffffff))
1263 /* if we get transitioned to only one device, take VGA back */
1265 * amdgpu_device_vga_set_decode - enable/disable vga decode
1267 * @cookie: amdgpu_device pointer
1268 * @state: enable/disable vga decode
1270 * Enable/disable vga decode (all asics).
1271 * Returns VGA resource flags.
1273 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1275 struct amdgpu_device *adev = cookie;
1276 amdgpu_asic_set_vga_state(adev, state);
1278 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1279 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1281 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1285 * amdgpu_device_check_block_size - validate the vm block size
1287 * @adev: amdgpu_device pointer
1289 * Validates the vm block size specified via module parameter.
1290 * The vm block size defines number of bits in page table versus page directory,
1291 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1292 * page table and the remaining bits are in the page directory.
1294 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1296 /* defines number of bits in page table versus page directory,
1297 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1298 * page table and the remaining bits are in the page directory */
1299 if (amdgpu_vm_block_size == -1)
1302 if (amdgpu_vm_block_size < 9) {
1303 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1304 amdgpu_vm_block_size);
1305 amdgpu_vm_block_size = -1;
1310 * amdgpu_device_check_vm_size - validate the vm size
1312 * @adev: amdgpu_device pointer
1314 * Validates the vm size in GB specified via module parameter.
1315 * The VM size is the size of the GPU virtual memory space in GB.
1317 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1319 /* no need to check the default value */
1320 if (amdgpu_vm_size == -1)
1323 if (amdgpu_vm_size < 1) {
1324 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1326 amdgpu_vm_size = -1;
1330 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1333 bool is_os_64 = (sizeof(void *) == 8);
1334 uint64_t total_memory;
1335 uint64_t dram_size_seven_GB = 0x1B8000000;
1336 uint64_t dram_size_three_GB = 0xB8000000;
1338 if (amdgpu_smu_memory_pool_size == 0)
1342 DRM_WARN("Not 64-bit OS, feature not supported\n");
1346 total_memory = (uint64_t)si.totalram * si.mem_unit;
1348 if ((amdgpu_smu_memory_pool_size == 1) ||
1349 (amdgpu_smu_memory_pool_size == 2)) {
1350 if (total_memory < dram_size_three_GB)
1352 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1353 (amdgpu_smu_memory_pool_size == 8)) {
1354 if (total_memory < dram_size_seven_GB)
1357 DRM_WARN("Smu memory pool size not supported\n");
1360 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1365 DRM_WARN("No enough system memory\n");
1367 adev->pm.smu_prv_buffer_size = 0;
1371 * amdgpu_device_check_arguments - validate module params
1373 * @adev: amdgpu_device pointer
1375 * Validates certain module parameters and updates
1376 * the associated values used by the driver (all asics).
1378 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1380 if (amdgpu_sched_jobs < 4) {
1381 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1383 amdgpu_sched_jobs = 4;
1384 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1385 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1387 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1390 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1391 /* gart size must be greater or equal to 32M */
1392 dev_warn(adev->dev, "gart size (%d) too small\n",
1394 amdgpu_gart_size = -1;
1397 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1398 /* gtt size must be greater or equal to 32M */
1399 dev_warn(adev->dev, "gtt size (%d) too small\n",
1401 amdgpu_gtt_size = -1;
1404 /* valid range is between 4 and 9 inclusive */
1405 if (amdgpu_vm_fragment_size != -1 &&
1406 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1407 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1408 amdgpu_vm_fragment_size = -1;
1411 if (amdgpu_sched_hw_submission < 2) {
1412 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1413 amdgpu_sched_hw_submission);
1414 amdgpu_sched_hw_submission = 2;
1415 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1416 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1417 amdgpu_sched_hw_submission);
1418 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1421 amdgpu_device_check_smu_prv_buffer_size(adev);
1423 amdgpu_device_check_vm_size(adev);
1425 amdgpu_device_check_block_size(adev);
1427 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1429 amdgpu_gmc_tmz_set(adev);
1431 amdgpu_gmc_noretry_set(adev);
1437 * amdgpu_switcheroo_set_state - set switcheroo state
1439 * @pdev: pci dev pointer
1440 * @state: vga_switcheroo state
1442 * Callback for the switcheroo driver. Suspends or resumes the
1443 * the asics before or after it is powered up using ACPI methods.
1445 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1446 enum vga_switcheroo_state state)
1448 struct drm_device *dev = pci_get_drvdata(pdev);
1451 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1454 if (state == VGA_SWITCHEROO_ON) {
1455 pr_info("switched on\n");
1456 /* don't suspend or resume card normally */
1457 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1459 pci_set_power_state(pdev, PCI_D0);
1460 amdgpu_device_load_pci_state(pdev);
1461 r = pci_enable_device(pdev);
1463 DRM_WARN("pci_enable_device failed (%d)\n", r);
1464 amdgpu_device_resume(dev, true);
1466 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1468 pr_info("switched off\n");
1469 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1470 amdgpu_device_suspend(dev, true);
1471 amdgpu_device_cache_pci_state(pdev);
1472 /* Shut down the device */
1473 pci_disable_device(pdev);
1474 pci_set_power_state(pdev, PCI_D3cold);
1475 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1480 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1482 * @pdev: pci dev pointer
1484 * Callback for the switcheroo driver. Check of the switcheroo
1485 * state can be changed.
1486 * Returns true if the state can be changed, false if not.
1488 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1490 struct drm_device *dev = pci_get_drvdata(pdev);
1493 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1494 * locking inversion with the driver load path. And the access here is
1495 * completely racy anyway. So don't bother with locking for now.
1497 return atomic_read(&dev->open_count) == 0;
1500 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1501 .set_gpu_state = amdgpu_switcheroo_set_state,
1503 .can_switch = amdgpu_switcheroo_can_switch,
1507 * amdgpu_device_ip_set_clockgating_state - set the CG state
1509 * @dev: amdgpu_device pointer
1510 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1511 * @state: clockgating state (gate or ungate)
1513 * Sets the requested clockgating state for all instances of
1514 * the hardware IP specified.
1515 * Returns the error code from the last instance.
1517 int amdgpu_device_ip_set_clockgating_state(void *dev,
1518 enum amd_ip_block_type block_type,
1519 enum amd_clockgating_state state)
1521 struct amdgpu_device *adev = dev;
1524 for (i = 0; i < adev->num_ip_blocks; i++) {
1525 if (!adev->ip_blocks[i].status.valid)
1527 if (adev->ip_blocks[i].version->type != block_type)
1529 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1531 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1532 (void *)adev, state);
1534 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1535 adev->ip_blocks[i].version->funcs->name, r);
1541 * amdgpu_device_ip_set_powergating_state - set the PG state
1543 * @dev: amdgpu_device pointer
1544 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1545 * @state: powergating state (gate or ungate)
1547 * Sets the requested powergating state for all instances of
1548 * the hardware IP specified.
1549 * Returns the error code from the last instance.
1551 int amdgpu_device_ip_set_powergating_state(void *dev,
1552 enum amd_ip_block_type block_type,
1553 enum amd_powergating_state state)
1555 struct amdgpu_device *adev = dev;
1558 for (i = 0; i < adev->num_ip_blocks; i++) {
1559 if (!adev->ip_blocks[i].status.valid)
1561 if (adev->ip_blocks[i].version->type != block_type)
1563 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1565 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1566 (void *)adev, state);
1568 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1569 adev->ip_blocks[i].version->funcs->name, r);
1575 * amdgpu_device_ip_get_clockgating_state - get the CG state
1577 * @adev: amdgpu_device pointer
1578 * @flags: clockgating feature flags
1580 * Walks the list of IPs on the device and updates the clockgating
1581 * flags for each IP.
1582 * Updates @flags with the feature flags for each hardware IP where
1583 * clockgating is enabled.
1585 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1590 for (i = 0; i < adev->num_ip_blocks; i++) {
1591 if (!adev->ip_blocks[i].status.valid)
1593 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1594 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1599 * amdgpu_device_ip_wait_for_idle - wait for idle
1601 * @adev: amdgpu_device pointer
1602 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1604 * Waits for the request hardware IP to be idle.
1605 * Returns 0 for success or a negative error code on failure.
1607 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1608 enum amd_ip_block_type block_type)
1612 for (i = 0; i < adev->num_ip_blocks; i++) {
1613 if (!adev->ip_blocks[i].status.valid)
1615 if (adev->ip_blocks[i].version->type == block_type) {
1616 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1627 * amdgpu_device_ip_is_idle - is the hardware IP idle
1629 * @adev: amdgpu_device pointer
1630 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1632 * Check if the hardware IP is idle or not.
1633 * Returns true if it the IP is idle, false if not.
1635 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1636 enum amd_ip_block_type block_type)
1640 for (i = 0; i < adev->num_ip_blocks; i++) {
1641 if (!adev->ip_blocks[i].status.valid)
1643 if (adev->ip_blocks[i].version->type == block_type)
1644 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1651 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1653 * @adev: amdgpu_device pointer
1654 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1656 * Returns a pointer to the hardware IP block structure
1657 * if it exists for the asic, otherwise NULL.
1659 struct amdgpu_ip_block *
1660 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1661 enum amd_ip_block_type type)
1665 for (i = 0; i < adev->num_ip_blocks; i++)
1666 if (adev->ip_blocks[i].version->type == type)
1667 return &adev->ip_blocks[i];
1673 * amdgpu_device_ip_block_version_cmp
1675 * @adev: amdgpu_device pointer
1676 * @type: enum amd_ip_block_type
1677 * @major: major version
1678 * @minor: minor version
1680 * return 0 if equal or greater
1681 * return 1 if smaller or the ip_block doesn't exist
1683 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1684 enum amd_ip_block_type type,
1685 u32 major, u32 minor)
1687 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1689 if (ip_block && ((ip_block->version->major > major) ||
1690 ((ip_block->version->major == major) &&
1691 (ip_block->version->minor >= minor))))
1698 * amdgpu_device_ip_block_add
1700 * @adev: amdgpu_device pointer
1701 * @ip_block_version: pointer to the IP to add
1703 * Adds the IP block driver information to the collection of IPs
1706 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1707 const struct amdgpu_ip_block_version *ip_block_version)
1709 if (!ip_block_version)
1712 switch (ip_block_version->type) {
1713 case AMD_IP_BLOCK_TYPE_VCN:
1714 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1717 case AMD_IP_BLOCK_TYPE_JPEG:
1718 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1725 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1726 ip_block_version->funcs->name);
1728 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1734 * amdgpu_device_enable_virtual_display - enable virtual display feature
1736 * @adev: amdgpu_device pointer
1738 * Enabled the virtual display feature if the user has enabled it via
1739 * the module parameter virtual_display. This feature provides a virtual
1740 * display hardware on headless boards or in virtualized environments.
1741 * This function parses and validates the configuration string specified by
1742 * the user and configues the virtual display configuration (number of
1743 * virtual connectors, crtcs, etc.) specified.
1745 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1747 adev->enable_virtual_display = false;
1749 if (amdgpu_virtual_display) {
1750 const char *pci_address_name = pci_name(adev->pdev);
1751 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1753 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1754 pciaddstr_tmp = pciaddstr;
1755 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1756 pciaddname = strsep(&pciaddname_tmp, ",");
1757 if (!strcmp("all", pciaddname)
1758 || !strcmp(pci_address_name, pciaddname)) {
1762 adev->enable_virtual_display = true;
1765 res = kstrtol(pciaddname_tmp, 10,
1773 adev->mode_info.num_crtc = num_crtc;
1775 adev->mode_info.num_crtc = 1;
1781 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1782 amdgpu_virtual_display, pci_address_name,
1783 adev->enable_virtual_display, adev->mode_info.num_crtc);
1790 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1792 * @adev: amdgpu_device pointer
1794 * Parses the asic configuration parameters specified in the gpu info
1795 * firmware and makes them availale to the driver for use in configuring
1797 * Returns 0 on success, -EINVAL on failure.
1799 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1801 const char *chip_name;
1804 const struct gpu_info_firmware_header_v1_0 *hdr;
1806 adev->firmware.gpu_info_fw = NULL;
1808 if (adev->mman.discovery_bin) {
1809 amdgpu_discovery_get_gfx_info(adev);
1812 * FIXME: The bounding box is still needed by Navi12, so
1813 * temporarily read it from gpu_info firmware. Should be droped
1814 * when DAL no longer needs it.
1816 if (adev->asic_type != CHIP_NAVI12)
1820 switch (adev->asic_type) {
1821 #ifdef CONFIG_DRM_AMDGPU_SI
1828 #ifdef CONFIG_DRM_AMDGPU_CIK
1838 case CHIP_POLARIS10:
1839 case CHIP_POLARIS11:
1840 case CHIP_POLARIS12:
1845 case CHIP_ALDEBARAN:
1846 case CHIP_SIENNA_CICHLID:
1847 case CHIP_NAVY_FLOUNDER:
1848 case CHIP_DIMGREY_CAVEFISH:
1849 case CHIP_BEIGE_GOBY:
1853 chip_name = "vega10";
1856 chip_name = "vega12";
1859 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1860 chip_name = "raven2";
1861 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1862 chip_name = "picasso";
1864 chip_name = "raven";
1867 chip_name = "arcturus";
1870 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1871 chip_name = "renoir";
1873 chip_name = "green_sardine";
1876 chip_name = "navi10";
1879 chip_name = "navi14";
1882 chip_name = "navi12";
1885 chip_name = "vangogh";
1889 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1890 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1893 "Failed to load gpu_info firmware \"%s\"\n",
1897 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1900 "Failed to validate gpu_info firmware \"%s\"\n",
1905 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1906 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1908 switch (hdr->version_major) {
1911 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1912 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1913 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1916 * Should be droped when DAL no longer needs it.
1918 if (adev->asic_type == CHIP_NAVI12)
1919 goto parse_soc_bounding_box;
1921 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1922 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1923 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1924 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1925 adev->gfx.config.max_texture_channel_caches =
1926 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1927 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1928 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1929 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1930 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1931 adev->gfx.config.double_offchip_lds_buf =
1932 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1933 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1934 adev->gfx.cu_info.max_waves_per_simd =
1935 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1936 adev->gfx.cu_info.max_scratch_slots_per_cu =
1937 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1938 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1939 if (hdr->version_minor >= 1) {
1940 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1941 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1942 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1943 adev->gfx.config.num_sc_per_sh =
1944 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1945 adev->gfx.config.num_packer_per_sc =
1946 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1949 parse_soc_bounding_box:
1951 * soc bounding box info is not integrated in disocovery table,
1952 * we always need to parse it from gpu info firmware if needed.
1954 if (hdr->version_minor == 2) {
1955 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1956 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1957 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1958 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1964 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1973 * amdgpu_device_ip_early_init - run early init for hardware IPs
1975 * @adev: amdgpu_device pointer
1977 * Early initialization pass for hardware IPs. The hardware IPs that make
1978 * up each asic are discovered each IP's early_init callback is run. This
1979 * is the first stage in initializing the asic.
1980 * Returns 0 on success, negative error code on failure.
1982 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1986 amdgpu_device_enable_virtual_display(adev);
1988 if (amdgpu_sriov_vf(adev)) {
1989 r = amdgpu_virt_request_full_gpu(adev, true);
1994 switch (adev->asic_type) {
1995 #ifdef CONFIG_DRM_AMDGPU_SI
2001 adev->family = AMDGPU_FAMILY_SI;
2002 r = si_set_ip_blocks(adev);
2007 #ifdef CONFIG_DRM_AMDGPU_CIK
2013 if (adev->flags & AMD_IS_APU)
2014 adev->family = AMDGPU_FAMILY_KV;
2016 adev->family = AMDGPU_FAMILY_CI;
2018 r = cik_set_ip_blocks(adev);
2026 case CHIP_POLARIS10:
2027 case CHIP_POLARIS11:
2028 case CHIP_POLARIS12:
2032 if (adev->flags & AMD_IS_APU)
2033 adev->family = AMDGPU_FAMILY_CZ;
2035 adev->family = AMDGPU_FAMILY_VI;
2037 r = vi_set_ip_blocks(adev);
2047 case CHIP_ALDEBARAN:
2048 if (adev->flags & AMD_IS_APU)
2049 adev->family = AMDGPU_FAMILY_RV;
2051 adev->family = AMDGPU_FAMILY_AI;
2053 r = soc15_set_ip_blocks(adev);
2060 case CHIP_SIENNA_CICHLID:
2061 case CHIP_NAVY_FLOUNDER:
2062 case CHIP_DIMGREY_CAVEFISH:
2063 case CHIP_BEIGE_GOBY:
2065 if (adev->asic_type == CHIP_VANGOGH)
2066 adev->family = AMDGPU_FAMILY_VGH;
2068 adev->family = AMDGPU_FAMILY_NV;
2070 r = nv_set_ip_blocks(adev);
2075 /* FIXME: not supported yet */
2079 amdgpu_amdkfd_device_probe(adev);
2081 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2082 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2083 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2084 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2085 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2087 for (i = 0; i < adev->num_ip_blocks; i++) {
2088 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2089 DRM_ERROR("disabled ip block: %d <%s>\n",
2090 i, adev->ip_blocks[i].version->funcs->name);
2091 adev->ip_blocks[i].status.valid = false;
2093 if (adev->ip_blocks[i].version->funcs->early_init) {
2094 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2096 adev->ip_blocks[i].status.valid = false;
2098 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2099 adev->ip_blocks[i].version->funcs->name, r);
2102 adev->ip_blocks[i].status.valid = true;
2105 adev->ip_blocks[i].status.valid = true;
2108 /* get the vbios after the asic_funcs are set up */
2109 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2110 r = amdgpu_device_parse_gpu_info_fw(adev);
2115 if (!amdgpu_get_bios(adev))
2118 r = amdgpu_atombios_init(adev);
2120 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2121 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2125 /*get pf2vf msg info at it's earliest time*/
2126 if (amdgpu_sriov_vf(adev))
2127 amdgpu_virt_init_data_exchange(adev);
2132 adev->cg_flags &= amdgpu_cg_mask;
2133 adev->pg_flags &= amdgpu_pg_mask;
2138 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2142 for (i = 0; i < adev->num_ip_blocks; i++) {
2143 if (!adev->ip_blocks[i].status.sw)
2145 if (adev->ip_blocks[i].status.hw)
2147 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2148 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2149 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2150 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2152 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2153 adev->ip_blocks[i].version->funcs->name, r);
2156 adev->ip_blocks[i].status.hw = true;
2163 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2167 for (i = 0; i < adev->num_ip_blocks; i++) {
2168 if (!adev->ip_blocks[i].status.sw)
2170 if (adev->ip_blocks[i].status.hw)
2172 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2174 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2175 adev->ip_blocks[i].version->funcs->name, r);
2178 adev->ip_blocks[i].status.hw = true;
2184 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2188 uint32_t smu_version;
2190 if (adev->asic_type >= CHIP_VEGA10) {
2191 for (i = 0; i < adev->num_ip_blocks; i++) {
2192 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2195 if (!adev->ip_blocks[i].status.sw)
2198 /* no need to do the fw loading again if already done*/
2199 if (adev->ip_blocks[i].status.hw == true)
2202 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2203 r = adev->ip_blocks[i].version->funcs->resume(adev);
2205 DRM_ERROR("resume of IP block <%s> failed %d\n",
2206 adev->ip_blocks[i].version->funcs->name, r);
2210 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2212 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2213 adev->ip_blocks[i].version->funcs->name, r);
2218 adev->ip_blocks[i].status.hw = true;
2223 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2224 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2230 * amdgpu_device_ip_init - run init for hardware IPs
2232 * @adev: amdgpu_device pointer
2234 * Main initialization pass for hardware IPs. The list of all the hardware
2235 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2236 * are run. sw_init initializes the software state associated with each IP
2237 * and hw_init initializes the hardware associated with each IP.
2238 * Returns 0 on success, negative error code on failure.
2240 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2244 r = amdgpu_ras_init(adev);
2248 for (i = 0; i < adev->num_ip_blocks; i++) {
2249 if (!adev->ip_blocks[i].status.valid)
2251 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2253 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2254 adev->ip_blocks[i].version->funcs->name, r);
2257 adev->ip_blocks[i].status.sw = true;
2259 /* need to do gmc hw init early so we can allocate gpu mem */
2260 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2261 r = amdgpu_device_vram_scratch_init(adev);
2263 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2266 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2268 DRM_ERROR("hw_init %d failed %d\n", i, r);
2271 r = amdgpu_device_wb_init(adev);
2273 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2276 adev->ip_blocks[i].status.hw = true;
2278 /* right after GMC hw init, we create CSA */
2279 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2280 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2281 AMDGPU_GEM_DOMAIN_VRAM,
2284 DRM_ERROR("allocate CSA failed %d\n", r);
2291 if (amdgpu_sriov_vf(adev))
2292 amdgpu_virt_init_data_exchange(adev);
2294 r = amdgpu_ib_pool_init(adev);
2296 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2297 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2301 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2305 r = amdgpu_device_ip_hw_init_phase1(adev);
2309 r = amdgpu_device_fw_loading(adev);
2313 r = amdgpu_device_ip_hw_init_phase2(adev);
2318 * retired pages will be loaded from eeprom and reserved here,
2319 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2320 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2321 * for I2C communication which only true at this point.
2323 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2324 * failure from bad gpu situation and stop amdgpu init process
2325 * accordingly. For other failed cases, it will still release all
2326 * the resource and print error message, rather than returning one
2327 * negative value to upper level.
2329 * Note: theoretically, this should be called before all vram allocations
2330 * to protect retired page from abusing
2332 r = amdgpu_ras_recovery_init(adev);
2336 if (adev->gmc.xgmi.num_physical_nodes > 1)
2337 amdgpu_xgmi_add_device(adev);
2339 /* Don't init kfd if whole hive need to be reset during init */
2340 if (!adev->gmc.xgmi.pending_reset)
2341 amdgpu_amdkfd_device_init(adev);
2343 amdgpu_fru_get_product_info(adev);
2346 if (amdgpu_sriov_vf(adev))
2347 amdgpu_virt_release_full_gpu(adev, true);
2353 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2355 * @adev: amdgpu_device pointer
2357 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2358 * this function before a GPU reset. If the value is retained after a
2359 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2361 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2363 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2367 * amdgpu_device_check_vram_lost - check if vram is valid
2369 * @adev: amdgpu_device pointer
2371 * Checks the reset magic value written to the gart pointer in VRAM.
2372 * The driver calls this after a GPU reset to see if the contents of
2373 * VRAM is lost or now.
2374 * returns true if vram is lost, false if not.
2376 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2378 if (memcmp(adev->gart.ptr, adev->reset_magic,
2379 AMDGPU_RESET_MAGIC_NUM))
2382 if (!amdgpu_in_reset(adev))
2386 * For all ASICs with baco/mode1 reset, the VRAM is
2387 * always assumed to be lost.
2389 switch (amdgpu_asic_reset_method(adev)) {
2390 case AMD_RESET_METHOD_BACO:
2391 case AMD_RESET_METHOD_MODE1:
2399 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2401 * @adev: amdgpu_device pointer
2402 * @state: clockgating state (gate or ungate)
2404 * The list of all the hardware IPs that make up the asic is walked and the
2405 * set_clockgating_state callbacks are run.
2406 * Late initialization pass enabling clockgating for hardware IPs.
2407 * Fini or suspend, pass disabling clockgating for hardware IPs.
2408 * Returns 0 on success, negative error code on failure.
2411 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2412 enum amd_clockgating_state state)
2416 if (amdgpu_emu_mode == 1)
2419 for (j = 0; j < adev->num_ip_blocks; j++) {
2420 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2421 if (!adev->ip_blocks[i].status.late_initialized)
2423 /* skip CG for GFX on S0ix */
2424 if (adev->in_s0ix &&
2425 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2427 /* skip CG for VCE/UVD, it's handled specially */
2428 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2429 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2430 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2431 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2432 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2433 /* enable clockgating to save power */
2434 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2437 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2438 adev->ip_blocks[i].version->funcs->name, r);
2447 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2448 enum amd_powergating_state state)
2452 if (amdgpu_emu_mode == 1)
2455 for (j = 0; j < adev->num_ip_blocks; j++) {
2456 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2457 if (!adev->ip_blocks[i].status.late_initialized)
2459 /* skip PG for GFX on S0ix */
2460 if (adev->in_s0ix &&
2461 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2463 /* skip CG for VCE/UVD, it's handled specially */
2464 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2465 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2466 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2467 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2468 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2469 /* enable powergating to save power */
2470 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2473 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2474 adev->ip_blocks[i].version->funcs->name, r);
2482 static int amdgpu_device_enable_mgpu_fan_boost(void)
2484 struct amdgpu_gpu_instance *gpu_ins;
2485 struct amdgpu_device *adev;
2488 mutex_lock(&mgpu_info.mutex);
2491 * MGPU fan boost feature should be enabled
2492 * only when there are two or more dGPUs in
2495 if (mgpu_info.num_dgpu < 2)
2498 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2499 gpu_ins = &(mgpu_info.gpu_ins[i]);
2500 adev = gpu_ins->adev;
2501 if (!(adev->flags & AMD_IS_APU) &&
2502 !gpu_ins->mgpu_fan_enabled) {
2503 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2507 gpu_ins->mgpu_fan_enabled = 1;
2512 mutex_unlock(&mgpu_info.mutex);
2518 * amdgpu_device_ip_late_init - run late init for hardware IPs
2520 * @adev: amdgpu_device pointer
2522 * Late initialization pass for hardware IPs. The list of all the hardware
2523 * IPs that make up the asic is walked and the late_init callbacks are run.
2524 * late_init covers any special initialization that an IP requires
2525 * after all of the have been initialized or something that needs to happen
2526 * late in the init process.
2527 * Returns 0 on success, negative error code on failure.
2529 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2531 struct amdgpu_gpu_instance *gpu_instance;
2534 for (i = 0; i < adev->num_ip_blocks; i++) {
2535 if (!adev->ip_blocks[i].status.hw)
2537 if (adev->ip_blocks[i].version->funcs->late_init) {
2538 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2540 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2541 adev->ip_blocks[i].version->funcs->name, r);
2545 adev->ip_blocks[i].status.late_initialized = true;
2548 amdgpu_ras_set_error_query_ready(adev, true);
2550 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2551 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2553 amdgpu_device_fill_reset_magic(adev);
2555 r = amdgpu_device_enable_mgpu_fan_boost();
2557 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2559 /* For XGMI + passthrough configuration on arcturus, enable light SBR */
2560 if (adev->asic_type == CHIP_ARCTURUS &&
2561 amdgpu_passthrough(adev) &&
2562 adev->gmc.xgmi.num_physical_nodes > 1)
2563 smu_set_light_sbr(&adev->smu, true);
2565 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2566 mutex_lock(&mgpu_info.mutex);
2569 * Reset device p-state to low as this was booted with high.
2571 * This should be performed only after all devices from the same
2572 * hive get initialized.
2574 * However, it's unknown how many device in the hive in advance.
2575 * As this is counted one by one during devices initializations.
2577 * So, we wait for all XGMI interlinked devices initialized.
2578 * This may bring some delays as those devices may come from
2579 * different hives. But that should be OK.
2581 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2582 for (i = 0; i < mgpu_info.num_gpu; i++) {
2583 gpu_instance = &(mgpu_info.gpu_ins[i]);
2584 if (gpu_instance->adev->flags & AMD_IS_APU)
2587 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2588 AMDGPU_XGMI_PSTATE_MIN);
2590 DRM_ERROR("pstate setting failed (%d).\n", r);
2596 mutex_unlock(&mgpu_info.mutex);
2602 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2606 for (i = 0; i < adev->num_ip_blocks; i++) {
2607 if (!adev->ip_blocks[i].version->funcs->early_fini)
2610 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2612 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2613 adev->ip_blocks[i].version->funcs->name, r);
2617 amdgpu_amdkfd_suspend(adev, false);
2619 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2620 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2622 /* need to disable SMC first */
2623 for (i = 0; i < adev->num_ip_blocks; i++) {
2624 if (!adev->ip_blocks[i].status.hw)
2626 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2627 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2628 /* XXX handle errors */
2630 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2631 adev->ip_blocks[i].version->funcs->name, r);
2633 adev->ip_blocks[i].status.hw = false;
2638 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2639 if (!adev->ip_blocks[i].status.hw)
2642 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2643 /* XXX handle errors */
2645 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2646 adev->ip_blocks[i].version->funcs->name, r);
2649 adev->ip_blocks[i].status.hw = false;
2656 * amdgpu_device_ip_fini - run fini for hardware IPs
2658 * @adev: amdgpu_device pointer
2660 * Main teardown pass for hardware IPs. The list of all the hardware
2661 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2662 * are run. hw_fini tears down the hardware associated with each IP
2663 * and sw_fini tears down any software state associated with each IP.
2664 * Returns 0 on success, negative error code on failure.
2666 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2670 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2671 amdgpu_virt_release_ras_err_handler_data(adev);
2673 amdgpu_ras_pre_fini(adev);
2675 if (adev->gmc.xgmi.num_physical_nodes > 1)
2676 amdgpu_xgmi_remove_device(adev);
2678 amdgpu_amdkfd_device_fini_sw(adev);
2680 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2681 if (!adev->ip_blocks[i].status.sw)
2684 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2685 amdgpu_ucode_free_bo(adev);
2686 amdgpu_free_static_csa(&adev->virt.csa_obj);
2687 amdgpu_device_wb_fini(adev);
2688 amdgpu_device_vram_scratch_fini(adev);
2689 amdgpu_ib_pool_fini(adev);
2692 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2693 /* XXX handle errors */
2695 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2696 adev->ip_blocks[i].version->funcs->name, r);
2698 adev->ip_blocks[i].status.sw = false;
2699 adev->ip_blocks[i].status.valid = false;
2702 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2703 if (!adev->ip_blocks[i].status.late_initialized)
2705 if (adev->ip_blocks[i].version->funcs->late_fini)
2706 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2707 adev->ip_blocks[i].status.late_initialized = false;
2710 amdgpu_ras_fini(adev);
2712 if (amdgpu_sriov_vf(adev))
2713 if (amdgpu_virt_release_full_gpu(adev, false))
2714 DRM_ERROR("failed to release exclusive mode on fini\n");
2720 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2722 * @work: work_struct.
2724 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2726 struct amdgpu_device *adev =
2727 container_of(work, struct amdgpu_device, delayed_init_work.work);
2730 r = amdgpu_ib_ring_tests(adev);
2732 DRM_ERROR("ib ring test failed (%d).\n", r);
2735 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2737 struct amdgpu_device *adev =
2738 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2740 mutex_lock(&adev->gfx.gfx_off_mutex);
2741 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2742 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2743 adev->gfx.gfx_off_state = true;
2745 mutex_unlock(&adev->gfx.gfx_off_mutex);
2749 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2751 * @adev: amdgpu_device pointer
2753 * Main suspend function for hardware IPs. The list of all the hardware
2754 * IPs that make up the asic is walked, clockgating is disabled and the
2755 * suspend callbacks are run. suspend puts the hardware and software state
2756 * in each IP into a state suitable for suspend.
2757 * Returns 0 on success, negative error code on failure.
2759 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2763 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2764 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2766 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2767 if (!adev->ip_blocks[i].status.valid)
2770 /* displays are handled separately */
2771 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2774 /* XXX handle errors */
2775 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2776 /* XXX handle errors */
2778 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2779 adev->ip_blocks[i].version->funcs->name, r);
2783 adev->ip_blocks[i].status.hw = false;
2790 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2792 * @adev: amdgpu_device pointer
2794 * Main suspend function for hardware IPs. The list of all the hardware
2795 * IPs that make up the asic is walked, clockgating is disabled and the
2796 * suspend callbacks are run. suspend puts the hardware and software state
2797 * in each IP into a state suitable for suspend.
2798 * Returns 0 on success, negative error code on failure.
2800 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2805 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
2807 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2808 if (!adev->ip_blocks[i].status.valid)
2810 /* displays are handled in phase1 */
2811 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2813 /* PSP lost connection when err_event_athub occurs */
2814 if (amdgpu_ras_intr_triggered() &&
2815 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2816 adev->ip_blocks[i].status.hw = false;
2820 /* skip unnecessary suspend if we do not initialize them yet */
2821 if (adev->gmc.xgmi.pending_reset &&
2822 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2823 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
2824 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2825 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
2826 adev->ip_blocks[i].status.hw = false;
2830 /* skip suspend of gfx and psp for S0ix
2831 * gfx is in gfxoff state, so on resume it will exit gfxoff just
2832 * like at runtime. PSP is also part of the always on hardware
2833 * so no need to suspend it.
2835 if (adev->in_s0ix &&
2836 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
2837 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX))
2840 /* XXX handle errors */
2841 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2842 /* XXX handle errors */
2844 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2845 adev->ip_blocks[i].version->funcs->name, r);
2847 adev->ip_blocks[i].status.hw = false;
2848 /* handle putting the SMC in the appropriate state */
2849 if(!amdgpu_sriov_vf(adev)){
2850 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2851 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2853 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2854 adev->mp1_state, r);
2865 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2867 * @adev: amdgpu_device pointer
2869 * Main suspend function for hardware IPs. The list of all the hardware
2870 * IPs that make up the asic is walked, clockgating is disabled and the
2871 * suspend callbacks are run. suspend puts the hardware and software state
2872 * in each IP into a state suitable for suspend.
2873 * Returns 0 on success, negative error code on failure.
2875 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2879 if (amdgpu_sriov_vf(adev)) {
2880 amdgpu_virt_fini_data_exchange(adev);
2881 amdgpu_virt_request_full_gpu(adev, false);
2884 r = amdgpu_device_ip_suspend_phase1(adev);
2887 r = amdgpu_device_ip_suspend_phase2(adev);
2889 if (amdgpu_sriov_vf(adev))
2890 amdgpu_virt_release_full_gpu(adev, false);
2895 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2899 static enum amd_ip_block_type ip_order[] = {
2900 AMD_IP_BLOCK_TYPE_GMC,
2901 AMD_IP_BLOCK_TYPE_COMMON,
2902 AMD_IP_BLOCK_TYPE_PSP,
2903 AMD_IP_BLOCK_TYPE_IH,
2906 for (i = 0; i < adev->num_ip_blocks; i++) {
2908 struct amdgpu_ip_block *block;
2910 block = &adev->ip_blocks[i];
2911 block->status.hw = false;
2913 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2915 if (block->version->type != ip_order[j] ||
2916 !block->status.valid)
2919 r = block->version->funcs->hw_init(adev);
2920 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2923 block->status.hw = true;
2930 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2934 static enum amd_ip_block_type ip_order[] = {
2935 AMD_IP_BLOCK_TYPE_SMC,
2936 AMD_IP_BLOCK_TYPE_DCE,
2937 AMD_IP_BLOCK_TYPE_GFX,
2938 AMD_IP_BLOCK_TYPE_SDMA,
2939 AMD_IP_BLOCK_TYPE_UVD,
2940 AMD_IP_BLOCK_TYPE_VCE,
2941 AMD_IP_BLOCK_TYPE_VCN
2944 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2946 struct amdgpu_ip_block *block;
2948 for (j = 0; j < adev->num_ip_blocks; j++) {
2949 block = &adev->ip_blocks[j];
2951 if (block->version->type != ip_order[i] ||
2952 !block->status.valid ||
2956 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2957 r = block->version->funcs->resume(adev);
2959 r = block->version->funcs->hw_init(adev);
2961 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2964 block->status.hw = true;
2972 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2974 * @adev: amdgpu_device pointer
2976 * First resume function for hardware IPs. The list of all the hardware
2977 * IPs that make up the asic is walked and the resume callbacks are run for
2978 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2979 * after a suspend and updates the software state as necessary. This
2980 * function is also used for restoring the GPU after a GPU reset.
2981 * Returns 0 on success, negative error code on failure.
2983 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2987 for (i = 0; i < adev->num_ip_blocks; i++) {
2988 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2990 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2991 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2992 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2994 r = adev->ip_blocks[i].version->funcs->resume(adev);
2996 DRM_ERROR("resume of IP block <%s> failed %d\n",
2997 adev->ip_blocks[i].version->funcs->name, r);
3000 adev->ip_blocks[i].status.hw = true;
3008 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3010 * @adev: amdgpu_device pointer
3012 * First resume function for hardware IPs. The list of all the hardware
3013 * IPs that make up the asic is walked and the resume callbacks are run for
3014 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3015 * functional state after a suspend and updates the software state as
3016 * necessary. This function is also used for restoring the GPU after a GPU
3018 * Returns 0 on success, negative error code on failure.
3020 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3024 for (i = 0; i < adev->num_ip_blocks; i++) {
3025 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3027 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3028 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3029 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3030 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3032 r = adev->ip_blocks[i].version->funcs->resume(adev);
3034 DRM_ERROR("resume of IP block <%s> failed %d\n",
3035 adev->ip_blocks[i].version->funcs->name, r);
3038 adev->ip_blocks[i].status.hw = true;
3045 * amdgpu_device_ip_resume - run resume for hardware IPs
3047 * @adev: amdgpu_device pointer
3049 * Main resume function for hardware IPs. The hardware IPs
3050 * are split into two resume functions because they are
3051 * are also used in in recovering from a GPU reset and some additional
3052 * steps need to be take between them. In this case (S3/S4) they are
3054 * Returns 0 on success, negative error code on failure.
3056 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3060 r = amdgpu_device_ip_resume_phase1(adev);
3064 r = amdgpu_device_fw_loading(adev);
3068 r = amdgpu_device_ip_resume_phase2(adev);
3074 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3076 * @adev: amdgpu_device pointer
3078 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3080 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3082 if (amdgpu_sriov_vf(adev)) {
3083 if (adev->is_atom_fw) {
3084 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3085 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3087 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3088 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3091 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3092 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3097 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3099 * @asic_type: AMD asic type
3101 * Check if there is DC (new modesetting infrastructre) support for an asic.
3102 * returns true if DC has support, false if not.
3104 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3106 switch (asic_type) {
3107 #if defined(CONFIG_DRM_AMD_DC)
3108 #if defined(CONFIG_DRM_AMD_DC_SI)
3119 * We have systems in the wild with these ASICs that require
3120 * LVDS and VGA support which is not supported with DC.
3122 * Fallback to the non-DC driver here by default so as not to
3123 * cause regressions.
3125 return amdgpu_dc > 0;
3129 case CHIP_POLARIS10:
3130 case CHIP_POLARIS11:
3131 case CHIP_POLARIS12:
3138 #if defined(CONFIG_DRM_AMD_DC_DCN)
3144 case CHIP_SIENNA_CICHLID:
3145 case CHIP_NAVY_FLOUNDER:
3146 case CHIP_DIMGREY_CAVEFISH:
3147 case CHIP_BEIGE_GOBY:
3150 return amdgpu_dc != 0;
3154 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3155 "but isn't supported by ASIC, ignoring\n");
3161 * amdgpu_device_has_dc_support - check if dc is supported
3163 * @adev: amdgpu_device pointer
3165 * Returns true for supported, false for not supported
3167 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3169 if (amdgpu_sriov_vf(adev) ||
3170 adev->enable_virtual_display ||
3171 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3174 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3177 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3179 struct amdgpu_device *adev =
3180 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3181 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3183 /* It's a bug to not have a hive within this function */
3188 * Use task barrier to synchronize all xgmi reset works across the
3189 * hive. task_barrier_enter and task_barrier_exit will block
3190 * until all the threads running the xgmi reset works reach
3191 * those points. task_barrier_full will do both blocks.
3193 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3195 task_barrier_enter(&hive->tb);
3196 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3198 if (adev->asic_reset_res)
3201 task_barrier_exit(&hive->tb);
3202 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3204 if (adev->asic_reset_res)
3207 if (adev->mmhub.ras_funcs &&
3208 adev->mmhub.ras_funcs->reset_ras_error_count)
3209 adev->mmhub.ras_funcs->reset_ras_error_count(adev);
3212 task_barrier_full(&hive->tb);
3213 adev->asic_reset_res = amdgpu_asic_reset(adev);
3217 if (adev->asic_reset_res)
3218 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3219 adev->asic_reset_res, adev_to_drm(adev)->unique);
3220 amdgpu_put_xgmi_hive(hive);
3223 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3225 char *input = amdgpu_lockup_timeout;
3226 char *timeout_setting = NULL;
3232 * By default timeout for non compute jobs is 10000
3233 * and 60000 for compute jobs.
3234 * In SR-IOV or passthrough mode, timeout for compute
3235 * jobs are 60000 by default.
3237 adev->gfx_timeout = msecs_to_jiffies(10000);
3238 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3239 if (amdgpu_sriov_vf(adev))
3240 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3241 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3243 adev->compute_timeout = msecs_to_jiffies(60000);
3245 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3246 while ((timeout_setting = strsep(&input, ",")) &&
3247 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3248 ret = kstrtol(timeout_setting, 0, &timeout);
3255 } else if (timeout < 0) {
3256 timeout = MAX_SCHEDULE_TIMEOUT;
3258 timeout = msecs_to_jiffies(timeout);
3263 adev->gfx_timeout = timeout;
3266 adev->compute_timeout = timeout;
3269 adev->sdma_timeout = timeout;
3272 adev->video_timeout = timeout;
3279 * There is only one value specified and
3280 * it should apply to all non-compute jobs.
3283 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3284 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3285 adev->compute_timeout = adev->gfx_timeout;
3292 static const struct attribute *amdgpu_dev_attributes[] = {
3293 &dev_attr_product_name.attr,
3294 &dev_attr_product_number.attr,
3295 &dev_attr_serial_number.attr,
3296 &dev_attr_pcie_replay_count.attr,
3301 * amdgpu_device_init - initialize the driver
3303 * @adev: amdgpu_device pointer
3304 * @flags: driver flags
3306 * Initializes the driver info and hw (all asics).
3307 * Returns 0 for success or an error on failure.
3308 * Called at driver startup.
3310 int amdgpu_device_init(struct amdgpu_device *adev,
3313 struct drm_device *ddev = adev_to_drm(adev);
3314 struct pci_dev *pdev = adev->pdev;
3319 adev->shutdown = false;
3320 adev->flags = flags;
3322 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3323 adev->asic_type = amdgpu_force_asic_type;
3325 adev->asic_type = flags & AMD_ASIC_MASK;
3327 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3328 if (amdgpu_emu_mode == 1)
3329 adev->usec_timeout *= 10;
3330 adev->gmc.gart_size = 512 * 1024 * 1024;
3331 adev->accel_working = false;
3332 adev->num_rings = 0;
3333 adev->mman.buffer_funcs = NULL;
3334 adev->mman.buffer_funcs_ring = NULL;
3335 adev->vm_manager.vm_pte_funcs = NULL;
3336 adev->vm_manager.vm_pte_num_scheds = 0;
3337 adev->gmc.gmc_funcs = NULL;
3338 adev->harvest_ip_mask = 0x0;
3339 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3340 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3342 adev->smc_rreg = &amdgpu_invalid_rreg;
3343 adev->smc_wreg = &amdgpu_invalid_wreg;
3344 adev->pcie_rreg = &amdgpu_invalid_rreg;
3345 adev->pcie_wreg = &amdgpu_invalid_wreg;
3346 adev->pciep_rreg = &amdgpu_invalid_rreg;
3347 adev->pciep_wreg = &amdgpu_invalid_wreg;
3348 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3349 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3350 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3351 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3352 adev->didt_rreg = &amdgpu_invalid_rreg;
3353 adev->didt_wreg = &amdgpu_invalid_wreg;
3354 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3355 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3356 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3357 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3359 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3360 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3361 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3363 /* mutex initialization are all done here so we
3364 * can recall function without having locking issues */
3365 mutex_init(&adev->firmware.mutex);
3366 mutex_init(&adev->pm.mutex);
3367 mutex_init(&adev->gfx.gpu_clock_mutex);
3368 mutex_init(&adev->srbm_mutex);
3369 mutex_init(&adev->gfx.pipe_reserve_mutex);
3370 mutex_init(&adev->gfx.gfx_off_mutex);
3371 mutex_init(&adev->grbm_idx_mutex);
3372 mutex_init(&adev->mn_lock);
3373 mutex_init(&adev->virt.vf_errors.lock);
3374 hash_init(adev->mn_hash);
3375 atomic_set(&adev->in_gpu_reset, 0);
3376 init_rwsem(&adev->reset_sem);
3377 mutex_init(&adev->psp.mutex);
3378 mutex_init(&adev->notifier_lock);
3380 r = amdgpu_device_check_arguments(adev);
3384 spin_lock_init(&adev->mmio_idx_lock);
3385 spin_lock_init(&adev->smc_idx_lock);
3386 spin_lock_init(&adev->pcie_idx_lock);
3387 spin_lock_init(&adev->uvd_ctx_idx_lock);
3388 spin_lock_init(&adev->didt_idx_lock);
3389 spin_lock_init(&adev->gc_cac_idx_lock);
3390 spin_lock_init(&adev->se_cac_idx_lock);
3391 spin_lock_init(&adev->audio_endpt_idx_lock);
3392 spin_lock_init(&adev->mm_stats.lock);
3394 INIT_LIST_HEAD(&adev->shadow_list);
3395 mutex_init(&adev->shadow_list_lock);
3397 INIT_LIST_HEAD(&adev->reset_list);
3399 INIT_DELAYED_WORK(&adev->delayed_init_work,
3400 amdgpu_device_delayed_init_work_handler);
3401 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3402 amdgpu_device_delay_enable_gfx_off);
3404 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3406 adev->gfx.gfx_off_req_count = 1;
3407 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3409 atomic_set(&adev->throttling_logging_enabled, 1);
3411 * If throttling continues, logging will be performed every minute
3412 * to avoid log flooding. "-1" is subtracted since the thermal
3413 * throttling interrupt comes every second. Thus, the total logging
3414 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3415 * for throttling interrupt) = 60 seconds.
3417 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3418 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3420 /* Registers mapping */
3421 /* TODO: block userspace mapping of io register */
3422 if (adev->asic_type >= CHIP_BONAIRE) {
3423 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3424 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3426 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3427 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3430 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3431 if (adev->rmmio == NULL) {
3434 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3435 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3437 /* enable PCIE atomic ops */
3438 r = pci_enable_atomic_ops_to_root(adev->pdev,
3439 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3440 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3442 adev->have_atomics_support = false;
3443 DRM_INFO("PCIE atomic ops is not supported\n");
3445 adev->have_atomics_support = true;
3448 amdgpu_device_get_pcie_info(adev);
3451 DRM_INFO("MCBP is enabled\n");
3453 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3454 adev->enable_mes = true;
3456 /* detect hw virtualization here */
3457 amdgpu_detect_virtualization(adev);
3459 r = amdgpu_device_get_job_timeout_settings(adev);
3461 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3465 /* early init functions */
3466 r = amdgpu_device_ip_early_init(adev);
3470 /* doorbell bar mapping and doorbell index init*/
3471 amdgpu_device_doorbell_init(adev);
3473 if (amdgpu_emu_mode == 1) {
3474 /* post the asic on emulation mode */
3475 emu_soc_asic_init(adev);
3476 goto fence_driver_init;
3479 amdgpu_reset_init(adev);
3481 /* detect if we are with an SRIOV vbios */
3482 amdgpu_device_detect_sriov_bios(adev);
3484 /* check if we need to reset the asic
3485 * E.g., driver was not cleanly unloaded previously, etc.
3487 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3488 if (adev->gmc.xgmi.num_physical_nodes) {
3489 dev_info(adev->dev, "Pending hive reset.\n");
3490 adev->gmc.xgmi.pending_reset = true;
3491 /* Only need to init necessary block for SMU to handle the reset */
3492 for (i = 0; i < adev->num_ip_blocks; i++) {
3493 if (!adev->ip_blocks[i].status.valid)
3495 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3496 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3497 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3498 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3499 DRM_DEBUG("IP %s disabled for hw_init.\n",
3500 adev->ip_blocks[i].version->funcs->name);
3501 adev->ip_blocks[i].status.hw = true;
3505 r = amdgpu_asic_reset(adev);
3507 dev_err(adev->dev, "asic reset on init failed\n");
3513 pci_enable_pcie_error_reporting(adev->pdev);
3515 /* Post card if necessary */
3516 if (amdgpu_device_need_post(adev)) {
3518 dev_err(adev->dev, "no vBIOS found\n");
3522 DRM_INFO("GPU posting now...\n");
3523 r = amdgpu_device_asic_init(adev);
3525 dev_err(adev->dev, "gpu post error!\n");
3530 if (adev->is_atom_fw) {
3531 /* Initialize clocks */
3532 r = amdgpu_atomfirmware_get_clock_info(adev);
3534 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3535 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3539 /* Initialize clocks */
3540 r = amdgpu_atombios_get_clock_info(adev);
3542 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3543 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3546 /* init i2c buses */
3547 if (!amdgpu_device_has_dc_support(adev))
3548 amdgpu_atombios_i2c_init(adev);
3553 r = amdgpu_fence_driver_init(adev);
3555 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3556 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3560 /* init the mode config */
3561 drm_mode_config_init(adev_to_drm(adev));
3563 r = amdgpu_device_ip_init(adev);
3565 /* failed in exclusive mode due to timeout */
3566 if (amdgpu_sriov_vf(adev) &&
3567 !amdgpu_sriov_runtime(adev) &&
3568 amdgpu_virt_mmio_blocked(adev) &&
3569 !amdgpu_virt_wait_reset(adev)) {
3570 dev_err(adev->dev, "VF exclusive mode timeout\n");
3571 /* Don't send request since VF is inactive. */
3572 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3573 adev->virt.ops = NULL;
3575 goto release_ras_con;
3577 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3578 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3579 goto release_ras_con;
3583 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3584 adev->gfx.config.max_shader_engines,
3585 adev->gfx.config.max_sh_per_se,
3586 adev->gfx.config.max_cu_per_sh,
3587 adev->gfx.cu_info.number);
3589 adev->accel_working = true;
3591 amdgpu_vm_check_compute_bug(adev);
3593 /* Initialize the buffer migration limit. */
3594 if (amdgpu_moverate >= 0)
3595 max_MBps = amdgpu_moverate;
3597 max_MBps = 8; /* Allow 8 MB/s. */
3598 /* Get a log2 for easy divisions. */
3599 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3601 amdgpu_fbdev_init(adev);
3603 r = amdgpu_pm_sysfs_init(adev);
3605 adev->pm_sysfs_en = false;
3606 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3608 adev->pm_sysfs_en = true;
3610 r = amdgpu_ucode_sysfs_init(adev);
3612 adev->ucode_sysfs_en = false;
3613 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3615 adev->ucode_sysfs_en = true;
3617 if ((amdgpu_testing & 1)) {
3618 if (adev->accel_working)
3619 amdgpu_test_moves(adev);
3621 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3623 if (amdgpu_benchmarking) {
3624 if (adev->accel_working)
3625 amdgpu_benchmark(adev, amdgpu_benchmarking);
3627 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3631 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3632 * Otherwise the mgpu fan boost feature will be skipped due to the
3633 * gpu instance is counted less.
3635 amdgpu_register_gpu_instance(adev);
3637 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3638 * explicit gating rather than handling it automatically.
3640 if (!adev->gmc.xgmi.pending_reset) {
3641 r = amdgpu_device_ip_late_init(adev);
3643 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3644 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3645 goto release_ras_con;
3648 amdgpu_ras_resume(adev);
3649 queue_delayed_work(system_wq, &adev->delayed_init_work,
3650 msecs_to_jiffies(AMDGPU_RESUME_MS));
3653 if (amdgpu_sriov_vf(adev))
3654 flush_delayed_work(&adev->delayed_init_work);
3656 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3658 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3660 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3661 r = amdgpu_pmu_init(adev);
3663 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3665 /* Have stored pci confspace at hand for restore in sudden PCI error */
3666 if (amdgpu_device_cache_pci_state(adev->pdev))
3667 pci_restore_state(pdev);
3669 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3670 /* this will fail for cards that aren't VGA class devices, just
3672 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3673 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3675 if (amdgpu_device_supports_px(ddev)) {
3677 vga_switcheroo_register_client(adev->pdev,
3678 &amdgpu_switcheroo_ops, px);
3679 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3682 if (adev->gmc.xgmi.pending_reset)
3683 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3684 msecs_to_jiffies(AMDGPU_RESUME_MS));
3689 amdgpu_release_ras_context(adev);
3692 amdgpu_vf_error_trans_all(adev);
3695 iounmap(adev->rmmio);
3701 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
3703 /* Clear all CPU mappings pointing to this device */
3704 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
3706 /* Unmap all mapped bars - Doorbell, registers and VRAM */
3707 amdgpu_device_doorbell_fini(adev);
3709 iounmap(adev->rmmio);
3711 if (adev->mman.aper_base_kaddr)
3712 iounmap(adev->mman.aper_base_kaddr);
3713 adev->mman.aper_base_kaddr = NULL;
3715 /* Memory manager related */
3716 if (!adev->gmc.xgmi.connected_to_cpu) {
3717 arch_phys_wc_del(adev->gmc.vram_mtrr);
3718 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
3723 * amdgpu_device_fini - tear down the driver
3725 * @adev: amdgpu_device pointer
3727 * Tear down the driver info (all asics).
3728 * Called at driver shutdown.
3730 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
3732 dev_info(adev->dev, "amdgpu: finishing device.\n");
3733 flush_delayed_work(&adev->delayed_init_work);
3734 ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3735 adev->shutdown = true;
3737 /* make sure IB test finished before entering exclusive mode
3738 * to avoid preemption on IB test
3740 if (amdgpu_sriov_vf(adev)) {
3741 amdgpu_virt_request_full_gpu(adev, false);
3742 amdgpu_virt_fini_data_exchange(adev);
3745 /* disable all interrupts */
3746 amdgpu_irq_disable_all(adev);
3747 if (adev->mode_info.mode_config_initialized){
3748 if (!amdgpu_device_has_dc_support(adev))
3749 drm_helper_force_disable_all(adev_to_drm(adev));
3751 drm_atomic_helper_shutdown(adev_to_drm(adev));
3753 amdgpu_fence_driver_fini_hw(adev);
3755 if (adev->pm_sysfs_en)
3756 amdgpu_pm_sysfs_fini(adev);
3757 if (adev->ucode_sysfs_en)
3758 amdgpu_ucode_sysfs_fini(adev);
3759 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3761 amdgpu_fbdev_fini(adev);
3763 amdgpu_irq_fini_hw(adev);
3765 amdgpu_device_ip_fini_early(adev);
3767 amdgpu_gart_dummy_page_fini(adev);
3769 amdgpu_device_unmap_mmio(adev);
3772 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
3774 amdgpu_device_ip_fini(adev);
3775 amdgpu_fence_driver_fini_sw(adev);
3776 release_firmware(adev->firmware.gpu_info_fw);
3777 adev->firmware.gpu_info_fw = NULL;
3778 adev->accel_working = false;
3780 amdgpu_reset_fini(adev);
3782 /* free i2c buses */
3783 if (!amdgpu_device_has_dc_support(adev))
3784 amdgpu_i2c_fini(adev);
3786 if (amdgpu_emu_mode != 1)
3787 amdgpu_atombios_fini(adev);
3791 if (amdgpu_device_supports_px(adev_to_drm(adev))) {
3792 vga_switcheroo_unregister_client(adev->pdev);
3793 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3795 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3796 vga_client_register(adev->pdev, NULL, NULL, NULL);
3798 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3799 amdgpu_pmu_fini(adev);
3800 if (adev->mman.discovery_bin)
3801 amdgpu_discovery_fini(adev);
3803 kfree(adev->pci_state);
3812 * amdgpu_device_suspend - initiate device suspend
3814 * @dev: drm dev pointer
3815 * @fbcon : notify the fbdev of suspend
3817 * Puts the hw in the suspend state (all asics).
3818 * Returns 0 for success or an error on failure.
3819 * Called at driver suspend.
3821 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3823 struct amdgpu_device *adev = drm_to_adev(dev);
3825 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3828 adev->in_suspend = true;
3830 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
3831 DRM_WARN("smart shift update failed\n");
3833 drm_kms_helper_poll_disable(dev);
3836 amdgpu_fbdev_set_suspend(adev, 1);
3838 cancel_delayed_work_sync(&adev->delayed_init_work);
3840 amdgpu_ras_suspend(adev);
3842 amdgpu_device_ip_suspend_phase1(adev);
3845 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
3847 /* evict vram memory */
3848 amdgpu_bo_evict_vram(adev);
3850 amdgpu_fence_driver_suspend(adev);
3852 amdgpu_device_ip_suspend_phase2(adev);
3853 /* evict remaining vram memory
3854 * This second call to evict vram is to evict the gart page table
3857 amdgpu_bo_evict_vram(adev);
3863 * amdgpu_device_resume - initiate device resume
3865 * @dev: drm dev pointer
3866 * @fbcon : notify the fbdev of resume
3868 * Bring the hw back to operating state (all asics).
3869 * Returns 0 for success or an error on failure.
3870 * Called at driver resume.
3872 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3874 struct amdgpu_device *adev = drm_to_adev(dev);
3877 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3881 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3884 if (amdgpu_device_need_post(adev)) {
3885 r = amdgpu_device_asic_init(adev);
3887 dev_err(adev->dev, "amdgpu asic init failed\n");
3890 r = amdgpu_device_ip_resume(adev);
3892 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3895 amdgpu_fence_driver_resume(adev);
3898 r = amdgpu_device_ip_late_init(adev);
3902 queue_delayed_work(system_wq, &adev->delayed_init_work,
3903 msecs_to_jiffies(AMDGPU_RESUME_MS));
3905 if (!adev->in_s0ix) {
3906 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
3911 /* Make sure IB tests flushed */
3912 flush_delayed_work(&adev->delayed_init_work);
3915 amdgpu_fbdev_set_suspend(adev, 0);
3917 drm_kms_helper_poll_enable(dev);
3919 amdgpu_ras_resume(adev);
3922 * Most of the connector probing functions try to acquire runtime pm
3923 * refs to ensure that the GPU is powered on when connector polling is
3924 * performed. Since we're calling this from a runtime PM callback,
3925 * trying to acquire rpm refs will cause us to deadlock.
3927 * Since we're guaranteed to be holding the rpm lock, it's safe to
3928 * temporarily disable the rpm helpers so this doesn't deadlock us.
3931 dev->dev->power.disable_depth++;
3933 if (!amdgpu_device_has_dc_support(adev))
3934 drm_helper_hpd_irq_event(dev);
3936 drm_kms_helper_hotplug_event(dev);
3938 dev->dev->power.disable_depth--;
3940 adev->in_suspend = false;
3942 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
3943 DRM_WARN("smart shift update failed\n");
3949 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3951 * @adev: amdgpu_device pointer
3953 * The list of all the hardware IPs that make up the asic is walked and
3954 * the check_soft_reset callbacks are run. check_soft_reset determines
3955 * if the asic is still hung or not.
3956 * Returns true if any of the IPs are still in a hung state, false if not.
3958 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3961 bool asic_hang = false;
3963 if (amdgpu_sriov_vf(adev))
3966 if (amdgpu_asic_need_full_reset(adev))
3969 for (i = 0; i < adev->num_ip_blocks; i++) {
3970 if (!adev->ip_blocks[i].status.valid)
3972 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3973 adev->ip_blocks[i].status.hang =
3974 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3975 if (adev->ip_blocks[i].status.hang) {
3976 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3984 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3986 * @adev: amdgpu_device pointer
3988 * The list of all the hardware IPs that make up the asic is walked and the
3989 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3990 * handles any IP specific hardware or software state changes that are
3991 * necessary for a soft reset to succeed.
3992 * Returns 0 on success, negative error code on failure.
3994 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3998 for (i = 0; i < adev->num_ip_blocks; i++) {
3999 if (!adev->ip_blocks[i].status.valid)
4001 if (adev->ip_blocks[i].status.hang &&
4002 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4003 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4013 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4015 * @adev: amdgpu_device pointer
4017 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4018 * reset is necessary to recover.
4019 * Returns true if a full asic reset is required, false if not.
4021 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4025 if (amdgpu_asic_need_full_reset(adev))
4028 for (i = 0; i < adev->num_ip_blocks; i++) {
4029 if (!adev->ip_blocks[i].status.valid)
4031 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4032 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4033 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4034 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4035 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4036 if (adev->ip_blocks[i].status.hang) {
4037 dev_info(adev->dev, "Some block need full reset!\n");
4046 * amdgpu_device_ip_soft_reset - do a soft reset
4048 * @adev: amdgpu_device pointer
4050 * The list of all the hardware IPs that make up the asic is walked and the
4051 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4052 * IP specific hardware or software state changes that are necessary to soft
4054 * Returns 0 on success, negative error code on failure.
4056 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4060 for (i = 0; i < adev->num_ip_blocks; i++) {
4061 if (!adev->ip_blocks[i].status.valid)
4063 if (adev->ip_blocks[i].status.hang &&
4064 adev->ip_blocks[i].version->funcs->soft_reset) {
4065 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4075 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4077 * @adev: amdgpu_device pointer
4079 * The list of all the hardware IPs that make up the asic is walked and the
4080 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4081 * handles any IP specific hardware or software state changes that are
4082 * necessary after the IP has been soft reset.
4083 * Returns 0 on success, negative error code on failure.
4085 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4089 for (i = 0; i < adev->num_ip_blocks; i++) {
4090 if (!adev->ip_blocks[i].status.valid)
4092 if (adev->ip_blocks[i].status.hang &&
4093 adev->ip_blocks[i].version->funcs->post_soft_reset)
4094 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4103 * amdgpu_device_recover_vram - Recover some VRAM contents
4105 * @adev: amdgpu_device pointer
4107 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4108 * restore things like GPUVM page tables after a GPU reset where
4109 * the contents of VRAM might be lost.
4112 * 0 on success, negative error code on failure.
4114 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4116 struct dma_fence *fence = NULL, *next = NULL;
4117 struct amdgpu_bo *shadow;
4120 if (amdgpu_sriov_runtime(adev))
4121 tmo = msecs_to_jiffies(8000);
4123 tmo = msecs_to_jiffies(100);
4125 dev_info(adev->dev, "recover vram bo from shadow start\n");
4126 mutex_lock(&adev->shadow_list_lock);
4127 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4129 /* No need to recover an evicted BO */
4130 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4131 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4132 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4135 r = amdgpu_bo_restore_shadow(shadow, &next);
4140 tmo = dma_fence_wait_timeout(fence, false, tmo);
4141 dma_fence_put(fence);
4146 } else if (tmo < 0) {
4154 mutex_unlock(&adev->shadow_list_lock);
4157 tmo = dma_fence_wait_timeout(fence, false, tmo);
4158 dma_fence_put(fence);
4160 if (r < 0 || tmo <= 0) {
4161 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4165 dev_info(adev->dev, "recover vram bo from shadow done\n");
4171 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4173 * @adev: amdgpu_device pointer
4174 * @from_hypervisor: request from hypervisor
4176 * do VF FLR and reinitialize Asic
4177 * return 0 means succeeded otherwise failed
4179 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4180 bool from_hypervisor)
4184 if (from_hypervisor)
4185 r = amdgpu_virt_request_full_gpu(adev, true);
4187 r = amdgpu_virt_reset_gpu(adev);
4191 amdgpu_amdkfd_pre_reset(adev);
4193 /* Resume IP prior to SMC */
4194 r = amdgpu_device_ip_reinit_early_sriov(adev);
4198 amdgpu_virt_init_data_exchange(adev);
4199 /* we need recover gart prior to run SMC/CP/SDMA resume */
4200 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4202 r = amdgpu_device_fw_loading(adev);
4206 /* now we are okay to resume SMC/CP/SDMA */
4207 r = amdgpu_device_ip_reinit_late_sriov(adev);
4211 amdgpu_irq_gpu_reset_resume_helper(adev);
4212 r = amdgpu_ib_ring_tests(adev);
4213 amdgpu_amdkfd_post_reset(adev);
4216 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4217 amdgpu_inc_vram_lost(adev);
4218 r = amdgpu_device_recover_vram(adev);
4220 amdgpu_virt_release_full_gpu(adev, true);
4226 * amdgpu_device_has_job_running - check if there is any job in mirror list
4228 * @adev: amdgpu_device pointer
4230 * check if there is any job in mirror list
4232 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4235 struct drm_sched_job *job;
4237 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4238 struct amdgpu_ring *ring = adev->rings[i];
4240 if (!ring || !ring->sched.thread)
4243 spin_lock(&ring->sched.job_list_lock);
4244 job = list_first_entry_or_null(&ring->sched.pending_list,
4245 struct drm_sched_job, list);
4246 spin_unlock(&ring->sched.job_list_lock);
4254 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4256 * @adev: amdgpu_device pointer
4258 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4261 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4263 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4264 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4268 if (amdgpu_gpu_recovery == 0)
4271 if (amdgpu_sriov_vf(adev))
4274 if (amdgpu_gpu_recovery == -1) {
4275 switch (adev->asic_type) {
4281 case CHIP_POLARIS10:
4282 case CHIP_POLARIS11:
4283 case CHIP_POLARIS12:
4294 case CHIP_SIENNA_CICHLID:
4295 case CHIP_NAVY_FLOUNDER:
4296 case CHIP_DIMGREY_CAVEFISH:
4298 case CHIP_ALDEBARAN:
4308 dev_info(adev->dev, "GPU recovery disabled.\n");
4312 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4317 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4319 dev_info(adev->dev, "GPU mode1 reset\n");
4322 pci_clear_master(adev->pdev);
4324 amdgpu_device_cache_pci_state(adev->pdev);
4326 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4327 dev_info(adev->dev, "GPU smu mode1 reset\n");
4328 ret = amdgpu_dpm_mode1_reset(adev);
4330 dev_info(adev->dev, "GPU psp mode1 reset\n");
4331 ret = psp_gpu_reset(adev);
4335 dev_err(adev->dev, "GPU mode1 reset failed\n");
4337 amdgpu_device_load_pci_state(adev->pdev);
4339 /* wait for asic to come out of reset */
4340 for (i = 0; i < adev->usec_timeout; i++) {
4341 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4343 if (memsize != 0xffffffff)
4348 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4352 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4353 struct amdgpu_reset_context *reset_context)
4356 struct amdgpu_job *job = NULL;
4357 bool need_full_reset =
4358 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4360 if (reset_context->reset_req_dev == adev)
4361 job = reset_context->job;
4363 /* no need to dump if device is not in good state during probe period */
4364 if (!adev->gmc.xgmi.pending_reset)
4365 amdgpu_debugfs_wait_dump(adev);
4367 if (amdgpu_sriov_vf(adev)) {
4368 /* stop the data exchange thread */
4369 amdgpu_virt_fini_data_exchange(adev);
4372 /* block all schedulers and reset given job's ring */
4373 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4374 struct amdgpu_ring *ring = adev->rings[i];
4376 if (!ring || !ring->sched.thread)
4379 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4380 amdgpu_fence_driver_force_completion(ring);
4384 drm_sched_increase_karma(&job->base);
4386 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4387 /* If reset handler not implemented, continue; otherwise return */
4393 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4394 if (!amdgpu_sriov_vf(adev)) {
4396 if (!need_full_reset)
4397 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4399 if (!need_full_reset) {
4400 amdgpu_device_ip_pre_soft_reset(adev);
4401 r = amdgpu_device_ip_soft_reset(adev);
4402 amdgpu_device_ip_post_soft_reset(adev);
4403 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4404 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4405 need_full_reset = true;
4409 if (need_full_reset)
4410 r = amdgpu_device_ip_suspend(adev);
4411 if (need_full_reset)
4412 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4414 clear_bit(AMDGPU_NEED_FULL_RESET,
4415 &reset_context->flags);
4421 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4422 struct amdgpu_reset_context *reset_context)
4424 struct amdgpu_device *tmp_adev = NULL;
4425 bool need_full_reset, skip_hw_reset, vram_lost = false;
4428 /* Try reset handler method first */
4429 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4431 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4432 /* If reset handler not implemented, continue; otherwise return */
4438 /* Reset handler not implemented, use the default method */
4440 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4441 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4444 * ASIC reset has to be done on all XGMI hive nodes ASAP
4445 * to allow proper links negotiation in FW (within 1 sec)
4447 if (!skip_hw_reset && need_full_reset) {
4448 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4449 /* For XGMI run all resets in parallel to speed up the process */
4450 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4451 tmp_adev->gmc.xgmi.pending_reset = false;
4452 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4455 r = amdgpu_asic_reset(tmp_adev);
4458 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4459 r, adev_to_drm(tmp_adev)->unique);
4464 /* For XGMI wait for all resets to complete before proceed */
4466 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4467 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4468 flush_work(&tmp_adev->xgmi_reset_work);
4469 r = tmp_adev->asic_reset_res;
4477 if (!r && amdgpu_ras_intr_triggered()) {
4478 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4479 if (tmp_adev->mmhub.ras_funcs &&
4480 tmp_adev->mmhub.ras_funcs->reset_ras_error_count)
4481 tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev);
4484 amdgpu_ras_intr_cleared();
4487 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4488 if (need_full_reset) {
4490 r = amdgpu_device_asic_init(tmp_adev);
4492 dev_warn(tmp_adev->dev, "asic atom init failed!");
4494 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4495 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4499 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4501 DRM_INFO("VRAM is lost due to GPU reset!\n");
4502 amdgpu_inc_vram_lost(tmp_adev);
4505 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4509 r = amdgpu_device_fw_loading(tmp_adev);
4513 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4518 amdgpu_device_fill_reset_magic(tmp_adev);
4521 * Add this ASIC as tracked as reset was already
4522 * complete successfully.
4524 amdgpu_register_gpu_instance(tmp_adev);
4526 if (!reset_context->hive &&
4527 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4528 amdgpu_xgmi_add_device(tmp_adev);
4530 r = amdgpu_device_ip_late_init(tmp_adev);
4534 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4537 * The GPU enters bad state once faulty pages
4538 * by ECC has reached the threshold, and ras
4539 * recovery is scheduled next. So add one check
4540 * here to break recovery if it indeed exceeds
4541 * bad page threshold, and remind user to
4542 * retire this GPU or setting one bigger
4543 * bad_page_threshold value to fix this once
4544 * probing driver again.
4546 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
4548 amdgpu_ras_resume(tmp_adev);
4554 /* Update PSP FW topology after reset */
4555 if (reset_context->hive &&
4556 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4557 r = amdgpu_xgmi_update_topology(
4558 reset_context->hive, tmp_adev);
4564 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4565 r = amdgpu_ib_ring_tests(tmp_adev);
4567 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4568 need_full_reset = true;
4575 r = amdgpu_device_recover_vram(tmp_adev);
4577 tmp_adev->asic_reset_res = r;
4581 if (need_full_reset)
4582 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4584 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4588 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4589 struct amdgpu_hive_info *hive)
4591 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4595 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4597 down_write(&adev->reset_sem);
4600 switch (amdgpu_asic_reset_method(adev)) {
4601 case AMD_RESET_METHOD_MODE1:
4602 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4604 case AMD_RESET_METHOD_MODE2:
4605 adev->mp1_state = PP_MP1_STATE_RESET;
4608 adev->mp1_state = PP_MP1_STATE_NONE;
4615 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4617 amdgpu_vf_error_trans_all(adev);
4618 adev->mp1_state = PP_MP1_STATE_NONE;
4619 atomic_set(&adev->in_gpu_reset, 0);
4620 up_write(&adev->reset_sem);
4624 * to lockup a list of amdgpu devices in a hive safely, if not a hive
4625 * with multiple nodes, it will be similar as amdgpu_device_lock_adev.
4627 * unlock won't require roll back.
4629 static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive)
4631 struct amdgpu_device *tmp_adev = NULL;
4633 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4635 dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes");
4638 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4639 if (!amdgpu_device_lock_adev(tmp_adev, hive))
4642 } else if (!amdgpu_device_lock_adev(adev, hive))
4647 if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) {
4649 * if the lockup iteration break in the middle of a hive,
4650 * it may means there may has a race issue,
4651 * or a hive device locked up independently.
4652 * we may be in trouble and may not, so will try to roll back
4653 * the lock and give out a warnning.
4655 dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock");
4656 list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4657 amdgpu_device_unlock_adev(tmp_adev);
4663 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4665 struct pci_dev *p = NULL;
4667 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4668 adev->pdev->bus->number, 1);
4670 pm_runtime_enable(&(p->dev));
4671 pm_runtime_resume(&(p->dev));
4675 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4677 enum amd_reset_method reset_method;
4678 struct pci_dev *p = NULL;
4682 * For now, only BACO and mode1 reset are confirmed
4683 * to suffer the audio issue without proper suspended.
4685 reset_method = amdgpu_asic_reset_method(adev);
4686 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4687 (reset_method != AMD_RESET_METHOD_MODE1))
4690 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4691 adev->pdev->bus->number, 1);
4695 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4698 * If we cannot get the audio device autosuspend delay,
4699 * a fixed 4S interval will be used. Considering 3S is
4700 * the audio controller default autosuspend delay setting.
4701 * 4S used here is guaranteed to cover that.
4703 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4705 while (!pm_runtime_status_suspended(&(p->dev))) {
4706 if (!pm_runtime_suspend(&(p->dev)))
4709 if (expires < ktime_get_mono_fast_ns()) {
4710 dev_warn(adev->dev, "failed to suspend display audio\n");
4711 /* TODO: abort the succeeding gpu reset? */
4716 pm_runtime_disable(&(p->dev));
4721 static void amdgpu_device_recheck_guilty_jobs(
4722 struct amdgpu_device *adev, struct list_head *device_list_handle,
4723 struct amdgpu_reset_context *reset_context)
4727 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4728 struct amdgpu_ring *ring = adev->rings[i];
4730 struct drm_sched_job *s_job;
4732 if (!ring || !ring->sched.thread)
4735 s_job = list_first_entry_or_null(&ring->sched.pending_list,
4736 struct drm_sched_job, list);
4740 /* clear job's guilty and depend the folowing step to decide the real one */
4741 drm_sched_reset_karma(s_job);
4742 drm_sched_resubmit_jobs_ext(&ring->sched, 1);
4744 ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout);
4745 if (ret == 0) { /* timeout */
4746 DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n",
4747 ring->sched.name, s_job->id);
4750 drm_sched_increase_karma(s_job);
4753 if (amdgpu_sriov_vf(adev)) {
4754 amdgpu_virt_fini_data_exchange(adev);
4755 r = amdgpu_device_reset_sriov(adev, false);
4757 adev->asic_reset_res = r;
4759 clear_bit(AMDGPU_SKIP_HW_RESET,
4760 &reset_context->flags);
4761 r = amdgpu_do_asic_reset(device_list_handle,
4763 if (r && r == -EAGAIN)
4768 * add reset counter so that the following
4769 * resubmitted job could flush vmid
4771 atomic_inc(&adev->gpu_reset_counter);
4775 /* got the hw fence, signal finished fence */
4776 atomic_dec(ring->sched.score);
4777 dma_fence_get(&s_job->s_fence->finished);
4778 dma_fence_signal(&s_job->s_fence->finished);
4779 dma_fence_put(&s_job->s_fence->finished);
4781 /* remove node from list and free the job */
4782 spin_lock(&ring->sched.job_list_lock);
4783 list_del_init(&s_job->list);
4784 spin_unlock(&ring->sched.job_list_lock);
4785 ring->sched.ops->free_job(s_job);
4790 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4792 * @adev: amdgpu_device pointer
4793 * @job: which job trigger hang
4795 * Attempt to reset the GPU if it has hung (all asics).
4796 * Attempt to do soft-reset or full-reset and reinitialize Asic
4797 * Returns 0 for success or an error on failure.
4800 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4801 struct amdgpu_job *job)
4803 struct list_head device_list, *device_list_handle = NULL;
4804 bool job_signaled = false;
4805 struct amdgpu_hive_info *hive = NULL;
4806 struct amdgpu_device *tmp_adev = NULL;
4808 bool need_emergency_restart = false;
4809 bool audio_suspended = false;
4810 int tmp_vram_lost_counter;
4811 struct amdgpu_reset_context reset_context;
4813 memset(&reset_context, 0, sizeof(reset_context));
4816 * Special case: RAS triggered and full reset isn't supported
4818 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4821 * Flush RAM to disk so that after reboot
4822 * the user can read log and see why the system rebooted.
4824 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4825 DRM_WARN("Emergency reboot.");
4828 emergency_restart();
4831 dev_info(adev->dev, "GPU %s begin!\n",
4832 need_emergency_restart ? "jobs stop":"reset");
4835 * Here we trylock to avoid chain of resets executing from
4836 * either trigger by jobs on different adevs in XGMI hive or jobs on
4837 * different schedulers for same device while this TO handler is running.
4838 * We always reset all schedulers for device and all devices for XGMI
4839 * hive so that should take care of them too.
4841 hive = amdgpu_get_xgmi_hive(adev);
4843 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4844 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4845 job ? job->base.id : -1, hive->hive_id);
4846 amdgpu_put_xgmi_hive(hive);
4848 drm_sched_increase_karma(&job->base);
4851 mutex_lock(&hive->hive_lock);
4854 reset_context.method = AMD_RESET_METHOD_NONE;
4855 reset_context.reset_req_dev = adev;
4856 reset_context.job = job;
4857 reset_context.hive = hive;
4858 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
4861 * lock the device before we try to operate the linked list
4862 * if didn't get the device lock, don't touch the linked list since
4863 * others may iterating it.
4865 r = amdgpu_device_lock_hive_adev(adev, hive);
4867 dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4868 job ? job->base.id : -1);
4870 /* even we skipped this reset, still need to set the job to guilty */
4872 drm_sched_increase_karma(&job->base);
4877 * Build list of devices to reset.
4878 * In case we are in XGMI hive mode, resort the device list
4879 * to put adev in the 1st position.
4881 INIT_LIST_HEAD(&device_list);
4882 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4883 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
4884 list_add_tail(&tmp_adev->reset_list, &device_list);
4885 if (!list_is_first(&adev->reset_list, &device_list))
4886 list_rotate_to_front(&adev->reset_list, &device_list);
4887 device_list_handle = &device_list;
4889 list_add_tail(&adev->reset_list, &device_list);
4890 device_list_handle = &device_list;
4893 /* block all schedulers and reset given job's ring */
4894 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4896 * Try to put the audio codec into suspend state
4897 * before gpu reset started.
4899 * Due to the power domain of the graphics device
4900 * is shared with AZ power domain. Without this,
4901 * we may change the audio hardware from behind
4902 * the audio driver's back. That will trigger
4903 * some audio codec errors.
4905 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4906 audio_suspended = true;
4908 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4910 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4912 if (!amdgpu_sriov_vf(tmp_adev))
4913 amdgpu_amdkfd_pre_reset(tmp_adev);
4916 * Mark these ASICs to be reseted as untracked first
4917 * And add them back after reset completed
4919 amdgpu_unregister_gpu_instance(tmp_adev);
4921 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4923 /* disable ras on ALL IPs */
4924 if (!need_emergency_restart &&
4925 amdgpu_device_ip_need_full_reset(tmp_adev))
4926 amdgpu_ras_suspend(tmp_adev);
4928 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4929 struct amdgpu_ring *ring = tmp_adev->rings[i];
4931 if (!ring || !ring->sched.thread)
4934 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4936 if (need_emergency_restart)
4937 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4939 atomic_inc(&tmp_adev->gpu_reset_counter);
4942 if (need_emergency_restart)
4943 goto skip_sched_resume;
4946 * Must check guilty signal here since after this point all old
4947 * HW fences are force signaled.
4949 * job->base holds a reference to parent fence
4951 if (job && job->base.s_fence->parent &&
4952 dma_fence_is_signaled(job->base.s_fence->parent)) {
4953 job_signaled = true;
4954 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4958 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4959 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4960 r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context);
4961 /*TODO Should we stop ?*/
4963 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4964 r, adev_to_drm(tmp_adev)->unique);
4965 tmp_adev->asic_reset_res = r;
4969 tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter));
4970 /* Actual ASIC resets if needed.*/
4971 /* TODO Implement XGMI hive reset logic for SRIOV */
4972 if (amdgpu_sriov_vf(adev)) {
4973 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4975 adev->asic_reset_res = r;
4977 r = amdgpu_do_asic_reset(device_list_handle, &reset_context);
4978 if (r && r == -EAGAIN)
4984 /* Post ASIC reset for all devs .*/
4985 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4988 * Sometimes a later bad compute job can block a good gfx job as gfx
4989 * and compute ring share internal GC HW mutually. We add an additional
4990 * guilty jobs recheck step to find the real guilty job, it synchronously
4991 * submits and pends for the first job being signaled. If it gets timeout,
4992 * we identify it as a real guilty job.
4994 if (amdgpu_gpu_recovery == 2 &&
4995 !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter)))
4996 amdgpu_device_recheck_guilty_jobs(
4997 tmp_adev, device_list_handle, &reset_context);
4999 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5000 struct amdgpu_ring *ring = tmp_adev->rings[i];
5002 if (!ring || !ring->sched.thread)
5005 /* No point to resubmit jobs if we didn't HW reset*/
5006 if (!tmp_adev->asic_reset_res && !job_signaled)
5007 drm_sched_resubmit_jobs(&ring->sched);
5009 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
5012 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
5013 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5016 tmp_adev->asic_reset_res = 0;
5019 /* bad news, how to tell it to userspace ? */
5020 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5021 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5023 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5024 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5025 DRM_WARN("smart shift update failed\n");
5030 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5031 /* unlock kfd: SRIOV would do it separately */
5032 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5033 amdgpu_amdkfd_post_reset(tmp_adev);
5035 /* kfd_post_reset will do nothing if kfd device is not initialized,
5036 * need to bring up kfd here if it's not be initialized before
5038 if (!adev->kfd.init_complete)
5039 amdgpu_amdkfd_device_init(adev);
5041 if (audio_suspended)
5042 amdgpu_device_resume_display_audio(tmp_adev);
5043 amdgpu_device_unlock_adev(tmp_adev);
5048 atomic_set(&hive->in_reset, 0);
5049 mutex_unlock(&hive->hive_lock);
5050 amdgpu_put_xgmi_hive(hive);
5053 if (r && r != -EAGAIN)
5054 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5059 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5061 * @adev: amdgpu_device pointer
5063 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5064 * and lanes) of the slot the device is in. Handles APUs and
5065 * virtualized environments where PCIE config space may not be available.
5067 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5069 struct pci_dev *pdev;
5070 enum pci_bus_speed speed_cap, platform_speed_cap;
5071 enum pcie_link_width platform_link_width;
5073 if (amdgpu_pcie_gen_cap)
5074 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5076 if (amdgpu_pcie_lane_cap)
5077 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5079 /* covers APUs as well */
5080 if (pci_is_root_bus(adev->pdev->bus)) {
5081 if (adev->pm.pcie_gen_mask == 0)
5082 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5083 if (adev->pm.pcie_mlw_mask == 0)
5084 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5088 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5091 pcie_bandwidth_available(adev->pdev, NULL,
5092 &platform_speed_cap, &platform_link_width);
5094 if (adev->pm.pcie_gen_mask == 0) {
5097 speed_cap = pcie_get_speed_cap(pdev);
5098 if (speed_cap == PCI_SPEED_UNKNOWN) {
5099 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5100 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5101 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5103 if (speed_cap == PCIE_SPEED_32_0GT)
5104 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5105 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5106 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5107 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5108 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5109 else if (speed_cap == PCIE_SPEED_16_0GT)
5110 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5111 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5112 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5113 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5114 else if (speed_cap == PCIE_SPEED_8_0GT)
5115 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5116 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5117 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5118 else if (speed_cap == PCIE_SPEED_5_0GT)
5119 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5120 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5122 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5125 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5126 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5127 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5129 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5130 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5131 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5132 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5133 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5134 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5135 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5136 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5137 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5138 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5139 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5140 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5141 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5142 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5143 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5144 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5145 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5146 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5148 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5152 if (adev->pm.pcie_mlw_mask == 0) {
5153 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5154 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5156 switch (platform_link_width) {
5158 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5159 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5160 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5161 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5162 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5163 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5164 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5167 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5168 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5169 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5170 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5171 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5172 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5175 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5176 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5177 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5178 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5179 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5182 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5183 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5184 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5185 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5188 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5189 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5190 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5193 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5194 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5197 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5206 int amdgpu_device_baco_enter(struct drm_device *dev)
5208 struct amdgpu_device *adev = drm_to_adev(dev);
5209 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5211 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5214 if (ras && adev->ras_enabled &&
5215 adev->nbio.funcs->enable_doorbell_interrupt)
5216 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5218 return amdgpu_dpm_baco_enter(adev);
5221 int amdgpu_device_baco_exit(struct drm_device *dev)
5223 struct amdgpu_device *adev = drm_to_adev(dev);
5224 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5227 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5230 ret = amdgpu_dpm_baco_exit(adev);
5234 if (ras && adev->ras_enabled &&
5235 adev->nbio.funcs->enable_doorbell_interrupt)
5236 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5241 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
5245 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5246 struct amdgpu_ring *ring = adev->rings[i];
5248 if (!ring || !ring->sched.thread)
5251 cancel_delayed_work_sync(&ring->sched.work_tdr);
5256 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5257 * @pdev: PCI device struct
5258 * @state: PCI channel state
5260 * Description: Called when a PCI error is detected.
5262 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5264 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5266 struct drm_device *dev = pci_get_drvdata(pdev);
5267 struct amdgpu_device *adev = drm_to_adev(dev);
5270 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5272 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5273 DRM_WARN("No support for XGMI hive yet...");
5274 return PCI_ERS_RESULT_DISCONNECT;
5278 case pci_channel_io_normal:
5279 return PCI_ERS_RESULT_CAN_RECOVER;
5280 /* Fatal error, prepare for slot reset */
5281 case pci_channel_io_frozen:
5283 * Cancel and wait for all TDRs in progress if failing to
5284 * set adev->in_gpu_reset in amdgpu_device_lock_adev
5286 * Locking adev->reset_sem will prevent any external access
5287 * to GPU during PCI error recovery
5289 while (!amdgpu_device_lock_adev(adev, NULL))
5290 amdgpu_cancel_all_tdr(adev);
5293 * Block any work scheduling as we do for regular GPU reset
5294 * for the duration of the recovery
5296 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5297 struct amdgpu_ring *ring = adev->rings[i];
5299 if (!ring || !ring->sched.thread)
5302 drm_sched_stop(&ring->sched, NULL);
5304 atomic_inc(&adev->gpu_reset_counter);
5305 return PCI_ERS_RESULT_NEED_RESET;
5306 case pci_channel_io_perm_failure:
5307 /* Permanent error, prepare for device removal */
5308 return PCI_ERS_RESULT_DISCONNECT;
5311 return PCI_ERS_RESULT_NEED_RESET;
5315 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5316 * @pdev: pointer to PCI device
5318 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5321 DRM_INFO("PCI error: mmio enabled callback!!\n");
5323 /* TODO - dump whatever for debugging purposes */
5325 /* This called only if amdgpu_pci_error_detected returns
5326 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5327 * works, no need to reset slot.
5330 return PCI_ERS_RESULT_RECOVERED;
5334 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5335 * @pdev: PCI device struct
5337 * Description: This routine is called by the pci error recovery
5338 * code after the PCI slot has been reset, just before we
5339 * should resume normal operations.
5341 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5343 struct drm_device *dev = pci_get_drvdata(pdev);
5344 struct amdgpu_device *adev = drm_to_adev(dev);
5346 struct amdgpu_reset_context reset_context;
5348 struct list_head device_list;
5350 DRM_INFO("PCI error: slot reset callback!!\n");
5352 memset(&reset_context, 0, sizeof(reset_context));
5354 INIT_LIST_HEAD(&device_list);
5355 list_add_tail(&adev->reset_list, &device_list);
5357 /* wait for asic to come out of reset */
5360 /* Restore PCI confspace */
5361 amdgpu_device_load_pci_state(pdev);
5363 /* confirm ASIC came out of reset */
5364 for (i = 0; i < adev->usec_timeout; i++) {
5365 memsize = amdgpu_asic_get_config_memsize(adev);
5367 if (memsize != 0xffffffff)
5371 if (memsize == 0xffffffff) {
5376 reset_context.method = AMD_RESET_METHOD_NONE;
5377 reset_context.reset_req_dev = adev;
5378 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5379 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5381 adev->no_hw_access = true;
5382 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5383 adev->no_hw_access = false;
5387 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5391 if (amdgpu_device_cache_pci_state(adev->pdev))
5392 pci_restore_state(adev->pdev);
5394 DRM_INFO("PCIe error recovery succeeded\n");
5396 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5397 amdgpu_device_unlock_adev(adev);
5400 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5404 * amdgpu_pci_resume() - resume normal ops after PCI reset
5405 * @pdev: pointer to PCI device
5407 * Called when the error recovery driver tells us that its
5408 * OK to resume normal operation.
5410 void amdgpu_pci_resume(struct pci_dev *pdev)
5412 struct drm_device *dev = pci_get_drvdata(pdev);
5413 struct amdgpu_device *adev = drm_to_adev(dev);
5417 DRM_INFO("PCI error: resume callback!!\n");
5419 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5420 struct amdgpu_ring *ring = adev->rings[i];
5422 if (!ring || !ring->sched.thread)
5426 drm_sched_resubmit_jobs(&ring->sched);
5427 drm_sched_start(&ring->sched, true);
5430 amdgpu_device_unlock_adev(adev);
5433 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5435 struct drm_device *dev = pci_get_drvdata(pdev);
5436 struct amdgpu_device *adev = drm_to_adev(dev);
5439 r = pci_save_state(pdev);
5441 kfree(adev->pci_state);
5443 adev->pci_state = pci_store_saved_state(pdev);
5445 if (!adev->pci_state) {
5446 DRM_ERROR("Failed to store PCI saved state");
5450 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5457 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5459 struct drm_device *dev = pci_get_drvdata(pdev);
5460 struct amdgpu_device *adev = drm_to_adev(dev);
5463 if (!adev->pci_state)
5466 r = pci_load_saved_state(pdev, adev->pci_state);
5469 pci_restore_state(pdev);
5471 DRM_WARN("Failed to load PCI state, err:%d\n", r);