2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
38 #include "amdgpu_i2c.h"
40 #include "amdgpu_atombios.h"
42 #ifdef CONFIG_DRM_AMDGPU_CIK
46 #include "bif/bif_4_1_d.h"
48 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
49 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
51 static const char *amdgpu_asic_name[] = {
67 bool amdgpu_device_is_px(struct drm_device *dev)
69 struct amdgpu_device *adev = dev->dev_private;
71 if (adev->flags & AMD_IS_PX)
77 * MMIO register access helper functions.
79 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
82 if ((reg * 4) < adev->rmmio_size && !always_indirect)
83 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
88 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
89 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
90 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
91 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
97 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
100 if ((reg * 4) < adev->rmmio_size && !always_indirect)
101 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
105 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
106 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
107 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
108 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
112 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
114 if ((reg * 4) < adev->rio_mem_size)
115 return ioread32(adev->rio_mem + (reg * 4));
117 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
118 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
122 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
125 if ((reg * 4) < adev->rio_mem_size)
126 iowrite32(v, adev->rio_mem + (reg * 4));
128 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
129 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
134 * amdgpu_mm_rdoorbell - read a doorbell dword
136 * @adev: amdgpu_device pointer
137 * @index: doorbell index
139 * Returns the value in the doorbell aperture at the
140 * requested doorbell index (CIK).
142 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
144 if (index < adev->doorbell.num_doorbells) {
145 return readl(adev->doorbell.ptr + index);
147 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
153 * amdgpu_mm_wdoorbell - write a doorbell dword
155 * @adev: amdgpu_device pointer
156 * @index: doorbell index
159 * Writes @v to the doorbell aperture at the
160 * requested doorbell index (CIK).
162 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
164 if (index < adev->doorbell.num_doorbells) {
165 writel(v, adev->doorbell.ptr + index);
167 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
172 * amdgpu_invalid_rreg - dummy reg read function
174 * @adev: amdgpu device pointer
175 * @reg: offset of register
177 * Dummy register read function. Used for register blocks
178 * that certain asics don't have (all asics).
179 * Returns the value in the register.
181 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
183 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
189 * amdgpu_invalid_wreg - dummy reg write function
191 * @adev: amdgpu device pointer
192 * @reg: offset of register
193 * @v: value to write to the register
195 * Dummy register read function. Used for register blocks
196 * that certain asics don't have (all asics).
198 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
200 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
206 * amdgpu_block_invalid_rreg - dummy reg read function
208 * @adev: amdgpu device pointer
209 * @block: offset of instance
210 * @reg: offset of register
212 * Dummy register read function. Used for register blocks
213 * that certain asics don't have (all asics).
214 * Returns the value in the register.
216 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
217 uint32_t block, uint32_t reg)
219 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
226 * amdgpu_block_invalid_wreg - dummy reg write function
228 * @adev: amdgpu device pointer
229 * @block: offset of instance
230 * @reg: offset of register
231 * @v: value to write to the register
233 * Dummy register read function. Used for register blocks
234 * that certain asics don't have (all asics).
236 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
238 uint32_t reg, uint32_t v)
240 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
245 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
249 if (adev->vram_scratch.robj == NULL) {
250 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
251 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
252 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
253 NULL, NULL, &adev->vram_scratch.robj);
259 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
260 if (unlikely(r != 0))
262 r = amdgpu_bo_pin(adev->vram_scratch.robj,
263 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
265 amdgpu_bo_unreserve(adev->vram_scratch.robj);
268 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
269 (void **)&adev->vram_scratch.ptr);
271 amdgpu_bo_unpin(adev->vram_scratch.robj);
272 amdgpu_bo_unreserve(adev->vram_scratch.robj);
277 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
281 if (adev->vram_scratch.robj == NULL) {
284 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
285 if (likely(r == 0)) {
286 amdgpu_bo_kunmap(adev->vram_scratch.robj);
287 amdgpu_bo_unpin(adev->vram_scratch.robj);
288 amdgpu_bo_unreserve(adev->vram_scratch.robj);
290 amdgpu_bo_unref(&adev->vram_scratch.robj);
294 * amdgpu_program_register_sequence - program an array of registers.
296 * @adev: amdgpu_device pointer
297 * @registers: pointer to the register array
298 * @array_size: size of the register array
300 * Programs an array or registers with and and or masks.
301 * This is a helper for setting golden registers.
303 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
304 const u32 *registers,
305 const u32 array_size)
307 u32 tmp, reg, and_mask, or_mask;
313 for (i = 0; i < array_size; i +=3) {
314 reg = registers[i + 0];
315 and_mask = registers[i + 1];
316 or_mask = registers[i + 2];
318 if (and_mask == 0xffffffff) {
329 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
331 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
335 * GPU doorbell aperture helpers function.
338 * amdgpu_doorbell_init - Init doorbell driver information.
340 * @adev: amdgpu_device pointer
342 * Init doorbell driver information (CIK)
343 * Returns 0 on success, error on failure.
345 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
347 /* doorbell bar mapping */
348 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
349 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
351 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
352 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
353 if (adev->doorbell.num_doorbells == 0)
356 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
357 if (adev->doorbell.ptr == NULL) {
360 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
361 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
367 * amdgpu_doorbell_fini - Tear down doorbell driver information.
369 * @adev: amdgpu_device pointer
371 * Tear down doorbell driver information (CIK)
373 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
375 iounmap(adev->doorbell.ptr);
376 adev->doorbell.ptr = NULL;
380 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
383 * @adev: amdgpu_device pointer
384 * @aperture_base: output returning doorbell aperture base physical address
385 * @aperture_size: output returning doorbell aperture size in bytes
386 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
388 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
389 * takes doorbells required for its own rings and reports the setup to amdkfd.
390 * amdgpu reserved doorbells are at the start of the doorbell aperture.
392 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
393 phys_addr_t *aperture_base,
394 size_t *aperture_size,
395 size_t *start_offset)
398 * The first num_doorbells are used by amdgpu.
399 * amdkfd takes whatever's left in the aperture.
401 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
402 *aperture_base = adev->doorbell.base;
403 *aperture_size = adev->doorbell.size;
404 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
414 * Writeback is the the method by which the the GPU updates special pages
415 * in memory with the status of certain GPU events (fences, ring pointers,
420 * amdgpu_wb_fini - Disable Writeback and free memory
422 * @adev: amdgpu_device pointer
424 * Disables Writeback and frees the Writeback memory (all asics).
425 * Used at driver shutdown.
427 static void amdgpu_wb_fini(struct amdgpu_device *adev)
429 if (adev->wb.wb_obj) {
430 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
431 amdgpu_bo_kunmap(adev->wb.wb_obj);
432 amdgpu_bo_unpin(adev->wb.wb_obj);
433 amdgpu_bo_unreserve(adev->wb.wb_obj);
435 amdgpu_bo_unref(&adev->wb.wb_obj);
437 adev->wb.wb_obj = NULL;
442 * amdgpu_wb_init- Init Writeback driver info and allocate memory
444 * @adev: amdgpu_device pointer
446 * Disables Writeback and frees the Writeback memory (all asics).
447 * Used at driver startup.
448 * Returns 0 on success or an -error on failure.
450 static int amdgpu_wb_init(struct amdgpu_device *adev)
454 if (adev->wb.wb_obj == NULL) {
455 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
456 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
459 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
462 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
463 if (unlikely(r != 0)) {
464 amdgpu_wb_fini(adev);
467 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
470 amdgpu_bo_unreserve(adev->wb.wb_obj);
471 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
472 amdgpu_wb_fini(adev);
475 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
476 amdgpu_bo_unreserve(adev->wb.wb_obj);
478 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
479 amdgpu_wb_fini(adev);
483 adev->wb.num_wb = AMDGPU_MAX_WB;
484 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
486 /* clear wb memory */
487 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
494 * amdgpu_wb_get - Allocate a wb entry
496 * @adev: amdgpu_device pointer
499 * Allocate a wb slot for use by the driver (all asics).
500 * Returns 0 on success or -EINVAL on failure.
502 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
504 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
505 if (offset < adev->wb.num_wb) {
506 __set_bit(offset, adev->wb.used);
515 * amdgpu_wb_free - Free a wb entry
517 * @adev: amdgpu_device pointer
520 * Free a wb slot allocated for use by the driver (all asics)
522 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
524 if (wb < adev->wb.num_wb)
525 __clear_bit(wb, adev->wb.used);
529 * amdgpu_vram_location - try to find VRAM location
530 * @adev: amdgpu device structure holding all necessary informations
531 * @mc: memory controller structure holding memory informations
532 * @base: base address at which to put VRAM
534 * Function will place try to place VRAM at base address provided
535 * as parameter (which is so far either PCI aperture address or
536 * for IGP TOM base address).
538 * If there is not enough space to fit the unvisible VRAM in the 32bits
539 * address space then we limit the VRAM size to the aperture.
541 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
542 * this shouldn't be a problem as we are using the PCI aperture as a reference.
543 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
546 * Note: we use mc_vram_size as on some board we need to program the mc to
547 * cover the whole aperture even if VRAM size is inferior to aperture size
548 * Novell bug 204882 + along with lots of ubuntu ones
550 * Note: when limiting vram it's safe to overwritte real_vram_size because
551 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
552 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
555 * Note: IGP TOM addr should be the same as the aperture addr, we don't
556 * explicitly check for that thought.
558 * FIXME: when reducing VRAM size align new size on power of 2.
560 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
562 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
564 mc->vram_start = base;
565 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
566 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
567 mc->real_vram_size = mc->aper_size;
568 mc->mc_vram_size = mc->aper_size;
570 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
571 if (limit && limit < mc->real_vram_size)
572 mc->real_vram_size = limit;
573 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
574 mc->mc_vram_size >> 20, mc->vram_start,
575 mc->vram_end, mc->real_vram_size >> 20);
579 * amdgpu_gtt_location - try to find GTT location
580 * @adev: amdgpu device structure holding all necessary informations
581 * @mc: memory controller structure holding memory informations
583 * Function will place try to place GTT before or after VRAM.
585 * If GTT size is bigger than space left then we ajust GTT size.
586 * Thus function will never fails.
588 * FIXME: when reducing GTT size align new size on power of 2.
590 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
592 u64 size_af, size_bf;
594 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
595 size_bf = mc->vram_start & ~mc->gtt_base_align;
596 if (size_bf > size_af) {
597 if (mc->gtt_size > size_bf) {
598 dev_warn(adev->dev, "limiting GTT\n");
599 mc->gtt_size = size_bf;
601 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
603 if (mc->gtt_size > size_af) {
604 dev_warn(adev->dev, "limiting GTT\n");
605 mc->gtt_size = size_af;
607 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
609 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
610 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
611 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
615 * GPU helpers function.
618 * amdgpu_card_posted - check if the hw has already been initialized
620 * @adev: amdgpu_device pointer
622 * Check if the asic has been initialized (all asics).
623 * Used at driver startup.
624 * Returns true if initialized or false if not.
626 bool amdgpu_card_posted(struct amdgpu_device *adev)
630 /* then check MEM_SIZE, in case the crtcs are off */
631 reg = RREG32(mmCONFIG_MEMSIZE);
641 * amdgpu_dummy_page_init - init dummy page used by the driver
643 * @adev: amdgpu_device pointer
645 * Allocate the dummy page used by the driver (all asics).
646 * This dummy page is used by the driver as a filler for gart entries
647 * when pages are taken out of the GART
648 * Returns 0 on sucess, -ENOMEM on failure.
650 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
652 if (adev->dummy_page.page)
654 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
655 if (adev->dummy_page.page == NULL)
657 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
658 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
659 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
660 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
661 __free_page(adev->dummy_page.page);
662 adev->dummy_page.page = NULL;
669 * amdgpu_dummy_page_fini - free dummy page used by the driver
671 * @adev: amdgpu_device pointer
673 * Frees the dummy page used by the driver (all asics).
675 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
677 if (adev->dummy_page.page == NULL)
679 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
680 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
681 __free_page(adev->dummy_page.page);
682 adev->dummy_page.page = NULL;
686 /* ATOM accessor methods */
688 * ATOM is an interpreted byte code stored in tables in the vbios. The
689 * driver registers callbacks to access registers and the interpreter
690 * in the driver parses the tables and executes then to program specific
691 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
692 * atombios.h, and atom.c
696 * cail_pll_read - read PLL register
698 * @info: atom card_info pointer
699 * @reg: PLL register offset
701 * Provides a PLL register accessor for the atom interpreter (r4xx+).
702 * Returns the value of the PLL register.
704 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
710 * cail_pll_write - write PLL register
712 * @info: atom card_info pointer
713 * @reg: PLL register offset
714 * @val: value to write to the pll register
716 * Provides a PLL register accessor for the atom interpreter (r4xx+).
718 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
724 * cail_mc_read - read MC (Memory Controller) register
726 * @info: atom card_info pointer
727 * @reg: MC register offset
729 * Provides an MC register accessor for the atom interpreter (r4xx+).
730 * Returns the value of the MC register.
732 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
738 * cail_mc_write - write MC (Memory Controller) register
740 * @info: atom card_info pointer
741 * @reg: MC register offset
742 * @val: value to write to the pll register
744 * Provides a MC register accessor for the atom interpreter (r4xx+).
746 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
752 * cail_reg_write - write MMIO register
754 * @info: atom card_info pointer
755 * @reg: MMIO register offset
756 * @val: value to write to the pll register
758 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
760 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
762 struct amdgpu_device *adev = info->dev->dev_private;
768 * cail_reg_read - read MMIO register
770 * @info: atom card_info pointer
771 * @reg: MMIO register offset
773 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
774 * Returns the value of the MMIO register.
776 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
778 struct amdgpu_device *adev = info->dev->dev_private;
786 * cail_ioreg_write - write IO register
788 * @info: atom card_info pointer
789 * @reg: IO register offset
790 * @val: value to write to the pll register
792 * Provides a IO register accessor for the atom interpreter (r4xx+).
794 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
796 struct amdgpu_device *adev = info->dev->dev_private;
802 * cail_ioreg_read - read IO register
804 * @info: atom card_info pointer
805 * @reg: IO register offset
807 * Provides an IO register accessor for the atom interpreter (r4xx+).
808 * Returns the value of the IO register.
810 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
812 struct amdgpu_device *adev = info->dev->dev_private;
820 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
822 * @adev: amdgpu_device pointer
824 * Frees the driver info and register access callbacks for the ATOM
825 * interpreter (r4xx+).
826 * Called at driver shutdown.
828 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
830 if (adev->mode_info.atom_context)
831 kfree(adev->mode_info.atom_context->scratch);
832 kfree(adev->mode_info.atom_context);
833 adev->mode_info.atom_context = NULL;
834 kfree(adev->mode_info.atom_card_info);
835 adev->mode_info.atom_card_info = NULL;
839 * amdgpu_atombios_init - init the driver info and callbacks for atombios
841 * @adev: amdgpu_device pointer
843 * Initializes the driver info and register access callbacks for the
844 * ATOM interpreter (r4xx+).
845 * Returns 0 on sucess, -ENOMEM on failure.
846 * Called at driver startup.
848 static int amdgpu_atombios_init(struct amdgpu_device *adev)
850 struct card_info *atom_card_info =
851 kzalloc(sizeof(struct card_info), GFP_KERNEL);
856 adev->mode_info.atom_card_info = atom_card_info;
857 atom_card_info->dev = adev->ddev;
858 atom_card_info->reg_read = cail_reg_read;
859 atom_card_info->reg_write = cail_reg_write;
860 /* needed for iio ops */
862 atom_card_info->ioreg_read = cail_ioreg_read;
863 atom_card_info->ioreg_write = cail_ioreg_write;
865 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
866 atom_card_info->ioreg_read = cail_reg_read;
867 atom_card_info->ioreg_write = cail_reg_write;
869 atom_card_info->mc_read = cail_mc_read;
870 atom_card_info->mc_write = cail_mc_write;
871 atom_card_info->pll_read = cail_pll_read;
872 atom_card_info->pll_write = cail_pll_write;
874 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
875 if (!adev->mode_info.atom_context) {
876 amdgpu_atombios_fini(adev);
880 mutex_init(&adev->mode_info.atom_context->mutex);
881 amdgpu_atombios_scratch_regs_init(adev);
882 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
886 /* if we get transitioned to only one device, take VGA back */
888 * amdgpu_vga_set_decode - enable/disable vga decode
890 * @cookie: amdgpu_device pointer
891 * @state: enable/disable vga decode
893 * Enable/disable vga decode (all asics).
894 * Returns VGA resource flags.
896 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
898 struct amdgpu_device *adev = cookie;
899 amdgpu_asic_set_vga_state(adev, state);
901 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
902 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
904 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
908 * amdgpu_check_pot_argument - check that argument is a power of two
910 * @arg: value to check
912 * Validates that a certain argument is a power of two (all asics).
913 * Returns true if argument is valid.
915 static bool amdgpu_check_pot_argument(int arg)
917 return (arg & (arg - 1)) == 0;
921 * amdgpu_check_arguments - validate module params
923 * @adev: amdgpu_device pointer
925 * Validates certain module parameters and updates
926 * the associated values used by the driver (all asics).
928 static void amdgpu_check_arguments(struct amdgpu_device *adev)
930 if (amdgpu_sched_jobs < 4) {
931 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
933 amdgpu_sched_jobs = 4;
934 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
935 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
937 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
940 if (amdgpu_gart_size != -1) {
941 /* gtt size must be greater or equal to 32M */
942 if (amdgpu_gart_size < 32) {
943 dev_warn(adev->dev, "gart size (%d) too small\n",
945 amdgpu_gart_size = -1;
949 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
950 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
955 if (amdgpu_vm_size < 1) {
956 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
962 * Max GPUVM size for Cayman, SI and CI are 40 bits.
964 if (amdgpu_vm_size > 1024) {
965 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
970 /* defines number of bits in page table versus page directory,
971 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
972 * page table and the remaining bits are in the page directory */
973 if (amdgpu_vm_block_size == -1) {
975 /* Total bits covered by PD + PTs */
976 unsigned bits = ilog2(amdgpu_vm_size) + 18;
978 /* Make sure the PD is 4K in size up to 8GB address space.
979 Above that split equal between PD and PTs */
980 if (amdgpu_vm_size <= 8)
981 amdgpu_vm_block_size = bits - 9;
983 amdgpu_vm_block_size = (bits + 3) / 2;
985 } else if (amdgpu_vm_block_size < 9) {
986 dev_warn(adev->dev, "VM page table size (%d) too small\n",
987 amdgpu_vm_block_size);
988 amdgpu_vm_block_size = 9;
991 if (amdgpu_vm_block_size > 24 ||
992 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
993 dev_warn(adev->dev, "VM page table size (%d) too large\n",
994 amdgpu_vm_block_size);
995 amdgpu_vm_block_size = 9;
1000 * amdgpu_switcheroo_set_state - set switcheroo state
1002 * @pdev: pci dev pointer
1003 * @state: vga_switcheroo state
1005 * Callback for the switcheroo driver. Suspends or resumes the
1006 * the asics before or after it is powered up using ACPI methods.
1008 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1010 struct drm_device *dev = pci_get_drvdata(pdev);
1012 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1015 if (state == VGA_SWITCHEROO_ON) {
1016 unsigned d3_delay = dev->pdev->d3_delay;
1018 printk(KERN_INFO "amdgpu: switched on\n");
1019 /* don't suspend or resume card normally */
1020 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1022 amdgpu_resume_kms(dev, true, true);
1024 dev->pdev->d3_delay = d3_delay;
1026 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1027 drm_kms_helper_poll_enable(dev);
1029 printk(KERN_INFO "amdgpu: switched off\n");
1030 drm_kms_helper_poll_disable(dev);
1031 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1032 amdgpu_suspend_kms(dev, true, true);
1033 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1038 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1040 * @pdev: pci dev pointer
1042 * Callback for the switcheroo driver. Check of the switcheroo
1043 * state can be changed.
1044 * Returns true if the state can be changed, false if not.
1046 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1048 struct drm_device *dev = pci_get_drvdata(pdev);
1051 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1052 * locking inversion with the driver load path. And the access here is
1053 * completely racy anyway. So don't bother with locking for now.
1055 return dev->open_count == 0;
1058 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1059 .set_gpu_state = amdgpu_switcheroo_set_state,
1061 .can_switch = amdgpu_switcheroo_can_switch,
1064 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1065 enum amd_ip_block_type block_type,
1066 enum amd_clockgating_state state)
1070 for (i = 0; i < adev->num_ip_blocks; i++) {
1071 if (adev->ip_blocks[i].type == block_type) {
1072 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1081 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1082 enum amd_ip_block_type block_type,
1083 enum amd_powergating_state state)
1087 for (i = 0; i < adev->num_ip_blocks; i++) {
1088 if (adev->ip_blocks[i].type == block_type) {
1089 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1098 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1099 struct amdgpu_device *adev,
1100 enum amd_ip_block_type type)
1104 for (i = 0; i < adev->num_ip_blocks; i++)
1105 if (adev->ip_blocks[i].type == type)
1106 return &adev->ip_blocks[i];
1112 * amdgpu_ip_block_version_cmp
1114 * @adev: amdgpu_device pointer
1115 * @type: enum amd_ip_block_type
1116 * @major: major version
1117 * @minor: minor version
1119 * return 0 if equal or greater
1120 * return 1 if smaller or the ip_block doesn't exist
1122 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1123 enum amd_ip_block_type type,
1124 u32 major, u32 minor)
1126 const struct amdgpu_ip_block_version *ip_block;
1127 ip_block = amdgpu_get_ip_block(adev, type);
1129 if (ip_block && ((ip_block->major > major) ||
1130 ((ip_block->major == major) &&
1131 (ip_block->minor >= minor))))
1137 static int amdgpu_early_init(struct amdgpu_device *adev)
1141 switch (adev->asic_type) {
1145 case CHIP_POLARIS11:
1146 case CHIP_POLARIS10:
1149 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1150 adev->family = AMDGPU_FAMILY_CZ;
1152 adev->family = AMDGPU_FAMILY_VI;
1154 r = vi_set_ip_blocks(adev);
1158 #ifdef CONFIG_DRM_AMDGPU_CIK
1164 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1165 adev->family = AMDGPU_FAMILY_CI;
1167 adev->family = AMDGPU_FAMILY_KV;
1169 r = cik_set_ip_blocks(adev);
1175 /* FIXME: not supported yet */
1179 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1180 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1181 if (adev->ip_block_status == NULL)
1184 if (adev->ip_blocks == NULL) {
1185 DRM_ERROR("No IP blocks found!\n");
1189 for (i = 0; i < adev->num_ip_blocks; i++) {
1190 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1191 DRM_ERROR("disabled ip block: %d\n", i);
1192 adev->ip_block_status[i].valid = false;
1194 if (adev->ip_blocks[i].funcs->early_init) {
1195 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1197 adev->ip_block_status[i].valid = false;
1199 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1202 adev->ip_block_status[i].valid = true;
1205 adev->ip_block_status[i].valid = true;
1213 static int amdgpu_init(struct amdgpu_device *adev)
1217 for (i = 0; i < adev->num_ip_blocks; i++) {
1218 if (!adev->ip_block_status[i].valid)
1220 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1222 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1225 adev->ip_block_status[i].sw = true;
1226 /* need to do gmc hw init early so we can allocate gpu mem */
1227 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1228 r = amdgpu_vram_scratch_init(adev);
1230 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1233 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1235 DRM_ERROR("hw_init %d failed %d\n", i, r);
1238 r = amdgpu_wb_init(adev);
1240 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1243 adev->ip_block_status[i].hw = true;
1247 for (i = 0; i < adev->num_ip_blocks; i++) {
1248 if (!adev->ip_block_status[i].sw)
1250 /* gmc hw init is done early */
1251 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1253 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1255 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1258 adev->ip_block_status[i].hw = true;
1264 static int amdgpu_late_init(struct amdgpu_device *adev)
1268 for (i = 0; i < adev->num_ip_blocks; i++) {
1269 if (!adev->ip_block_status[i].valid)
1271 /* enable clockgating to save power */
1272 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1275 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1278 if (adev->ip_blocks[i].funcs->late_init) {
1279 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1281 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1290 static int amdgpu_fini(struct amdgpu_device *adev)
1294 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1295 if (!adev->ip_block_status[i].hw)
1297 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1298 amdgpu_wb_fini(adev);
1299 amdgpu_vram_scratch_fini(adev);
1301 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1302 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1303 AMD_CG_STATE_UNGATE);
1305 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1308 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1309 /* XXX handle errors */
1311 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1313 adev->ip_block_status[i].hw = false;
1316 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1317 if (!adev->ip_block_status[i].sw)
1319 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1320 /* XXX handle errors */
1322 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1324 adev->ip_block_status[i].sw = false;
1325 adev->ip_block_status[i].valid = false;
1331 static int amdgpu_suspend(struct amdgpu_device *adev)
1335 /* ungate SMC block first */
1336 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1337 AMD_CG_STATE_UNGATE);
1339 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1342 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1343 if (!adev->ip_block_status[i].valid)
1345 /* ungate blocks so that suspend can properly shut them down */
1346 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1347 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1348 AMD_CG_STATE_UNGATE);
1350 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1353 /* XXX handle errors */
1354 r = adev->ip_blocks[i].funcs->suspend(adev);
1355 /* XXX handle errors */
1357 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1364 static int amdgpu_resume(struct amdgpu_device *adev)
1368 for (i = 0; i < adev->num_ip_blocks; i++) {
1369 if (!adev->ip_block_status[i].valid)
1371 r = adev->ip_blocks[i].funcs->resume(adev);
1373 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1382 * amdgpu_device_init - initialize the driver
1384 * @adev: amdgpu_device pointer
1385 * @pdev: drm dev pointer
1386 * @pdev: pci dev pointer
1387 * @flags: driver flags
1389 * Initializes the driver info and hw (all asics).
1390 * Returns 0 for success or an error on failure.
1391 * Called at driver startup.
1393 int amdgpu_device_init(struct amdgpu_device *adev,
1394 struct drm_device *ddev,
1395 struct pci_dev *pdev,
1399 bool runtime = false;
1401 adev->shutdown = false;
1402 adev->dev = &pdev->dev;
1405 adev->flags = flags;
1406 adev->asic_type = flags & AMD_ASIC_MASK;
1407 adev->is_atom_bios = false;
1408 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1409 adev->mc.gtt_size = 512 * 1024 * 1024;
1410 adev->accel_working = false;
1411 adev->num_rings = 0;
1412 adev->mman.buffer_funcs = NULL;
1413 adev->mman.buffer_funcs_ring = NULL;
1414 adev->vm_manager.vm_pte_funcs = NULL;
1415 adev->vm_manager.vm_pte_num_rings = 0;
1416 adev->gart.gart_funcs = NULL;
1417 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1419 adev->smc_rreg = &amdgpu_invalid_rreg;
1420 adev->smc_wreg = &amdgpu_invalid_wreg;
1421 adev->pcie_rreg = &amdgpu_invalid_rreg;
1422 adev->pcie_wreg = &amdgpu_invalid_wreg;
1423 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1424 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1425 adev->didt_rreg = &amdgpu_invalid_rreg;
1426 adev->didt_wreg = &amdgpu_invalid_wreg;
1427 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1428 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1430 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1431 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1432 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1434 /* mutex initialization are all done here so we
1435 * can recall function without having locking issues */
1436 mutex_init(&adev->vm_manager.lock);
1437 atomic_set(&adev->irq.ih.lock, 0);
1438 mutex_init(&adev->pm.mutex);
1439 mutex_init(&adev->gfx.gpu_clock_mutex);
1440 mutex_init(&adev->srbm_mutex);
1441 mutex_init(&adev->grbm_idx_mutex);
1442 mutex_init(&adev->mn_lock);
1443 hash_init(adev->mn_hash);
1445 amdgpu_check_arguments(adev);
1447 /* Registers mapping */
1448 /* TODO: block userspace mapping of io register */
1449 spin_lock_init(&adev->mmio_idx_lock);
1450 spin_lock_init(&adev->smc_idx_lock);
1451 spin_lock_init(&adev->pcie_idx_lock);
1452 spin_lock_init(&adev->uvd_ctx_idx_lock);
1453 spin_lock_init(&adev->didt_idx_lock);
1454 spin_lock_init(&adev->audio_endpt_idx_lock);
1456 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1457 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1458 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1459 if (adev->rmmio == NULL) {
1462 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1463 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1465 /* doorbell bar mapping */
1466 amdgpu_doorbell_init(adev);
1468 /* io port mapping */
1469 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1470 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1471 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1472 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1476 if (adev->rio_mem == NULL)
1477 DRM_ERROR("Unable to find PCI I/O BAR\n");
1479 /* early init functions */
1480 r = amdgpu_early_init(adev);
1484 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1485 /* this will fail for cards that aren't VGA class devices, just
1487 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1489 if (amdgpu_runtime_pm == 1)
1491 if (amdgpu_device_is_px(ddev))
1493 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1495 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1498 if (!amdgpu_get_bios(adev))
1500 /* Must be an ATOMBIOS */
1501 if (!adev->is_atom_bios) {
1502 dev_err(adev->dev, "Expecting atombios for GPU\n");
1505 r = amdgpu_atombios_init(adev);
1507 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1511 /* See if the asic supports SR-IOV */
1512 adev->virtualization.supports_sr_iov =
1513 amdgpu_atombios_has_gpu_virtualization_table(adev);
1515 /* Post card if necessary */
1516 if (!amdgpu_card_posted(adev) ||
1517 adev->virtualization.supports_sr_iov) {
1519 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1522 DRM_INFO("GPU not posted. posting now...\n");
1523 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1526 /* Initialize clocks */
1527 r = amdgpu_atombios_get_clock_info(adev);
1529 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1532 /* init i2c buses */
1533 amdgpu_atombios_i2c_init(adev);
1536 r = amdgpu_fence_driver_init(adev);
1538 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1542 /* init the mode config */
1543 drm_mode_config_init(adev->ddev);
1545 r = amdgpu_init(adev);
1547 dev_err(adev->dev, "amdgpu_init failed\n");
1552 adev->accel_working = true;
1554 amdgpu_fbdev_init(adev);
1556 r = amdgpu_ib_pool_init(adev);
1558 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1562 r = amdgpu_ib_ring_tests(adev);
1564 DRM_ERROR("ib ring test failed (%d).\n", r);
1566 r = amdgpu_gem_debugfs_init(adev);
1568 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1571 r = amdgpu_debugfs_regs_init(adev);
1573 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1576 if ((amdgpu_testing & 1)) {
1577 if (adev->accel_working)
1578 amdgpu_test_moves(adev);
1580 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1582 if ((amdgpu_testing & 2)) {
1583 if (adev->accel_working)
1584 amdgpu_test_syncing(adev);
1586 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1588 if (amdgpu_benchmarking) {
1589 if (adev->accel_working)
1590 amdgpu_benchmark(adev, amdgpu_benchmarking);
1592 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1595 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1596 * explicit gating rather than handling it automatically.
1598 r = amdgpu_late_init(adev);
1600 dev_err(adev->dev, "amdgpu_late_init failed\n");
1607 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1610 * amdgpu_device_fini - tear down the driver
1612 * @adev: amdgpu_device pointer
1614 * Tear down the driver info (all asics).
1615 * Called at driver shutdown.
1617 void amdgpu_device_fini(struct amdgpu_device *adev)
1621 DRM_INFO("amdgpu: finishing device.\n");
1622 adev->shutdown = true;
1623 /* evict vram memory */
1624 amdgpu_bo_evict_vram(adev);
1625 amdgpu_ib_pool_fini(adev);
1626 amdgpu_fence_driver_fini(adev);
1627 amdgpu_fbdev_fini(adev);
1628 r = amdgpu_fini(adev);
1629 kfree(adev->ip_block_status);
1630 adev->ip_block_status = NULL;
1631 adev->accel_working = false;
1632 /* free i2c buses */
1633 amdgpu_i2c_fini(adev);
1634 amdgpu_atombios_fini(adev);
1637 vga_switcheroo_unregister_client(adev->pdev);
1638 vga_client_register(adev->pdev, NULL, NULL, NULL);
1640 pci_iounmap(adev->pdev, adev->rio_mem);
1641 adev->rio_mem = NULL;
1642 iounmap(adev->rmmio);
1644 amdgpu_doorbell_fini(adev);
1645 amdgpu_debugfs_regs_cleanup(adev);
1646 amdgpu_debugfs_remove_files(adev);
1654 * amdgpu_suspend_kms - initiate device suspend
1656 * @pdev: drm dev pointer
1657 * @state: suspend state
1659 * Puts the hw in the suspend state (all asics).
1660 * Returns 0 for success or an error on failure.
1661 * Called at driver suspend.
1663 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1665 struct amdgpu_device *adev;
1666 struct drm_crtc *crtc;
1667 struct drm_connector *connector;
1670 if (dev == NULL || dev->dev_private == NULL) {
1674 adev = dev->dev_private;
1676 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1679 drm_kms_helper_poll_disable(dev);
1681 /* turn off display hw */
1682 drm_modeset_lock_all(dev);
1683 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1684 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1686 drm_modeset_unlock_all(dev);
1688 /* unpin the front buffers and cursors */
1689 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1690 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1691 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1692 struct amdgpu_bo *robj;
1694 if (amdgpu_crtc->cursor_bo) {
1695 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1696 r = amdgpu_bo_reserve(aobj, false);
1698 amdgpu_bo_unpin(aobj);
1699 amdgpu_bo_unreserve(aobj);
1703 if (rfb == NULL || rfb->obj == NULL) {
1706 robj = gem_to_amdgpu_bo(rfb->obj);
1707 /* don't unpin kernel fb objects */
1708 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1709 r = amdgpu_bo_reserve(robj, false);
1711 amdgpu_bo_unpin(robj);
1712 amdgpu_bo_unreserve(robj);
1716 /* evict vram memory */
1717 amdgpu_bo_evict_vram(adev);
1719 amdgpu_fence_driver_suspend(adev);
1721 r = amdgpu_suspend(adev);
1723 /* evict remaining vram memory */
1724 amdgpu_bo_evict_vram(adev);
1726 pci_save_state(dev->pdev);
1728 /* Shut down the device */
1729 pci_disable_device(dev->pdev);
1730 pci_set_power_state(dev->pdev, PCI_D3hot);
1735 amdgpu_fbdev_set_suspend(adev, 1);
1742 * amdgpu_resume_kms - initiate device resume
1744 * @pdev: drm dev pointer
1746 * Bring the hw back to operating state (all asics).
1747 * Returns 0 for success or an error on failure.
1748 * Called at driver resume.
1750 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1752 struct drm_connector *connector;
1753 struct amdgpu_device *adev = dev->dev_private;
1754 struct drm_crtc *crtc;
1757 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1764 pci_set_power_state(dev->pdev, PCI_D0);
1765 pci_restore_state(dev->pdev);
1766 if (pci_enable_device(dev->pdev)) {
1774 if (!amdgpu_card_posted(adev))
1775 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1777 r = amdgpu_resume(adev);
1779 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1781 amdgpu_fence_driver_resume(adev);
1784 r = amdgpu_ib_ring_tests(adev);
1786 DRM_ERROR("ib ring test failed (%d).\n", r);
1789 r = amdgpu_late_init(adev);
1794 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1795 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1797 if (amdgpu_crtc->cursor_bo) {
1798 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1799 r = amdgpu_bo_reserve(aobj, false);
1801 r = amdgpu_bo_pin(aobj,
1802 AMDGPU_GEM_DOMAIN_VRAM,
1803 &amdgpu_crtc->cursor_addr);
1805 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1806 amdgpu_bo_unreserve(aobj);
1811 /* blat the mode back in */
1813 drm_helper_resume_force_mode(dev);
1814 /* turn on display hw */
1815 drm_modeset_lock_all(dev);
1816 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1817 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1819 drm_modeset_unlock_all(dev);
1822 drm_kms_helper_poll_enable(dev);
1823 drm_helper_hpd_irq_event(dev);
1826 amdgpu_fbdev_set_suspend(adev, 0);
1834 * amdgpu_gpu_reset - reset the asic
1836 * @adev: amdgpu device pointer
1838 * Attempt the reset the GPU if it has hung (all asics).
1839 * Returns 0 for success or an error on failure.
1841 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1843 unsigned ring_sizes[AMDGPU_MAX_RINGS];
1844 uint32_t *ring_data[AMDGPU_MAX_RINGS];
1851 atomic_inc(&adev->gpu_reset_counter);
1854 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1856 r = amdgpu_suspend(adev);
1858 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1859 struct amdgpu_ring *ring = adev->rings[i];
1863 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1864 if (ring_sizes[i]) {
1866 dev_info(adev->dev, "Saved %d dwords of commands "
1867 "on ring %d.\n", ring_sizes[i], i);
1872 r = amdgpu_asic_reset(adev);
1874 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1877 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1878 r = amdgpu_resume(adev);
1882 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1883 struct amdgpu_ring *ring = adev->rings[i];
1887 amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1889 ring_data[i] = NULL;
1892 r = amdgpu_ib_ring_tests(adev);
1894 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1897 r = amdgpu_suspend(adev);
1902 amdgpu_fence_driver_force_completion(adev);
1903 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1905 kfree(ring_data[i]);
1909 drm_helper_resume_force_mode(adev->ddev);
1911 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1913 /* bad news, how to tell it to userspace ? */
1914 dev_info(adev->dev, "GPU reset failed\n");
1920 #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1921 #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1923 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1928 if (amdgpu_pcie_gen_cap)
1929 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1931 if (amdgpu_pcie_lane_cap)
1932 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1934 /* covers APUs as well */
1935 if (pci_is_root_bus(adev->pdev->bus)) {
1936 if (adev->pm.pcie_gen_mask == 0)
1937 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1938 if (adev->pm.pcie_mlw_mask == 0)
1939 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1943 if (adev->pm.pcie_gen_mask == 0) {
1944 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1946 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1947 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1948 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1950 if (mask & DRM_PCIE_SPEED_25)
1951 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1952 if (mask & DRM_PCIE_SPEED_50)
1953 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1954 if (mask & DRM_PCIE_SPEED_80)
1955 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1957 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1960 if (adev->pm.pcie_mlw_mask == 0) {
1961 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1965 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1966 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1967 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1971 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1974 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1975 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1976 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1978 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1979 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1982 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1984 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1985 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1989 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1990 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1991 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1995 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1996 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1997 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2000 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2001 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2004 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2010 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2018 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2019 const struct drm_info_list *files,
2024 for (i = 0; i < adev->debugfs_count; i++) {
2025 if (adev->debugfs[i].files == files) {
2026 /* Already registered */
2031 i = adev->debugfs_count + 1;
2032 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2033 DRM_ERROR("Reached maximum number of debugfs components.\n");
2034 DRM_ERROR("Report so we increase "
2035 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2038 adev->debugfs[adev->debugfs_count].files = files;
2039 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2040 adev->debugfs_count = i;
2041 #if defined(CONFIG_DEBUG_FS)
2042 drm_debugfs_create_files(files, nfiles,
2043 adev->ddev->control->debugfs_root,
2044 adev->ddev->control);
2045 drm_debugfs_create_files(files, nfiles,
2046 adev->ddev->primary->debugfs_root,
2047 adev->ddev->primary);
2052 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2054 #if defined(CONFIG_DEBUG_FS)
2057 for (i = 0; i < adev->debugfs_count; i++) {
2058 drm_debugfs_remove_files(adev->debugfs[i].files,
2059 adev->debugfs[i].num_files,
2060 adev->ddev->control);
2061 drm_debugfs_remove_files(adev->debugfs[i].files,
2062 adev->debugfs[i].num_files,
2063 adev->ddev->primary);
2068 #if defined(CONFIG_DEBUG_FS)
2070 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2071 size_t size, loff_t *pos)
2073 struct amdgpu_device *adev = f->f_inode->i_private;
2077 if (size & 0x3 || *pos & 0x3)
2083 if (*pos > adev->rmmio_size)
2086 value = RREG32(*pos >> 2);
2087 r = put_user(value, (uint32_t *)buf);
2100 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2101 size_t size, loff_t *pos)
2103 struct amdgpu_device *adev = f->f_inode->i_private;
2107 if (size & 0x3 || *pos & 0x3)
2113 if (*pos > adev->rmmio_size)
2116 r = get_user(value, (uint32_t *)buf);
2120 WREG32(*pos >> 2, value);
2131 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2132 size_t size, loff_t *pos)
2134 struct amdgpu_device *adev = f->f_inode->i_private;
2138 if (size & 0x3 || *pos & 0x3)
2144 value = RREG32_PCIE(*pos >> 2);
2145 r = put_user(value, (uint32_t *)buf);
2158 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2159 size_t size, loff_t *pos)
2161 struct amdgpu_device *adev = f->f_inode->i_private;
2165 if (size & 0x3 || *pos & 0x3)
2171 r = get_user(value, (uint32_t *)buf);
2175 WREG32_PCIE(*pos >> 2, value);
2186 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2187 size_t size, loff_t *pos)
2189 struct amdgpu_device *adev = f->f_inode->i_private;
2193 if (size & 0x3 || *pos & 0x3)
2199 value = RREG32_DIDT(*pos >> 2);
2200 r = put_user(value, (uint32_t *)buf);
2213 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2214 size_t size, loff_t *pos)
2216 struct amdgpu_device *adev = f->f_inode->i_private;
2220 if (size & 0x3 || *pos & 0x3)
2226 r = get_user(value, (uint32_t *)buf);
2230 WREG32_DIDT(*pos >> 2, value);
2241 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2242 size_t size, loff_t *pos)
2244 struct amdgpu_device *adev = f->f_inode->i_private;
2248 if (size & 0x3 || *pos & 0x3)
2254 value = RREG32_SMC(*pos >> 2);
2255 r = put_user(value, (uint32_t *)buf);
2268 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2269 size_t size, loff_t *pos)
2271 struct amdgpu_device *adev = f->f_inode->i_private;
2275 if (size & 0x3 || *pos & 0x3)
2281 r = get_user(value, (uint32_t *)buf);
2285 WREG32_SMC(*pos >> 2, value);
2296 static const struct file_operations amdgpu_debugfs_regs_fops = {
2297 .owner = THIS_MODULE,
2298 .read = amdgpu_debugfs_regs_read,
2299 .write = amdgpu_debugfs_regs_write,
2300 .llseek = default_llseek
2302 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2303 .owner = THIS_MODULE,
2304 .read = amdgpu_debugfs_regs_didt_read,
2305 .write = amdgpu_debugfs_regs_didt_write,
2306 .llseek = default_llseek
2308 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2309 .owner = THIS_MODULE,
2310 .read = amdgpu_debugfs_regs_pcie_read,
2311 .write = amdgpu_debugfs_regs_pcie_write,
2312 .llseek = default_llseek
2314 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2315 .owner = THIS_MODULE,
2316 .read = amdgpu_debugfs_regs_smc_read,
2317 .write = amdgpu_debugfs_regs_smc_write,
2318 .llseek = default_llseek
2321 static const struct file_operations *debugfs_regs[] = {
2322 &amdgpu_debugfs_regs_fops,
2323 &amdgpu_debugfs_regs_didt_fops,
2324 &amdgpu_debugfs_regs_pcie_fops,
2325 &amdgpu_debugfs_regs_smc_fops,
2328 static const char *debugfs_regs_names[] = {
2335 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2337 struct drm_minor *minor = adev->ddev->primary;
2338 struct dentry *ent, *root = minor->debugfs_root;
2341 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2342 ent = debugfs_create_file(debugfs_regs_names[i],
2343 S_IFREG | S_IRUGO, root,
2344 adev, debugfs_regs[i]);
2346 for (j = 0; j < i; j++) {
2347 debugfs_remove(adev->debugfs_regs[i]);
2348 adev->debugfs_regs[i] = NULL;
2350 return PTR_ERR(ent);
2354 i_size_write(ent->d_inode, adev->rmmio_size);
2355 adev->debugfs_regs[i] = ent;
2361 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2365 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2366 if (adev->debugfs_regs[i]) {
2367 debugfs_remove(adev->debugfs_regs[i]);
2368 adev->debugfs_regs[i] = NULL;
2373 int amdgpu_debugfs_init(struct drm_minor *minor)
2378 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2382 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2386 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }